SLAS205B − DECEMBER 1998 − REVISED OCTOBER 2003
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D8-Bit Resolution 80 MSPS Sampling
Analog-to-Digital Converter (ADC)
DLow Power Consumption: 165 mW Typ
Using External references
DWide Analog Input Bandwidth: 700 MHz Typ
D3.3 V Single-Supply Operation
D3.3 V TTL/CMOS-Compatible Digital I/O
DInternal Bottom and Top Reference Voltages
DAdjustable Reference Input Range
DPower Down (Standby) Mode
DSeparate Power Down for Internal Voltage
References
DThree-State Outputs
D28-Pin Small Outline IC (SOIC) and Thin
Shrink SOP (TSSOP) Packages
DApplications
− Digital Communications
− Flat Panel Displays
− High-Speed DSP Front-End
(TMS320C6000)
− Medical Imaging
− Graphics Processing (Scan Rate/Format
Conversion)
− DVD Read Channel Digitization
DESCRIPTION
The TLV5580 is an 8-bit 80 MSPS high-speed A/D
converter. It converts the analog input signal into
8-bit binary-coded digital words up to a sampling
rate of 80 MHz. All digital inputs and outputs are
3.3 V TTL/CMOS-compatible.
The device consumes very little power due to the
3.3 V supply and an innovative single-pipeline
architecture implemented in a CMOS process.
The user obtains maximum flexibility by setting
both bottom and top voltage references from
user-supplied voltages. If no external references
are available, on-chip references are available for
internal and external use. The full-scale range is
1 Vpp up to 1.6 Vpp, depending on the analog
supply voltage. If external references are
available, the internal references can be disabled
independently from the rest of the chip, resulting
in an even greater power saving.
While usable in a wide variety of applications, the
device is specifically suited for the digitizing of
high-speed graphics and for interfacing to LCD
panels or LCD/DMD projection modules . Other
applications include DVD read channel
digitization, medical imaging and
communications. This device is suitable for IF
sampling of communication systems using
sub-Nyquist sampling methods because of its
high analog input bandwidth.
! "#$ ! %#&'" ($) (#"!
" !%$""! %$ *$ $! $+! !#$! !(( ,-)
(#" %"$!!. ($! $"$!!'- "'#($ $!. '' %$$!)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
1
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7
8
9
10
11
12
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28
27
26
25
24
23
22
21
20
19
18
17
16
15
DRVDD
D0
D1
D2
D3
D4
D5
D6
D7
DRVSS
DVSS
CLK
OE
DVDD
AVSS
AVDD
AIN
CML
PWDN_REF
AVSS
REFBO
REFBI
REFTI
REFTO
AVSS
BG
AVDD
STBY
DW OR P W PACKAGE
(TOP VIEW)
Copyright 1999−2003, Texas Instruments Incorporated
www.ti.com
SLAS205B − DECEMBER 1998 − REVISED OCTOBER 2003
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2
FUNCTIONAL BLOCK DIAGRAM
SHA
DACADC
+−ADC
Correction Logic
Output Buffers
2222 2
D0(LSB)−D7(MSB)
2
2
SHA SHA SHA SHA SHA
The single-pipeline architecture uses 6 ADC/DAC stages and one final flash ADC. Each stage produces a
resolution of 2 bits. The correction logic generates its result using the 2-bit result from the first stage, 1 bit from
each of the 5 succeeding stages, and 1 bit from the final stage in order to arrive at an 8-bit result. The correction
logic ensures no missing codes over the full operating temperature range.
PACKAGE/ORDERING INFORMATION
PRODUCT PACKAGE−LEAD PACKAGE
DESIGNATOR(1)
SPECIFIED
TEMPERATURE
RANGE PACKAGE
MARKING ORDERING
NUMBER TRANSPORT MEDIA,
QUANTITY
TLV5580 SOIC, 28 DW 0°C to +70°C TLV5580C TLV5580CDW Rails, 20
″ ″ ″ ″ ″ TLV5580CDWR Tape and Reel, 1000
TLV5580 TSSOP. 2 8 PW 0°C to +70°C TV5580 TLV5580CPW Rails, 20
″ ″ ″ ″ ″ TLV5580CPWR Tape and Reel, 2000
TLV5580 SOIC, 28 DW −40°C to +85°C TLV5580I TLV5580IDW Rails, 50
″ ″ ″ ″ ″ TLV5580IDWR Tape and Reel, 1000
TLV5580 TSSOP, 2 8 PW −40°C to +85°C TY5580 TLV5580IPW Rails, 50
″ ″ ″ ″ ″ TLV5580IPWR Tape and Reel, 2000
(1) For the most current specifications and package information, refer to our web site at www.ti.com.
SLAS205B − DECEMBER 1998 − REVISED OCTOBER 2003
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3
CIRCUIT DIAGRAMS OF INPUTS AND OUTPUTS
DVDD AVDD
AVDD
0.5 p F
Internal
Reference
Generator
REFTO
or
REFBO
AVDD
REFBI
or
REFTI
OE
ALL DIGITAL INPUT CIRCUITS AIN INPUT CIRCUIT
REFERENCE INPUT CIRCUIT D0−D7 OUTPUT CIRCUIT DRVDD
DRVSS
D_Out
D
SLAS205B − DECEMBER 1998 − REVISED OCTOBER 2003
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4
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME NO.
I/O
DESCRIPTION
AIN 26 I Analog input
AVDD 16, 27 IAnalog supply voltage
AVSS 18, 23, 28 IAnalog ground
BG 17 O Band gap reference voltage. A 1 µF capacitor (with an optional 0.1 µF capacitor in parallel) should be
connected between this terminal and AVSS for external filtering.
CLK 12 I Clock input. The input is sampled on each rising edge of CLK.
CML 25 O Common mode level. This voltage is equal to (AVDD − AVSS) ÷ 2. An external 0.1 µF capacitor should be
connected between this terminal and AVSS.
D0 − D7 2 − 9 OData outputs. D7 is the MSB
DRVDD 1 I Supply voltage for digital output drivers
DRVSS 10 I Ground for digital output drivers
DVDD 14 I Digital supply voltage
OE 13 I Output enable. When high the D0 − D7 outputs go in high-impedance mode.
DVSS 11 IDigital ground
PWDN_REF 24 I Power down for internal reference voltages. A high on this terminal will disable the internal reference circuit.
REFBI 21 I Reference voltage bottom input. The voltage at this terminal defines the bottom reference voltage for the
ADC. I t can be connected to REFBO or to an externally generated reference level. Sufficient filtering should
be applied to this input. The use a 0.1 µF capacitor connected between REFBI and AVSS is recommended.
Additionally, a 0.1 µF capacitor can be connected between REFTI and REFBI.
REFBO 22 O Reference voltage bottom output. An internally generated reference is available at this terminal. It can be
connected to REFBI or left unconnected. A 1 µF capacitor between REFBO and AVSS will provide sufficient
decoupling required for this output.
REFTI 20 I Reference voltage top input. The voltage at this terminal defines the top reference voltage for the ADC. It
can be connected to REFTO or to an externally generated reference level. Sufficient filtering should be
applied t o this input. The use of a 0.1 µF capacitor between REFTI and AVSS is recommended. Additionally ,
a 0.1 µF capacitor can be connected between REFTI and REFBI.
REFTO 19 O Reference voltage top output. An internally generated reference is available at this terminal. It can be
connected to REFTI or left unconnected. A 1 µF capacitor between REFT O and AVSS will provide sufficient
decoupling required for this output.
STBY 15 I Standby input. A high level on this input enables a power-down mode.
SLAS205B − DECEMBER 1998 − REVISED OCTOBER 2003
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5
ABSOLUTE MAXIMUM RATINGS OVER OPERATING FREE-AIR TEMPERATURE (unless
otherwise noted)†
Supply voltage: AVDD to AGND, DVDD to DGND −0.5 V to 4.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supply voltage: AVDD to DVDD, AGND to DGND −0.5 V to 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital input voltage range to DGND −0.5 V to DVDD + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog input voltage range to AGND −0.5 V to AVDD + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital output voltage applied from external source to DGND −0.5 V to DVDD + 0.5 V. . . . . . . . . . . . . . . . . . .
Reference voltage input range to AGND: V(REFTI), V(REFTO), V(REFBI), V(REFBO) −0.5 V to AVDD + 0.5 V
Operating free-air temperature range, TA: TLV5580C 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TLV5580I −40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg −55°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(1) †Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS OVER OPERATING FREE-TEMPERATURE RANGE
POWER SUPPLY
MIN NOM MAX UNIT
AVDD
Supply voltage DVDD 3 3.
3
3.
6
V
Supply voltage
DRVDD
3
3.3
3.6
V
ANALOG AND REFERENCE INPUTS
MIN NOM MAX UNIT
Reference input voltage (top), V(REFTI) (NOM) − 0.2 2 + (AVDD − 3) (NOM) + 0.2 V
Reference input voltage (bottom), V(REFBI) 0.8 1 1.2 V
Reference voltage differential, V(REFTI) − V(REFBI) 1 + (AVDD − 3) V
Analog input voltage, V(AIN) V(REFBI) V(REFTI) V
DIGITAL INPUTS
MIN NOM MAX UNIT
High-level input voltage, VIH 2.0 DVDD V
Low-level input voltage, VIL DGND 0.2xDVDD V
Clock period, tc12.5 ns
Pulse duration, clock high, tw(CLKH) 5.25 ns
Pulse duration, clock low, tw(CLKL) 5.25 ns
SLAS205B − DECEMBER 1998 − REVISED OCTOBER 2003
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6
ELECTRICAL CHARACTERISTICS OVER RECOMMENDED OPERATING CONDITIONS WITH FCLK = 80
MSPS AND USE OF EXTERNAL VOLTAGE REFERENCES (unless otherwise noted)
POWER SUPPLY
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
AVDD
AVDD = DVDD = 3.3 V, DRVDD = 3 V,
57 71
I
DD
Operating supply current DVDD AVDD = DVDD = 3.3 V, DRVDD = 3 V,
CL = 15 pF, VI = 1 MHz, −1 dBFS
3 3.6 mA
IDD
Operating supply current
DRVDD
CL = 15 pF, VI = 1 MHz, −1 dBFS
5 7.5
mA
PD
Power dissipation
PWDN_REF = L 213 270
P
D
Power dissipation
PWDN_REF = H 165 210 mW
PD(STBY) Standby power STBY = H, CLK held high or low 11 15
mW
DIGITAL LOGIC INPUTS
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IIH High-level input current on CLK†AVDD = DVDD = DRVDD = CLK = 3.6 V 10 µA
IIL Low-level input current on digital inputs
(OE, STDBY, PWDN_REF, CLK) AVDD = DVDD = DRVDD = 3.6 V,
Digital inputs at 0 V 10 µA
CIInput capacitance 5 pF
†IIH leakage current on other digital inputs (OE, STDBY, PWDN_REF) is not measured since these inputs have an internal pull-down resistor of
4 KΩ to DGND.
LOGIC OUTPUTS
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOH High-level output voltage AVDD = DVDD = DRVDD = 3 V at IOH = 50 µA,
Digital output forced high 2.8 V
VOL Low-level output voltage AVDD = DVDD = DRVDD = 3.6 V at IOL = 50 µA,
Digital output forced low 0.1 V
COOutput capacitance 5 pF
IOZH High-impedance state output current to
high level
AVDD = DVDD = DRVDD = 3.6 V
10 µA
IOZL High-impedance state output current to
low level
AV
DD
= DV
DD
= DRV
DD
= 3.6 V
10 µA
SLAS205B − DECEMBER 1998 − REVISED OCTOBER 2003
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7
ELECTRICAL CHARACTERISTICS OVER RECOMMENDED OPERATING CONDITIONS WITH FCLK = 80
MSPS AND USE OF EXTERNAL VOLTAGE REFERENCES (unless otherwise noted)
DC ACCURACY
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Integral nonlinearity (INL), best-fit
Internal references (see Note 1)
TA = −40°C to 85°C
−2.4
±1
2.4
LSB
Integral nonlinearity (INL), best-fit
Internal references (see Note 1)
TA = −40
°
C to 85
°
C
−2.4
±
1
2.4
LSB
Differential nonlinearity (DNL) Internal references (see Note 2) TA = −40°C to 85°C −1 ±0.6 1.3 LSB
Zero error
AVDD = DVDD = 3.3 V, DRVDD = 3 V
See Note 3
5 %FS
Full scale error
AV
DD
= DV
DD
= 3.3 V, DRV
DD
= 3 V
See Note 3
5 %FS
1. Integral nonlinearity refers to the deviation of each individual code from a line drawn from zero to full scale. The point used as zero
occurs 1/2 LSB before the first code transition. The full−scale point is defined as a level 1/2 LSB beyond the last code transition. The deviation
is measured from the center of each particular code to the true straight line between these two endpoints.
2. An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Therefore this measure indicates
how uniform the transfer function step sizes are. The ideal step size is defined here as the step size for the device under test (i.e., (last transition
level − first transition level) ÷ (2n − 2)). Using this definition for DNL separates the effects of gain and of fset error. A minimum DNL better than −1
LSB ensures no missing codes.
3. Zero error is defined as the difference in analog input voltage − between the ideal voltage and the actual voltage − that will switch the ADC output
from code 0 to code 1. The ideal voltage level is determined by adding the voltage corresponding to 1/2 LSB to the bottom reference level. The
voltage corresponding to 1 LSB is found from the difference of top and bottom references divided by the number of ADC output levels (256).
Full-scale error is defined as the difference in analog input voltage – between the ideal voltage and the actual voltage – that will switch the ADC
output from code 254 to code 255. The ideal voltage level is determined by subtracting the voltage corresponding to 1.5 LSB from the top reference
level. The voltage corresponding to 1 LSB is found from the difference of top and bottom references divided by the number of ADC output levels
(256).
ANALOG INPUT
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CIInput capacitance 4 pF
REFERENCE INPUT (AVDD = DVDD = DRVDD = 3.6 V)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Rref Reference input resistance 200 Ω
Iref Reference input current 5 mA
REFERENCE OUTPUTS
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V(REFTO) Reference top offset voltage
Absolute min/max values valid
2.07 2 + [(AVDD − 3) ÷ 2] 2.21 V
V(REFBO) Reference bottom offset voltage
Absolute min/max values valid
and tested for AVDD = 3.3 V 1.09 1 + [(AVDD − 3) ÷ 2] 1.21 V
SLAS205B − DECEMBER 1998 − REVISED OCTOBER 2003
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8
ELECTRICAL CHARACTERISTICS OVER RECOMMENDED OPERATING CONDITIONS WITH FCLK = 80
MSPS AND USE OF EXTERNAL VOLTAGE REFERENCES (unless otherwise noted) (continued)
DYNAMIC PERFORMANCE†
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fin = 1 MHz 6.2 6.7
Effective number of bits, ENOB
fin = 4.43 MHz 6.2 6.7
Bits
Effective number of bits, ENOB
fin = 15 MHz 6.4
Bits
fin = 76 MHz 6.5
fin = 1 MHz 39 42
Signal-to-total harmonic distortion + noise, S/(THD+N)
fin = 4.43 MHz 39 42
dB
Signal-to-total harmonic distortion + noise, S/(THD+N)
fin = 15 MHz 40
dB
fin = 76 MHz 40
fin = 1 MHz −46 −50
Total harmonic distortion (THD)
fin = 4.43 MHz −45.5 −49
dB
Total harmonic distortion (THD)
fin = 15 MHz −44
dB
fin = 76 MHz −45.5
fin = 1 MHz 48 51
Spurious free dynamic range (SFDR)
fin = 4.43 MHz 48 51
dB
Spurious free dynamic range (SFDR)
fin = 15 MHz 46
dB
fin = 76 MHz 48
Analog input full-power bandwidth, BW See Note 4 700 MHz
Differential phase, DP
fclk = 40 MHz, fin = 4.43 MHz,
0.8
°
Differential phase, DP
f
clk
= 40 MHz, f
in
= 4.43 MHz,
20 IRE amplitude vs. full-scale of 140 IRE
0.8
°
Differential gain, DG
fclk = 40 MHz, fin = 4.43 MHz,
20 IRE amplitude vs. full-scale of 140 IRE
0.6
%
Differential gain, DG
20 IRE amplitude vs. full-scale of 140 IRE
0.6
%
†Based on analog input voltage of − 1 dBFS referenced to a 1.3 Vpp full-scale input range and using the external voltage references at
fclk = 80 MSPS with AVDD = DVDD = 3.3 V and DRVDD = 3.0 V at 25°C.
4. The analog input bandwidth is defined as the maximum frequency of a −1 dBFS input sine that can be applied to the device for which an extra
3 dB attenuation is observed in the reconstructed output signal.
SLAS205B − DECEMBER 1998 − REVISED OCTOBER 2003
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9
ELECTRICAL CHARACTERISTICS OVER RECOMMENDED OPERATING CONDITIONS WITH FCLK = 80
MSPS AND USE OF EXTERNAL VOLTAGE REFERENCES (unless otherwise noted) (continued)
TIMING REQUIREMENTS
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fclk Maximum conversion rate 80 MHz
fclk Minimum conversion rate 10 kHz
td(o) Output delay time (see Figure 1) CL = 10 pF, See Notes 5 and 6 4.5 9 ns
th(o) Output hold time CL = 2 pF, See Note 5 2 ns
td(pipe) Pipeline delay (latency) See Note 6 4.5 4.5 4.5 CLK
cycles
td(a) Aperture delay time 3 ns
tj(a) Aperture jitter
See Note 5
1.5 ps, rms
tdis Disable time, OE rising to Hi-Z
See Note 5
5 8 ns
ten Enable, OE falling to valid data 5 8 ns
5. Output timing td(o) is measured from the 1.5 V level of the CLK input falling edge to the 10%/90% level of the digital output. The digital output load
is not higher than 10 pF.
Output hold time th(o) is measured from the 1.5 V level of the CLK input falling edge to the 10%/90% level of the digital output. The digital output
is load is not less than 2 pF.
Aperture delay td(A) is measured from the 1.5 V level of the CLK input to the actual sampling instant.
The OE signal is asynchronous.
OE timing tdis is measured from the VIH(MIN) level of OE to the high-impedance state of the output data. The digital output load is not higher than
10 pF.
OE timing ten is measured from the VIL(MAX) level of OE to the instant when the output data reaches VOH(min) or VOL(max) output levels. The digital
output load is not higher than 10 pF.
6. The number of clock cycles between conversion initiation on an input sample and the corresponding output data being made available from the
ADC pipeline. Once the data pipeline is full, new valid output data is provided on every clock cycle. In order to know when data is stable on the
output pins, the output delay time td(o) (i.e., the delay time through the digital output buffers) needs to be added to the pipeline latency. Note that
since the max. td(o) is more than 1/2 clock period at 80 MHz; data cannot be reliably clocked in on a rising edge of CLK at this speed. The falling
edge should be used.
D0−D7 N−4 N−3 N−2 N−1 N N+1
N
N+1
N+2
N+3
N+4 N+5
tj(A)
td(A)
VIL
(max) 1.5 V
tw(CLKH)tw(CLKL) 1/fCLK
th(o)
1.5 V
td(o)
tdis ten
CLK
OE
90%
10%
VIH(min)
td(pipe)
VOH(min)
VOL(max)
VIL(max)
VIH
(min)
Figure 1. Timing Diagram
SLAS205B − DECEMBER 1998 − REVISED OCTOBER 2003
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10
PERFORMANCE PLOTS AT 25°C
−0.4
−1 0 50 100 150
DNL − LSB
0
0.6
ADC Code
1
200 250
0.8
0.4
0.2
−0.2
−0.6
−0.8
Figure 2. DNL vs Input Code At 80 MSPS (With External Reference, PW Package)
−1
−2 0 50 100 150
INL − LSB
0
1
ADC Code
2
200 250
1.5
0.5
−0.5
−1.5
Figure 3. INL vs Input Code At 80 MSPS (With External Reference, PW Package)
SLAS205B − DECEMBER 1998 − REVISED OCTOBER 2003
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11
PERFORMANCE PLOTS AT 25°C (Continued)
80 MSPS
40 MSPS 60 MSPS
25
20
10
00 102030405060
S(THD+N) − dB
40
45
Analog Input Frequency − MHz
50
70 80 90 100
35
30
15
5
Figure 4. S/(THD+N) vs VIN At 80 MSPS (Internal Reference),
60 MSPS (External Reference), 40 MSPS (External Reference)
−40
−60
−90 0 5 10 15 20 25 30
Power − dBFS
−30
−20
f − Frequency − MHz
−10
0
−50
−70
−80
Figure 5. Spectral Plot fIN = 1.011 MHz At 60 MSPS
SLAS205B − DECEMBER 1998 − REVISED OCTOBER 2003
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12
PERFORMANCE PLOTS AT 25°C (Continued)
−70
−90 0 5 10 15 20 25
Power − dBFS
−40
−20
f − Frequency − MHz
0
30 35 40
−10
−30
−50
−60
−80
Figure 6. Spectral Plot fIN = 0.996 MHz At 80MSPS
−40
−60
−90 0 5 10 15 20 25 30
Power − dBFS
−30
−20
f − Frequency − MHz
−10
35 40
0
−50
−70
−80
Figure 7. Spectral Plot fIN = 15.527 MHz At 80 MSPS
−40
−60
−90 0 5 10 15 20 25 30
Power − dBFS
−30
−20
f − Frequency − MHz
−10
35 40
0
−50
−70
−80
Figure 8. Spectral Plot fIN = 75.02 MHz At 80MSPS
(Plot shows folded spectrum of undersampled input signal)
SLAS205B − DECEMBER 1998 − REVISED OCTOBER 2003
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13
PERFORMANCE PLOTS AT 25°C (Continued)
100
50
00 102030405060
Power − mW
150
200
Sampling Frequency − MHz
250
70 80 90 100
Figure 9. Power vs fCLK
At V
IN
= 1 MHz, −1 dBFS Figure 10. IDRVDD vs fCLK
At V
IN
= 1 MHz, −1 dBFS
2.5
2
1
00 102030405060
IDRVDD − mA
3.5
4.5
Sampling Frequency − MHz
5
70 80 90 100
4
3
1.5
0.5
106
−5
−6
−8
−10
Fundamental Power − dBFS
−3
−1
Analog Input Frequency − Hz
0
−2
−4
−7
−9
107108109
Figure 11. ADC Output Power With Respect To −1 dBFS VIN
(Internal Reference, DW Package)
SLAS205B − DECEMBER 1998 − REVISED OCTOBER 2003
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14
PRINCIPLE OF OPERATION
The TLV5580 implements a high-speed 80 MSPS converter in a cost-effective CMOS process. Powered from
3.3 V, the single-pipeline design architecture ensures low-power operation and 8 bit accuracy. Signal input and
clock signals are all single-ended. The digital inputs are 3.3 V TTL/CMOS compatible. Internal voltage
references are included for both bottom and top voltages. Therefore the converter forms a self-contained
solution. Alternatively the user may apply externally generated reference voltages. In doing so, both input of fset
and input range can be modified to suit the application.
A high-speed sampling-and-hold captures the analog input signal. Multiple stages will generate the output code
with a pipeline delay of 4.5 CLK cycles. Correction logic combines the multistage data and aligns the 8-bit output
word. All digital logic operates at the rising edge of CLK.
ANALOG INPUT
AIN
CI
S1
RSW
RS
VS
TLV5580
Figure 12. Simplified Equivalent Input Circuit
A first-order approximation for the equivalent analog input circuit of the TLV5580 is shown in Figure 12. The
equivalent input capacitance CI is 4 pF typical. The input must charge/discharge this capacitance within the
sample period of one half clock cycle. When a full-scale voltage step is applied, the input source provides the
charging current through the switch resistance RSW (200 Ω) of S1 and quickly settles. In this case the input
impedance is low. Alternatively, when the source voltage equals the value previously stored on CI, the hold
capacitor requires no input current and the equivalent input impedance is very high.
To maintain the frequency performance outlined in the specifications, the total source impedance should be
limited to about 80 Ω, as follows from the equation with fCLK = 80 MHz, CI = 4 pF, RSW = 200 Ω:
RStƪ1÷ǒ2fCLK CI In(256)Ǔ–RSWƫ
So, for applications running at a lower fCLK, the total source resistance can increase proportionally.
SLAS205B − DECEMBER 1998 − REVISED OCTOBER 2003
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15
PRINCIPLE OF OPERATION
DC COUPLED INPUT
_
+
AVDD
VIN
REFTI
REFTO
REFBI
REFBO
AIN TLV5580 _
+
VREF
VIN
REFTI
REFTO
REFBI
REFBO
AIN TLV5580
RIN
R1
RIN
R2
(a) (b)
Figure 13. DC-Coupled Input Circuit
For dc-coupled systems an op amp can level-shift a ground-referenced input signal. A circuit as shown in
Figure 13(a) is acceptable. Alternatively, the user might want a bipolar shift together with the bottom reference
voltage as seen in Figure 13(b). In this case the AIN voltage is given by:
AIN +2 R2÷ǒR1)R2Ǔ VREF –V
IN
AC COUPLED INPUT
VIN AIN TLV5580
R1
R2
VBIAS
+
−
C1
C2
Figure 14. AC-Coupled Input Circuit
For many applications, especially in single supply operation, ac coupling offers a convenient way for biasing
the analog input signal at the proper signal range. Figure 14 shows a typical configuration. To maintain the
outlined specifications, the component values need to be carefully selected. The most important issue is the
positioning of the 3 dB high-pass corner point f−3 dB, which is a function of R2 and the parallel combination of
C1 and C2, called Ceq. This is given by the following equation:
f–3 dB +1÷ǒ2πxR
2xC
eqǓ
where Ceq is the parallel combination of C1 and C2.
Since C1 is typically a large electrolytic or tantalum capacitor, the impedance becomes inductive at higher
frequencies. Adding a small ceramic or polystyrene capacitor, C2 of approximately 0.01 µF, which is not
inductive within the frequency range of interest, maintains low impedance. If the minimum expected input signal
frequency is 20 kHz, and R2 equals 1 kΩ and R1 equals 50 Ω, the parallel capacitance of C1 and C2 must be
a minimum of 8 nF to avoid attenuating signals close to 20 kHz.
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16
PRINCIPLE OF OPERATION
REFERENCE TERMINALS
The voltages on terminals REFBI and REFTI determine the TLV5580’s input range. Since the device has an
internal voltage reference generator with outputs available on REFBO respectively REFTO, corresponding
terminals can be directly connected externally to provide a contained ADC solution. Especially at higher
sampling rates, it is advantageous to have a wider analog input range. The wider analog input range is
achievable by using external voltage references (e.g., at AVDD = 3.3 V, the full scale range can be extended
from 1 Vpp (internal reference) to 1.3 Vpp (external reference) as shown in Table 1). These voltages should
not be derived via a voltage divider from a power supply source. Instead, use a bandgap-derived voltage
reference to derive both references via an op amp circuit. Refer to the schematic of the TLV5580 evaluation
module for an example circuit.
When using external references, the full-scale ADC input range and its dc position can be adjusted. The
full-scale ADC range is always equal to VREFT – VREFB. The maximum full-scale range is dependent on AVDD
as shown in the specification section. In addition to the limitation on their difference, VREFT and VREFB each
also have limits on their useful range. These limits are also dependent on AVDD.
Table 3 summarizes these limits for 3 cases.
Table 1. Recommended Operating Modes
AVDD VREFB(min) VREFB(max) VREFT(min) VREFT(max) [VREFT−VREFB]max
3 V 0.8 V 1.2 V 1.8 V 2.2 V 1 V
3.3 V 0.8 V 1.2 V 2.1 V 2.5 V 1.3 V
3.6 V 0.8 V 1.2 V 2.4 V 2.8 V 1.6 V
DIGITAL INPUTS
The digital inputs are CLK, STDBY, PWDN_REF, and OE. All these signals, except CLK, have an internal
pull-down resistor to connect to digital ground. This provides a default active operation mode using internal
references when left unconnected.
The CLK signal at high frequencies should be considered as an analog input. Overshoot/undershoot should
be minimized by proper termination of the signal close to the TLV5580. An important cause of performance
degradation for a high-speed ADC is clock jitter. Clock jitter causes uncertainty in the sampling instant of the
ADC, in addition to the inherent uncertainty on the sampling instant caused by the part itself, as specified by
its aperture jitter. There is a theoretical relationship between the frequency (f) and resolution (2N) of a signal
that needs to be sampled and the maximum amount of aperture error dtmax that is tolerable. The following
formula shows the relation:
dtmax +1Bƪpf2
ǒN)1Ǔƫ
As an example, for an 8−bit converter with a 15-MHz input, the jitter needs to be kept <41 pF in order not to
have changes in the LSB of the ADC output due to the total aperture error.
SLAS205B − DECEMBER 1998 − REVISED OCTOBER 2003
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17
PRINCIPLE OF OPERATION
DIGITAL OUTPUTS
The output of TLV5580 is a standard binary code. Capacitive loading on the output should be kept as low as
possible (a maximum loading of 10 pF is recommended) to provide best performance. Higher output loading
causes higher dynamic output currents and can increase noise coupling into the device’ s analog front end. To
drive higher loads, use an output buffer is recommended.
When clocking output data from TLV5580, it is important to observe its timing relation to CLK. Pipeline ADC
delay is 4.5 clock cycles to which the maximum output propagation delay is added. See Note 6 in the
specification section for more details.
LAYOUT, DECOUPLING AND GROUNDING RULES
It is necessary for any PCB using the TLV5580 to have proper grounding and layout to achieve the stated
performance. Separate analog and digital ground planes that are spliced underneath the device are advisable.
TLV5580 has digital and analog terminals on opposite sides of the package to make proper grounding easier.
Since there is no internal connection between analog and digital grounds, they have to be joined on the PCB.
Joining the digital and analog grounds at a point in close proximity to the TLV5580 is advised.
As for power supplies, separate analog and digital supply terminals are provided on the device (AVDD/DVDD).
The supply to the digital output drivers is kept separate also (DRVDD). Lowering the voltage on this supply from
the nominal 3.3 V to 3 V improves performance because of the lower switching noise caused by the output
buffers.
Due to the high sampling rate and switched-capacitor architecture, TLV5580 generates transients on the supply
and reference lines. Proper decoupling of these lines is essential. Decoupling as shown in the schematic of the
TLV5580 EVM is recommended.
SLAS205B − DECEMBER 1998 − REVISED OCTOBER 2003
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18
TLV5580 EVALUATION MODULE
TLV5580 EVALUATION MODULE
TI provides an evaluation module (EVM) for TLV5580. The EVM also includes a 10-bit 80 MSPS DAC so that
the user can convert the digitized signal back to the analog domain for functional testing. Performance
measurements can be done by capturing the ADC’s output data.
The EVM provides the following additional features:
DProvision of footprint for the connection of an onboard crystal oscillator, instead of using an external clock input.
DUse of TLV5580 internal or external voltage references. In the case of external references, an onboard circuit
is used that derives adjustable bottom and top reference voltages from a bandgap reference. Two potentiometers
allow for the independent adjustments of both references. The full scale ADC range can be adjusted to the input
signal amplitude.
DAll digital output, control signal I/O (output enable, standby, reference power-down) and clock I/O are provided
on a single connector. The EVM can thus be part of a larger (DSP) system for prototyping.
DOnboard prototyping area with analog and digital supply and ground connections.
Figure 15 shows the EVM schematic.
The EVM is factory shipped for use in the following configuration:
DUse of external (onboard) voltage references
DExternal clock input
ANALOG INPUT
A signal in the range between V(REFBI) and V(REFTI) should be applied to avoid overflow/underflow on connector
J10. This signal is onboard terminated with 50Ω. There is no onboard biasing of the signal. When using external
(onboard) references, these levels can be adjusted with R7 (V(REFTI)) and R6 (V(REFBI)). Adjusting R7 causes
both references to shift. R6 only impacts the bottom reference. The range of these signals for which the device
is specified depends on AVDD and is shown under the Recommended Operating Conditions.
Internally generated reference levels are also dependent on AVDD as shown in the electrical characteristics
section.
CLOCK INPUT
A clock signal should be applied with amplitudes ranging from 0 t o AVDD with a frequency equal to the desired
sampling frequency on connector J9. This signal is onboard terminated with 50 Ω. Both ADC and DAC run off
the same clock signal. Alternatively the clock can be applied from terminal 1 on connector J11. A third option
is using a crystal oscillator. The EVM board provides the footprint for a crystal oscillator that can be populated
by the end-user, depending on the desired frequency. The footprint is compatible with the Epson EG-8002DC
series of programmable high-frequency crystal oscillators. Refer to the TLV5580 EVM Settings for selecting
between the different clock modes.
SLAS205B − DECEMBER 1998 − REVISED OCTOBER 2003
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19
TLV5580 EVALUATION MODULE
POWER SUPPLIES
The board provides seven power supply connectors (see Table 2). For optimum performance, analog and digital
supplies should be kept separate. Using separate supplies for the digital logic portion of TLV5580 (DVDD) and
its output drivers (DRVDD) benefits dynamic performance, especially when DRVDD is put at the minimum
required voltage (3 V), while DVDD might be higher (up to 3.6 V). This lowers the switching noise on the die
caused by the output drivers.
Table 2. Power Supplies
SIGNAL
NAME CONNECTOR BOARD
LABEL DESCRIPTION
DRV3 J1 3DRV 3.3 V digital supply for TLV5580 (digital output drivers)
DV3 J2 3VD 3.3 V digital supply for TL V5580 (digital logic) and peripherals
DV5 J3 5VD 5 V digital supply for D/A converter and peripherals
AV3 J4 3VA 3.3 V analog supply for TLV5580
AV5 J5 5VA 5 V analog supply for onboard reference circuit and D/A converter. Can be left unconnected if
internal references are used and no D/A conversion is required.
AV+12 J6 12VA 12 V analog supply for onboard reference circuit. Can be left unconnected if internal references
are used.
AV−12 J7 −12VA −12 V analog supply for onboard reference circuit. Can be left unconnected if internal references
are used.
VOLTAGE REFERENCES
SW1 and SW2 switch between internal and external top and bottom references respectively. The external
references are onboard generated from a stable bandgap-derived 3.3 V signal (using TI’s TPS7133 and
quad-op amp TLE2144). They can be adjusted via potentiometers R6 (V(REFBI)) and R7 (V(REFTI)). It is advised
to power down the internal voltage references by asserting PWN_REF when onboard references are used.
The references are measured at test points TP3 (V(REFB)) and TP4 (V(REFT)).
DAC OUTPUT
The onboard DAC is a 10-bit 80 MSPS converter. It is connected back-to-back to the TLV5580. While the user
could use its analog output for measurements, the DAC output is directly connected to connector J8 and does
not pass through an analog reconstruction filter . So mirror spectra from aliased signal components feed through
into the analog output.
For this reason and to separate ADC and DAC contributions, performance measurements should be made by
capturing the ADC output data available on connector J11 and not by evaluating the DAC output.
SLAS205B − DECEMBER 1998 − REVISED OCTOBER 2003
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20
TLV5580 EVALUATION MODULE
TLV5580 EVM SETTINGS
CLOCK INPUT SETTINGS
REFERENCE
DESIGNATOR FUNCTION
W1 Clock selection switch
1−2 J11: clock from pin1 on J11 connector
2−3 J9: clock from J9 SMA connector
W2 Clock source switch
JXTL: clock from onboard crystal oscillator
jCLK: clock from pin 1 on J11 connector (if W1/1−2) or J9 SMA connector (if W1/2−3)
NOTE: If set to XTL and a XTL oscillator is populated, no clock signal should be applied to J9 or J11, depending on the W1
setting.
W3 Clock output switch
1−2 Rising: clock output on J1 1 connector is the same phase as the clock to the digital output buffer. Data changes on rising
CLK edge.
2−3 Falling: clock output on J1 1 connector is the opposite phase as the digital output buffer. Data changes on falling CLK edge.
REFERENCE SETTINGS
REFERENCE
DESIGNATOR FUNCTION
SW1 REFT external/internal switch
Jj REFT internal: REFT from TL V5580 internal reference
jJ REFT external: REFT from onboard voltage reference circuit
SW2 REFB external/internal switch
Jj REFB internal: REFB from TL V5580 internal reference
jJ REFB external: REFB from onboard voltage reference circuit
CONTROL SETTINGS
REFERENCE
DESIGNATOR FUNCTION
W4 TLV5580 and digital output buffer output enable control (1)
J5580-574 OE-connected: Connects OEs of TLV5580 and digital output buffer (574 buffer). Use this when no board-external
OE is used. In addition, close W5 to have both OEs permanently enabled.
j5580-574 OE -disconnected: Disconnects OEs of TLV5580 and digital output buf fer (574 buf fer). The OE for the output buf fer
needs to b e pulled low from pin 5 on J11 connector to enable. The OE for TL V5580 is independently controlled from pin 7 on
J11 connector (W5 open) or is permanently enabled if W5 is closed.
W5 TLV5580 and digital output buffer output enable control (2)
J5580 OE to GND: Connects OEs of TL V5580 to GND. Additionally connects OE of 74ALS574 to GND if W4 is 5580-574
OE-connected.
j5580 OE external: Enables control of OE of TL V5580 via pin 7 on J11 connector . When taken high (internal pulldown) the
output can be disabled.
W6 TLV5580 STDBY control
JStdby: STDBY is active (high).
jActive: STDBY i s l o w, via internal pulldown. STDBY can be taken high from pin 9 on J11 connector to enable standby mode.
SLAS205B − DECEMBER 1998 − REVISED OCTOBER 2003
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TLV5580 EVALUATION MODULE
CONTROL SETTINGS (Continued)
REFERENCE
DESIGNATOR FUNCTION
W7 TLV5580 PWDN REF control
JPwdn_ref: PWDN_REF is active (high).
jActive: PWDN_REF is low, via internal pulldown. PWDN_REF can be taken high from pin 10 on J11 connector to enable
pwdn_ref mode.
W8 DAC enable
JActive: D/A on
jStandby: D/A off
SLAS205B − DECEMBER 1998 − REVISED OCTOBER 2003
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22
AVSS
NC
DVSS
DVDD
NC
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
NC
IO
CE
NC
DVSS
VB
DVDD
NC
BLK
CLK
IO
VG
AVDD
AVDD
VREF
SREF
IREF
25
26
27
28
29
30
31
32
1
2
3
4
5
6
7
8
11
16
15
14
13
12
10
9
C30
.1 µF
DV5
24
23
22
21
20
19
18
17
R3
200
C25
.1 µF
R4
3.24 kΩ
U3
C26
.1 µF
CXD2306Q
C29
.1 µF
DV5
C28
.1 µF
R11
10 kΩDV5
R14
10 kΩDV5
W8
R25
R23
R22
R21
R20
R19
R18
20
20
20
20
20
20
20
R24
20
10 kΩ
10 kΩ
10 kΩ
10 kΩ
10 kΩ
10 kΩ
10 kΩ
10 kΩ
R48
R47
R46
R45
R44
R43
R42
R41
DV5 19
18
17
16
15
14
13
12
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q DGND
DV3
20
10
1D
2D
3D
4D
5D
6D
7D
8D
OC
CLK
1
11
2
3
4
5
6
7
8
9
U5
C41
.1 µF
DV3
SN74LVT574DW
20
20
20
20
20
20
20
20
R39
R38
R36
R35
R33
R32
R31
R30
C24
.1 µF
DV5DV5
OE
OUT
VCC
GND
W2
12
13 11 R13
20
J9
CLOCK IN
J8
DAC_OUT
AV5
R29
20
U2D
SN74ALVC00
9
10 8R17
20
U2C
1
23
U2A
4
56
U2B
W3
R37
20
CLK_OUT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
W1
3
21
R28
49.9
CLK_IN
Q(0−7)
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
W4
1DRVDD AVSS 28
2
3
4
5
6
7
8
9
10
11
12
13
14
U6
D0
D1
D2
D3
D4
D5
D6
D7
DRVSS
DVSS
CLK
OE
DVDD
27
26
25
24
23
22
21
20
19
18
17
16
15
AVDD
AIN
CML
PWDN_REF
AVSS
REFBO
REFBI
REFTI
REFTO
AVSS
BG
AVDD
STDBY
R40
10 kΩ
DRV3 C45
.1 µF
C35
.1 µF
DV3
TLV5580PW
W5
W6
C33
.1 µF
C34
.1 µF
AV3
W7
DV3
C42
.1 µF
C46
.1 µF
AV3 J10
ANALOG IN R34
49.9
C36
.01 µF
C39
.1 µF
+C38
10µFC37 .01 µF
C43
.1 µF
+C44
10µF
SW2 SW1
REFBO
EXT_REFB EXT_REFT
REFTO
REFBI
REFTI
TP3 TP4
C40
.1 µF
3IN
3IN −
+3OUT
11
12 10 4IN
4IN −
+4OUT
15
14 16
U4C U4D
1IN
1IIN −
+1OUT
2
31
U4A
R7 1 kΩ
R8
1 kΩ
REF3V
R9
1 kΩ
R12
1 kΩ
R16
1 kΩ
R27
10
EXT_REFT
R6 5 kΩ
R5
2.1 k Ω
REF3V
2IN
2IN −
+2OUT
6
57
U4B
C32
.1 µF
AV −12
C31
.1 µF
AV +12
R15
1 kΩ
EXT_REFB
R26
10
TLE2144CDW
IN
IN
EN
GND
PG
OUT
OUT
SENSE
R1
10 kΩ
3
4
2
1
8
6
5
7
+C23
10µF
C27
.1 µF
+C22
10µF
AV5
REF3V
TP1 TP2
R2
0
1 kΩ
R10
TLE2144CDW
J11
X1
4
13
U1
TPS7133QD
SN74ALVC00
SN74ALVC00
SN74ALVC00
Figure 15. EVM Schematic
SLAS205B − DECEMBER 1998 − REVISED OCTOBER 2003
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23
TLV5580 EVALUATION MODULE
+
+C20
10 µF
C12
10 µF
C11
1 µF
L6
4.7 µH
1
2
J6
Analog +12 V
AV +12 V
C21
10 µF
C14
10 µF
C13
1 µF
L7
4.7 µH
1
2
J7
Analog −12 V
AV −12 V
++
+
+C19
10 µF
C10
10 µF
C9
1 µF
L5
4.7 µH
1
2
J5
Analog +5 V
AV5
+
+C18
10 µF
C8
10 µF
C7
1 µF
L4
4.7 µH
1
2
J4
Analog +3.3 V
AV3
+
+C17
10 µF
C6
10 µF
C5
1 µF
L3
4.7 µH
1
2
J3
Digital +5 V
DV5
+
+C16
10 µF
C4
10 µF
C3
1 µF
L2
4.7 µH
1
2
J2
Digital +3.3 V (DVDD)
DV3
+
+C15
10 µF
C2
10 µF
C1
1 µF
L1
4.7 µH
1
2
J1
Digital +3.3 V (DRVDD)
DRV3
Figure 15. EVM Schematic (Continued)
SLAS205B − DECEMBER 1998 − REVISED OCTOBER 2003
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24
TLV5580 EVALUATION MODULE
Top Overlay
Figure 15. EVM Schematic (Continued)
SLAS205B − DECEMBER 1998 − REVISED OCTOBER 2003
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25
TLV5580 EVALUATION MODULE
Top Layer
Figure 15. EVM Schematic (Continued)
SLAS205B − DECEMBER 1998 − REVISED OCTOBER 2003
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26
TLV5580 EVALUATION MODULE
Internal P l a n e 1
Figure 15. EVM Schematic (Continued)
SLAS205B − DECEMBER 1998 − REVISED OCTOBER 2003
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27
TLV5580 EVALUATION MODULE
Internal Plane 2
Figure 15. EVM Schematic (Continued)
SLAS205B − DECEMBER 1998 − REVISED OCTOBER 2003
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TLV5580 EVALUATION MODULE
3350 (mil)
4200 (mil)
Drill Drawing for Through Hole
Figure 15. EVM Schematic (Continued)
SLAS205B − DECEMBER 1998 − REVISED OCTOBER 2003
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29
TLV5580 EVALUATION MODULE
Bottom Layer
Figure 15. EVM Schematic (Continued)
SLAS205B − DECEMBER 1998 − REVISED OCTOBER 2003
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30
TLV5580 EVALUATION MODULE
Table 3. TLV5580EVM Bill of Material
QTY. REFERENCE DESIGNATOR VALUE SIZE DESCRIPTION MANUFACTURER/
PART NUMBER†
7C1, C11, C13, C3, C5, C7, C9 1 µF 1206 ceramic multi-layer capacitor Any
18 C10, C12, C14, C15, C16, C17,
C18, C19, C2, C20, C21, C22,
C23, C4, C6, C8, C38, C44
10 µF 3216 16 V, 10 µF, tantalum capacitor Any
2C36, C43 0.01 µF 805 Ceramic multi-layer Any
19 C24, C25, C26, C27, C28, C29,
C30, C31, C32, C33, C34, C35,
C37, C39, C40, C41, C42, C45,
C46
0.1 µF 805 Ceramic multi-layer capacitor Any
7J1, J2, J3, J4, J5, J6, J7 Screw Con 2 terminal screw connector Lumberg
KRMZ2
3J10, J8, J9 SMA PCM mount, SMA Jack Johnson Components
142-0701-206
1 J11 IDC26 13I × 2.025I square pin header Samtec
TSW-113-07-L-D
7L1, L2, L3, L4, L5, L6, L7 4.7 µH4.7 µH DO1608C-472-Coil Craft Coil Craft
DO1608-472
1 R2 0 1206 Chip resistor Any
2R26, R27 10 1206 Chip resistor Any
12 R1, R11, R14, R40, R41, R42,
R43, R44, R45, R46, R47, R48 10 K 1206 Chip resistor Any
6R10, R12, R15, R16, R8, R9 1 K 1206 Chip resistor Any
1 R5 2.1 K 1206 Chip resistor Any
20 R13, R17, R18, R19, R20, R21,
R22, R23, R24, R25, R29, R30,
R31, R32, R33, R35, R36, R37,
R38, R39
20 1206 Chip resistor Any
1 R3 200 1206 Chip resistor Any
1 R4 3.24 K 1206 Chip resistor Any
2R28, R34 49.9 1206 Chip resistor Any
1 R6 5 K 4 mm SM pot-top adjust Bourns
3214W-5K
1 R7 1 K 4 mm SM pot-top adjust Bourns
3214W-1K
2SW1, SW2 SPDT C&K tiny series−slide switch C&K
TS01CLE
4TP1, TP2, TP3, TP4 TP Test point, single 0.025I pin Samtec
TSW-101-07-L-S
or equivalent
1 U3 CXD2306Q Sony
CXD2306Q
1 U2 SN74ALVC00D 14-SOIC (D) Quad 2-input positive NAND Texas Instruments
SN74ALVC00D
1 U5 SN74LVT574DW 20-SOP (DW) Texas Instruments
SN74LVT574DW
†Manufacturer and part number data for reference only. Equivalent parts might be substituted on the EVM.
SLAS205B − DECEMBER 1998 − REVISED OCTOBER 2003
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31
TLV5580 EVALUATION MODULE
Table 3. TLV5580EVM Bill of Material (Continued)
QTY. REFERENCE DESIGNATOR VALUE SIZE DESCRIPTION MANUFACTURER/
PART NUMBER†
1 U4 TLE2144CDW 16-SOP(D) Quad op amp Texas Instruments
TLE2144CDW/
TLE2144IDW
1 U6 TLV5580PW 28-TSSOP (PW) Texas Instruments
TLV5580PW
1 U1 TPS7133 8-SOP(D) Low-dropout voltage regulator Texas Instruments
TPS7133QD
6W2, W4, W5, W6, W7, W8 SPST 2 position jumper, 0.1I spacing Samtec
TSW-102-07-L-S
or equivalent
2W1, W3 DPFT 3 position jumper, 0.1I spacing Samtec
TSW-103-07-L-S
or equivalent
1 X1 NA Crystal oscillator Epson
SG-8002DC series
†Manufacturer and part number data for reference only. Equivalent parts might be substituted on the EVM.
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
TLV5580CDW NRND SOIC DW 28 20 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV5580CDWG4 ACTIVE SOIC DW 28 20 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV5580CDWRG4 ACTIVE SOIC DW 28 TBD Call TI Call TI
TLV5580CPW NRND TSSOP PW 28 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV5580CPWG4 ACTIVE TSSOP PW 28 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV5580CPWRG4 ACTIVE TSSOP PW 28 TBD Call TI Call TI
TLV5580IDW NRND SOIC DW 28 20 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV5580IDWG4 ACTIVE SOIC DW 28 20 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV5580IDWRG4 ACTIVE SOIC DW 28 TBD Call TI Call TI
TLV5580IPW NRND TSSOP PW 28 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV5580IPWG4 ACTIVE TSSOP PW 28 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV5580IPWRG4 ACTIVE TSSOP PW 28 TBD Call TI Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 19-Jun-2007
Addendum-Page 1
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,65 M
0,10
0,10
0,25
0,50
0,75
0,15 NOM
Gage Plane
28
9,80
9,60
24
7,90
7,70
2016
6,60
6,40
4040064/F 01/97
0,30
6,60
6,20
80,19
4,30
4,50
7
0,15
14
A
1
1,20 MAX
14
5,10
4,90
8
3,10
2,90
A MAX
A MIN
DIM PINS **
0,05
4,90
5,10
Seating Plane
0°–8°
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
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