Datasheet Middle Power Class-D Speaker Amplifier series 20W+20W Full Digital Speaker Amplifier with built-in DSP BM28720MUV General Description Features BM28720MUV is a Full Digital Speaker Amplifier with built-in DSP (Digital Sound Processor) designed for Flat-panel TVs in particular for space-saving and low-power consumption, delivers an output power of 20W+20W. This IC employs Bipolar, CMOS, and DMOS (BCD) process technology that eliminates turn-on resistance in the output power stage and internal loss due to line resistances up to an ultimate level. With this technology, the IC can achieve high efficiency. In addition, the IC is packaged in a compact reverse heat radiation type power package to achieve low power consumption and low heat generation and eliminates necessity of external heat-sink up to a total output power of 40W. This product satisfies both needs for drastic downsizing, low-profile structures and many function, high quality playback of sound system. Key Specifications 10V to 24V 20W+20W (Typ.) 0.07 [%] (Typ.) Applications Flat Panel TVs (LCD, OEL) Home Audio Desktop PC Amusement equipments Electronic Music equipments, etc. Typical Application Circuit SP ch1 (Lch) OUT2N BSP2N OUT2P BCLK BSP2P SDATA LRCLK BSP1N OUT1N SP ch2 (Rch) SDATAO ERROR MUTE RSTX BSP1P VQFN032V5050 W(Typ) x D(Typ) x H(Max) 5.00mm x 5.00mm x 1.00mm OUT1P Package SDA SCL Supply voltage (VCC) Speaker output power (VCC=18.5V, RL=8) THD+N This IC includes the DSP (digital sound processor) for Audio signal processing for Flat TVs. 12 Band/ch BQ, 3 Band DRC, Pre-Scaler, Channel Mixer, Fine Master Volume, Hard Clipper, Level Meter etc. This IC has one input systems of digital audio interface. (No needs of Master Clock) 2 - I S / LJ / RJ format - LRCLK: 32k/44.1k/48KHz - BCLK: 32fs / 48fs / 64fs - SDATA: 16 / 20 / 24bit This IC has one output systems of digital audio interface. 2 - I S format - SDATA: 16 / 20 / 24bit With wide range of power supply voltage. The monaural output that can reduce the number of external parts can be used. With high efficiency and low heat dissipation contributing to miniaturization, slim design, and also power saving of the system. Eliminates pop-noise generated during the power supply on/off. High quality muting performance is realized by using the soft-muting technology. This IC is built-in with various protection functions for highly reliability design. - High temperature protection - Under voltage protection - Output short protection - DC voltage protection - Clock stop protection Small package VQFN032V5050 MCU Digital Audio Source Figure 1. Typical application circuits Product structureSilicon monolithic integrated circuit .www.rohm.com (c) 2016 ROHM Co., Ltd. All rights reserved. TSZ2211114001 This product has not designed protection against radioactive rays 1/75 TSZ02201-0C1C0E900060-1-2 10.Jun.2016 Rev.003 BM28720MUV Pin configuration and Block diagram 32 31 4 26 25 BSP1P OUT1P REG_G 24 VCCP1 Driver FET 1P 23 BCLK GNDP1 LRCLK I2S/LJ/RJ I/F Driver FET 1N 8 Times OverSampling Digital Filter SDATA Audio DSP TEST1 5 6 27 NC RSTX 3 28 Control I/F 2 wire I/F ADDR 29 MUTEX 2 SCL SDA 1 30 OUT2P Driver FET 2P REG15 7 OUT1N PWM Modulator PLL PLL BSP1N BSP2P 21 20 19 18 Driver FET 2N GNDP2 Protection 8 22 17 VCCP2 DGND DVDD TEST2 9 10 TEST3 SDATAO 11 BSP2N ERROR NC 13 14 12 15 OUT2N 16 Figure 2. Pin configurations and Block diagram (Top View) Pin Description No. Name I/O No. Name 1 ADDR 2 BCLK 3 LRCK I 11 4 SDATA I 12 5 TEST1 I 13 I/O No. I 9 I 10 Name I/O No. Name I/O TEST2 I DVDD - 17 VCCP2 - 25 OUT1P O 18 GNDP2 - 26 BSP1P I TEST3 I 19 SDATAO O 20 BSP2P I 27 REG_G O OUT2P O 28 NC - ERROR O 21 OUT1N O 29 RSTX I 6 PLL - 14 NC - 22 BSP1N I 30 MUTEX I 7 REG15 O 15 BSP2N I 23 GNDP1 - 31 SCL I 8 DGND - 16 OUT2N O 24 VCCP1 - 32 SDA I/O I = input; O = output; - = others www.rohm.com (c) 2013 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 2/75 TSZ02201-0C1C0E900060-1-2 10.Jun.2016 Rev.003 BM28720MUV Absolute Maximum Ratings (Ta=25) Item Symbol VCC DVDD Supply voltage Pd Power dissipation VIN1 Input voltage 1 Terminal voltage 1 Terminal voltage 2 Terminal voltage 3 Operating temperature range Storage temperature range Maximum junction temperature VPIN1 VPIN2 VPIN3 Topr Tstg Tjmax Limit -0.3 to 34 -0.3 to 4.5 3.26 4.56 -0.3 to DVDD+0.3 -0.3 to 7.0 -0.3 to 29 OUTxx+6.0 -25 to +85 -55 to +150 +150 Unit V V W W Conditions Pin 17, 24 Pin 10 (Note 1) (Note 2) (Note 1) (Note 3) (Note 4) V Pin 1 - 5, 9, 11, 12, 13, 29 -32 (Note 1) V V V Pin 27 Pin 16, 20, 21, 25 Pin 15, 19, 22, 26 (Note 1) (Note 1)(Note 5) (Note 1) (Note 1) The voltage that can be applied reference to GND (Pin 8, 18, 23). (Note 2) Do not exceed Pd and Tjmax=150. (Note 3) 74.2mm x 74.2mm x 1.6mm, FR4, 4-layer glass epoxy board (Top and bottom layer back copper foil size: 20.2mm2, 2nd and 3rd layer back copper foil size: 5505mm2) Derating in done at 26.1 mW/ for operating above Ta25. There are thermal via on the board. (Note 4) 74.2mm x 74.2mm x 1.6mm, FR4, 4-layer glass epoxy board (Copper area 5505mm2) Derating in done at 36.5 mW/ for operating above Ta25. There are thermal via on the board. (Note 5) It should use it below this ratings limit including the AC peak waveform (overshoot) for all conditions. At only undershoot, it is admitted using at 10ns and 29V by the VCC reference. (Please refer following figure.) VCC Overshoot to GND 29V (Max.) Undershoot from VCC 29V(Max.) GND 10ns Figure 3. Recommended Operating Ratings (Ta=25) Item Supply voltage Minimum load impedance Symbol VCC Limit 10 to 24 Unit V DVDD 3 to 3.6 V 5.4 3.6 RL Conditions Pin 17, 24 (Note 1) (Note 2) Pin 10 (Note 1) Pin 16, 20, 21, 25 VCC = 18V to 24V Pin 16, 20, 21, 25 VCC < 18V (Note 6) (Note 6) (Note 6) Do not exceed Pd. www.rohm.com (c) 2013 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 3/75 TSZ02201-0C1C0E900060-1-2 10.Jun.2016 Rev.003 BM28720MUV Electrical Characteristics (Unless otherwise specified Ta=25, VCC=18V, DVDD=3.3V, RSTX=3.3V, MUTEX=3.3V, f=1kHz, RL=8, DSP : Through, fs=48kHz, Snubber circuit for output terminal : Rsnb=5.6, Csnb=680pF) Min Limit Typ Max ICC1 IDD1 - 45 9 90 19 mA mA ICC2 - 10 40 A IDD2 - 2.5 7.0 mA VERR - - 0.8 V Pin 13, IO=0.5mA VREG_G VREG15 VIH VIL 4.9 5.7 6.5 1.5 - 1.7 3.3 0.8 V V V V Pin 27 1.3 2.5 0 IUP -150 -100 -50 A Pin 2 - 4 VIN = 0V IDN 35 70 105 A Pin 1, 29, 30, VIN = 3.3V IIL -1 0 - A Pin 31, 32, VIN = 0V IIH - 0 1 A Pin 31, 32, VIN = 3.3V Maximum output power 1 PO1 - 10 - W Maximum output power 2 PO2 - 20 - W Total harmonic distortion 1 THD1 - 0.07 - % Crosstalk 1 CT1 60 80 - dB Output noise voltage 1 VNO1 - 80 - Vrms PWM sampling frequency fPWM1 fPWM2 fPWM3 - 256 352.8 384 - kHz kHz kHz Item Total circuit Circuit current 1 (Normal mode) Circuit current 2 (Reset mode) Open-drain terminal Low level voltage Regulator output voltage 1 Regulator output voltage 2 High level input voltage Low level input voltage Input current (Input pull-up terminal) Input current (Input pull-down terminal) Input current (SCL, SDA terminal) Input current (SCL, SDA terminal) Speaker amplifier output Symbol Unit Conditions Pin 17, 24, No load Pin 10, -infinity dBFS input, No load Pin 17, 24, No load RSTX=0V, MUTEX=0V Pin 10, -infinity dBFS input, No load RSTX=0V, MUTEX=0V Pin 7 Pin 1 - 5, 9, 11, 29 -32 Pin 1 - 5, 9, 11, 29 -32 VCC=13V,THD+N=10% (Note 7) VCC=18.5V,THD+N=10% (Note 7) PO=1W, AES17 (Note 7) VCC=13V, PO=1W, A-weighted (Note 7) -infinity dBFS input, A-weighted (Note 7) fs=32 kHz fs=44.1 kHz fs=48 kHz (Note 7) These items show the typical performance of device and depend on board layout, parts, and power supply. The standard value is in mounting device and parts on surface of ROHM's board directly. www.rohm.com (c) 2013 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 4/75 TSZ02201-0C1C0E900060-1-2 10.Jun.2016 Rev.003 BM28720MUV Typical Performance Curves Speaker output(Ta=25, VCC=18V, DVDD=3.3V, RSTX=0V/3.3V, MUTEX=0V/3.3V, f=1kHz, DSP : Through, fs=48kHz, Snubber circuit for output terminal : Rsnb=5.6, Csnb=680pF) Measured by ROHM designed 4 layer board. 14 60 RSTX=MUTEX=L RL=8 No Signal 12 50 10 40 ICC [mA] ICC [A] RSTX=H RL=8 No Signal 8 6 MUTEX=H 30 20 4 10 2 MUTEX=L 0 0 6 8 6 10 12 14 16 18 20 22 24 26 28 30 VCC [V] 8 10 12 14 16 18 20 22 24 26 28 30 VCC [V] Figure 4. Figure 5. Power supply voltage- Current consumption Power supply voltage- Current consumption 3.0 100 RL=8 90 RL=6 80 RL=4 70 2.0 60 ICC [A] Efficiency [%] RL=6 2.5 50 RL=4 RL=8 1.5 40 1.0 30 20 0.5 10 0.0 0 0 5 10 15 0 20 Output Power [W/CH] 10 15 20 Output Power [W/CH] Figure 7. Figure 6. Output power - Efficiency www.rohm.com (c) 2013 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 5 Output power - Current consumption 5/75 TSZ02201-0C1C0E900060-1-2 10.Jun.2016 Rev.003 BM28720MUV Typical Performance Curves Speaker output(Ta=25, VCC=18V, DVDD=3.3V, RSTX=3.3V, MUTEX=3.3V, f=1kHz, DSP : Through, fs=48kHz, Snubber circuit for output terminal : Rsnb=5.6, Csnb=680pF) Measured by ROHM designed 4 layer board. RL=8 Po=1W RL=8 Po=1W Figure 8. Figure 9. Waveform at soft start Waveform at soft mute 45 2.5 RL=8 RL=8 40 2 VCC=18V 30 THD+N=10% 1.5 25 ICC [A] Output Power [W/CH] 35 20 THD+N=1% 1 15 10 0.5 5 0 0 6 8 0 10 12 14 16 18 20 22 24 26 28 30 10 VCC [V] 20 30 40 Output Pow er [W/CH] Figure 10. Figure 11. Output power - Current consumption (RL=8) Output voltage - Power voltage (RL=8) Dotted line means internal dissipation is over package power. www.rohm.com (c) 2013 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 6/75 TSZ02201-0C1C0E900060-1-2 10.Jun.2016 Rev.003 BM28720MUV Typical Performance Curves Speaker output(Ta=25, VCC=18V, DVDD=3.3V, RSTX=3.3V, MUTEX=3.3V, f=1kHz, DSP : Through, fs=48kHz, Snubber circuit for output terminal : Rsnb=5.6, Csnb=680pF) Measured by ROHM designed 4 layer board. 45 3.5 RL=6 RL=6 40 VCC=18V 3 THD+N=1% 2.5 30 THD+N=10% 25 ICC [A] Output Power [W/CH] 35 2 20 1.5 15 1 10 0.5 5 0 0 0 6 8 10 10 12 14 16 18 20 22 24 26 28 30 20 30 40 Output Pow er [W/CH] VCC [V] Figure 13. Figure 12. Output power - Current consumption (RL=6) Output voltage - Power voltage (RL=6) 3.5 45 RL=4 RL=4 40 VCC=18V 3 2.5 30 25 THD+N=10% 20 ICC [A] Output Power [W/CH] 35 THD+N=1% 2 1.5 15 1 10 0.5 5 0 0 6 8 10 12 14 16 18 20 22 24 26 28 30 0 10 VCC [V] 20 30 40 Output Pow er [W/CH] Figure 14. Figure 15. Output Voltage - Power Voltage (RL=4) Output power - Current consumption (RL=4) Dotted line means internal dissipation is over package power. www.rohm.com (c) 2013 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 7/75 TSZ02201-0C1C0E900060-1-2 10.Jun.2016 Rev.003 BM28720MUV Typical Performance Curves Speaker output(RL=8, Ta=25, VCC=18V, DVDD=3.3V, RSTX=3.3V, MUTEX=3.3V, f=1kHz, DSP : Through, fs=48kHz, Snubber circuit for output terminal : Rsnb=5.6, Csnb=680pF) Measured by ROHM designed 4 layer board. 0 10 No Signal B.W. none RL=8 OUT1 OUT2 -20 5 Voltage Gain [dBrA] -40 Noise FFT [dBV] Po=1W=0dB B.W. none RL=8 OUT1 OUT2 -60 -80 -100 0 -5 -120 -140 10 100 1k 10k -10 100k 10 100 1k Frequency [Hz] Figure 17. Frequency - Output power FFT of output noise voltage 100 10 AES17 RL=8 f=1kHz f=100Hz f=6kHz OUT1 OUT2 AES17 Po=1W RL=8 1 THD+N [%] 10 THD+N [%] 100k Frequency [Hz] Figure 16. 1 0.1 0.1 0.01 0.01 0.001 0.01 10k 0.1 1 10 100 100 1k 10k 100k Frequency [Hz] Po [W] Figure 18. Output Power - THD+N www.rohm.com (c) 2013 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 10 Figure 19. Frequency - THD+N 8/75 TSZ02201-0C1C0E900060-1-2 10.Jun.2016 Rev.003 BM28720MUV Typical Performance Curves Speaker output(RL=8, Ta=25, VCC=18V, DVDD=3.3V, RSTX=3.3V, MUTEX=3.3V, f=1kHz, DSP : Through, fs=48kHz, Snubber circuit for output terminal : Rsnb=5.6, Csnb=680pF) Measured by ROHM designed 4 layer board. 0 OUT1 OUT2 -10 Po=1W RL=8 -20 Crosstalk [dB] -30 -40 -50 -60 -70 -80 -90 -100 10 100 1k 10k 100k Frequency [Hz] Figure 20. Frequency - Crosstalk www.rohm.com (c) 2013 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 9/75 TSZ02201-0C1C0E900060-1-2 10.Jun.2016 Rev.003 BM28720MUV Typical Performance Curves Speaker output(RL=6, Ta=25, VCC=18V, DVDD=3.3V, RSTX=3.3V, MUTEX=3.3V, f=1kHz, DSP : Through, fs=48kHz, Snubber circuit for output terminal : Rsnb=5.6, Csnb=680pF) Measured by ROHM designed 4 layer board. 0 OUT1 OUT2 -20 OUT1 OUT2 Po=1W=0dB B.W. none RL=6 5 -40 Voltage Gain [dB] Noise FFT [dBV] 10 No Signal B.W. none RL=6 -60 -80 -100 0 -5 -120 -140 -10 10 100 1k 10k 100k 10 100 Frequency [Hz] Frequency - Output power 10 AES17 RL=6 THD+N [%] THD+N [%] OUT1 OUT2 AES17 Po=1W RL=6 1 10 1 0.1 0.1 0.01 0.01 0.001 0.01 100k Figure 22. FFT of output noise voltage f=1kHz f=100Hz f=6kHz 10k Frequency [Hz] Figure 21. 100 1k 0.1 1 10 100 10 100 1k 100k Frequency [Hz] Po [W] Figure 23. Figure 24. Output Power - THD+N Frequency - THD+N www.rohm.com (c) 2013 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 10k 10/75 TSZ02201-0C1C0E900060-1-2 10.Jun.2016 Rev.003 BM28720MUV Typical Performance Curves Speaker output RL=6, Ta=25, VCC=18V, DVDD=3.3V, RSTX=3.3V, MUTEX=3.3V, f=1kHz, DSP : Through, fs=48kHz, Snubber circuit for output terminal : Rsnb=5.6, Csnb=680pF) Measured by ROHM designed 4 layer board. 0 OUT1 OUT2 -10 Po=1W RL=6 -20 Crosstalk [dB] -30 -40 -50 -60 -70 -80 -90 -100 10 100 1k 10k 100k Frequency [Hz] Figure 25. Frequency - Crosstalk www.rohm.com (c) 2013 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 11/75 TSZ02201-0C1C0E900060-1-2 10.Jun.2016 Rev.003 BM28720MUV Typical Performance Curves Speaker output(RL=4, Ta=25, VCC=18V, DVDD=3.3V, RSTX=3.3V, MUTEX=3.3V, f=1kHz, DSP : Through, fs=48kHz, Snubber circuit for output terminal : Rsnb=5.6, Csnb=680pF) Measured by ROHM designed 4 layer board. 0 OUT1 OUT2 -20 OUT1 OUT2 Po=1W=0dB B.W. none RL=4 5 -40 Voltage Gain [dB] Noise FFT [dBV] 10 No Signal B.W. none RL=4 -60 -80 -100 0 -5 -120 -140 -10 10 100 1k 10k 100k 10 100 1k Figure 26. Figure 27. Frequency - Output power FFT of output noise voltage f=1kHz f=100Hz f=6kHz 100k Frequency [Hz] Frequency [Hz] 10 10k 10 AES17 RL=4 OUT1 OUT2 AES17 Po=1W RL=4 1 THD+N [%] THD+N [%] 1 0.1 0.1 0.01 0.01 0.01 0.001 0.1 1 10 100 Po [W] 100 1k 10k 100k Frequency [Hz] Figure 28. Output Power - THD+N www.rohm.com (c) 2013 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 10 Figure 29. Frequency - THD+N 12/75 TSZ02201-0C1C0E900060-1-2 10.Jun.2016 Rev.003 BM28720MUV Typical Performance Curves Speaker output(RL=4, Ta=25, VCC=18V, DVDD=3.3V, RSTX=3.3V, MUTEX=3.3V, f=1kHz, DSP : Through, fs=48kHz, Snubber circuit for output terminal : Rsnb=5.6, Csnb=680pF) Measured by ROHM designed 4 layer board. 0 Po=1W RL=4 OUT1 OUT2 -10 -20 Crosstalk [dB] -30 -40 -50 -60 -70 -80 -90 -100 10 100 1k 10k 100k Frequency [Hz] Figure 30. Frequency - Crosstalk www.rohm.com (c) 2013 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 13/75 TSZ02201-0C1C0E900060-1-2 10.Jun.2016 Rev.003 BM28720MUV Digital Block Functional Overview No. 1 Function Pre-Scaler 2 Channel Mixer 3 12 Band BQ 4 Fine Master Volume 5 3 Band DRC 6 Post-Scaler 7 Fine Post-Scaler 8 DC Cut HPF 9 Clipper Input1 I2S LJ RJ Specification Lch / Rch become same set point. +48dB to -79dB (0.5dB step),-dB Lch <= Mute, Lch(default), Rch, (L+R)/2, L-R Rch <= Mute, Lch, Rch(default), (L+R)/2, L-R Lch/Rch are independent phase reversal control available 12 Band biquad type filter Only 5 coefficient is required.(b0,b1,b2,a1,a2) The Filter types which can be realized is Peaking/Low-shelf/High-shelf/Low-pass/High-pass/All-pass/Notch. Lch/Rch become same set point or independent set. There is soft transition function. Lch / Rch become same set point or independent set. +24dB to -103dB (0.125dB step),-dB There is soft transition function Non clip output is achieved Available three band operation Threshold level : +12dB to -32dB (0.5dB step) Lch / Rch become same set point +48dB to -79dB (0.5dB step),-dB Lch / Rch become independent set point +0.7dB to -0.8dB (0.1dB step) Fc : 1Hz Lch / Rch become same set point Clip level : +3dB to -22.5dB (-0.1dB step) Pre Channel Scaler Mixer 12Band /ch BQ Fine Master Volume/ ch 3Band DRC Post Scaler Fine Post Scaler/ ch DC Cut HPF Hard Clipper Main Figure 31. DSP Block diagram www.rohm.com (c) 2013 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 14/75 TSZ02201-0C1C0E900060-1-2 10.Jun.2016 Rev.003 BM28720MUV RSTX pin, MUTEX pin function RSTX (29pin) MUTEX (30pin) DSP block condition Low Low Reset ON High Low High High Low High Speaker output condition HiZ_low (Low consumption) (Note 4) HiZ_low (Mute ON) Normal operation (Mute OFF) Normal operation (Mute ON) Normal operation (Mute OFF) Don't use. (Note 1) RSTX is set to low, internal registers are initialized. (Note 2) VCCP1, VCCP2< 2.5V, IC latched by protection circuit and ERROR terminal condition are initialized. (Note 3) If DVDD is under 3V, RSTX is set to low once for 10ms(min), and set high again. Then DSP is needed to set parameter again. (Note 4) Speaker output becomes HiZ-low after elapse of PWM stop time after setting MUTEX low. Please refer to PWM sampling frequency. PWM sampling frequency PWM sampling frequency of Speaker output and Soft-mute transition time depends on sampling frequency (fs) of the digital sound input. These transition times are changed by sending select address 0x15[1:0]. Sampling frequency (fs) 48kHz 44.1kHz 32 kHz PWM frequency 384kHz 352.8kHz 256kHz Soft mute transition time 0x15[1:0] value Mute ON Mute OFF 0x0 0x1 0x2 10.7ms 21.4ms 42.7ms 10.7ms 10.7ms 10.7ms 86ms 106ms 125ms 0x3 85.4ms 10.7ms 162ms 0x0 0x1 0x2 11.7ms 23.3ms 46.5ms 11.7ms 11.7ms 11.7ms 93ms 113ms 135ms 0x3 92.9ms 11.7ms 177ms 0x0 0x1 0x2 16.1ms 32.1ms 64.1ms 16.1ms 16.1ms 16.1ms 116ms 148ms 178ms 0x3 128.1ms 16.1ms 241ms PWM stop time Wait time(Twait) rules from releasing RSTX to releasing MUTEX. When the time from releasing RSTX to releasing MUTEX prescribes Twait, please secure Twait by all means more than 450ms. www.rohm.com (c) 2013 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 15/75 TSZ02201-0C1C0E900060-1-2 10.Jun.2016 Rev.003 BM28720MUV 2 wire Bus control signal specification 1) Electrical characteristics and Timing of Bus line and I/O stage SDA tBUF tF tHD;STA tR tLOW SCL tHD;STA P tHIGH tHD;DAT tSU;DAT tSU;STA S tSU;STO Sr P Figure 32. SDA and SCL bus line characteristics(Unless otherwise specified Ta=25, VDD=3.3V) Parameter 1 2 3 4 5 6 7 8 9 10 11 12 fSCL High speed mode Min. Max. 0 400 tBUF 1.3 s tHD;STA 0.6 s tLOW tHIGH tSU;STA tHD;DAT tSU;DAT tR tF tSU;STO Cb 1.3 0.6 0.6 300 300 400 s s s s ns ns ns s pF Symbol SCL clock frequency Bus free time betweenStopcondition andStart condition Hold-time of (sending again)Startcondition. After this period the first clock pulse is generated. SCL clock's LOW state Hold-time SCL clock's HIGH state Hold-time Set-up time of sending againStartcondition Data hold time Data set-up time Rise-time of SDA and SCL signal Fall-time of SDA and SCL signal Set-up time of Stopcondition Capacitive load of each bus line 0 (Note 1) 250 20+0.1Cb 20+0.1Cb 0.6 Unit kHz The above-mentioned numerical values are all the values corresponding to VIH min and the VIL max level. (Note 1) To exceed an undefined area on the fall-edge of SCL (VIH min of the SCL signal), the transmitting set should internally offer the holding time of 300ns or more for the SDA signal. (Note 2) SCL and SDA pin is not corresponding to threshold tolerance of 5V. Please use it within 4.5V of the absolute maximum rating. 2)Command interface 2 wire Bus control is used for command interface. It not only writes but also it is possible to read it excluding a part of register. In addition to "Slave Address " , set and write 1 byte of "Select Address " to read out the data. 2 wire Bus Slave mode format is illustrated below. MSB S Slave Address LSB MSB A LSB Select Address MSB A LSB Data A P Figure 33. S Start Condition Slave Address The data of eight bits in total is sent putting up bit of Read mode (high) or Write mode (low) after slave address (7bit) set with the terminal ADDR. (MSB first) A The acknowledge bit adds to data that the acknowledge is sent and received in each byte. When data is correctly sent and received, "low" is sent and received. There was no acknowledgement for "high". Select Address The select address in one byte is used.(MSB first) Data Data byte is sent and received data(MSB first) P Stop Condition www.rohm.com (c) 2013 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 16/75 TSZ02201-0C1C0E900060-1-2 10.Jun.2016 Rev.003 BM28720MUV MSB SDA 6 5 LSB SCL Start Condition SDA SCL="high" 3)Slave Address Stop condition SDA SCL="high" Figure 34. While ADDR pin is "low" MSB A6 1 LSB A5 0 A4 0 A3 0 A2 0 A1 0 A0 0 R/W 1/0 A4 0 A3 0 A2 0 A1 0 A0 1 R/W 1/0 While ADDR pin is "high" MSB A6 1 A5 0 LSB Figure 35. 4) Writing of data Basic format S Slave Address A Select Address A Data A P Master to Slave, Slave to Master Auto-increment format S Slave Address A Select Address A Data 1 A Data 2 Master to Slave, A Data 3...N A P Slave to Master Figure 36. 5)Reading of data First of all, the destination address (0x20 in the example) for reading is written in the register of the 0xD0 address at the time of reading. In the following stream, data is read after the slave address. Please do not return acknowledge when you end the reception. S Slave Address (ex.) 0x80 S (ex.) Slave Address A Req_Addr 0xD0 A Data 1 0x81 Master to Slave 0x** A A Select Address 0x20 Data 2 0x** A A P A Data N P 0x** Slave to MasterAWith AcknowledgeWithout Acknowledge Figure 37. www.rohm.com (c) 2013 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 17/75 TSZ02201-0C1C0E900060-1-2 10.Jun.2016 Rev.003 BM28720MUV Format of digital audio input LRCLK: It is L/R clock input signal. It corresponds to 32kHz/44.1kHz/48kHz and that is same as the sampling frequency (fs). This signal shows left or right of audio data. BCLK: It is Bit Clock input signal. It is used for the latch of data in rising edge. Frequency of BCLK is 64 times of sampling frequency (64fs) or 48 times (48fs) or 32 times (32fs). If BCLK frequency is 32fs, only 16 bit data width is available. SDATA: It is data input signal. It is amplitude data. The data length is different according to the resolution of the input digital data. Data width is selectable as 16 bit, 20 bit or 24 bit. The digital input has I2S, Left-justified and Right-justified formats. The figure below shows the timing chart of each transmission mode. SDATAO: Audio data after DSP processing. Data is audio data after DSP processing. This output is synchronous to LRCK and BCLK. Output supports only I2S format. BCLK clock 64fs I2S 64fs Format LRCLK Left Channel 1 2 3 4 5 6 7 8 Right Channel 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 BCLK MSB SDATA LSB MSB LSB S 1413121110 9 8 7 6 5 4 3 2 1 0 S 1413121110 9 8 7 6 5 4 3 2 1 0 16bit Mode 16bit Mode 20bit Mode 20bit Mode 24bit Mode 24bit Mode Left-Justified 64fs Format LRCLK Left Channel 1 2 3 4 5 6 7 8 Right Channel 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 BCLK MSB LSB SDATA S 1413121110 9 8 7 6 5 4 3 2 1 0 LSB MSB S 1413121110 9 8 7 6 5 4 3 2 1 0 16bit Mode 16bit Mode 20bit Mode 20bit Mode 24bit Mode 24bit Mode Right-Justified 64fs Format LRCLK Left Channel 1 2 3 4 5 6 7 8 Right Channel 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 BCLK MSB SDATA LSB S 1413121110 9 8 7 6 5 4 3 2 1 0 16bit Mode MSB LSB S 1413121110 9 8 7 6 5 4 3 2 1 0 16bit Mode 20bit Mode 20bit Mode 24bit Mode 24bit Mode Figure 38. www.rohm.com (c) 2013 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 18/75 TSZ02201-0C1C0E900060-1-2 10.Jun.2016 Rev.003 BM28720MUV BCLK clock 48fs I2S 48fs Format LRCLK Left Channel Right Channel 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 1 BCLK MSB SDATA LSB MSB LSB S 1413121110 9 8 7 6 5 4 3 2 1 0 S 1413121110 9 8 7 6 5 4 3 2 1 0 16bit Mode 16bit Mode 20bit Mode 20bit Mode 24bit Mode 24bit Mode Left-Justified 48fs Format LRCLK Left Channel Right Channel 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 BCLK MSB LSB SDATA S 1413121110 9 8 7 6 5 4 3 2 1 0 MSB LSB S 1413121110 9 8 7 6 5 4 3 2 1 0 16bit Mode 16bit Mode 20bit Mode 20bit Mode 24bit Mode 24bit Mode Right-Justified 48fs Format LRCLK Left Channel Right Channel 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 BCLK MSB SDATA LSB MSB S 1413121110 9 8 7 6 5 4 3 2 1 0 LSB S 1413121110 9 8 7 6 5 4 3 2 1 0 16bit Mode 16bit Mode 20bit Mode 20bit Mode 24bit Mode 24bit Mode Figure 39. BCLK clock 32fs I2S 32fs Format LRCLK Left Channel Right Channel 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 BCLK MSB SDATA LSB MSB LSB S 1413121110 9 8 7 6 5 4 3 2 1 0 S 1413121110 9 8 7 6 5 4 3 2 1 0 16bit Mode 16bit Mode Left-Justified 32fs Format LRCLK Left Channel Right Channel 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 BCLK MSB LSB MSB LSB SDATA S 1413121110 9 8 7 6 5 4 3 2 1 0 S 1413121110 9 8 7 6 5 4 3 2 1 0 16bit Mode 16bit Mode Right-Justified 32fs Format LRCLK Left Channel Right Channel 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 BCLK MSB LSB MSB LSB SDATA S 1413121110 9 8 7 6 5 4 3 2 1 0 S 1413121110 9 8 7 6 5 4 3 2 1 0 16bit Mode 16bit Mode Figure 40. www.rohm.com (c) 2013 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 19/75 TSZ02201-0C1C0E900060-1-2 10.Jun.2016 Rev.003 BM28720MUV Format setting for Digital Audio Interface Please set BCLK clock fs, Data length and Format by transmitting command according to inputted Digital Serial Audio signal. SDATAO output data bit width is able to be set independently. 2 Output supports only I S format. BCLK clock Default = 0x0 *Blue square means initial value. Select Address 0x03[ 5:4 ] Value 0x0 64fs Explanation of operation 0x1 48fs 0x2 32fs 0x3 Don't use Data format Default = 0x0 *Blue square means initial value. Select Address 0x03[ 3:2 ] Value 0x0 Explanation of operation 2 I S format 0x1 Left-justified format 0x2 Right-justified format 0x3 Don't use Data width Default = 0x2 *Blue square means initial value. Select Address 0x03[ 1:0 ] Value 0x0 Explanation of operation 16 bit 0x1 20 bit 0x2 24 bit 0x3 Don't use SDATAO output data width Default = 0x2 *Blue square means initial value. Select Address 0x78[ 1:0 ] www.rohm.com (c) 2013 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 Value 0x0 Explanation of operation 16 bit 0x1 20 bit 0x2 24 bit 0x3 Don't use 20/75 TSZ02201-0C1C0E900060-1-2 10.Jun.2016 Rev.003 BM28720MUV Audio Interface format and timing Recommended timing and operating conditions (BCLK, LRCLK, SDATA) 1/fLRCLK VIH LRCLK VIL 1/fBCLK VIH BCLK VIL Figure 41. Clock timing VIH LRCLK VIL tHD;LR tSU;LR VIH BCLK VIL tSU ; SD tHD ; SD VIH SDATA VIL Figure 42. Audio Interface timing No. Parameter 1 LRCLK frequency 2 BCLK frequency 3 Symbol Limit Unit fLRCLK Min. 32 Max. 48 fBCLK 2.048 3.072 MHz kHz tSU;LR 20 ns tHD;LR 20 ns Setup time, SDATA tSU;SD 20 ns Hold time, SDATA LRCLK, DUTY BCLK, DUTY tHD;SD dLRCLK dBCLK 20 40 40 60 60 ns % % Setup time, LRCLK 4 Hold time, LRCLK 5 6 7 8 (Note 1) (Note 1) (Note 1) This regulation is to keep rising edge of LRCK and rising edge of BCLK from overlapping. www.rohm.com (c) 2013 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 21/75 TSZ02201-0C1C0E900060-1-2 10.Jun.2016 Rev.003 BM28720MUV Power supply start-up sequence Power up VCCP1, VCCP2 simultaneously. VCCP1 VCCP2 VCCP1,VCCP2 DVDD t DVDD BCLK LRCLK SDATA t More than 10ms After DVDD rises and 10ms or more passes, please set RSTX to H. RSTX t After RSTX rises and 1ms or more passes, please send command. More than 1ms SCL SDA t Start data transmission Twait *please refer to P.15 MUTEX Set MUTEX to high. t OUT1P OUT1N OUT2P OUT2N t Soft-start Speaker BTL output (After LC filter) t *Please make sure to input low to RSTX terminal from external at the time power up DVDD. *Please refer to [7The wake-up Procedure of power-up]. Figure 43. www.rohm.com (c) 2013 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 22/75 TSZ02201-0C1C0E900060-1-2 10.Jun.2016 Rev.003 BM28720MUV Power supply shut-down sequence VCCP1 VCCP2 Power down VCCP1, VCCP2 simultaneously. VCCP1, VCCP2 DVDD t Please don'tstopI2S data before completion of mute transition BCLK LRCLK SDATA t SetMUTEXlow MUTEX t SCL SDA t After the complition of a mute transition, set RSTX=low RSTX t OUT1P OUT1N OUT2P OUT2N t PWM stop time Soft mute transition time t Speaker BTL output (After LC filter) Please make sure to input low to RSTX terminal when DVDD is powered down. Figure 44. www.rohm.com (c) 2013 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 23/75 TSZ02201-0C1C0E900060-1-2 10.Jun.2016 Rev.003 BM28720MUV About the protection function Protection function Detecting & Releasing condition (Note 1) Speaker PWM output ERROR output Output short protection Detecting condition Detecting current = 7.2A (TYP.) HiZ_low (Note 2) (latch) Low (latch) DC voltage protection Detecting condition PWM output Duty=0% or 100% for 12s(TYP)and over HiZ_low (Note 2) (latch) Low (latch) High temperature protection Detecting condition Releasing condition Under voltage protection Chip temperature to be above 150 (TYP.) HiZ_low Chip temperature to be below 120 (TYP.) Normal operation Detecting condition Power supply voltage to be below 7.0V (TYP.) HiZ_low Releasing condition Power supply voltage to be above 7.5V (TYP.) Normal operation Detecting condition Clock stop protection Releasing condition BCLK signal have stopped among constant period. LRCLK signal have stopped among constant period. BCLK frequency is under constant value. BCLK frequency is over constant value. Please refer to P.55-58 about constant value. LRCLK signal haven't stopped among constant period and BCLK continues maximum 60ms or more of continuous appropriate frequency. Please refer to P.55-58 about constant value. Low High HiZ_low High Normal operation (Note 1) The ERROR pin is Nch open-drain output. (Note 2) Once an IC is latched, the circuit is not released automatically even after an abnormal status is removed. The following procedures or is available for recovery. After MUTEX pin is made low once over PWM stop time, MUTEX pin is returned to high again. Turning on the power supply again (VCCP1, VCCP2<2.5V, 10ms(min)). www.rohm.com (c) 2013 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 24/75 TSZ02201-0C1C0E900060-1-2 10.Jun.2016 Rev.003 BM28720MUV 1) Output short protection (Short to the power supply) This IC has the output short protection circuit that stops the PWM output when the PWM output is short-circuited to the power supply due to abnormality. Detecting condition - It will detect when MUTEX pin is set high and the current that flows in the PWM output pin becomes 7.2A(TYP.) or more. The PWM output instantaneously enters the state of HiZ-low if detected, and IC does the latch. Releasing method - After MUTEX pin is set low once over the PWM stop time(see page 15), MUTEX pin is returned to high again. Turning on the power supply again (VCCP1, VCCP2<2.5V, 10ms(min)). Short to VCC Release from short to VCC OUT1P (25pin) OUT1N (21pin) OUT2P (20pin) OUT2N (16pin) t Normal operation after released from latch state. PWM outIC latches with HiZ-low. Over current 7.2A(TYP.) t PWM stop time ERROR (13pin) t s(TYP.) MUTEX30pin Latch release t Figure 45. 2) Output short protection (Short to GND) This IC has the output short protection circuit that stops the PWM output when the PWM output is short-circuited to GND due to abnormality. Detecting condition - It will detect when MUTEX pin is set high and the current that flows in the PWM output terminal becomes 7.2A(TYP.) or more. The PWM output instantaneously enters the state of HiZ-low if detected, and IC does the latch. Releasing method - After MUTEX pin is set low once over the PWM stop time(see page 15), MUTEX pin is returned to high again. Turning on the power supply again (VCCP1, VCCP2<2.5V, 10ms(min)). Short to GND Release from short to GND OUT1P (25pin) OUT1N (21pin) OUT2P (20pin) OUT2N (16pin) t PWM out IC latches with HiZ-low state. Normal operation after released from latch state. Over current 7.2A(TYP.) t PWM stop time ERROR (13pin) t s(TYP.) MUTEX30pin Latch release t Figure 46. www.rohm.com (c) 2013 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 25/75 TSZ02201-0C1C0E900060-1-2 10.Jun.2016 Rev.003 BM28720MUV 3) DC voltage protection in the speaker When the DC voltage in the speaker is impressed due to abnormality, this IC has the protection circuit where the speaker is defended from destruction. Detecting condition - It will detect when MUTEX pin is set high and PWM output Duty=0% or 100% over 12s.(fs=48kHz) Once detected, The PWM output instantaneously enters the state of HiZ-low, and IC does the latch. Releasing method - After MUTEX pin is set low once over the PWM stop time(see page 15), MUTEX pin is returned to high again. Turning on the power supply again (VCCP1, VCCP2<2.5V, 10ms(min)). PWM out locked duty=100% abnormal state. OUT1P (25pin) OUT1N (21pin) OUT2P (20pin) OUT2N (16pin) Abnormal state release PWM out : IC latches with HiZ - low state t Latch release state . Speaker out t Soft - start Protection start surge current into speaker output for 12s and over. ERROR (13pin) PWM stop time t MUTEX(30pin) Latch release t Figure 47. www.rohm.com (c) 2013 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 26/75 TSZ02201-0C1C0E900060-1-2 10.Jun.2016 Rev.003 BM28720MUV 4) High temperature protection This IC has the high temperature protection circuit that prevents thermal reckless driving under an abnormal state for the temperature of the chip to exceed Tjmax=150. Detecting condition - It will detect when MUTEX pin is set high and the temperature of the chip becomes 150(TYP.) or more. The speaker output is muted when detected. Releasing condition - It will release when MUTEX pin is set high and the temperature of the chip becomes 120(TYP.) or less. The speaker output is outputted when released. Temparature of IC chip junction () 150 120 t OUT1P (25pin) OUT1N (21pin) OUT2P (20pin) OUT2N (16pin) HiZ-low t Speaker BTL output (After LC filter) t ERROR (13pin) 3.3V t Figure 48. www.rohm.com (c) 2013 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 27/75 TSZ02201-0C1C0E900060-1-2 10.Jun.2016 Rev.003 BM28720MUV 5) Under voltage protection This IC has the under voltage protection circuit that make speaker output mute once detecting extreme drop of the power supply voltage. Detecting condition - It will detect when MUTEX pin is set high and the power supply voltage becomes lower than 7.0V. The speaker output is muted when detected. Releasing condition - It will release when MUTEX pin is set high and the power supply voltage becomes more than 7.5V. The speaker output is outputted when released. VCCP1 (24pin) VCCP2 (17pin) 7.5V 7.0V t OUT1P (25pin) OUT1N (21pin) OUT2P (20pin) OUT2N (16pin) HiZ- low t Speaker BTL output (After LC filter) t ERROR(13pin) 3.3V t Figure 49. www.rohm.com (c) 2013 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 28/75 TSZ02201-0C1C0E900060-1-2 10.Jun.2016 Rev.003 BM28720MUV 6) Clock stop protection This IC has the clock stop protection circuits that make the speaker output mute when the BCLK and LRCLK frequency of the digital sound input are decreased or low frequency. Detecting condition - BCLK frequency is low or stop, LRCLK frequency is stop. Speaker output is muted. Releasing condition - Mute is released when it passes more than 60ms after an internal error state was removed. (max). Low frequency or stop Normal input BCLK LRCLK Max 60m Max 60ms Internal Error flag t OUT1P OUT1N OUT2P OUT2N t Soft-start Speaker BTL output (After LC filter) t Figure 50. www.rohm.com (c) 2013 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 29/75 TSZ02201-0C1C0E900060-1-2 10.Jun.2016 Rev.003 BM28720MUV Functional descriptions of DSP Block 1Digital Sound Processing(DSP) The digital sound processing (DSP) part of BM28720 is composed of the special hardware which is the optimal for FPD-TV, the Mini/Micro Compo. BM28720MUV does the following processing using this special DSP. Pre-Scaler, Channel Mixer, 12 Band BQ, Fine Master Volume, 3 Band DRC, Fine Post-Scaler, DC Cut HPF, Hard Clipper The outline and signal flow of the DSP part Data width: 32 bit (DATA Machine cycle: 20.3ns Multiplier: 32x24 56 bit Adder: 5656 56 bit Data RAM: 512x32 bit Coefficient RAM: 512x24 bit Sampling frequency : fs=32k,44.1k,48kHz RAM RAM) (1024fs, fs=48kHz) MUX 0 M U X MUX RAM ADD Acc Input1 I2S LJ RJ Pre Chanel Scaler Mixer 12Band /ch BQ Fine Master Volum e/ch Fine Post Scaler/ ch Post Scaler 3Band DRC DC Cut HPF Hard Clipper Main Figure 51. The digital signal from 16 bits to 24 bits is inputted to the DSP but extends 8bit(+48dB) as the overflow margin to the upper side. When doing the processing which exceeds this range, it processes a clip in the DSP. Incidentally, in case of the 2nd IIR-type (BQ) filter which is often used generally as the digital filter, because it consumes a lot of overflow margins, the output of the multiplier and the adder inside needs note. The output of multipliers and the adding machine might exceed +48dB by the coefficient of a1, a2, b0, b1, and b2. In that case, data becomes saturation power. Therefore, the output of the filter cannot obtain the aimed characteristic. X[n] Y[n] b0 Z-1 X[n-1] Z-1 b1 a1 -1 Z X[n-2] Y[n-1] -1 Z b2 a2 Y[n-2] -1 is multiplied by the coefficient of a1 and a2. Direct form 1 Figure 52. www.rohm.com (c) 2013 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 30/75 TSZ02201-0C1C0E900060-1-2 10.Jun.2016 Rev.003 BM28720MUV The management of audio data is as follows by each block. Decimal point 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 S Extension bit 9 8 7 6 5 4 3 2 DATA[22:0] Decimal point 1 0 Audio DATA Data of DSP part 23 22 21 20 19 18 17 16 15 14 13 12 11 10 S EXT. bit 9 8 7 6 5 4 3 2 1 0 Coefficient data[20:0] Coefficient data Coefficient data of DSP part Figure 53. 1-1. Bypass It enable pass the some function of the DSP. By using it, it left the set value of the each function and can be passed that function. it is possible to make ON/OFF of the sound effect easily. 1) 12 Band BQ, 2) 3 Band DRC and the 3) whole DSP can be passed. Input1 I2S LJ RJ Pre Chanel Scaler Mixer Fine 12Band Master /ch BQ SW1 Volume /ch Post 3Band DRC SW2 Scaler Fine Post Scaler/ ch DC Cut Hard HPF SW3 Clipper Main Figure 54. Default = 0x00 *Blue square means initial value. Select Address bit Explanation of operation 0x02 [2:0] www.rohm.com (c) 2013 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 2 Bypass of 12 Band BQ (SW1) 1 Bypass of 3 Band DRC (SW2) 0:Normal 1:Bypass 0 Bypass of DSP (SW3) 0:Normal 1:Bypass 31/75 0:Normal 1:Bypass TSZ02201-0C1C0E900060-1-2 10.Jun.2016 Rev.003 BM28720MUV 1-2. Pre-Scaler Pre-Scaler adjusts gain of input audio data. The adjustable-range can be set from +48 dB to -79 dB with the 0.5-dB step. (Lch/Rch use same value) Pre-Scaler doesn't have a soft transfer feature. Default = 0x60 *Blue square means initial value. Select Address Explanation of operation 0x16 [ 7:0 ] Command Value Gain 0x00 +48dB 0x01 +47.5dB ... ... 0x60 0dB 0x61 -0.5dB 0x62 -1dB ... ... 0xFE -79dB 0xFF - 1-3. Channel setup with a phase inversion function (Channel Mixer 1)) It sets a mixing in the sound on the left channel and the right channel of the digital signal which was inputted to the DSP. It makes a stereo signal a monaural here. Also, the phase-inversion, the mute on each channel can be set. Channel Mixer L L Input 1/2 I2S LJ RJ 1 Lch 1 Rch (L+R)/2 L-R PreScaler - R R Mute 0 Figure 55. www.rohm.com (c) 2013 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 32/75 TSZ02201-0C1C0E900060-1-2 10.Jun.2016 Rev.003 BM28720MUV DSP input: The data inputted into Lch of DSP is inverted. Default = 0x0 *Blue square means initial value. Select Address Value 0x17[7] 0x0 Normal Explanation of operation 0x1 Invert DSP input: The data inputted into Lch of DSP is mixed. Default = 0x1 *Blue square means initial value. Select Address Value Explanation of operation 0x17 [ 6:4 ] 0x0 Mute 0x1 Lch data input 0x2 Rch data input 0x3 (Lch + Rch) / 2 0x4 Lch-Rch DSP input: The data inputted into Rch of DSP is inverted. Default = 0x0 *Blue square means initial value. Select Address Value Explanation of operation 0x17 [3] 0x0 Normal 0x1 Invert DSP input: The data inputted into Rch of DSP is mixed. Default = 0x2 *Blue square means initial value. Select Address Value 0x17 [ 2:0 ] 0x0 Mute 0x1 Lch data input 0x2 Rch data input 0x3 (Lch + Rch) / 2 0x4 Lch-Rch www.rohm.com (c) 2013 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 Explanation of operation 33/75 TSZ02201-0C1C0E900060-1-2 10.Jun.2016 Rev.003 BM28720MUV 1-4. Biquad filter In this IC, the following block has the biquad type filter(BQ). There are 12 Band BQ, Crossover filter of 3 Band DRC block and BQ of the smooth transition. The shape is used as peaking filter, low shelf filter, high shelf filter, low-pass filter, high-pass filter, notch filter and all path filters. Setting the coefficient of the digital filter in the IC by transmit to the coefficient RAM via command. 12 Band BQ have the soft transfer feature. About the detailed order of the parameter setting, please refers to the following BQ setting method. Select of BQ independence or synchronous setting Default = 0x0 *Blue square means initial value. Select Address Value Explanation of operation 0x0 L/R common setting 0x60 [ 4 ]* 0x1 L/R independence setting *0x60[4] setting note. Please re-set all BQ when you change the setting of 0x60[4]. Total 18 BQ needs to be set again. (BQ1-12, DRC1, DRC2 and DRC3). BQ soft transition destination band Default = 0x0 *Blue square means initial value. Select Address Explanation of operation 0x51 [ 4:0 ]* Value Destination Value Destination 0x00 12BAND(1) 0x0A 12BAND(11) 0x01 12BAND(2) 0x0B 12BAND(12) 0x02 12BAND(3) 0x03 12BAND(4) 0x04 12BAND(5) 0x05 12BAND(6) 0x06 12BAND(7) 0x07 12BAND(8) 0x08 12BAND(9) 0x09 12BAND(10) Select of smooth transition Default = 0x0 *Blue square means initial value. Select Address 0x53 [ 6 ] Value 0x0 0x1 www.rohm.com (c) 2013 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 Explanation of operation Use smooth transition Not use smooth transition 34/75 TSZ02201-0C1C0E900060-1-2 10.Jun.2016 Rev.003 BM28720MUV Select the destination channel of smooth transition Default = 0x0 *Blue square means initial value. Select Address Value Explanation of operation 0x53 [ 5:4 ] Lch Rch 0x0 0x1 Lch 0x2 Rch 0x3 Don't use Setting of smooth transition time Default = 0x3 *Blue square means initial value. Select Address Value Explanation of operation 0x53 [ 3:2 ] 0x0 2.7ms 0x1 5.3ms 0x2 10.7ms 0x3 21.3ms Setting of smooth transition wait time Default = 0x0 *Blue square means initial value. Select Address Value 0x53 [ 1:0 ] 0x0 2.7ms Explanation of operation 0x1 5.3ms 0x2 10.7ms 0x3 21.3ms Setting of smooth transition start Default = 0x0 *Blue square means initial value. Select Address Value Explanation of operation 0x58 [ 0 ] 0x0 Stop the smooth transition operation 0x1 Start the smooth transition operation (After the transition is completed, it becomes 0 automatically) This register is write only. Read-out smooth transition status Read only Select Address 0x59 [ 0 ] www.rohm.com (c) 2013 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 Explanation of operation 1 : Executing soft transition 0 : Not during soft transition 35/75 TSZ02201-0C1C0E900060-1-2 10.Jun.2016 Rev.003 BM28720MUV 1-5. Volume Volume is from+24dB to -103dB, and can be selected by the step of 0.125dB. And it is possible to be setting of -dB, too. At the time of switching of Volume, smooth transition is performed. Soft transition duration is optional with the command. L/R synchronous or L/R independent can be selected by 0x10[7]. It becomes the following formula at the transition from AdB to BdB. C is smooth transition duration selected by 0x15[7:6] command. Transition time = |(10 A B 20 20 - 10 ) * C ms | Setting of soft transition time Default = 0x0 *Blue square means initial value. Select Address Value 0x15 [ 7:6 ] 0x0 21.3ms 0x1 42.7ms 0x2 85.3ms 0x3 Don't use Lch/common volume setting Default = 0xFF *Blue square means initial value. Select Address Explanation of operation Value 0x00 0x01 0x11 [ 7:0 ] ... ... 0x30 0dB -0.5dB -1dB 0x31 0x32 ... ... 0xFE -103dB - 0xFF www.rohm.com (c) 2013 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 36/75 Gain +24dB +23.5dB TSZ02201-0C1C0E900060-1-2 10.Jun.2016 Rev.003 BM28720MUV Setting of fine volume This command becomes effective by sending the following command after setting. When using this command, it is possible to set a volume in 0.125dB carving. When L/R synchronous volume setting, 0x11[7:0] is enable. When L/R independent volume setting, 0x11[7:0] is the volume setting of Lch. Lch/common fine volume setting Default = 0x0 *Blue square means initial value. Select Address Value Explanation of operation 0x10 [ 1:0 ] 0x0 0dB 0x1 -0.125dB 0x2 -0.25dB 0x3 -0.375dB Note1 It is possible to use with the 0.5-dB step in changing only 0x11[7:0] when 0x10[1:0]=0x0. The Lch/Rch independent volume setting and the synchronous volume setting can be selected by 0x10[7] command. When Lch/Rch independent volume set, the volume setting of Lch is the setting of 0x10[1:0] and 0x11, and the volume setting of Rch is the settings of 0x10[5:4] and 0x12. Setting of Lch/Rch independent volume Default = 0x0 *Blue square means initial value. Select Address Value 0x10[ 7 ] 0x0 Lch/Rch common volume setting Explanation of operation 0x1 Lch/Rch independent volume setting Setting of volume (Setting of Rch volume, It is enable only to set an independent volume.) Default = 0xFF *Blue square means initial value. Select Address Explanation of operation 0x12 [ 7:0 ] Value 0x00 0x01 Gain +24dB +23.5dB ... ... 0x30 0dB -0.5dB -1dB 0x31 0x32 ... ... 0xFE -103dB - 0xFF Setting of fine volume This command becomes effective by sending the following command after setting. When using this command, it is possible to set a volume in 0.125dB carving. Setting of fine volume (Setting of Rch fine volume, It is enable only to set an independent volume.) Default = 0x0 *Blue square means initial value. Select Address Value Explanation of operation 0x10 [ 5:4 ] 0x0 0dB 0x1 -0.125dB 0x2 -0.25dB 0x3 -0.375dB Note2 It is possible to use with the 0.5-dB step in changing only 0x12[7:0] when 0x10[5:4]=0. www.rohm.com (c) 2013 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 37/75 TSZ02201-0C1C0E900060-1-2 10.Jun.2016 Rev.003 BM28720MUV Note3 It is possible to use with the 0.125-dB step in setting both 0x10[1:0] and 0x11[7:0]. In case of 0x10[1:0] = 0x0, it becomes the set value of 0x11[7:0]. In case of 0x10[1:0] = 0x1, it becomes the -0.125dB set value of 0x11[7:0]. In case of 0x10[1:0] = 0x2, it becomes the -0.25dB set value of 0x11[7:0]. In case of 0x10[1:0] = 0x3, it becomes the -0.375dB set value of 0x11[7:0]. Because it is fixed by the transfer of 0x11 in any case, the soft transfer can be beforehand begun in the set value for the direct following of the purpose in setting 0x11 after setting in 0x10. 0x10[5:4] is the same function as 0x10[1:0], 0x12 is the same function as 0x11 when Lch/Rch independently set for Rch. 0x100x11 0x11 0x100x11 0x11 Volume Volume When use 0.125dB steps When use 0.5dB steps Figure 56. 1-6. 3 band DRC This DRC is used in order to prevent clip output of a large audio signal. There are three kinds of DRC (DRC1, DRC2, and DRC3), and non clip output can be achieved at each band. DRC1, DRC2 and DRC3 can set up two threshold value levels. Moreover, it is possible to also change slope. 3 Band DRC block diagram Crossover Filters AGC_TH1, Slope DRC3 HPF Input DRC4 Output AGC_TH1, Slope DRC1 LPF AGC_TH1, Slope DRC2 APF Figure 57. www.rohm.com (c) 2013 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 38/75 TSZ02201-0C1C0E900060-1-2 10.Jun.2016 Rev.003 BM28720MUV DRC transition figure Input A_TIME AGC_TH Volume Level Output AGC_TH R_TIME R_TIME A_ RATE A_TIME R_ RATE In here A_TIME is the time for detecting time before starting gain down operation. And A_RATE decides the slope of gain compression. On the other hand R_TIME is the time for detecting before starting to release gain operation. And R_RATE decides slope of release gain. Figure 58. DRC1, DRC2, DRC3 can be set AGC_TH1 and AGC_TH2 as shown in below. If output is in between AGC_TH1 and AGC_TH2, a slant for output gain can be made. If input become bigger and output over AGC_TH2, output gain don't have slant and become constant level. Value for slant setting () is calculated by AGC_TH1, AGC_TH2 and the value of input gain for reaching AGC_TH2 (xdB). The operation between AGC_TH1 and AGC_TH2 is decided as DRC1 slope and DRC2slope and DRC3slope. And the operation over AGC_TH2 is decided as DRC1comp and DRC2comp and DRC3comp. Each operation can be set ON/OFF, A_TIME, A_RATE, R_TIME, R_RATE respectively. DRC input-and-output gain characteristics [dB] VO The formula which asks for Slope alpha is described below. = 0x00 Alpha changes into 8bit Hex data of the complement of 2 the value calculated by calculation. y x 20 20 = AGC_TH2 y = -6dB 10 - 10 TH 20 x 20 x 128 10 - 10 AGC_TH1 -12dB = 0x80 TH is AGC_TH1. x is input level. y is output level. Ex) It asks for alpha at the time of AGC_TH1 = -12dB, x = 0dB y = -6dB -6 = 0 1020 - 1020 -12 20 0 20 x 128 10 - 10 = 85.266 0x55 VOinf 0x55 calculated is set as 0x29, 0x31 or 0x39. VIinf -12dB x = 0dB VI Figure 59. www.rohm.com (c) 2013 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 39/75 TSZ02201-0C1C0E900060-1-2 10.Jun.2016 Rev.003 BM28720MUV Volume Curve Volume Level Linear Curve Linear Curve Exponential Curve Exponential Curve AGC_TH A_RATE R_RATE Time Figure 60. DRC1slope ON/OFF setting OFF is through output. Default = 0x1 *Blue square means initial value. Select Address Value 0x20 [ 7] 0x0 Not use Explanation of operation 0x1 Use DRC1comp ON/OFF setting OFF is through output. Default = 0x1 *Blue square means initial value. Select Address Value 0x20 [ 6 ] 0x0 Not use Explanation of operation 0x1 Use DRC2slope ON/OFF setting OFF is through output. Default = 0x1 *Blue square means initial value. Select Address Value 0x20 [ 5 ] 0x0 Not use Explanation of operation 0x1 Use DRC2comp ON/OFF setting OFF is through output. Default = 0x1 *Blue square means initial value. Select Address Value 0x20 [ 4 ] 0x0 Not use 0x1 Use www.rohm.com (c) 2013 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 Explanation of operation 40/75 TSZ02201-0C1C0E900060-1-2 10.Jun.2016 Rev.003 BM28720MUV DRC3slope ON/OFF setting OFF is through output. Default = 0x1 *Blue square means initial value. Select Address Value 0x20 [ 3 ] 0x0 Not use Explanation of operation 0x1 Use DRC3comp ON/OFF setting of compressor OFF is through output. Default = 0x1 *Blue square means initial value. Select Address Value 0x20 [ 2 ] 0x0 Not use Explanation of operation 0x1 Use DRC4 ON/OFF setting DRC4 have only compression function. DRC4 don't have slope function. OFF is through output. Default = 0x0 *Blue square means initial value. Select Address Value Explanation of operation 0x3F [ 4 ] 0x0 Not use 0x1 Use The volume curve at the time of an attack (A_RATE) is selected. Default = 0x1 *Blue square means initial value. Select Address Value 0x21[ 7 ] 0x0 Linear curve Explanation of operation 0x1 Exponential curve The volume curve at the time of a release (R_RATE) is selected. Default = 0x1 *Blue square means initial value. Select Address Value 0x21 [ 6 ] 0x0 Linear curve Explanation of operation 0x1 Exponential curve DRC is 1 Band setting at initial state. To set the crossover filter (HPF, LPF and APF) which divides the frequency band of 3 Band DRC, therefore, it is referred to the 1-4. www.rohm.com (c) 2013 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 41/75 TSZ02201-0C1C0E900060-1-2 10.Jun.2016 Rev.003 BM28720MUV Slope () setting of DRC1slope, DRC2slope, and DRC3slope DRC1slope, DRC2slope and DRC3slope can be set individually. Default = 0x80 *Blue square means initial value. Select Address DRC1slope 0x29 [ 7:0 ] DRC2slope 0x31 [ 7:0 ] DRC3slope 0x39 [ 7:0 ] Explanation of operation [dB] VO The formula which asks for Slope alpha is described below. = 0x00 Alpha changes into 8bit Hex data of the complement of 2 the value calculated by calculation. y x 20 20 = AGC_TH2 y = -6dB 10 - 10 TH x x 128 1020 - 1020 AGC_TH1 -12dB = 0x80 TH is AGC_TH1. x is input level. y is output level. Ex) It asks for alpha at the time of AGC_TH1 = -12dB, x = 0dB y = -6dB -6 = 0 1020 - 1020 -12 0 x 128 1020 - 1020 = 85.266 0x55 VOinf 0x55 calculated is set as 0x29, 0x31 or 0x39. VIinf -12dB x = 0dB VI AGC_TH1 setting of DRC1slope, DRC2slope, and DRC3slope DRC1slope, DRC2slope and DRC3slope can be set individually. Please set this value is smaller than the value of AGC_TH2. Default = 0x40 *Blue square means initial value. Select Address Explanation of operation DRC1slope 0x28 [ 6:0 ] DRC2slope 0x30 [ 6:0 ] DRC3slope 0x38 [ 6:0 ] Value 0x00 ... 0x3F 0x40 0x41 -32dB ... -0.5dB 0dB +0.5dB ... 0x58 ... +12dB Threshold AGC_TH2 setting of DRC1comp, DRC2comp, DRC3comp, and DRC4 DRC1comp, DRC2comp, DRC3comp and DRC4 can be set individually. Default = 0x40 *Blue square means initial value. Select Address Explanation of operation DRC1comp 0x2C [ 6:0 ] DRC2comp 0x34 [ 6:0 ] DRC3comp 0x3C [ 6:0 ] DRC4 0x40 [ 6:0 ] www.rohm.com (c) 2013 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 42/75 Value 0x00 ... 0x3F 0x40 0x41 -32dB ... -0.5dB 0dB +0.5dB ... 0x58 ... +12dB Threshold TSZ02201-0C1C0E900060-1-2 10.Jun.2016 Rev.003 BM28720MUV A_RATE setting of DRC1slope, DRC2slope, DRC3slope, DRC1comp, DRC2comp, DRC3comp, DRC4 DRC1slope, DRC2slope, DRC3slope, DRC1comp, DRC2comp, DRC3comp, DRC4 can be set individually. Default = 0x3 *Blue square means initial value. Select Address Explanation of operation DRC1slope 0x2A [ 6:4 ] DRC2slope 0x32 [ 6:4 ] DRC3slope 0x3A [ 6:4 ] DRC1comp 0x2E [ 6:4 ] DRC2comp 0x36 [ 6:4 ] DRC3comp 0x3D [ 6:4 ] DRC4 Value A_RATE Value A_RATE 0x0 0x1 0x2 0x3 1ms 2ms 3ms 4ms 0x4 0x5 0x6 0x7 5ms 10ms 20ms 40ms 0x41 [ 6:4 ] R_RATE setting of DRC1slope, DRC2slope, DRC3slope, DRC1comp, DRC2comp, DRC3comp, DRC4 DRC1slope, DRC2slope, DRC3slope, DRC1comp, DRC2comp, DRC3comp, DRC4 can be set individually. Default = 0xB *Blue square means initial value. Select Address Explanation of operation DRC1slope 0x2A [ 3:0 ] DRC2slope 0x32 [ 3:0 ] DRC3slope 0x3A [ 3:0 ] DRC1comp 0x2E [ 3:0 ] DRC2comp 0x36 [ 3:0 ] DRC3comp 0x3D [ 3:0 ] DRC4 0x41 [ 3:0 ] Value R_RATE Value R_RATE 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0.125s 0.1825s 0.25s 0.5s 0.75s 1s 1.25s 1.5s 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF 2s 2.5s 3s 4s 5s 6s 7s 8s A_TIME setting of DRC1slope, DRC2slope, DRC3slope, DRC1comp, DRC2comp, DRC3comp, DRC4 DRC1slope, DRC2slope, DRC3slope, DRC1comp, DRC2comp, DRC3comp, DRC4 can be set individually. Default = 0x1 *Blue square means initial value. Select Address Explanation of operation DRC1slope 0x2B [ 7:4 ] DRC2slope 0x33 [ 7:4 ] DRC3slope 0x3B [ 7:4 ] DRC1comp 0x2F [ 7:4 ] DRC2comp 0x37 [ 7:4 ] DRC3comp 0x3E [ 7:4 ] DRC4 0x42 [ 7:4 ] www.rohm.com (c) 2013 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 43/75 Value A_TIME Value A_TIME 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0ms 0.5ms 1ms 1.5ms 2ms 3ms 4ms 5ms 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF 6ms 7ms 8ms 9ms 10ms 20ms 30ms 40ms TSZ02201-0C1C0E900060-1-2 10.Jun.2016 Rev.003 BM28720MUV R_TIME setting of DRC1, DRC2, DRC3, and DRC4 DRC1, DRC2, DRC3 and DRC4 are individually setting. Default = 0x3 *Blue square means initial value. Select Address Explanation of operation DRC1slope 0x2B [ 2:0 ] DRC2slope 0x33 [ 2:0 ] DRC3slope 0x3B [ 2:0 ] DRC1comp 0x2F [ 2:0 ] DRC2comp 0x37 [ 2:0 ] DRC3comp 0x3E [ 2:0 ] DRC4 Value R_TIME Value R_TIME 0x0 0x1 0x2 0x3 5ms 10ms 25ms 50ms 0x4 0x5 0x6 0x7 100ms 200ms 300ms 400ms 0x42 [ 2:0 ] www.rohm.com (c) 2013 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 44/75 TSZ02201-0C1C0E900060-1-2 10.Jun.2016 Rev.003 BM28720MUV 1-7. Post-Scaler Post-Scaler adjusts gain of output audio data. The adjustable-range can be set from +48 dB to -79 dB with the 0.5-dB step. (Lch/Rch use same value) Pre-Scaler doesn't have a soft transfer feature. Default = 0x60 *Blue square means initial value. Select Address Explanation of operation 0x13 [ 7:0 ] Value 0x00 0x01 Gain +48dB +47.5dB ... ... 0x60 0x61 0x62 0dB -0.5dB -1dB ... ... 0xFE 0xFF -79dB - 1-8. Fine Post-Scaler An adjustable range can be set up at a 0.1dB step from +0.7dB to -0.8dB. Fine Post-Scaler does not have a smooth transition function. (Lch and Rch can be set different value.) Default= 0x8 *Blue square means initial value. Select Address Lch 0x14 [ 7:4 ] Rch 0x14 [ 3:0 ] www.rohm.com (c) 2013 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 Explanation of operation Command 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 45/75 Gain -0.8dB -0.7dB -0.6dB -0.5dB -0.4dB -0.3dB -0.2dB -0.1dB Command 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF Gain 0dB +0.1dB +0.2dB +0.3dB +0.4dB +0.5dB +0.6dB +0.7dB TSZ02201-0C1C0E900060-1-2 10.Jun.2016 Rev.003 BM28720MUV 1-9. Hard Clipper Measuring output of the television, output power is measured in 10% THD+N condition. It can be made to clip with any output amplitude by using a clipper function. For example, the output of 10W or 5W can be gained using the amplifier of 15W output. Hard clip Clip level0dB +3dB Clip level-3dB Clip level+3dB +3dB +3dB 0dB 0dB 0dB -3dB -3dB -3dB -6dB -6dB -6dB Figure 61. Clipper setting Default = 0x1 *Blue square means initial value. Select Address Value 0x1A [ 0 ] 0x0 Clipper function is not used. Explanation of operation 0x1 Hard clipper function is used. Clip level selection Default = 0xE1 *Blue square means initial value. Select Address Explanation of operation 0x1B [ 7:0 ] ... 0xE0 0xE1 0xE2 -0.1dB 0dB +0.1dB ... ... 46/75 Gain -22.5dB -22.4dB ... www.rohm.com (c) 2013 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 Value 0x00 0x01 0xFE 0xFF +2.9dB +3dB TSZ02201-0C1C0E900060-1-2 10.Jun.2016 Rev.003 BM28720MUV 1-10. DC Cut HPF DC offset element of the digital signal outputted from audio DSP is cut by this HPF. The cutoff frequency fc of HPF uses the 1Hz filter, and the degree uses the first-order filter. Default = 0x1 *Blue square means initial value. Select Address Value 0x18 [ 0 ] 0x0 Not use Explanation of operation 0x1 Use 1-11. RAM clear The data RAM of DSP and coefficient RAM are cleared. 40s or more is required until all the data is cleared. Clear of the data RAM Default = 0x1 *Blue square means initial value. Select Address Value 0x01 [ 7 ] 0x0 Normal Explanation of operation 0x1 Clear Clear of coefficient RAM Default = 0x1 *Blue square means initial value. Select Address Value 0x01 [ 6 ] 0x0 Normal 0x1 Clear www.rohm.com (c) 2013 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 Explanation of operation 47/75 TSZ02201-0C1C0E900060-1-2 10.Jun.2016 Rev.003 BM28720MUV 1-12. Audio Output Level Meter It is possible to output the peak level of the PCM data inputted into a PWM processor. A peak value can be read using the 2-wire command interface as 16 bit data of an absolute value. The interval holding a peak value can be selected from six steps (50ms step) from 50ms to 300ms. A peak hold result can be selected from L channel, R channel, and a monophonic channel {(Lch+Rch) /2}. Audio Output Level Meter block diagram I2s DSP Peak Hold (Lch) Peak Hold (Rch) 0.5 Selector 0x75 METER_LOAD [1:0] Level Output Register 0x76, 0x77 OUT_LEVEL [15:0] Figure 62. Setting of the peak level hold time interval of Audio Output Level Meter Default = 0x0 *Blue square means initial value. Select Address Explanation of operation 0x74 [ 2:0 ] Value Hold time 0x0 50ms 100ms 150ms 200ms 250ms 300ms 0x1 0x2 0x3 0x4 0x5 www.rohm.com (c) 2013 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 48/75 TSZ02201-0C1C0E900060-1-2 10.Jun.2016 Rev.003 BM28720MUV The signal of Audio Level Meter read-back is selected. A value will be taken into a read-only register if a setting value is written in. In order to update this register value, it is necessary to write in a setting value again. Write only Select Address Value 0x75 [ 1:0 ] 0x0 The peak level of L channel Explanation of operation 0x1 The peak level of R channel 0x2 The peak level of monophonic channel {(Lch+Rch) /2} Read-back of Audio Output Level 0x76 (upper 8 bits) and a 0x77 (lower 8 bits) commands are read for the maximum within the period appointed by the command 0x74 using the 2-wire interface. (Example) When 0xFFFF is read, mean 1.0 (0dBFs). When 0x8000 is read, mean 0.5 (-6dBFs). www.rohm.com (c) 2013 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 49/75 TSZ02201-0C1C0E900060-1-2 10.Jun.2016 Rev.003 BM28720MUV 2Setting and reading method of BQ It explains a detailed sequence of the setting method and the reading method of the parametric equalizer separately for usage. 2-1 BQ coefficient setting The parametric equalizer consists of biquad filter as follows. Each coefficient of biquad filter can be written directly. It is S2.21 format, and setting range is -4x+4. Moreover, the coefficient address is shown in Table 1. The output of multipliers and the adding machine might exceed +48dB by the coefficient of a1, a2, b0, b1, and b2. In that case, data becomes saturation power. Therefore, the output of the filter cannot obtain the aimed characteristic. X[n] Y[n] b0 Z-1 X[n-1] Z-1 b1 a1 -1 Z X[n-2] Y[n-1] -1 Z b2 a2 Y[n-2] -1 is multiplied by the coefficient of a1 and a2. Direct form 1 Figure 63. 2-1-1 Writing sequence (It sets up in number order) 1. Address setting (0x61) (*1)Table 1 is referred to. 2. 24bit coefficient upper [23:16] bit setting (0x62[7:0]) 3. 24bit coefficient middle [15:8] bit setting (0x63[7:0]) 4. 24bit coefficient lower [7:0] bit setting (0x64[7:0]) 5. The writing of coefficients is performed. (0x65[0] = 0x1) * * After completion of writing coefficients this register is cleared automatically. It is not necessary to transmit 0x65[0] = 0x0. Coefficient writing takes about 100s.100s should not change an address setup and several 24-bit setup after coefficient write-in execution. (ex) When 0x3DEDE7 is written, same L/Rch, 12band BQ1 b0 1. 0x61 = 0x00 (12band BQ1 b0 is appointed) 2. 0x62 = 0x3D (Upper [23:16] is setting) 3. 0x63 = 0xED (Middle [15:8] is setting) 4. 0x64 = 0xE7 (Lower [7:0] is setting) 5. 0x65 = 0x01 (Coefficient transfer)* *After completion of writing coefficients this register is cleared automatically. 6. 100s or more wait 2-1-2 Read-back sequence (It sets up in number order) 1. 2. 3. 4. 5. Address setting (0x61) . Please refer to Table 1. Setting of a read-back register address (0xD0) Read-back of the 24bit coefficient upper[23:16]bit (0x66[7:0]) Read-back of the 24bit coefficient middle[15:8]bit (0x67[7:0]) Read-back of the 24bit coefficient lower[7:0]bit (0x68[7:0]) 2-1-3 When the coefficient of PEQ is set up directly and a soft transition is performed 1. Set PEQ coefficient to soft transition address whose address is 0x50-0x54. Please refer to Table1. Since in the case of 0x60[4] = 0x1(Enable L/R independent setting) and 0x53 [5:4] = 0x0 a soft transition is carried out and it is set to LR simultaneously, please write a coefficient in both LR address. In the case of 0x53[5:4] = 0x1, coefficient is set to only Lch address. In the case of 0x53[5:4] = 0x2, coefficient is set to only Rch address. 2. Select PEQ Band that is performed soft transition by setting 0x51[4:0] address.(Refer to chapter 1-4) 3. 0x58[0] = 0x1Start soft transition (After the completion of soft transition this register is automatically cleared.) 4. Wait soft transition completion (It depend on soft transition time setting), or read command 0x59 [0], and stand by until it is cleared. www.rohm.com (c) 2013 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 50/75 TSZ02201-0C1C0E900060-1-2 10.Jun.2016 Rev.003 BM28720MUV Table1. Specified coefficient 0x61[6:0] Destination 0x61[6:0] Destination 0x00 12BandBQ1 b0 0x23 12BandBQ8 b0 0x01 12BandBQ1 b1 0x24 12BandBQ8 b1 0x02 12BandBQ1 b2 0x25 12BandBQ8 b2 0x03 12BandBQ1 a1 0x26 12BandBQ8 a1 0x04 12BandBQ1 a2 0x27 12BandBQ8 a2 0x05 12BandBQ2 b0 0x28 12BandBQ9 b0 0x06 12BandBQ2 b1 0x29 12BandBQ9 b1 0x07 12BandBQ2 b2 0x2A 12BandBQ9 b2 0x08 12BandBQ2 a1 0x2B 12BandBQ9 a1 0x09 12BandBQ2 a2 0x2C 12BandBQ9 a2 0x0A 12BandBQ3 b0 0x2D 12BandBQ10 b0 0x0B 12BandBQ3 b1 0x2E 12BandBQ10 b1 0x0C 12BandBQ3 b2 0x2F 12BandBQ10 b2 0x0D 12BandBQ3 a1 0x30 12BandBQ10 a1 0x0E 12BandBQ3 a2 0x31 12BandBQ10 a2 0x0F 12BandBQ4 b0 0x32 12BandBQ11 b0 0x10 12BandBQ4 b1 0x33 12BandBQ11 b1 0x11 12BandBQ4 b2 0x34 12BandBQ11 b2 0x12 12BandBQ4 a1 0x35 12BandBQ11 a1 0x13 12BandBQ4 a2 0x36 12BandBQ11 a2 0x14 12BandBQ5 b0 0x37 12BandBQ12 b0 0x15 12BandBQ5 b1 0x38 12BandBQ12 b1 0x16 12BandBQ5 b2 0x39 12BandBQ12 b2 0x17 12BandBQ5 a1 0x3A 12BandBQ12 a1 0x18 12BandBQ5 a2 0x3B 12BandBQ12 a2 0x19 12BandBQ6 b0 0x3C DRC1_1 b0 0x1A 12BandBQ6 b1 0x3D DRC1_1 b1 0x1B 12BandBQ6 b2 0x3E DRC1_1 b2 0x1C 12BandBQ6 a1 0x3F DRC1_1 a1 0x1D 12BandBQ6 a2 0x40 DRC1_1 a2 0x1E 12BandBQ7 b0 0x41 DRC1_2 b0 0x1F 12BandBQ7 b1 0x42 DRC1_2 b1 0x20 12BandBQ7 b2 0x43 DRC1_2 b2 0x21 12BandBQ7 a1 0x44 DRC1_2 a1 0x22 12BandBQ7 a2 0x45 DRC1_2 a2 When L/R independent, Lch:0x61[7]=0x0, Rch:0x61[7]=0x1. When L/R is same, 0x61[7] is not effective. www.rohm.com (c) 2013 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 51/75 0x61[6:0] Destination 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E DRC2_1 b0 DRC2_1 b1 DRC2_1 b2 DRC2_1 a1 DRC2_1 a2 DRC2_2 b0 DRC2_2 b1 DRC2_2 b2 DRC2_2 a1 DRC2_2 a2 Smooth BQ b0 Smooth BQ b1 Smooth BQ b2 Smooth BQ a1 Smooth BQ a2 DRC3_1 b0 DRC3_1 b1 DRC3_1 b2 DRC3_1 a1 DRC3_1 a2 DRC3_2 b0 DRC3_2 b1 DRC3_2 b2 DRC3_2 a1 DRC3_2 a2 TSZ02201-0C1C0E900060-1-2 10.Jun.2016 Rev.003 BM28720MUV 3The mute function by a terminal BM28720MUV has a mute function of audio DSP by a terminal. It is possible to perform mute of the output from Audio DSP by setting a MUTEX terminal to low. Transition time setting at the time of mute is as follows. Smooth transition mute time setting The transition time when changing to a mute state is selected. The soft transition time at the time of mute release is 10.7ms fixed. Default = 0x3 *Blue square means initial value. Select Address Value 0x15 [ 1:0 ] 0x0 10.7ms Explanation of operation 0x1 21.4ms 0x2 42.7ms 0x3 85.4ms 0x15[1:0] Mute time setting It is only operated by mute terminal. XdB Mute state Audio output data TA TB Figure 64. 0x15[1:0] setting Command TA 0x0 10.7ms 0x1 21.4ms 0x2 42.7ms 0x3 85.4ms www.rohm.com (c) 2013 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 TB 10.7ms 10.7ms 10.7ms 10.7ms 52/75 TSZ02201-0C1C0E900060-1-2 10.Jun.2016 Rev.003 BM28720MUV Smooth transition mute release time setting Time after detecting mute release until it actually begins mute release operation is set up. Default = 0x0 *Blue square means initial value. Select Address Value Explanation of operation 0x15 [ 5:4 ] 0x0 0ms 0x1 100ms 0x2 200ms 0x3 300ms Operation of mute delay 0x15[5:4] MUTEX Command 0x0 0 0x1 0x2 0x3 Audio output data TM TM 0ms 100ms 200ms 300ms Figure 65. www.rohm.com (c) 2013 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 53/75 TSZ02201-0C1C0E900060-1-2 10.Jun.2016 Rev.003 BM28720MUV 4Small signal input detection function There is a function which detects the audio data input of a non-signal or a small signal. This function is used in order to reduce the standby power consumption of an audio set. Setting of a detection level and detection time can be performed. If the signal below a setting detection level continues in both low channel and R channel, a small signal detection flag will become "high". A detection result can be read from command 0x72 [0]. The point which acts as a monitor of the small signal becomes input data of audio DSP block. I2S DSP Block diagram Peak Detector Peak Detector (Lch) (Rch) Counter Flag 0x72 [0] NOSIG_DET_FLAG Figure 66. Detection level setting Default = 0x00 *Blue square means initial value. Select Address Explanation of operation 0x70 [ 4:0 ] Value 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 Level -103dB -93dB -91dB -87dB -84dB -80dB -79dB -78dB Value 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F Level -77dB -76dB -75dB -74dB -73dB -72dB -71dB -70dB Value 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 Level -69dB -68dB -67dB -66dB -65dB -64dB -62dB -60dB Detection time setting Default = 0x0 *Blue square means initial value. Select Address Value Explanation of operation 0x71 [ 1:0 ] 0x0 42.7ms 0x1 85.4ms 0x2 170.7ms 0x3 341.4ms * Sampling frequency is value of Fs = 48kHz. In the case of Fs = 44.1kHz, it will be about 1.09 times the setting value. Detection flag read-back Read Only Select Address Value 0x72 [ 0 ] 0x0 Undetected 0x1 Detecting www.rohm.com (c) 2013 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 Explanation of operation 54/75 TSZ02201-0C1C0E900060-1-2 10.Jun.2016 Rev.003 BM28720MUV 5Clock stop detection and detection of BCLK frequency begin too low or too high or asynchronous state detection 5-1. Clock stops detection BM28720MUV needs some clock source for generating proper clock to process Audio data. By stopping these cock sources, these clocks to process Audio data also stop. To prevent noise sounds, we need to detect BCLK or LRCLK stop condition. As we detect stop flag that is to be valid, output is gone to mute state (mute instantly). Internal frequency generator Clock stop detecion circuit BCLK Judge OK/NG LRCLK Figure 67. Each detect condition is set by below command. We can check detected result by reading back flag register. These flags are cleared only by sending specified commands. LRCLK stop detection time Default = 0x2 *Blue square means initial value. Select Address LRCLK 0x07 [ 2:0 ] Value 0x0 Operation 10s to 20s 0x1 20s to 40s 0x2 50s to 100s 0x3 100s to 200s 0x4 200s to 400s 0x5 300s to 600s 0x6 400s to 800s 0x7 500s to 1000s Detection time has the above-mentioned variation within the limits. BCLK stop detection time Default = 0x0 *Blue square means initial value. Select Address Value BCLK 0x08 [ 6:4 ] 0x0 10s to 20s 0x1 20s to 40s 0x2 50s to 100s 0x3 100s to 200s 0x4 200s to 400s 0x5 300s to 600s 0x6 400s to 800s 0x7 500s to 1000s Operation Detection time has the above-mentioned variation within the limits. www.rohm.com (c) 2013 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 55/75 TSZ02201-0C1C0E900060-1-2 10.Jun.2016 Rev.003 BM28720MUV Stop detection flag read back register Read Only Select Address Value 0x09 [ 5 ] 0x0 Normal 0x1 Detection of LRCLK stop flag 0x0 Normal 0x1 Detection of BCLK stop flag 0x09 [ 4 ] Operation Stop detection flag clear register Write Only Select Address Operation 0x09 [ 1 ] LRCLK stop detection flag is cleared by writing 1. 0x09 [ 0 ] BCLK stop detection flag is cleared by writing 1. When using a clock error auto return function (P.59), this flag is cleared automatically. LRCLK stop flag valid or invalid selection Default = 0x1 *Blue square means initial value. Select Address Value 0x07 [ 3 ] Operation 0x0 Valid 0x1 Invalid BCLK stop flag valid or invalid selection Default = 0x0 *Blue square means initial value. Select Address Value 0x08 [ 7 ] Operation 0x0 Valid 0x1 Invalid 5-2. Synchronous blank detection As for synchronous blank detecting function, it detects as synchronous blank error when it counts between the rising edges of LRCK with internal clock (49.152MHz), and it shifts more than the definite value, and whether PLL is normally locked is judged. Input sampling frequency 32kHz,44.1kHz,48kHz Count value 1023 (Start of counting from 0) As for the detection result, reading from the register is possible. Register value is not cleared until a clear command is transmitted even if the state of the clock returns normally. Moreover, the setting of the detection approval frequency is also possible, and if the error counts more than the predetermined number is detected, the flag (0x06[1]) becomes 1. Synchronous blank flag reading register Read Only Select Address 0x06 [ 1 ] Value Explanation of operation 0x0 Normal 0x1 Detect synchronous error Synchronous blank flag clear register Write Only Select Address 0x06 [ 0 ] Explanation of operation When 1 is written, the synchronous blank flag is cleared. * When using a clock error auto return function (P.59), this flag is cleared automatically. www.rohm.com (c) 2013 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 56/75 TSZ02201-0C1C0E900060-1-2 10.Jun.2016 Rev.003 BM28720MUV Synchronous blank count setting Default = 0x2 *Blue square means initial value. Select Address 0x06 [ 6:4 ] Explanation of operation Please set more than 1. 5-3. BCLK high or low speed detection BCLK high or low speed detection function is to judge BCLK speed being too high or low by measuring by using internal clock (12MHz to 25MHz). When using BCLK speed detection, speed failure detection can be more correctly performed by setting a command according to inputted sample rate. When you use error detection function, please set up the sample rate by setting address 0x0C[1:0]. A high speed and the low-speed detection flag can be set up valid or invalid respectively, and if the error is detected, mute (mute instantly) will be carried out. Valid or invalid frequency value setting up by 0x0C[1:0] command. Default = 0x0 *Blue square means initial value. Select Address Value Operation 0x0A [ 3 ] 0x0 Valid 0x1 Invalid Setting of sampling rate Default = 0x0 *Blue square means initial value. Select Address Value Operation 0x0C [ 1:0 ] 0x0 48kHz 0x1 44.1kHz 0x2 32kHz The constraints of a high speed or a low-speed condition Default = 0x0 *Blue square means initial value. Select Address Value 0x0A [ 2 ] 0x0 Operation 10% We can check detection result by reading back. The result judged that is once unusual is not cleared until it transmits a clear command, even if the condition of a clock returns to normal. We can set up We can set up the constraints of the count of formation, and it does not set a flag until it detects it by count continuation. BCLK high speed flag Read Only Select Address Value Operation 0x0A [ 1 ] 0x0 Normal 0x1 High speed detection flag BCLK low speed flag Read Only Select Address Value 0x0B [ 1 ] 0x0 Normal 0x1 Low speed detection flag www.rohm.com (c) 2013 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 Operation 57/75 TSZ02201-0C1C0E900060-1-2 10.Jun.2016 Rev.003 BM28720MUV High speed detection clear register Write Only Select Address 0x0A [ 0 ] Operation If 1 is written in, a high speed detection flag will be cleared. When using a clock error auto return function (P.59), this flag is cleared automatically. Low speed detection clear register Write Only Select Address 0x0B [ 0 ] Operation If 1 is written in, a high speed detection flag will be cleared. When using a clock error auto return function (P.59), this flag is cleared automatically. A constraint of the count of judging with high speed flag detection Default = 0x2 *Blue square means initial value. Select Address 0x0A [ 6:4 ] Operation Please set more than 1. A constraint of the count of judging with low speed flag detection Default = 0x2 *Blue square means initial value. Select Address 0x0B [ 6:4 ] Operation Please set more than 1. High speed detection flag valid or invalid Default = 0x0 *Blue square means initial value.0x0h Select Address 0x0A [ 7 ] Value Operation 0x0 Valid 0x1 Invalid Low speed detection flag valid or invalid Default = 0x0 *Blue square means initial value. Select Address Value Operation 0x0B [ 7 ] 0x0 Valid 0x1 Invalid The frequency range of BCLK by which high speed detection or low speed detection is carried out becomes below. Setting1 64fs 48fs 32fs BCLK(0x03[ 5:4 ]=0x0) BCLK(0x03[ 5:4 ]=0x1) BCLK(0x03[ 5:4 ]=0x2) www.rohm.com (c) 2013 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 Settin2 48kHz(0x0C[1:0]=0x0) Low detection lowest frequency (MHz) 1.28 High detection highest frequency (MHz) 7.13 44.1kHz(0x0C[1:0]=0x1) 1.21 6.55 32kHz(0x0C[1:0]=0x2) 0.88 4.76 48kHz(0x0C[1:0]=0x0) 0.96 5.35 44.1kHz(0x0C[1:0]=0x1) 0.91 4.92 32kHz(0x0C[1:0]=0x2) 0.66 3.57 48kHz(0x0C[1:0]=0x0) 0.64 3.56 44.1kHz(0x0C[1:0]=0x1) 0.60 3.28 32kHz(0x0C[1:0]=0x2) 0.44 2.38 58/75 TSZ02201-0C1C0E900060-1-2 10.Jun.2016 Rev.003 BM28720MUV 6Auto recovery from clock error function If clock error is detected, immediately output is muted. In that case, if the clock error auto return function is enabled, when it returns to a normal input, a mute condition will be canceled automatically. If the clock error auto return function is OFF, it is necessary to clear these error flag manually. Since it is invalid at initial state, we recommend to send 0x0D[6] = 0x1 and to enable auto recovery function. Valid or invalid auto recover from clock error Default = 0x0 *Blue square means initial value. Select Address Value 0x0D [ 6 ] Operation 0x0 Invalid 0x1 Valid Each error flag can be read from the following addresses. When 1 is read from a read address, the error flag stands. Error flag is not cleared automatically until this register is cleared manually. Error flag read register Select Address Operation 0x0E [ 6 ] Asynchronous flag 0x0E [ 4 ] LRCLK stop flag 0x0E [ 3 ] BCLK stop flag 0x0E [ 2 ] BCLK high speed detection flag 0x0E [ 1 ] BCLK low speed detection flag 7The wake-up Procedure of power-up It recommends starting power-up in the following Procedures. 1. Power up Wait over 10ms 2. Release reset(RSTX=H) Wait over 1ms 3. 0x0C[1:0]=0x* Sampling rate(Please set up 0x0 in the case of 48kHz, set up 0x1 in the case of 44.1kHz and 0x02 in 32kHz.) Please input BCLK and LRCLK changing clock to normal state 5. 0x01=0x00 Set RAM clear OFF 6. 0x0D=0x40 Valid auto recover from clock error 7. 0x0E=0x00 Clear error flag 8. 0x92=0x11 PWM setting1 9. 0x93=0x1C PWM setting2 10. 0x94=0x15 PWM setting3 11. 0x95=0x04 PWM setting4 4. 0xE9=0x10 Wait over 100ms 12. Please set up DSP function such as volume, PEQ, DRC, and Scaler etc. 13. MUTEX=high Release mute * The wait time, Twait, is necessary between 2 and 13.(Please refer to P15 for Twait) www.rohm.com (c) 2013 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 59/75 TSZ02201-0C1C0E900060-1-2 10.Jun.2016 Rev.003 BM28720MUV 8The operating procedure in a status with an unstable clock 2 In the period which I S input may become unstable, please set to MUTEX=low and carry out mute. 1. Set MUTEX=low 2 2. Please wait over 20ms after stabilizing I S input. 2. Set MUTEX=high BCLK LRCLK SDATA Stable Unstable Stable MUTEX Over20ms PWM stop time Soft mute transition time Speaker BTL output (After LC filter) (Note 1)When clock stop was detected, mute release procedure world follow clock stop error release condition. Figure 68. www.rohm.com (c) 2013 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 60/75 TSZ02201-0C1C0E900060-1-2 10.Jun.2016 Rev.003 BM28720MUV 2 9I S Data output select 2 Output I S data signal From SDATAO (pin12). That SDATAO synchronize to inputted LRCK and BCK signal. And enable to select output SDATA signal as shown below. Whatever output is selected, hard clip is processed. SDATAO output select Default = 0x0 *Blue square means initial value. Input1 Select Address Value 0x78 [ 6:4 ] 0x0 DSP output (point1) 0x1 DSP input (pont2) 0x2 Pre Scaler output (point3) 0x3 Mixer output (point4) 0x4 12 Band PEQ output (point5) 0x5 Fine Master Volume output (point6) 0x6 No use 0x7 Fine Post Scaler output (point7) I2S LJ RJ Point2 Pre Chanel Scaler Mixer Point3 Explanation of operation 12Band /ch BQ Point4 Fine Master Volum e/ch Point5 3Band DRC Point6 Post Scaler Fine Post Scaler/ ch DC Cut HPF Point7 Hard Clipper Main Point1 Figure 69. www.rohm.com (c) 2013 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 61/75 TSZ02201-0C1C0E900060-1-2 10.Jun.2016 Rev.003 BM28720MUV Application Circuit Example1 (Stereo BTL output, RL=8, Vcc=10V to 18V) When using at Vcc>18V, fc of the LC filter should be lowered to about 60kHz and decrease the influence of LCR resonance using application circuit. Please refer 5) Output LC Filter Circuit (Vcc>18V) GNDP1 MCU C24A 1 F 32 10 F C27 31 30 2 LRCLK Digital Audio Source 3 R3 0 RSTX VSS BCLK R2 0 28 27 NC L25 3.3 F C26 26 25 BSP1P OUT1P C25B 680pF REG_G Control I/F 2 wire I/F ADDR 29 MUTEX SCL SDA DVDD 1 GNDP1 10k R31 10k R32 Slave Address Select RSTX MUTE SCL SDA DVDD DVDD C24B 100 F VCCP1 10 H R25 5.6 C25A 0.33 F R21 5.6 GNDP1 C21A C21B 0.33 F 680pF SP ch1 (Lch) 24 VCCP1 Driver FET 1P 23 BCLK GNDP1 I2S/LJ/RJ LRCLK I/F Driver FET 1N BSP1N 22 C22 3.3 F SDATA R4 0 4 VSS 6 Audio DSP TEST1 5 VSS C6B R6 0.027 F 1.5k C6A 2700pF VSS SDATA PLL 8 Times OverSampling Digital Filter OUT1N PWM Modulator OUT2P Driver FET 2P PLL BSP2P 21 L21 10 H 20 L20 10 H C19 C20B 3.3 F 680pF 19 7 REG15 VSS GNDP2 Protection 8 LRCLK 18 Driver FET 2N 1 F VCCP2 TEST2 9 DVDD 10 VSS SDATAO R16 5.6 TEST3 SDATAO 11 DVDD(3.3V) MCU GNDP2 17 DGND BCLK C20A 0.33 F R20 5.6 C7 1 F C10 VSS VSS ERROR NC 13 14 12 BSP2N 15 0 R12 OUT2N 16 C16A 0.33 F C16B 680pF C15 3.3 F 10 H VCCP2 R13 DVDD100k SP ch2 (Rch) C17A 1 F L16 C17B 100 F ERROR GNDP2 Figure 70. BOM list1(Stereo BTL output, RL=8, Vcc=10V to 18V) Parts Qty Parts No. Description Company Product No. Inductor 4 L16, L20, L21, L25 R16, R20 R21, R25 R6 10H / (20%) / 7.6mmx7.6mm TOKO B1047AS-100M 4 1 Resistor MCR03EZPJ5R6 1.5k / 1/16W / F(1%) / 1.0mmx0.5mm 10k / 1/16W / J(5%) / 1.0mmx0.5mm MCR01MZPF1501 ROHM 2 R31, R32 4 R2, R3, R4, R12 0 / 1/10W / J(5%) / 1.6mmx0.8mm MCR03EZPJ000 1 R13 C16B, C20B C21B, C25B C6A 100k / 1/16W / J(5%) / 1.0mmx0.5mm MCR01MZPJ104 680pF / 50V / B(10% / 1.6mmx0.8mm GRM188B11H681KA01 2700pF / 6.3V / B(10% / 0.6mmx0.3mm GRM033B10J272KA01 0.027F / 6.3V / B(10% / 0.6mmx0.3mm GRM033B10J273KE01 4 1 1 4 Capacitor 5.6 / 1/10W / J(5%) / 1.6mmx0.8mm 2 4 2 C6B C16A, C20A, C21A, C25A, C17A, C24A (Note 1) C15, C19, C22, C26 C7, C10 0.33F / 50V / B(10% / 2.0mmx1.25mm MURATA MCR01MZPJ103 GRM219B31H334KA87 1F / 50V / B(10% / 2.0mmx1.25mm GRM21BB31H105KA12 3.3F / 16V / B(10% / 1.6mmx0.8mm GRM188B31A335KE15 1F / 10V / B(10% / 1.6mmx0.8mm GRM185B31A105KE25 1 C27 10F / 10V / B(10%) / 1.6mmx0.8mm 2 C17B, C24B 100F / 35V / (20%) / 6.3mmx11.2mm GRM188B31A106KE69 PANASONIC ECA1VMH101 (Note 1) Please put the C17A and C24A near the VCCP1 and VCCP2 pins on the board. www.rohm.com (c) 2013 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 62/75 TSZ02201-0C1C0E900060-1-2 10.Jun.2016 Rev.003 BM28720MUV Application Circuit Example2 (Monaural BTL output, RL=8, Vcc=10V to 18V) When using at Vcc>18V, fc of the LC filter should be lowered to about 60kHz and decrease the influence of LCR resonance using application circuit. Please refer 5) Output LC Filter Circuit (Vcc>18V) GNDP1 MCU C24A 1 F 32 10 F C27 31 30 2 LRCLK Digital Audio Source RSTX VSS BCLK R2 0 28 27 SDATA R4 0 4 VSS C6B R6 0.027 F 1.5k VSS C6A 2700pF VSS TEST1 6 PLL R21 5.6 GNDP1 C21A C21B 0.33 F 680pF SP ch1 (Lch) 23 Driver FET 1N 8 Times OverSampling Digital Filter Audio DSP C25A 0.33 F 24 GNDP1 SDATA R25 5.6 VCCP1 Driver FET 1P BCLK 5 C25B 680pF REG_G I2S/LJ/RJ 3 LRCLK I/F R3 0 L25 3.3 F C26 26 25 BSP1P OUT1P NC Control I/F 2 wire I/F ADDR 29 MUTEX SCL SDA DVDD 1 GNDP1 10k R31 10k R32 Slave Address Select RSTX MUTE SCL SDA DVDD DVDD C24B 100 F VCCP1 10 H BSP1N OUT1N PWM Modulator OUT2P Driver FET 2P PLL BSP2P 22 C22 3.3 F 21 L21 10 H 20 19 C7 REG15 7 VSS GNDP2 Protection 8 LRCLK 18 Driver FET 2N 1 F 17 VCCP2 DGND BCLK TEST2 DVDD 9 10 GNDP2 TEST3 SDATAO 11 DVDD(3.3V) VSS MCU SDATAO 1 F C10 VSS VSS ERROR NC 13 14 12 BSP2N 15 OUT2N 16 0 R12 R13 DVDD100k ERROR Figure 71. BOM list2(Monaural BTL output, RL=8, Vcc=10V to 18V) Parts Qty Inductor 2 2 1 R6 1.5k / 1/16W / F(1%) / 1.0mmx0.5mm 2 R31, R32 10k / 1/16W / J(5%) / 1.0mmx0.5mm 4 R2, R3, R4, R12 0 / 1/10W / J(5%) / 1.6mmx0.8mm Resister Capacitor Parts No. Description Company L21, L25 10H / (20%) / 7.6mmx7.6mm TOKO R21, R25 5.6 / 1/10W / J(5%) / 1.6mmx0.8mm Product No. B1047AS-100M MCR03EZPJ5R6 MCR01MZPF1501 ROHM MCR01MZPJ103 MCR03EZPJ000 1 R13 100k / 1/16W / J(5%) / 1.0mmx0.5mm MCR01MZPJ104 2 C21B, C25B 680pF / 50V / B(10% / 1.6mmx0.8mm GRM188B11H681KA01 1 C6A 2700pF / 6.3V / B(10% / 0.6mmx0.3mm GRM033B10J272KA01 1 C6B 0.027F / 6.3V / B(10% / 0.6mmx0.3mm GRM033B10J273KE01 2 C21A, C25A 0.33F / 50V / B(10% / 2.0mmx1.25mm GRM219B31H334KA87 1 C24A (Note 1) 1F / 50V / B(10% / 2.0mmx1.25mm 2 C22, C26 3.3F / 16V / B(10% / 1.6mmx0.8mm GRM188B31A335KE15 2 C7, C10 1F / 10V / B(10% / 1.6mmx0.8mm GRM185B31A105KE25 1 C27 10F / 10V / B(10%) / 1.6mmx0.8mm 1 C24B 100F / 35V / 20% / 6.3mmx11.2mm MURATA GRM21BB31H105KA12 GRM188B31A106KE69 PANASONIC ECA1VMH101 (Note 1) Please put the C24A near the VCCP1 pins on the board. www.rohm.com (c) 2013 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 63/75 TSZ02201-0C1C0E900060-1-2 10.Jun.2016 Rev.003 BM28720MUV Selection of Components Externally Connected (Vcc=10V to 18V) 1) Output LC Filter Circuit An output filter is required to eliminate radio-frequency components exceeding the audio-frequency region supplied to a load (speaker). Because this IC uses sampling clock frequency 384kHz(fs=48kHz) in the output PWM signals, the high-frequency components must be appropriately removed. This section takes an example of an LC type LPF shown below, in which coil L and capacitor C compose a differential filter with an attenuation property of -12dB/oct. A large part of switching currents flow to capacitor C, and only a small part of the currents flow to speaker RL1. This filter reduces unwanted emission this way. In addition, coil L and capacitor Cg composes a filter against in-phase components, reducing unwanted emission further. L OUTP Cg RL Cg OUTN L Figure 72. Following presents output LC filter constants with typical load impedances. RL L Cg 4 6 10H 10H 1F 0.47F 8 10H 0.33F Use coils with a low direct-current resistance and with a sufficient margin of allowable currents. A high direct-current resistance causes power losses. In addition, select a closed magnetic circuit type product in normal cases to prevent unwanted emission. Use capacitors with a low equivalent series resistance, and good impedance characteristics at high frequency ranges (100kHz or higher). Also, select an item with sufficient withstand voltage because flowing massive amount of high-frequency currents is expected. 2) The value of the LC filter circuit computed equation The output LC filter circuit of BM28720MUV is as it is shown in Figure 73. The LC filter circuit of Figure 73 is thought to substitute it like Figure 74 on the occasion of the computation of the value of the LC filter circuit. L OUT+ Cg OUT+ or OUT- R = 1 RL 2 L Cg Cg OUT- RL L Figure 73. Output LC filter 1 www.rohm.com (c) 2013 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 Figure 74. Output LC filter 2 64/75 TSZ02201-0C1C0E900060-1-2 10.Jun.2016 Rev.003 BM28720MUV The transfer function H(s) of the LC filter circuit of Figure 74 becomes the following. 1 LCg 2 H ( s) 1 1 s2 s s2 s 2 Cg R LCg Q The and Q become the followings here. 1 1 fC 2 2f C 2 LCg LCg Cg 1 Cg QR RL L 2 L Therefore, L and Cg become the followings. L RL 1 C g 4f C Q 2 Cg Q Q R f C R L The RL and L should be made known, and fc is set up, and Cg is decided. 3) The settlement of the L value of the coil For selection of the L value of a coil, please consider side effect as shown below. When L value was made small. (1) Circuit electric currents increase without a signal. And, efficiency in the low output gets bad. (2) Direct current resistance value is restrained small when the coil of other L value and size are made the same. Therefore, maximum output is easy to take out. And, it can be used in the low power supply voltage because DC electric current (allowable electric current) value can be taken greatly. When L value was made large. (1) Circuit electric current is restrained low without a signal. Efficiency in the low output improves. (2) Direct current resistance value grows big when the coil of other L value and size are made the same. Therefore, maximum output is hard to take out. And, because it becomes small, use becomes difficult the DC electric current (allowable electric current) value in the low power supply voltage, too. 4) The settlement of the fC As for the settlement of the fixed number of the LC filter circuit, it is taken into consideration about two points of the following, and set up. The PWM sampling frequency fPWM (=8fS) of BM28720MUV is set up in 384kHz (@fS=48kHz). It is set up with fC < fPWM to restrain career frequency omission after the LC filter circuit. When fc is lowered too much, the voltage profit of the voice obi stage (especially, the neighborhood of 20kHz) declines in the speaker output frequency character of the difference movement mode. And, the speaker output frequency character of the difference movement mode becomes the following. RL=8 Cg[F] fc[kHz] L[H] 0.1 75.32 0.40 0.15 80.85 0.49 0.22 86.79 0.59 10 0.33 89.92 0.73 0.47 86.79 0.87 1.0 69.01 1.26 0.1 46.99 0.33 0.15 49.66 0.40 0.22 53.46 0.48 15 0.33 57.54 0.59 0.47 59.7 0.71 1.0 52.75 1.03 0.1 30.76 0.27 0.15 31.92 0.33 0.22 33.73 0.40 22 0.33 36.31 0.49 0.47 39.08 0.58 1.0 39.30 0.85 5) Output LC Filter Circuit (Vcc>18V) L[H] www.rohm.com (c) 2013 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 Cg[F] 10 15 22 RL=6 fc[kHz] L[H] 0.1 51.01 0.15 54.76 0.22 56.73 0.33 63.1 0.47 66.68 1.0 62.29 0.1 33.11 0.15 34.36 0.22 35.65 0.33 38.37 0.47 41.3 1.0 44.67 0.1 22.49 0.15 22.91 0.22 23.77 0.33 24.66 0.47 26.06 1.0 30.05 65/75 Cg[F] 0.30 0.37 0.44 0.54 0.65 0.95 0.24 0.30 0.36 0.44 0.53 0.77 0.20 0.25 0.30 0.37 0.44 0.64 fc[kHz] 10 15 22 RL=4 L[H] Cg[F] 0.1 32.19 0.15 33.35 0.22 34.55 0.33 35.8 0.47 38.37 1.0 44.1 0.1 21.68 0.15 22.08 0.22 22.49 0.33 22.91 0.47 23.77 1.0 27.47 0.1 14.72 0.15 14.72 0.22 15 0.33 15.28 0.47 15.56 1.0 17.33 fc[kHz] 0.20 0.24 0.30 0.36 0.43 0.63 0.16 0.20 0.24 0.30 0.35 0.52 0.13 0.17 0.20 0.24 0.29 0.43 TSZ02201-0C1C0E900060-1-2 10.Jun.2016 Rev.003 BM28720MUV When using at Vcc>18V, fc of the LC filter should be lowered to about 60kHz or less and decrease the influence of LCR resonance using application circuit. RL1 L C 4 6 10H 15H 1F 0.47F 8 15H 22H 0.33F 0.47F Use coils with a low direct current resistance and with a sufficient margin of allowable currents. A high direct current resistance causes power losses. In addition, select a closed magnetic circuit type product in normal cases to prevent unwanted emission. Use capacitors with a low equivalent series resistance and good impedance characteristics at high frequency ranges (100kHz or higher). Also, select an item with sufficient voltage rating because massive amount of high frequency currents flow is expected. In addition, please do not place the CBTL shown in Figure 75. When considering only common mode signals, OUTP and OUTN are equal to each other and this circuit is equivalent to the circuit shown in Figure 76. Therefore, LC resonance may occur depending on the constant of a LC filter. L L OUTP OUTP Csnb Rsnb Rsnb Cg CBTL Rsnb RL Cg Csnb OUTN L Figure 78. www.rohm.com (c) 2013 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 Cg Rsnb CBTL Csnb OUTN Csnb Cg RL L Figure 79. 66/75 TSZ02201-0C1C0E900060-1-2 10.Jun.2016 Rev.003 BM28720MUV 6) The settlement of the snubber The snubber circuit must be optimized for application circuit to reduce the overshoot and undershoot of output PWM. Measure the ringing resonance frequency f1 of the PWM output wave shape (When it stands up.) by using FET probe in the OUT terminal. (Figure 77) The FET probe is to monitor very near pin and shorten ground lead at the time of that. Measure resonance frequency f2 of the ringing as a snubber circuit fixed number R=0. (Only with connecting the capacitor C to GND) At this time, the value of the capacitor C is adjusted until it becomes half of the frequency (2f2=f1) of the resonance frequency f1 of . The value of C which it could get here is three times of the parasitic capacity Cp that a ringing is formed. (C=3Cp) Parasitic inductance Lp is looked for at the next formula. Lp 1 2f1 2 C p The character impedance Z of resonance is looked for from the parasitic capacity Cp and the parasitism inductance Lp at the next formula. Z Lp Cp A snubber circuit fixed number R is set up in the value which is the same as the character impedance Z. A snubber circuit fixed number C is set up in the value of 4-10 times of the parasitic capacity Cp. (C=4Cp to 10Cp) Decide it with trade-off with the character because switching electric currents increase when the value of C is enlarged too much. VCCP Snubber Ringing resonance frequency LC filter Driver OUT Csnb Cg Rsnb 5ns/div GNDP Figure 78. Snubber schematic Figure 77. PWM Output waveform (Measure of ringing resonance frequency Following presents snubber filter constants with the recommendation value at ROHM 4 layer board. RL 4 Csnb 680pF ~ 1200pF, 50V B(10%) Rsnb 5.6, 1/10W J(5%) 6 8 680pF ~ 1200pF, 50V B(10%) 680pF ~ 1200pF, 50V B(10%) 5.6, 1/10W J(5%) 5.6, 1/10W J(5%) 7) Operating condition with the application component Parameter Capacitor for BSP Parts No. C15, C19, C22, C26 Limit Min Typ 2.0 (Note 1) 2.0 (Note 1) 3.3 4.7 Max 4.5 (Note 2) 6.3 (Note 2) Unit Min F F Conditions Recommend characteristics, 16V ceramic type capacitor (Note1) Capacitor value should not be less than a minimum in consideration of temperature characteristics and dc-bias characteristics. (Note2) It is value in consideration of +/-10% of capacity unevenness, capacity rate of change 22%. Please use the capacitor within this limit. www.rohm.com (c) 2013 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 67/75 TSZ02201-0C1C0E900060-1-2 10.Jun.2016 Rev.003 BM28720MUV Level Diagram of Audio Signal 2 Level diagram of audio signal is shown the below figure. Speaker output level is depended on I S digital audio input level, DSP gain, PWM gain, BTL gain and Loss of power stage and low pass filter. I2S input level is full-scale signal, the supply voltage of the block is DVDD, and therefore, 0dBFS is equal to DVDD voltage [Vpp]. DSP gain is set by 2 wire control variably, and -0.3dB is set at PWM Modulator block usually. At the Power stage, the PWM Modulator output is shifted PWM signal level from DVDD to VCC, and added loss of the output transistor resistance rDS and DC resistance of coil rDC. (2) PWM Gain (1) DSP Gain 10 GD - 0.3 ( ) 20 VCC 2 2 I2S Input Level 10 ( 3.3V PWM signal VIN ) 20 (3) Loss of rDS and rDC RL 2( rDS rDC ) RL 1024V PWM signal SDATA LRCLK 24 I2S-IF BCLK 24 24 Sync. SRC Audio DSP 24 24 x8 over Sampling DF 24 24 PWM Modulator 24 Power Stage (4) BTL Gain (x2) Output LPF Output LPF L+ LR+ R- Figure 79. Level Diagram of Audio Signal VCC VCC ON rDS rDC OFF rDC RL OFF Cg Cg ON rDS Figure 80. Output LPF circuit In Bridge-Tied-Load (BTL) connection, the following formula gives an approximate value of output power Po at non-clipping output waveform: I2S Input Level VIN (10 PO 20 DSP Gain 10GD0.3 20 PWM Gain BTL Gain 2 Loss of rDS and rDC VCC RL 2 )2 2 (rDS rDC ) RL 2 2 RL VIN : I S Input level [dBFS] GD : DSP gain [dB] VCC : Power supply voltage of Power stage [V] DVDD : Power supply voltage of DSP block [V] RL : Load impedance [] rDS : Turn-on resistance of output MOS Tr. [] (typ.=160m) rDC : DC resistance of output LPF coil [] If the circuit is driven further until an output waveform is clipped, an output power higher than that without distortion is obtained. In general a clipped output is quantified where "THD+N = 1% and 10%," and a maximum output power under that status is calculated by the following formula: (10 ( -0.3 20) PO (1%) RL VCC )2 2(rDS rDC) RL 2 [W ] RL PO( 10 %) =PO( 1%)x1.25 [W] www.rohm.com (c) 2013 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 68/75 TSZ02201-0C1C0E900060-1-2 10.Jun.2016 Rev.003 BM28720MUV Power Dissipation 5.00 VQFN032V5050 PCB 4.56W 4.50 4.00 3.50 PCB 3.26W Pd [W] 3.00 2.50 2.00 1.50 1.00 0.50 0.00 0 25 50 75 100 125 150 Ta [] Figure 81. Allowable Power Dissipation Measuring instrumentTH-156(Shibukawa Kuwano Electrical Instruments Co, Ltd.) Measuring conditionsInstallation on ROHM's board Board size74.2mmx74.2mmx1.6mm(with thermal via on board) MaterialFR4 The board on exposed heat sink on the back of package are connected by soldering. 2 PCB14- layer board (Top and bottom layer back copper foil size: 20.2mm , 2nd and 3rd layer 2 back copper foil size: 5505mm ) , ja = 38.3C/W 2 PCB24-layer board(back copper foil size: 5505mm ), ja = 27.4C/W Use a thermal design that allows for a sufficient margin in light of the power dissipation (Pd) in actual operating conditions. This IC exposes its frame of the backside of package. Note that this part is assumed to use after providing heat dissipation treatment to improve heat dissipation efficiency. Try to occupy as wide as possible with heat dissipation pattern not only on the board surface but also the backside. Class D speaker amplifier is high efficiency and low heat generation by comparison with conventional Analog power amplifier. However, In case it is operated continuously by maximum output power, Power dissipation (Pdiss) may exceed package dissipation. Please consider about heat design that Power dissipation (Pdiss) does not exceed Package dissipation (Pd) in average power (Poav). (Tjmax Maximum junction temperature=150C, Ta Peripheral temperature[C], ja Thermal resistance of package[C/W], PoavAverage power[W], Efficiency) Package dissipation : Pd(W)=(Tjmax - Ta)ja Power dissipation : Pdiss(W)= Poav x(1- 1) www.rohm.com (c) 2013 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 69/75 TSZ02201-0C1C0E900060-1-2 10.Jun.2016 Rev.003 BM28720MUV I/O equivalence circuit (Provided pin voltages are typ. Values) Pin No. 29 30 Pin name RSTX MUTEX Pin voltage 0V 0V Pin explanation Internal equivalence circuit Reset pin for digital circuit High : Reset OFF Low : Reset ON 10 29,30 Speaker output mute control pin High : Mute OFF Low : Mute ON 8 DGND 0V GND pin for Digital I/O 31 SCL 2 wire Bus control transmit clock input pin Please notice. Absolute Maximum Voltage is 4.5V. 8 31 8 32 SDA 2 wire Bus control data input/output pin Please notice. Absolute Maximum Voltage is 4.5V. 32 8 1 ADDR 0V 2 wire Bus control Slave address select pin Select LSB data of slave address for 2 wire Bus control. 10 1 8 2 BCLK 3.3V Digital sound bit clock input pin Input bit clock of digital audio signal. 10 2 8 4 3 SDATA LRCLK 3.3V Digital sound signal input pin Input LR clock of digital audio signal to LRCLK terminal. Input data of digital audio signal to SDATA terminal. 10 3,4 8 12 SDATAO 3.3V Digital sound signal output pin Output data of digital audio signal. 10 12 8 www.rohm.com (c) 2013 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 70/75 TSZ02201-0C1C0E900060-1-2 10.Jun.2016 Rev.003 BM28720MUV I/O equivalence circuit (Provided pin voltages are typ. Values) Pin No. 6 Pin name PLL Pin voltage 1V Pin explanation PLL's filter pin Connect filter circuit for PLL. Internal equivalence circuit 10 6 8 10 DVDD 3.3V 5 9 11 TEST1 TEST2 TEST3 Power supply pin for Digital I/O. Test pin Connect VSS. 10 5,9,11 8 7 REG15 1.5V Internal power supply pin for Digital circuit Connect capacitor. 10 7 8 13 ERROR 3.3V Error flag pin H: Normal operation L: Error 500 13 8 14 28 NC www.rohm.com (c) 2013 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 No connection Pin 71/75 TSZ02201-0C1C0E900060-1-2 10.Jun.2016 Rev.003 BM28720MUV I/O equivalence circuit (Provided pin voltages are typ. Values) Pin No. 17 VCCP2 VCC 20 OUT2P VCC to 0V 19 BSP2P 18 GNDP2 0V Output pin of ch2 positive PWM Connect output LPF. Boot-strap pin of ch2 positive Connect capacitor. GND pin for ch2 PWM signal 16 OUT2N VCC to 0V Output pin of ch2 negative PWM 15 BSP2N 22 BSP1N 21 OUT1N VCC to 0V 23 GNDP1 0V 26 BSP1P 25 OUT1P VCC to 0V 24 VCCP1 VCC Pin name Pin voltage Pin explanation Internal equivalence circuit Power supply pin for ch2 PWM signal Please connect to Output LPF. Boot-strap pin of ch2 negative Connect capacitor. Boot-strap pin of ch1 negative Connect capacitor. Output pin of ch1 negative PWM Connect output LPF. GND pin for ch1 PWM signal Boot-strap pin of ch1 positive Connect capacitor. Output pin of ch1 positive PWM Connect output LPF. Power supply pin for ch1 PWM signal 17 15, 19 16, 20 18 24 22, 26 21, 25 23 27 REG_G 5.7V Internal power supply pin for gate driver Connect capacitor. 24 27 370K 23 www.rohm.com (c) 2013 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 72/75 TSZ02201-0C1C0E900060-1-2 10.Jun.2016 Rev.003 BM28720MUV Operational Notes 1 ) Absolute maximum ratings Use of the IC in excess of absolute maximum ratings such as the applied voltage or operating temperature range may result in IC damage. Assumptions should not be made regarding the state of the IC (short mode or open mode) when such damage is suffered. A physical safety measure such as a fuse should be implemented when use of the IC in a special mode where the absolute maximum ratings may be exceeded is anticipated. 2 ) Power supply lines As return of current regenerated by back EMF of output coil happens, take steps such as putting capacitor between power supply and GND as an electric pathway for the regenerated current. Be sure that there is no problem with each property such as emptied capacity at lower temperature regarding electrolytic capacitor to decide capacity value. If the connected power supply does not have sufficient current absorption capacity, regenerative current will cause the voltage on the power supply line to rise, which combined with the product and its peripheral circuitry may exceed the absolute maximum ratings. It is recommended to implement a physical safety measure such as the insertion of a voltage clamp diode between the power supply and GND pins. 3 ) GND potential (Pin 8, 18, 23) Any state must become the lowest voltage about DGND, GNDP1 and GNDP2 terminal. 4 ) Input terminal The parasitic elements are formed in the IC because of the voltage relation. The parasitic element operating causes the wrong operation and destruction. Therefore, please be careful so as not to operate the parasitic elements by impressing to input terminals lower voltage than DGND and VSS. Please do not apply the voltage to the input terminal when the power-supply voltage is not impressed. 5 ) Actions in strong magnetic field Use caution when using the IC in the presence of a strong magnetic field as doing so may cause the IC to malfunction. 6 ) Thermal shutdown circuit This product is provided with a built-in thermal shutdown circuit. When the thermal shutdown circuit operates, the output transistors are placed under open status. The thermal shutdown circuit is primarily intended to shut down the IC avoiding thermal runaway under abnormal conditions with a chip temperature exceeding Tjmax = 150. 7 ) Shorts between pins and miss-installation When mounting the IC on a board, pay adequate attention to orientation and placement discrepancies of the IC. If it is miss-installed and the power is turned on, the IC may be damaged. It also may be damaged if it is shorted by a foreign substance coming between pins of the IC or between a pin and a power supply or a pin and a GND. 8 ) Power supply on/off (Pin 10, 17, 24) In case power supply is started up, RSTX(Pin 29) and MUTEX(Pin 30) always should be set Low. And in case power supply is shut down, it should be set Low likewise. Then it is possible to eliminate pop noise when power supply is turned on/off. And also, all power supply terminals should start up and shut down together. 9 ) ERROR terminal (Pin 13) An error flag is outputted when Output short protection or DC voltage protection. This flag is the function which the condition of this product is shown in. 10 ) N.C. terminal (Pin 14, 28) N.C. terminal (Non Connection Pin) does not connect to the inside circuit. Therefore, possible to use open. 11 ) TEST terminal (Pin 5, 9, 11) TEST terminal connects with ground to prevent the malfunction by external noise. 12 ) Precautions for Speaker-setting If the impedance characteristics of the speakers at high-frequency range while increase rapidly, the IC might not have stable-operation in the resonance frequency range of the LC-filter. Therefore, consider adding damping-circuit, etc., depending on the impedance of the speaker. 13 ) External capacitor In order to use a ceramic capacitor as the external capacitor, determine the constant with consideration given to a degradation in the nominal capacitance due to DC bias and changes in the capacitance due to temperature, etc. 14 ) About the rush current For ICs with more than one power supply, it is possible that rush current may flow instantaneously due to the internal powering sequence and delays. Therefore, give special consideration to power coupling capacitance, power wiring, width of GND wiring, and routing of wiring. Status of this document The Japanese version of this document is formal specification. A customer may use this translation version only for a reference to help reading the formal version. If there are any differences in translation version of this document formal version takes priority www.rohm.com (c) 2013 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 73/75 TSZ02201-0C1C0E900060-1-2 10.Jun.2016 Rev.003 BM28720MUV Ordering Information B M 2 8 7 2 0 M U V - Package MUV: VQFN032V5050 E2 Packaging and forming specification E2: Embossed tape and reel Physical Dimensions Tape and Reel Information Marking Diagram VQFN032V5050 (TOP VIEW) Part Number Marking M 2 8 7 2 0 LOT Number 1PIN MARK Figure 82. www.rohm.com (c) 2013 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 74/75 TSZ02201-0C1C0E900060-1-2 10.Jun.2016 Rev.003 BM28720MUV Revision History Date Revision 21.Oct.2013 001 10.Dec.2013 002 10.Jun.2016 003 Changes First version Corrected (P.2) Corrected performance curves (P.5-7) Modified recommend constant (P.63-64, 67, 68) Deleted application circuit (P.63-64) Modify electric characteristics, condition, explanation of command Correction of errors Modify power up sequence(P.22) Modify procedure for power up(P.59) www.rohm.com (c) 2013 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 75/75 TSZ02201-0C1C0E900060-1-2 10.Jun.2016 Rev.003 Notice Precaution on using ROHM Products 1. Our Products are designed and manufactured for application in ordinary electronic equipments (such as AV equipment, OA equipment, telecommunication equipment, home electronic appliances, amusement equipment, etc.). If you (Note 1) intend to use our Products in devices requiring extremely high reliability (such as medical equipment , transport equipment, traffic equipment, aircraft/spacecraft, nuclear power controllers, fuel controllers, car equipment including car accessories, safety devices, etc.) and whose malfunction or failure may cause loss of human life, bodily injury or serious damage to property ("Specific Applications"), please consult with the ROHM sales representative in advance. Unless otherwise agreed in writing by ROHM in advance, ROHM shall not be in any way responsible or liable for any damages, expenses or losses incurred by you or third parties arising from the use of any ROHM's Products for Specific Applications. (Note1) Medical Equipment Classification of the Specific Applications JAPAN USA EU CHINA CLASS CLASSb CLASS CLASS CLASS CLASS 2. ROHM designs and manufactures its Products subject to strict quality control system. However, semiconductor products can fail or malfunction at a certain rate. Please be sure to implement, at your own responsibilities, adequate safety measures including but not limited to fail-safe design against the physical injury, damage to any property, which a failure or malfunction of our Products may cause. The following are examples of safety measures: [a] Installation of protection circuits or other protective devices to improve system safety [b] Installation of redundant circuits to reduce the impact of single or multiple circuit failure 3. Our Products are designed and manufactured for use under standard conditions and not under any special or extraordinary environments or conditions, as exemplified below. Accordingly, ROHM shall not be in any way responsible or liable for any damages, expenses or losses arising from the use of any ROHM's Products under any special or extraordinary environments or conditions. If you intend to use our Products under any special or extraordinary environments or conditions (as exemplified below), your independent verification and confirmation of product performance, reliability, etc, prior to use, must be necessary: [a] Use of our Products in any types of liquid, including water, oils, chemicals, and organic solvents [b] Use of our Products outdoors or in places where the Products are exposed to direct sunlight or dust [c] Use of our Products in places where the Products are exposed to sea wind or corrosive gases, including Cl2, H2S, NH3, SO2, and NO2 [d] Use of our Products in places where the Products are exposed to static electricity or electromagnetic waves [e] Use of our Products in proximity to heat-producing components, plastic cords, or other flammable items [f] Sealing or coating our Products with resin or other coating materials [g] Use of our Products without cleaning residue of flux (even if you use no-clean type fluxes, cleaning residue of flux is recommended); or Washing our Products by using water or water-soluble cleaning agents for cleaning residue after soldering [h] Use of the Products in places subject to dew condensation 4. The Products are not subject to radiation-proof design. 5. Please verify and confirm characteristics of the final or mounted products in using the Products. 6. In particular, if a transient load (a large amount of load applied in a short period of time, such as pulse. is applied, confirmation of performance characteristics after on-board mounting is strongly recommended. Avoid applying power exceeding normal rated power; exceeding the power rating under steady-state loading condition may negatively affect product performance and reliability. 7. De-rate Power Dissipation depending on ambient temperature. When used in sealed area, confirm that it is the use in the range that does not exceed the maximum junction temperature. 8. Confirm that operation temperature is within the specified range described in the product specification. 9. ROHM shall not be in any way responsible or liable for failure induced under deviant condition from what is defined in this document. Precaution for Mounting / Circuit board design 1. When a highly active halogenous (chlorine, bromine, etc.) flux is used, the residue of flux may negatively affect product performance and reliability. 2. In principle, the reflow soldering method must be used on a surface-mount products, the flow soldering method must be used on a through hole mount products. If the flow soldering method is preferred on a surface-mount products, please consult with the ROHM representative in advance. For details, please refer to ROHM Mounting specification Notice-PGA-E (c) 2015 ROHM Co., Ltd. All rights reserved. Rev.003 Precautions Regarding Application Examples and External Circuits 1. If change is made to the constant of an external circuit, please allow a sufficient margin considering variations of the characteristics of the Products and external components, including transient characteristics, as well as static characteristics. 2. You agree that application notes, reference designs, and associated data and information contained in this document are presented only as guidance for Products use. Therefore, in case you use such information, you are solely responsible for it and you must exercise your own independent verification and judgment in the use of such information contained in this document. ROHM shall not be in any way responsible or liable for any damages, expenses or losses incurred by you or third parties arising from the use of such information. Precaution for Electrostatic This Product is electrostatic sensitive product, which may be damaged due to electrostatic discharge. Please take proper caution in your manufacturing process and storage so that voltage exceeding the Products maximum rating will not be applied to Products. Please take special care under dry condition (e.g. Grounding of human body / equipment / solder iron, isolation from charged objects, setting of Ionizer, friction prevention and temperature / humidity control). Precaution for Storage / Transportation 1. Product performance and soldered connections may deteriorate if the Products are stored in the places where: [a] the Products are exposed to sea winds or corrosive gases, including Cl2, H2S, NH3, SO2, and NO2 [b] the temperature or humidity exceeds those recommended by ROHM [c] the Products are exposed to direct sunshine or condensation [d] the Products are exposed to high Electrostatic 2. Even under ROHM recommended storage condition, solderability of products out of recommended storage time period may be degraded. It is strongly recommended to confirm solderability before using Products of which storage time is exceeding the recommended storage time period. 3. Store / transport cartons in the correct direction, which is indicated on a carton with a symbol. Otherwise bent leads may occur due to excessive stress applied when dropping of a carton. 4. Use Products within the specified time after opening a humidity barrier bag. Baking is required before using Products of which storage time is exceeding the recommended storage time period. Precaution for Product Label A two-dimensional barcode printed on ROHM Products label is for ROHM's internal use only. Precaution for Disposition When disposing Products please dispose them properly using an authorized industry waste company. Precaution for Foreign Exchange and Foreign Trade act Since concerned goods might be fallen under listed items of export control prescribed by Foreign exchange and Foreign trade act, please consult with ROHM in case of export. Precaution Regarding Intellectual Property Rights 1. All information and data including but not limited to application example contained in this document is for reference only. ROHM does not warrant that foregoing information or data will not infringe any intellectual property rights or any other rights of any third party regarding such information or data. 2. ROHM shall not have any obligations where the claims, actions or demands arising from the combination of the Products with other articles such as components, circuits, systems or external equipment (including software). 3. No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of ROHM or any third parties with respect to the Products or the information contained in this document. Provided, however, that ROHM will not assert its intellectual property rights or other rights against you or your customers to the extent necessary to manufacture or sell products containing the Products, subject to the terms and conditions herein. Other Precaution 1. This document may not be reprinted or reproduced, in whole or in part, without prior written consent of ROHM. 2. The Products may not be disassembled, converted, modified, reproduced or otherwise changed without prior written consent of ROHM. 3. In no event shall you use in any way whatsoever the Products and the related technical information contained in the Products or this document for any military purposes, including but not limited to, the development of mass-destruction weapons. 4. The proper names of companies or products described in this document are trademarks or registered trademarks of ROHM, its affiliated companies or third parties. Notice-PGA-E (c) 2015 ROHM Co., Ltd. All rights reserved. Rev.003 Datasheet General Precaution 1. Before you use our Pro ducts, you are requested to care fully read this document and fully understand its contents. ROHM shall n ot be in an y way responsible or liabl e for fa ilure, malfunction or acci dent arising from the use of a ny ROHM's Products against warning, caution or note contained in this document. 2. All information contained in this docume nt is current as of the issuing date and subj ect to change without any prior notice. Before purchasing or using ROHM's Products, please confirm the la test information with a ROHM sale s representative. 3. The information contained in this doc ument is provi ded on an "as is" basis and ROHM does not warrant that all information contained in this document is accurate an d/or error-free. ROHM shall not be in an y way responsible or liable for an y damages, expenses or losses incurred b y you or third parties resulting from inaccur acy or errors of or concerning such information. Notice - WE (c) 2015 ROHM Co., Ltd. All rights reserved. Rev.001 Datasheet bm28720muv - Web Page Part Number Package Unit Quantity Minimum Package Quantity Packing Type Constitution Materials List RoHS bm28720muv VQFN032V5050 2500 2500 Taping inquiry Yes