ISL80121-5
9FN7713.6
March 21, 2016
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External Capacitor Requirements
External capacitors are required for proper operation. Careful
attention must be paid to the layout guidelines and selection of
capacitor type and value to ensure optimal performance.
OUTPUT CAPACITOR
The ISL80121-5 applies state-of-the-art internal compensation to
keep the selection of the output capacitor simple for the
customer. Stable operation over full temperature, VIN range,
VOUT range and load extremes are guaranteed for all capacitor
types and values assuming a minimum of 10µF X5R/X7R is used
for local bypass on VOUT. This output capacitor must be
connected to the VOUT and GND pins of the LDO with PCB traces
no longer than 0.5cm.
There is a growing trend to use very low ESR multilayer ceramic
capacitors (MLCC) because they can support fast load transients
and also bypass very high frequency noise from other sources.
However, the effective capacitance of MLCCs drops with applied
voltage, age and temperature. X7R and X5R dieletric ceramic
capacitors are strongly recommended as they typically maintain
a capacitance range within ±20% of nominal voltage over full
operating ratings of temperature and voltage.
Additional capacitors of any value in ceramic, POSCAP,
alum/tantalum electrolytic types may be placed in parallel to
improve PSRR at higher frequencies and/or load transient AC
output voltage tolerances.
INPUT CAPACITOR
For proper operation, a minimum capacitance of 10µF X5R/X7R
is required at the input. This ceramic input capacitor must be
connected to the VIN and GND pins of the LDO with PCB traces no
longer than 0.5cm.
Power Dissipation and Thermals
The junction temperature must not exceed the range specified in
the “Recommended Operating Conditions (Note 7)” on page 4.
The power dissipation can be calculated by using Equation 5:
The maximum allowable junction temperature, TJ(MAX) and the
maximum expected ambient temperature, TA(MAX) determine the
maximum allowable power dissipation, as shown in Equation 6:
JA is the junction-to-ambient thermal resistance.
For safe operation, ensure that the power dissipation PD,
calculated from Equation 5, is less than the maximum allowable
power dissipation PD (MAX).
The DFN package uses the copper area on the PCB as a heatsink.
The EPAD of this package must be soldered to the copper plane
(GND plane). Figure 15 shows a curve for the JA of the DFN
package for different copper area sizes.
Thermal Fault Protection
The power level and the thermal impedance of the package
(+48°C/W for DFN) determine when the junction temperature
exceeds the thermal shutdown temperature. In the event that the
die temperature exceeds around +160°C, the output of the LDO
will shut down until the die temperature cools down to about
+130°C.
General Power PAD Design Considerations
Figure 16 shows the recommended use of vias on the thermal
pad to remove heat from the IC. This typical array populates the
thermal pad footprint with vias spaced three times the radius
distance from the center of each via. Small via size is advisable,
but not to the extent that solder reflow becomes difficult.
All vias should be connected to the pad potential, with low
thermal resistance for efficient heat transfer. Complete
connection of the plated through-hole to each plane is important.
It is not recommended to use “thermal relief” patterns to connect
the vias.
PDVIN VOUT
–IOUT VIN IGND
+=(EQ. 5)
PDMAX
TJMAX
TA
–
JA
=(EQ. 6)
FIGURE 15. 3mmx3mm 10 LD DFN ON 4-LAYER PCB WITH THERMAL
VIAS JA vs EPAD-MOUNT COPPER LAND AREA ON PCB
46
44
42
40
38
36
34
JA (°C/W)
2 4 6 8 10 12 14 16 18 20 22 24
EPAD-MOUNT COPPER LAND AREA ON PCB, mm2
FIGURE 16. PCB VIA PATTERN