QP27C256 & QP27C256L
June 18, 2009
2945 Oakmead Village Ct, Santa Clara, CA 95051 • Phone: (408) 737-0992 • Fax: (408) 736—8708 • Internet: www.qpsemi.com
QP27C256 – 256 Kilobit (32K x 8) CMOS EPROM
General Description
The QP27C256 is a 32Kx8 (256-Kbit), UV erasable programmable read-only memory. It operates from a single +5 V
supply, has a static standby mode, and features fast single address location programming. The QP27C256 meets the
same specification requirements and utilizes the same programming methodology as the AMD 27C256 that it replaces.
Products are available in windowed and non-windowed (OTP) ceramic hermetic packages.
Data is typically accessed in less than 55 ns, allowing high-performance microprocessors to operate without any WAIT
states. The device offers separate Output Enable ( OE ) and Chip Enable ( CE ) pins, eliminating bus contention in a
multiple bus system.
Typical power consumption is only 80 mW in active mode, and 100 μW in standby mode.
All signals are TTL levels, including programming signals. Bit locations may be programmed singly, in blocks, or at
random. The device is programmed identically to the AMD27C256 device that it replaces, using the same programming
algorithm (100 us pulses).
The QP27C256 features:
- Same programming algorithm as the AMD27C256, allowing it to be programmed using the same equipment,
data and algorithm. When programming this device select AMD as the manufacturer and 27C256 as the device
type.
- Speed options as fast as 55ns
- JEDEC Pinout
- Single +5V power supply
- CMOS and TTL input/output compatibility
- Two line control functions
- Programming time typically 4 seconds.
The device/family is constructed using an advanced UV CMOS wafer fabrication process.
Block Diagram
QP27C256 & QP27C256L
QP SEMI, 2945 Oakmead Village Court, Santa Clara, CA 95051 Page 2 of 13
Pin Name Function
A0 – A14 Address Inputs
CE (E) Chip Enable Input
DQ0 – DQ7 Data Input/Output
OE (G) Output Enable Input
PGM (P) Program Enable Input
VCC V
CC Supply Voltage
VPP Program Voltage Input
Vss Ground
NC No Connection
Connection Diagrams
CERDIP / CERPACK LCC
Device Type
Functional Description
Device Erasure
In order to clear all locations of their programmed contents, the device must be exposed to an ultraviolet light source. A
dosage of 15 W seconds/cm2 is required to completely erase the device. This dosage can be obtained by exposure to
an ultraviolet lamp with a wavelength of 2537Å and an intensity of 12,000 μW/cm2 for 15 to 20 minutes. The device
should be directly under and about one inch from the source, and all filters should be removed from the UV light source
prior to erasure.
Note that all UV erasable devices will erase with light sources having wavelengths shorter than 4000Å, such as
fluorescent light and sunlight. Although the erasure process happens over a much longer time period, exposure to any
light source should be prevented for maximum system reliability. Simply cover the package window with an opaque
label or substance.
Device Programming
QP27C256 & QP27C256L
QP SEMI, 2945 Oakmead Village Court, Santa Clara, CA 95051 Page 3 of 13
Upon delivery, or after each erasure, the device has all of its bits in the “ONE”, or HIGH state. “ZEROs” are loaded into
the device through the programming procedure.
The device enters the programming mode when 12.75V ± 0.25V is applied to the VPP pin, and both OE is at VIH & CE
are at VIL.
For programming, the data to be programmed is applied 8 bits in parallel to the data pins.
The programming algorithm uses a 100 μs programming pulse and gives each address only as many pulses as needed
to reliably program the data. After each pulse is applied to a given address, the data in that address is verified. If the
data does not verify, additional pulses are given until it verifies or the maximum pulses allowed is reached. This process
is repeated while sequencing through each address of the device. This part of the algorithm is done with VCC = 6.25 V to
assure that each bit is programmed to a sufficiently high threshold voltage. After the final address is completed, the
entire EPROM memory is verified at VCC = VPP = 5.25 V.
Program Inhibit
Programming different data to multiple devices in parallel is easily accomplished. Except for CE , all like inputs of the
devices may be common. A TTL low-level program pulse applied to one device’s CE input with VPP = 12.75 V ± 0.25 V
and OE HIGH will program that particular device. A high-level CE input inhibits the other devices from being
programmed.
Program Verify
Verification should be performed on the programmed bits to determine that they were correctly programmed. Verify
should be performed with OE at VIL, CE at VIH and VPP between 12.5 V and 13.0 V.
Autoselect Mode
The autoselect mode provides manufacturer and device identification through identifier codes on DQ0–DQ7. This mode
is primarily intended for programming equipment to automatically match a device to be programmed with its
corresponding programming algorithm. This mode is functional in the 25°C ± 5°C ambient temperature range that is
required when programming the device. To activate this mode, the programming equipment must force VH on address
line A9. Two identifier bytes may then be sequenced from the device outputs by toggling address line A0 from VIL to VIH
(that is, changing the address from 00h to 01h). All other address lines must be held at VIL during the autoselect mode.
Byte 0 (A0 = VIL) represents the manufacturer code, and Byte 1 (A0 = VIH), the device identifier code. Both codes have
odd parity, with DQ7 as the parity bit.
Read Mode
To obtain data at the device outputs, Chip Enable ( CE ) and Output Enable ( OE ) must be driven low. CE controls the
power to the device and is typically used to select the device. OE enables the device to output data, independent of
device selection. Addresses must be stable for at least tACC–tOE.
Standby Mode
The device enters the CMOS standby mode when CE is at VCC ± 0.3 V. Maximum VCC current is reduced to 100 μA.
The device enters the TTL-standby mode when CE is at VIH. Maximum VCC current is reduced to 1.0 mA. When in
either standby mode, the device places its outputs in a high-impedance state, independent of the OE input.
Output OR Connection
To accommodate multiple memory connections, a two-line control function provides:
• Low memory power dissipation
• Assurance that output bus contention will not occur.
CE should be decoded and used as the primary device selecting function, while OE be made a common connection
to all devices in the array and connected to the READ line from the system control bus. This assures that all deselected
memory devices are in their low-power standby mode and that the output pins are only active when data is desired from
a particular memory device.
System Applications
During the switch between active and standby conditions, transient current peaks are produced on the rising and falling
edges of Chip Enable. The magnitude of these transient current peaks is dependent on the output capacitance loading
of the device. As a minimum, a 0.1μF ceramic capacitor (high frequency, low inductance) should be used on each
device between VCC and VSS to minimize transient effects. In addition, to overcome the voltage drop caused by the
inductive effects of the printed circuit board traces on EPROM arrays, a 4.7μF bulk electrolytic capacitor should be used
QP27C256 & QP27C256L
QP SEMI, 2945 Oakmead Village Court, Santa Clara, CA 95051 Page 4 of 13
between VCC and VSS for each eight devices. The location of the capacitor should be close to where the power supply is
connected to the array.
MODE Select Table
Mode CE OE A0 A9 VPP Outputs Notes
Read VIL V
IL X X X DOUT \1
Output Disable X VIH X X X High Z \1
Standby (TTL) VIH X X X X High Z \1
Standby (CMOS) VCC±0.3V X X X X High Z \1
Program VIL V
IH X X VPP DIN \1
Program Verify VIH V
IL X X VPP DOUT \1
Program Inhibit VIH V
IH X X VPP High Z \1
Manufacturer Code VIL V
IL V
IL V
H X 01h \1 \2 \3 \4
Device Code VIL V
IL V
IH V
H X 10h \1 \2 \3 \4
Notes:
\1 X = Either VIH or VIL
\2 VH = 12.0V ± 0.5V
\3 A1-A8 & A10-A14 = VIL
\4 Device Manufacture Code and Device ID match original AMD device for programming compatibility
Absolute Maximum Ratings
Stresses above the AMR may cause permanent damage, extended operation at AMR may degrade performance and affect reliability
Condition Units Notes
Power Supply (VCC) -0.6 to +7.0 Volts DC
Voltage with Respect to VSS
All pins except A9, VPP, VCC -0.6 to VCC+0.6 Volts \5 \9
A
9 and VPP -0.6 to 13.5 Volts \6 \9
Storage Temperature Range -65 to +150 ºC \7
Lead Temperature (soldering, 10 seconds) +300 ºC
Junction Temperature (TJ) +150 ºC \7
Maximum Operating Temperature
Commercial Devices 0 to 70 ºC \7 \8
Industrial Devices -40 to 85 ºC \7 \8
Military Temperature Range -55 to 125 ºC \7 \8
Data Retention 10 Years, minimum
Device must not be removed from or inserted into a socket when VCC or VPP is applied.
Recommended Operating Conditions
Condition Units Notes
Supply Voltage Range (VCC) 4.5 to 5.5 Volts DC
Input or Output Voltage Range 0.0 to VCC Volts DC \5 \6
Minimum High-Level Input Voltage (VIH) 2.0 Volts DC
Maximum Low-Level Input Voltage (VIL) 0.8 Volts DC
Case Operating Range (Tc)
Commercial Devices 0 to 70 ºC \7 \8
Industrial Devices -40 to 85 ºC \7 \8
Military Temperature Range -55 to 125 ºC \7 \8
QP27C256 & QP27C256L
QP SEMI, 2945 Oakmead Village Court, Santa Clara, CA 95051 Page 5 of 13
\5 – Minimum DC Input Voltage on input or I/O pins –0.5V. During voltage transitions, the input may overshoot VSS to –
2.0V for periods of up to 20ns. Maximum DC voltage on input and I/O pins is VCC+0.5V. During transitions, input
and I/O pins may overshoot to VCC +2.0V for periods up to 20ns.
\6 – Minimum DC Input Voltage on A9 is –0.5V. During voltage transitions, A9 and VPP may overshoot VSS to –2.0V for
periods of up to 20ns. A9 and VPP must not exceed +13.5V at any time.
\7 – Do not exceed 125ºC TC or TJ for plastic package devices.
\8 – Maximum PD, Maximum TJ Are Not to Be Exceeded.
\9 – During transitions, the inputs may undershoot to –2.0 V dc for periods less than 20 ns.
\10 – VPP may be connected directly to VCC except during programming.
\11 – Qualification Only.
\12 – If not tested, shall be guaranteed to the limits specified.
TABLE I – ELECTRICAL PERFORMANCE CHARACTERISTICS
Test Symbol Conditions
-55ºC ≤TA≤+125ºC
Unless Otherwise Specified
Min Max Unit
Input Load Current ILI V
IN = 5.5V or 0.0V
All other inputs at either VCC or GND -10.0 +10.0 μA
Output Leakage Current ILO V
OIT = 5.5V or 0.0V -10.0 +10.0 μA
Operating Current, TTL ICC TTL OE = CE = VIL 35ns 85 mA
V
PP = VCC 45ns 60 mA
O
0-O7 = 0 mA 55ns 60 mA
f = 1/tACCmax 70ns 60 mA
QP27C256 90ns 60 mA
QP27C256L 90ns 50 mA
QP27C256 120ns 60 mA
QP27C256L 120ns 50 mA
QP27C256 150ns 60 mA
QP27C256L 150ns 50 mA
QP27C256 170ns 60 mA
QP27C256L 170ns 50 mA
QP27C256 200ns 60 mA
QP27C256L 200ns 50 mA
QP27C256 250ns 60 mA
QP27C256L 250ns 50 mA
QP27C256 300ns 60 mA
QP27C256L 300ns 50 mA
QP27C256 & QP27C256L
QP SEMI, 2945 Oakmead Village Court, Santa Clara, CA 95051 Page 6 of 13
TABLE I – ELECTRICAL PERFORMANCE CHARACTERISTICS
Test Symbol Conditions
-55ºC ≤TA≤+125ºC
Unless Otherwise Specified
Min Max Unit
Operating Current, CMOS ICC CMOS OE = CE = VIL 35ns 60 mA
V
PP = VCC 45ns 60 mA
O
0-O7 = 0 mA 55ns 60 mA
f = 1/tACCmax 70ns 60 mA
QP27C256 90ns 60 mA
QP27C256L 90ns 25 mA
QP27C256 120ns 60 mA
QP27C256L 120ns 25 mA
QP27C256 150ns 60 mA
QP27C256L 150ns 25 mA
QP27C256 170ns 60 mA
QP27C256L 170ns 25 mA
QP27C256 200ns 60 mA
QP27C256L 200ns 25 mA
QP27C256 250ns 60 mA
QP27C256L 250ns 25 mA
QP27C256 300ns 60 mA
QP27C256L 300ns 25 mA
QP27C256 & QP27C256L
QP SEMI, 2945 Oakmead Village Court, Santa Clara, CA 95051 Page 7 of 13
TABLE I – ELECTRICAL PERFORMANCE CHARACTERISTICS
Test Symbol Conditions
-55ºC ≤TA≤+125ºC
Unless Otherwise Specified
Min Max Unit
Standby Current, TTL ISB TTL CE = VIH 35ns 25 mA
V
CC= 5.5V 45ns 25 mA
f = 0 MHz 55ns 25 mA
O
0-O7 = 0 mA 70ns 25 mA
QP27C256 90ns 25 mA
QP27C256L 90ns 5 mA
QP27C256 120ns 25 mA
QP27C256L 120ns 5 mA
QP27C256 150ns 25 mA
QP27C256L 150ns 3 mA
QP27C256 170ns 25 mA
QP27C256L 170ns 3 mA
QP27C256 200ns 25 mA
QP27C256L 200ns 3 mA
QP27C256 250ns 25 mA
QP27C256L 250ns 3 mA
QP27C256 300ns 25 mA
QP27C256L 300ns 3 mA
QP27C256 & QP27C256L
QP SEMI, 2945 Oakmead Village Court, Santa Clara, CA 95051 Page 8 of 13
TABLE I – ELECTRICAL PERFORMANCE CHARACTERISTICS
Test Symbol Conditions
-55ºC ≤TA≤+125ºC
Unless Otherwise Specified
Min Max Unit
Standby Current, CMOS ISB CMOS CE = VIH 35ns 25 mA
V
CC= 5.5V 45ns 25 mA
f = 0 MHz 55ns 25 mA
O
0-O7 = 0 mA 70ns 25 mA
QP27C256 90ns 25 mA
QP27C256L 90ns 300 uA
QP27C256 120ns 25 mA
QP27C256L 120ns 300 uA
QP27C256 150ns 25 mA
QP27C256L 150ns 300 uA
QP27C256 170ns 25 mA
QP27C256L 170ns 300 uA
QP27C256 200ns 25 mA
QP27C256L 200ns 300 uA
QP27C256 250ns 25 mA
QP27C256L 250ns 300 uA
QP27C256 300ns 25 mA
QP27C256L 300ns 300 uA
VPP Read Current IPP V
PP = VCC = 5.5V 10 μA
Input Low Voltage TTL VIL V
PP = VCC -0.1 0.8 V
Input Low Voltage CMOS VIL V
PP = VCC -0.2 0.2 V
Input High Voltage TTL VIH V
PP = VCC 2.0 VCC+1.0 V
Input High Voltage CMOS VIH V
PP = VCC V
CC-0.2 VCC+0.2 V
Output Low Voltage VOL I
OL= 2.1mA 0.45 V
Output High Voltage VOH V
IL=0.8V,VIH=2.0V 2.4 V
I
OL= -400μA,VCC=4.5V
Output Short Circuit Current IOS V
OUT = 0.0V
Duration not to exceed 1 second,
one output at a time
-100 mA
VPP Read Voltage \10 VPP V
CC - 0.7 VCC V
QP27C256 & QP27C256L
QP SEMI, 2945 Oakmead Village Court, Santa Clara, CA 95051 Page 9 of 13
TABLE I – ELECTRICAL PERFORMANCE CHARACTERISTICS
Test Symbol Conditions
-55ºC ≤TA≤+125ºC
Unless Otherwise Specified
Min Max Unit
Address to Output Delay tACC CE = VIL 35ns 35 ns
OE = VIL 45ns 45 ns
55ns 55 ns
70ns 70 ns
90ns 90 ns
120ns 120 ns
150ns 150 ns
170ns 170 ns
200ns 200 ns
250ns 250 ns
300ns 300 ns
CE to Output Delay tCE OE = VIL 35ns 40 ns
45ns 45 ns
55ns 55 ns
70ns 70 ns
90ns 90 ns
120ns 120 ns
150ns 150 ns
170ns 170 ns
200ns 200 ns
250ns 250 ns
300ns 300 ns
QP27C256 & QP27C256L
QP SEMI, 2945 Oakmead Village Court, Santa Clara, CA 95051 Page 10 of 13
TABLE I – ELECTRICAL PERFORMANCE CHARACTERISTICS
Test Symbol Conditions
-55ºC ≤TA≤+125ºC
Unless Otherwise Specified
Min Max Unit
OE to Output Delay tOE CE = VIL 35ns 20 ns
45ns 15 ns
55ns 25 ns
70ns 25 ns
90ns 30 ns
120ns 35 ns
150ns 40 ns
170ns 40 ns
200ns 60 ns
250ns 60 ns
300ns 60 ns
OE high to Output Float tDF OE = VIL 35ns 15 ns
45ns 15 ns
55ns 20 ns
70ns 25 ns
90ns 30 ns
120ns 35 ns
150ns 40 ns
170ns 40 ns
200ns 55 ns
250ns 60 ns
300ns 60 ns
Output hold from
Addresses, OE or CE
Whichever Occurred First \12
tOH CE = OE =VIL 0 ns
Input Capacitance CIN V
IN=0V, f=1Mhz 12 pF
Output Capacitance COUT V
IN=0V, f=1Mhz 14 pF
QP27C256 & QP27C256L
QP SEMI, 2945 Oakmead Village Court, Santa Clara, CA 95051 Page 11 of 13
Ordering Information
Part Number Package (Mil-Std-1835) Generic
5962-8606301UA GDIP3-T28 CDIP4-T28 (DIP) QP27C256L-200/UA
5962-8606301XA GDIP1-T28 CDIP2-T28 (DIP) QP27C256L-200/XA
5962-8606301YA CQCC1-N32 (LCC) QP27C256L-200/YA
5962-8606301YC CQCC1-N32 (LCC) QP27C256L-200/YC
5962-8606301ZA JLCC-N32 QP27C256L-200/ZA
5962-8606302UA GDIP3-T28 CDIP4-T28 (DIP) QP27C256L-250/UA
5962-8606302XA GDIP1-T28 CDIP2-T28 (DIP) QP27C256L-250/XA
5962-8606302YA CQCC1-N32 (LCC) QP27C256L-250/YA
5962-8606302YC CQCC1-N32 (LCC) QP27C256L-250/YC
5962-8606302ZA JLCC-N32 QP27C256L-250/ZA
5962-8606303UA GDIP3-T28 CDIP4-T28 (DIP) QP27C256L-300/UA
5962-8606303XA GDIP1-T28 CDIP2-T28 (DIP) QP27C256L-300/XA
5962-8606303YA CQCC1-N32 (LCC) QP27C256L-300/YA
5962-8606303YC CQCC1-N32 (LCC) QP27C256L-300/YC
5962-8606303ZA JLCC-N32 QP27C256L-300/ZA
5962-8606304UA GDIP3-T28 CDIP4-T28 (DIP) QP27C256L-170/UA
5962-8606304XA GDIP1-T28 CDIP2-T28 (DIP) QP27C256L-170/XA
5962-8606304YA CQCC1-N32 (LCC) QP27C256L-170/YA
5962-8606304YC CQCC1-N32 (LCC) QP27C256L-170/YC
5962-8606304ZA JLCC-N32 QP27C256L-170/ZA
5962-8606305UA GDIP3-T28 CDIP4-T28 (DIP) QP27C256L-150/UA
5962-8606305XA GDIP1-T28 CDIP2-T28 (DIP) QP27C256L-150/XA
5962-8606305YA CQCC1-N32 (LCC) QP27C256L-150/YA
5962-8606305YC CQCC1-N32 (LCC) QP27C256L-150/YC
5962-8606305ZA JLCC-N32 QP27C256L-150/ZA
5962-8606306UA GDIP3-T28 CDIP4-T28 (DIP) QP27C256L-120/UA
5962-8606306XA GDIP1-T28 CDIP2-T28 (DIP) QP27C256L-120/XA
5962-8606306YA CQCC1-N32 (LCC) QP27C256L-120/YA
5962-8606306YC CQCC1-N32 (LCC) QP27C256L-120/YC
5962-8606306ZA JLCC-N32 QP27C256L-120/ZA
5962-8606307UA GDIP3-T28 CDIP4-T28 (DIP) QP27C256L-90/UA
5962-8606307XA GDIP1-T28 CDIP2-T28 (DIP) QP27C256L-90/XA
5962-8606307YA CQCC1-N32 (LCC) QP27C256L-90/YA
5962-8606307YC CQCC1-N32 (LCC) QP27C256L-90/YC
5962-8606307ZA JLCC-N32 QP27C256L-90/ZA
5962-8606308UA GDIP3-T28 CDIP4-T28 (DIP) QP27C256-70/UA
5962-8606308XA GDIP1-T28 CDIP2-T28 (DIP) QP27C256-70/XA
5962-8606308YA CQCC1-N32 (LCC) QP27C256-70/YA
5962-8606308YC CQCC1-N32 (LCC) QP27C256-70/YC
5962-8606308ZA JLCC-N32 QP27C256-70/ZA
5962-8606309UA GDIP3-T28 CDIP4-T28 (DIP) QP27C256-55/UA
5962-8606309XA GDIP1-T28 CDIP2-T28 (DIP) QP27C256-55/XA
5962-8606309YA CQCC1-N32 (LCC) QP27C256-55/YA
5962-8606309YC CQCC1-N32 (LCC) QP27C256-55/YC
5962-8606310UA GDIP3-T28 CDIP4-T28 (DIP) QP27C256-45/UA
5962-8606310XA GDIP1-T28 CDIP2-T28 (DIP) QP27C256-45/XA
5962-8606310YA CQCC1-N32 (LCC) QP27C256-45/YA
5962-8606310YC CQCC1-N32 (LCC) QP27C256-45/YC
QP27C256 & QP27C256L
QP SEMI, 2945 Oakmead Village Court, Santa Clara, CA 95051 Page 12 of 13
Part Number Package (Mil-Std-1835) Generic
5962-8606311QXA GDIP1-T28 CDIP2-T28 (DIP) QP27C256-200/XA
5962-8606311QYA CQCC1-N32 (LCC) QP27C256-200/YA
5962-8606311UA GDIP3-T28 CDIP4-T28 (DIP) QP27C256-200/UA
5962-8606311XA GDIP1-T28 CDIP2-T28 (DIP) QP27C256-200/XA
5962-8606311YA CQCC1-N32 (LCC) QP27C256-200/YA
5962-8606312QXA GDIP1-T28 CDIP2-T28 (DIP) QP27C256-250/XA
5962-8606312QYA CQCC1-N32 (LCC) QP27C256-250/YA
5962-8606312UA GDIP3-T28 CDIP4-T28 (DIP) QP27C256-250/UA
5962-8606312XA GDIP1-T28 CDIP2-T28 (DIP) QP27C256-250/XA
5962-8606312YA CQCC1-N32 (LCC) QP27C256-250/YA
5962-8606313QXA GDIP1-T28 CDIP2-T28 (DIP) QP27C256-300/XA
5962-8606313QYA CQCC1-N32 (LCC) QP27C256-300/YA
5962-8606313UA GDIP3-T28 CDIP4-T28 (DIP) QP27C256-300/UA
5962-8606313XA GDIP1-T28 CDIP2-T28 (DIP) QP27C256-300/XA
5962-8606313YA CQCC1-N32 (LCC) QP27C256-300/YA
5962-8606314QXA GDIP1-T28 CDIP2-T28 (DIP) QP27C256-170/XA
5962-8606314QYA CQCC1-N32 (LCC) QP27C256-170/YA
5962-8606314UA GDIP3-T28 CDIP4-T28 (DIP) QP27C256-170/UA
5962-8606314XA GDIP1-T28 CDIP2-T28 (DIP) QP27C256-170/XA
5962-8606314YA CQCC1-N32 (LCC) QP27C256-170/YA
5962-8606315QXA GDIP1-T28 CDIP2-T28 (DIP) QP27C256-150/XA
5962-8606315QYA CQCC1-N32 (LCC) QP27C256-150/YA
5962-8606315UA GDIP3-T28 CDIP4-T28 (DIP) QP27C256-150/UA
5962-8606315XA GDIP1-T28 CDIP2-T28 (DIP) QP27C256-150/XA
5962-8606315YA CQCC1-N32 (LCC) QP27C256-150/YA
5962-8606316QXA GDIP1-T28 CDIP2-T28 (DIP) QP27C256-120/XA
5962-8606316QYA CQCC1-N32 (LCC) QP27C256-120/YA
5962-8606316UA GDIP3-T28 CDIP4-T28 (DIP) QP27C256-120/UA
5962-8606316XA GDIP1-T28 CDIP2-T28 (DIP) QP27C256-120/XA
5962-8606316YA CQCC1-N32 (LCC) QP27C256-120/YA
5962-8606317QXA GDIP1-T28 CDIP2-T28 (DIP) QP27C256-90/XA
5962-8606317QYA CQCC1-N32 (LCC) QP27C256-90/YA
5962-8606317UA GDIP3-T28 CDIP4-T28 (DIP) QP27C256-90/UA
5962-8606317XA GDIP1-T28 CDIP2-T28 (DIP) QP27C256-90/XA
5962-8606317YA CQCC1-N32 (LCC) QP27C256-90/YA
5962-8606318QXA GDIP1-T28 CDIP2-T28 (DIP) QP27C256-70/XA
5962-8606318QYA CQCC1-N32 (LCC) QP27C256-70/YA
5962-8606318UA GDIP3-T28 CDIP4-T28 (DIP) QP27C256-70/UA
5962-8606318XA GDIP1-T28 CDIP2-T28 (DIP) QP27C256-70/XA
5962-8606318YA CQCC1-N32 (LCC) QP27C256-70/YA
5962-8606319QXA GDIP1-T28 CDIP2-T28 (DIP) QP27C256-55/XA
5962-8606319QYA CQCC1-N32 (LCC) QP27C256-55/YA
5962-8606319UA GDIP3-T28 CDIP4-T28 (DIP) QP27C256-55/UA
5962-8606319XA GDIP1-T28 CDIP2-T28 (DIP) QP27C256-55/XA
5962-8606319YA CQCC1-N32 (LCC) QP27C256-55/YA
5962-8606320QUA GDIP3-T28 CDIP4-T28 (DIP) QP27C256-45/UA
5962-8606320QXA GDIP1-T28 CDIP2-T28 (DIP) QP27C256-45/XA
5962-8606320QYA CQCC1-N32 (LCC) QP27C256-45/YA
5962-8606321QUA GDIP3-T28 CDIP4-T28 (DIP) QP27C256-35/UA
QP27C256 & QP27C256L
QP SEMI, 2945 Oakmead Village Court, Santa Clara, CA 95051 Page 13 of 13
Part Number Package (Mil-Std-1835) Generic
5962-8606321QXA GDIP1-T28 CDIP2-T28 (DIP) QP27C256-35/XA
5962-8606321QYA CQCC1-N32 (LCC) QP27C256-35/YA
QP Semiconductor supports Source Control Drawing (SCD), and custom package development for this product family.
Notes:
Package outline information and specifications are defined by Mil-Std-1835 package dimension require ments.
“-MIL” products manufactured by QP Semiconductor are compliant to the assembly, burn-in, test and quality conformance
requirements of Test Methods 50 04 & 5005 of Mil-Std-883 for Class B devices. This datasheet defines the electrical test
requirements for the device(s).
The listed drawings, Mil-PRF-38535, Mil-Std-88 3 and Mil-Std-1835 are available online at http://www.dscc.dla.mil/
Additional information is available at our website http://www.qpsemi.com
