VG36128801A - Vanguard International Semiconductor

Document : 1G5-0154 Rev.1 Page 1

VIS VG36128401A

Preliminary VG36128801A

VG36128161A

CMOS Synchronous Dynamic RAM

Description

The device is CMOS Synchronous Dynamic RAM organized as 8,388,608 - word x 4 -bit x 4 - bank,

4,194,304 - word x 8 - bit x 4 - bank, or 2,097,152 - word x 16 - bit x 4 - bank. These various organizations

provide wide choice for different applications. It is designed with the state-of-the-art technology to meet stan-

dard PC100 or high speed PC133 requirement. Four internal independent banks greatly increase the perfor-

mance efficiency. It is packaged in JEDEC standard pinout and standard plastic 54-pin TSOP package.

Features

• Single 3.3V () power supply

• High speed clock cycle time : 7.5ns/10ns

• Fully synchronous with all signals referenced to a positive clock edge

• Programmable CAS Iatency (2,3)

• Programmable burst length (1,2,4,8,& Full page)

• Programmable wrap sequence (Sequential/Interleave)

• Automatic precharge and controlled precharge

• Auto refresh and self refresh modes

• Quad Internal banks controlled by BA0 & BA1 (Bank select)

• Each Bank can be operated simultaneously and independently

• I/O level : LVTTL compatible

• Random column access in every cycle

• x4, x8, x16 organization

• Input/Output controlled by DQM ( LDQM, UDQM )

• 4,096 refresh cycles/64ms

• Burst termination by burst stop and precharge command

• Burst read/single write option

The information shown is subject to change without notice.

0.3V

±

Document : 1G5-0154 Rev.1 Page 2

VIS VG36128401A

Preliminary VG36128801A

VG36128161A

CMOS Synchronous Dynamic RAM

Pin Description

VG36128801/VG36128161

Pin Name Function Pin Name Function

A0 - A11

BAO, BA1 Address inputs

Bank select DQM,

LDQM,

UDQM,

Upper DQ Mask enable,

Lower DQ Mask enable

DQ0 ~ DQ15 Data - in/data - out CLK Clock input

RAS Row address strobe CKE Clock enable

CAS Column address strobe CS Chip select

WE Write enable VDDQ Supply voltage for DQ

VSS Ground VSSQ Ground for DQ

VDD Power (+ 3.3V)

VDD

DQ0

VDDQ

V

SSQ

DQ2

V

DDQ

CAS

RAS

WE

A10

BA0

A1

A2

A3

VDD

VSS

VSSQ

VDDQ

DQ11

VSS

DQ9

VDDQ

NC

CLK

UDQM

CKE

NC

VSS

A9

A8

A7

A6

A5

A11

DQ1

DQ3

V

SSQ

V

DD

LDQM

CS

BA1

A0

A4

VSSQ

DQ13

DQ15

VG36128161 (X 16)

VDD

DQ0

VDDQ

V

SSQ

DQ2

V

DDQ

NC

CAS

RAS

WE

A10

A1

A2

A3

VDD

NC

DQ1

NC

DQ3

V

SSQ

NC

V

DD

NC

CS

BA1

A0

VSS

VSSQ

VDDQ

DQ5

VSS

DQ4

VDDQ

CLK

DQM

CKE

NC

VSS

A9

A8

A7

A6

A5

A11

NC

A4

NC

VSSQ

DQ6

DQ7

NC

DQ14

DQ12

DQ10

DQ8

DQ4

DQ5

DQ6

DQ7

BA0

VG36128801 (X 8)

Pin Configuration

1

2

3

4

5

6

7

8

9

10

11

12

13

14

16

17

18

19

20

21

22

44

43

42

23

24

25

26

27 29

28

31

30

36

35

34

33

32

38

37

39

40

41

46

45

47

48

49

50

51

52

53

54

15

VG36128401 (X 4)

VDD

NC

VDDQ

V

SSQ

DQ2

V

DDQ

NC

CAS

RAS

WE

A10

A1

A2

A3

VDD

NC

DQ1

NC

DQ3

V

SSQ

NC

V

DD

NC

CS

BA1

A0

BA0

VSS

VSSQ

VDDQ

DQ5

VSS

DQ4

VDDQ

CLK

DQM

CKE

NC

VSS

A9

A8

A7

A6

A5

A11

NC

A4

NC

VSSQ

DQ6

DQ7

NC

Document : 1G5-0154 Rev.1 Page 3

VIS VG36128401A

Preliminary VG36128801A

VG36128161A

CMOS Synchronous Dynamic RAM

Block Diagram

CLK

CKE

Clock

Generator

CS

RAS

Mode

Register

Column

Address

Buffer

&

Burst

Counter

CAS

WE

Command Decoder

Control Logic

Address Row

Address

Buffer

&

Refresh

Counter

Bank B

Bank A

Sense Amplifier

Column Decoder &

Latch Circuit

Row Decoder

Data Control Circuit DQ

DQM

Latch Circuit

Input & Output

Buffer

(Bank C)

(Bank D)

Document : 1G5-0154 Rev.1 Page 4

VIS VG36128401A

Preliminary VG36128801A

VG36128161A

CMOS Synchronous Dynamic RAM

Absolute Maximum D.C. Ratings

Caution: Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent

damage. The device is not meant to be operated under conditions outside the limits described in the

operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended

periods may affect device reliability.

Parameter Symbol Value Unit

Voltage on any pin relative to Vss VIN, VOUT -0.5 to + 4.6 V

Supply voltage relative to Vss VDD, VDDQ -0.5 to + 4.6 V

Short circuit output current IOUT 50 mA

Power dissipation PD1.0 W

Operating temperature TOPT 0 to + 70 ¢J

Storage temperature TSTG -55 to + 125 ¢J

Maximum A.C. Operating Requirements for LVTTL Compatible

Parameter Symbol Min Max Unit Notes

Input High Voltage VIH 2.0 VDD + 0.3 V1

Input Low Voltage VIL -0.3 0.8 V2

Recommended DC Operating Conditions for LVTTL Compatible

Parameter Symbol Min Typ Max Unit

Supply Voltage VDD, VDDQ 3.0 3.3 3.6 V

Input High Voltage, all inputs VIH 2.0 ¡ÐVDD + 0.3 V

Input Low Voltage, all inputs VIL -0.3 ¡Ð0.8 V

Capacitance

(Ta=25°C, f = 1MHZ)

Notes : 1. Capacitance measured with effective capacitance measuring method.

Parameter Symbol Min Max Unit Notes

Input capacitance (CLK) C11 2.5 4pF 1

Input capacitance (all input pins except data

pins.) C12 2.5 5pF 1

Data input/output capacitance CI/O 4.0 6.5 pF 1

Note: 1. Overshoot limit: VIH(max)=VDDQ +2.0V with a pulse with

2. Undershoot limit: VIL(min)=VSSQ -2.0V with a pulse with and -1.5v with a pulse

3ns

<

3ns

<

5ns

<

Document : 1G5-0154 Rev.1 Page 5

VIS VG36128401A

Preliminary VG36128801A

VG36128161A

CMOS Synchronous Dynamic RAM

DC Characteristics (Recommended Operating Conditions unless otherwise noted)

Parameter Symbol Test Conditions -75 -8H Unit Notes

Min Max Min Max

Operating current ICC1 Burst length = 1

One bank active

tRC tRC(MIN.), Io = 0mA

x4 120 100 mA 1

x 8 125 105

x16 135 115

Precharge standby

current in Power

down mode

ICC2P CKE VIL(MAX.) tCK = min. 2 2 mA

ICC2PS CKE VIL(MAX.) tCK = 2 2

Precharge standby

current in Nonpower

down mode

ICC2N CKE VIH(MIN.) tCK = min.

CS VIH(MIN.)

Input signals are changed one

time during 2 CLK cycles.

20 20 mA

ICC2NS CKE VIH(MIN.) tCK =

CLK VIL(MAX.)

Input signals are stable.

7 7

Active standby current

in Power

down mode

ICC3P CKE VIL(MAX.) tCK = min. 7 7 mA

ICC3PS CKE VIL(MAX.) tCK = 5 5

Active standby

current in Nonpower

down mode

ICC3N CKE VIH(MIN.) tCK = min.

CS VIH(MIN.)

Input signals are changed one

time during 2CLKs

30 30 mA

ICC3NS CKE VIH(MIN.) tCK =

CLK VIL(MAX.)

Input signals are stable.

20 20

Operating current

(Burst mode) ICC4 tCKtCK(MIN.) Io = 0mA

All banks Active

x4 115 105

x 8 130 120 mA 2

x16 160 150

Refresh current ICC5 tRC = 4 x tRC(MIN) 190 190 mA 3

Self refresh Current ICC6 CKE 0.2V 1 1 mA

Input Ieakage current

(Inputs) lLI VIN0, VIN VDD(MAX.)

Pins not under test = 0V

-1 1-1 1uA

Intput leakage current

(I/O pins) lLO VOUT0, VOUT VDD(MAX.)

DQ# in H - Z., Dout Disabled

-1.5 1.5 -1.5 1.5 uA

Output Low Voltage VOL IOL = 2mA 0.4 0.4 V4

Output High Voltage VOH IOH = -2mA 2.4 2.4 V4

≥

≤

∞

≥

∞

≤

∞

≥

∞

≤

≥

≤

≥

≤

≥

≤

Notes : 1. ICC1 depends on output loading and cycle rates. Specified values are obtained with the output open.

In addition to this, ICC1 is measured on condition that addresses are changed only one time during tCK(MIN.).

2. ICC4 depends on output loading and cycle rates. Specified values are obtained with the output open.

In addition to this, ICC4 is measured on condition that addresses are changed only one time during tCK(MIN.).

3. ICC5 is measured on condition that addresses are changed only one time during tCK(MIN.).

4. For LVTTL compatible.

Document : 1G5-0154 Rev.1 Page 6

VIS VG36128401A

Preliminary VG36128801A

VG36128161A

CMOS Synchronous Dynamic RAM

AC Characteristics : (Ta = 0 to 70°C VDD = 3.3V 0.3V ,VSS = 0V)

Test Conditions for LVTTL Compatible :

AC input Levels (VIH/VIL)2.0/0.8V Input timing reference level/

Output timing reference level 1.4V

Input rise and fall time 1ns Output load condition 50pF

±

Ω

AC Test Load Circuits (for LVTTL interface) :

V

DDQ

V

DDQ

V

OUT

Device

Under

Test 50PF

Z = 50

Document : 1G5-0154 Rev.1 Page 7

VIS VG36128401A

Preliminary VG36128801A

VG36128161A

CMOS Synchronous Dynamic RAM

AC Characteristics : (Ta = 0 to 70°C VDD = 3.3V0.3V, VSS = 0V)

symbol A.C. Parameter -75 -8H unit note

Min. Max. Min. Max.

tRC Row cycle time 60 70

ns

tRCD RAS to CAS delay 20 20

tRP Precharge to refresh/row activate command 15 20

tRRD Row activate to row activate delay 15 20

tRAS Row activate to precharge time 37.5 100,000 50 100,000

tCK2 Clock cycle time CL2 7.5 10

ns

tCK3 CL3 7.5 10

tCH Clock high time 2.25 3

tCL Clock low time 2.25 3

tAC2 Access time from CLK

(positive edge) CL2 5 6

tAC3 CL3 5 6

tTTransition time of CLK (Rise and Fall) 110 1 10

tCCD CAS to CAS Delay time 1 1 CLK

tOH Data output hold time 2.5 3

ns

tLZ Data output low impedance 0 0

tHZ2 Data output high impedance CL2 4 6 9

tHZ3 CL3 4 6

tIS Data/Address/Control Input setup time 1 2

tIH Data/Address/Control Input hold time 0.5 1

tSRX Minimum CKE ”High”for Self-Refresh exit 1 1 CLK

tPDE Power Down Exit set-up time 2 2 ns

tRSC Mode Register Set Cycle 2 2 CLK

tDPL Data-in to precharge 2 1 CLK

tDAL2 Data-in to ACT (REF) Command CL2 2clk+tRP 1clk+tRP ns

tDAL3 CL3 2clk+tRP 1clk+tRP

tBDL Last data in to burst stop 1 1 CLK

tREF Refresh time 64 64 ms

±

Document : 1G5-0154 Rev.1 Page 8

VIS VG36128401A

Preliminary VG36128801A

VG36128161A

CMOS Synchronous Dynamic RAM

Basic Features and Function Description

1.Simplified State Diagram

Self

Refresh

MRS

Mode

Register

Set IDLE

AUTO

Refresh

REF

ACT

CKE CKE

BST

Power

Down

Active

Power

Down

ROW

ACTIVE

Read

CKE

READ READ

SUSPEND

CKE

READA READA

SUSPEND

Read with

Auto Precharge

CKE

Write (Write recovery)

WRITE

SUSPEND

WRITEA

SUSPEND CKE

CKE

Write with

Auto Precharge

POWER

ON Precharge Precharge

PRE (Precharge termination)

Read with

Write with

Auto precharge

Auto Precharge

Read

BST

Write

Read with

Auto Precharge (write recovery)

Read with

Auto Precharge

Write

Read (write recovery)

PRE

CKE

Automatic sequence

Manual input

Note: After the AUTO refresh operation, precharge operation is

performed automatically and enter the IDLE state.

SELF entry

SELF exit

Write recovery

Document : 1G5-0154 Rev.1 Page 9

VIS VG36128401A

Preliminary VG36128801A

VG36128161A

CMOS Synchronous Dynamic RAM

2. Truth Table

2.1 Command Truth Table

2.2 DQM Truth Table

2.3 CKE Truth Table

H : High level, L : Low level

X : High or Low level (Don’t care), V : Valid Data input

FUNCTION Symbol

CKE

CS RAS CAS WE BA(1) A10

A11

A9 - A0

n -1 n

Device deselect DESL HXHX X X X X X

No operation NOP HXLH H H X X X

Mode register set MRS HXL L L L L L V

Bank activate ACT HXL L H H V V V

Read READ HXLHLHVLV

Read with auto precharge READA HXLHLHVHV

Write WRIT HXLHL L VLV

Write with auto precharge WRITA HXLHL L VHV

Precharge select bank PRE HXL L HLVLX

Precharge all banks PALL HXL L HLXHX

Burst stop BST HXLH H LX X X

CBR (Auto) refresh REF H H L L L HX X X

Self refresh SELF HL L L L HX X X

FUNCTION Symbol CKE DQM

n -1 n -1 UL

Data write/output enable ENB HXL

Data mask/output disable MASK HXH

Upper byte write enable/output enable ENBU HXLX

Lower byte write enable/output enable ENBL HX X L

Upper byte write inhibit/output disable MASKU HXHX

Lower byte write inhibit/output disable MASKL HX X H

Current State Function Symbol CKE CS RAS CAS WE Add -

ressn - 1 n

Activating Clock suspend mode entry HLX X X X X

Any Clock suspend L L X X X X X

Clock suspend Clock suspend mode exit LHX X X X X

Idle CBR refresh command REF H H L L L HX

Idle Self refresh entry SELF HL L L L HX

Self refresh Self refresh exit LHLHHH X

LH H X X X X

Idle Power down entry HLX X X X X

Power down Power down exit LHX X X X X

Document : 1G5-0154 Rev.1 Page 10

VIS VG36128401A

Preliminary VG36128801A

VG36128161A

CMOS Synchronous Dynamic RAM

2.4 Operative Command Table Notes 1

Current

state CS RAS CAS WE Address Command Action Notes

Idle HX X X X DESL Nop or Power down 2

LH H X X NOP or BST Nop or Power down 2

LHLHBA, CA, A10 READ/READA ILLEGAL 3

LHL L BA, CA, A10 WRIT/WRITA ILLEGAL 3

L L H H BR, RA ACT Row active

L L HLBA, A10 PRE/PALL Nop

L L L HXREF/SELF Refresh or Self refresh 4

L L L L Op - Code MPS Mode register access

Row active HX X X X DESL Nop

LH H X X NOP or BST Nop

LHLHBA, CA, A10 READ/READA Begin read : Determine AP 5

LHL L BA, CA, A10 WRIT/WRITA Begin write : Determine AP 5

L L H H BA, RA ACT ILLEGAL 3

L L HLBA, A10 PRE/PALL Precharge 6

L L L HXREF/SELF ILLEGAL

L L L L Op - Code MRS ILLEGAL

Read HX X X X DESL Continue burst to end Row active

LHHHXNOP Continue burst to end Row active

LH H LXBST Burst end Row active

LHLHBA, CA, A10 READ/READA Term burst, new read : Determine AP 7

LHL L BA, CA, A10 WRIT/WRITA Term burst, start write : Determine AP 7,8

L L H H BA, RA ACT ILLEGAL 3

L L HLBA, A10 PRE/PALL Term burst, precharging

L L L HXREF/SELF ILLEGAL

L L L L Op - Code MRS ILLEGAL

Write HX X X X DESL Continue burst to end Write recovering

LHHHXNOP Continue burst to end Write recovering

LH H LXBST Burst stop Row active

LHLHBA, CA, A10 READ/READA Term burst, start read : determine AP 7,8

LHL L BA, CA, A10 WRIT/WRITA Term burst, new write : Determine AP 7

L L H H BA, RA ACT ILLEGAL 3

L L HLBA, A10 PRE/PALL Term burst, precharging 9

L L L HXREF/SELF ILLEGAL

L L L L Op - Code MRS ILLEGAL

→

(1/3)

Document : 1G5-0154 Rev.1 Page 11

VIS VG36128401A

Preliminary VG36128801A

VG36128161A

CMOS Synchronous Dynamic RAM

Current state CS RAS CA WE Address Command Action Notes

Read with auto

precharge HX X X X DESL Continue burst to end Prcharging

LH H H XNOP Continue burst to end Prcharging

LH H LXBST Illegal for single bank, but legal for

multibanks interleave

LHLHBA, CA, A10 READ/READA Illegal for single bank, but legal for

multibanks interleave

LHL L BA, CA, A10 WRIT/WRITA ILLEGAL

L L H H BA, RA ACT ILLEGAL 3

L L HLBA, A10 PRE/PALL ILLEGAL 3

L L L HXPEF/SELF ILLEGAL

L L L L Op - Code MRS ILLEGAL

Write with auto

precharge HX X X X DESL Continue burst to endWrite

recovering with auto precharge

LH H H XNOP Continue burst to endWrite

recovering with auto precharge

LH H LXBST ILLEGAL

LHLHBA, CA, A10 READ/READA Illegal for single bank, but legal for

multibanks interleave

LHL L BA, CA, A10 WRIT/WRITA Illegal for single bank, but legal for

multibanks interleave

L L H H BA, RA ACT ILLEGAL 3

L L HLBA, A10 PRE/PALL ILLEGAL 3

L L L HXPEF/SELF ILLEGAL

L L L L Op - Code MRS ILLEGAL

precharging HX X X X DESL NopEnter idle after tRP

LH H H XNOP NopEnter idle after tRP

LH H LXBST NopEnter idle after tRP

LHLHBA, CA, A10 READ/READA ILLEGAL 3

LHL L BA, CA, A10 WRIT/WRITA ILLEGAL 3

L L H H BA, RA ACT ILLEGAL 3

L L HLBA, A10 PRE/PALL NopEnter idle after tRP

L L L HXPEF/SELF ILLEGAL

L L L L Op - Code MRS ILLEGAL

Row activating HX X X X DESL NopEnter row active idle after tRCD

LH H H XNOP NopEnter row active idle after tRCD

LH H LXBST NopEnter row active idle after tRCD

LHLHBA, CA, A10 READ/READA ILLEGAL 3

LHL L BA, CA, A10 WRIT/WRITA ILLEGAL 3

L L H H BA, RA ACT ILLEGAL 3,9

L L HLBA, A10 PRE/PALL ILLEGAL 3

L L L HXPEF/SELF ILLEGAL

L L L L Op - Code MRS ILLEGAL

→

(2/3)

Document : 1G5-0154 Rev.1 Page 12

VIS VG36128401A

Preliminary VG36128801A

VG36128161A

CMOS Synchronous Dynamic RAM

(3/3)

Note 1. All entries assume that CKE was active (High level) during the preceding clock cycle.

2. If both banks are idle, and CKE is inactive (Low level), the device will enter Power down mode.

All input buffers except CKE will be disabled.

3. Illegal to bank in specified states; Function may be legal in the bank indicated by Bank Address (BA),

depending on the state of that bank.

4. If both banks are idle, and CKE is inactive (Low level), the device will enter Self refresh mode.

All input buffers except CKE will be disabled.

5. Illegal if tRCD is not satisfied.

6. Illegal if tRAS is not satisfied.

7. Must satisfy burst interrupt condition.

8. Must satisfy bus contention, bus turn around, and/or write recovery requirements.

9. Must mask preceding data which don’t satisfy t DPL.

10. Illegal if tRRD is not satisfied.

11. Illegal for single bank, but for multibanks interleave

Current state CS RAS CA WE Address Command Action Notes

Write

recovering HX X X X DESL Nop Enter row active after tDPL

LH H H XNOP Nop Enter row active after tDPL

LH H LXBST Nop Enter row active after tDPL

LHLHBA, CA, A10 READ/READA Start read, Determine AP 8

LHL L BA, CA, A10 WRIT/WRITA New write, Determine AP

L L H H BA, RA ACT ILLEGAL 3

L L HLBA, A10 PRE/PALL ILLEGAL 3

LLLHXPEF/SELF ILLEGAL

L L L L Op - Code MRS ILLEGAL

Write

recovering

with auto

precharge

HX X X X DESL Nop Enter precharge after tDPL

LH H H XNOP Nop Enter precharge after tDPL

LH H LXBST Nop Enter precharge after tDPL

LHLHBA, CA, A10 READ/READA ILLEGAL 3,8

LHL L BA, CA, A10 WRIT/WRITA ILLEGAL 3

L L H H BA, RA ACT ILLEGAL 3

L L HLBA, A10 REF/PALL ILLEGAL 3

LLLHXREF/SELF ILLEGAL

L L L L Op - Code MRS ILLEGAL

Auto

Refreshing HX X X X DESL Nop Enter idle after tRC

LH H X X NOP/BST Nop Enter idle after tRC

LHLX X READ/WRIT ILLEGAL

L L HX X ACT/PRE/PALL ILLEGAL

LLLX X REF/SELF/MRS ILLEGAL

Mode regis-

ter setting HX X X X DESL Nop Enter idle after 2 Clocks

LH H H XNOP Nop Enter idle after 2 Clocks

LH H LXBST ILLEGAL

LHLX X READ/WRITE ILLEGAL

L L X X X ACT/PRE/

PALL/ ILLEGAL

→

Document : 1G5-0154 Rev.1 Page 13

VIS VG36128401A

Preliminary VG36128801A

VG36128161A

CMOS Synchronous Dynamic RAM

2.5 Command Truth Table for CKE Note 1

Note 1. H : Hight level, L : low level, X : High or low level (Don't care)

2. CKE Low to High transition will re-enable CLK and other inputs asynchronously. A minimum setup time

must be satisfied before any command other than EXIT.

3. Power down and Self refresh can be entered only from the both banks idle state.

4. Must be legal command as defined in Operative Command Table.

5. IIIegal if tSREX is not satisfied.

Current state CKE

n - 1 RAS

nCS RAS CAS WE Address Action Notes

Self refresh

(S.R.) HXXXX X X INVALID, CLK (n-1)would exit S.R.

LH H XX X X S.R. Recovery 2

LHLHHX X S.R. Recovery 2

LHLHLX X ILLEGAL

LHL L X X X ILLEGAL

L L XXX X X Maintain S.R.

Self refresh

recovery H H H XX X X Idle after tRC

H H LHHX X Idle after tRC

H H LHLX X ILLEGAL

H H L L X X X ILLEGAL

HLHXX X X Begin clock suspend next cycle 5

HL L HHX X Begin clock suspend next cycle 5

HL L HLX X ILLEGAL

HL L L X X X ILLEGAL

LHXXX X X Exit clock suspend next cycle 2

L L XXX X X Maintain clock suspend

Power down

(P.D.) HXXXX X INVALID, CLK(n-1) would exit P.D.

LHXXX X X EXIT P.D. Idle 2

L L XXX X X Maintain power down mode

Both banks idle H H H XX X Refer to operations in Operative

Command Table

H H LHX X Refer to operations in Operative

Command Table

H H L L HXRefer to operations in Operative

Command Table

H H LLLHXAuto Refresh

H H LLL L Op-Code Refer to operations in Operative

Command Table

HLHXX X Refer to operations in Operative

Command Table

HL L HX X Refer to operations in Operative

Command Table

HL L L HXRefer to operations in Operative

Command Table

HLLLLHXSelf refresh 3

HLLLL L Op-Code Refer to operations in Operative

Command Table

LXXXX X X Power down 3

Any state other

than listed above HHXXX X X Refer to operations in Operative

Command Table

HLXXX X X Begin clock suspend next cycle 4

LHXXX X X Exit clock suspend next cycle

L L XXX X X Maintain clock suspend

→

Document : 1G5-0154 Rev.1 Page 14

VIS VG36128401A

Preliminary VG36128801A

VG36128161A

CMOS Synchronous Dynamic RAM

5.Mode Register (Address Input for Mode Set)

0 0 0 0 1

13 12 11 10 9 8 5432 1 0

JEDEC Standard Test Set

xx100

11 10 987 6 543 2 10

Burst Read and Single Write (for Write Through Cache)

LTMODE WT BL

x x 00 0

11 10 987 6 543210

Burst Read and Burst Write X = Don’t care

LTMODE WT BL

Burst length

Bits2 - 0 WT = 1

WT = 0

000

001

010

011

100

101

110

111

1

2

4

8

R

Full page

1

2

4

8

R

Wrap type 0

1Sequential

Interleave

Latency

Bits6 - 4 CAS Iatency

000

001

010

011

100

101

110

111

R

2

3

R

mode

Remark R : Reserved

76

0

0Reserved

13 x

x

13 12

x

12

Document : 1G5-0154 Rev.1 Page 15

VIS VG36128401A

Preliminary VG36128801A

VG36128161A

CMOS Synchronous Dynamic RAM

5.1 Burst Length and Sequence

(Burst of Two)

(Burst of Four)

(Burst of Eight)

Full page burst is an extension of the above tables of Sequential Addressing, with the length being 2048 /

1024 / 512 for 32M x 4 / 16M x 8 / 8M X16 devices, respectively.

Starting Address

(column address A0, binary) Sequential Addressing

Sequence (decimal) Interleave Addressing Sequence (decimal)

00, 1 0, 1

11, 0 1, 0

Starting Address

(column address A1 - A0, binary) Sequential Addressing

Sequence (decimal) Interleave Addressing Sequence (decimal)

00 0, 1, 2, 3 0, 1, 2, 3

01 1, 2, 3, 0 1, 0, 3, 2

10 2, 3, 0, 1 2, 3, 0, 1

11 3, 0, 1, 2 3, 2, 1, 0

Starting Address

(column address A2 - A0, binary) Sequential Addressing

Sequence (decimal) Interleave Addressing Sequence (decimal)

000 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7

001 1, 2, 3, 4, 5, 6, 7, 0 1, 0, 3, 2, 5, 4, 7, 6

010 2, 3, 4, 5, 6, 7, 0, 1 2, 3, 0, 1, 6, 7, 4, 5

011 3, 4, 5, 6, 7, 0, 1 ,2 3, 2, 1, 0, 7, 6, 5, 4

100 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3

101 5, 6 ,7, 0, 1, 2, 3, 4 5, 4, 7, 6, 1, 0, 3, 2

110 6, 7 ,0 ,1 ,2 ,3 ,4 ,5 6, 7, 4, 5, 2, 3, 0, 1

111 7, 0, 1, 2, 3, 4, 5, 6 7, 6, 5, 4, 3, 2, 1, 0

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A12 A13 Result

0 0 Select Bank A

“Activate “ command

0 1 Select Bank B

“Activate” command

1 0 Select Bank C

“Activate” command

1 1 Select Bank D

“Activate” command

0Disables Auto - Precharge (End of Burst)

1Enables Auto - Precharge (End of Burst)

(Activate command)

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13

6 Address Bits of Bank-Select and precharge

6.1 Quad banks controlled by A12 & A13

A10 A12 A13 Result

0 0 0 Precharge Bank A

0 0 1 Precharge Bank B

0 1 0 Precharge Bank C

0 1 1 Precharge Bank D

1X X Precharge All Banks

A12 A13 Result

0 0 Enables Read/Write

commands for Bank A

0 1 Enables Read/Write

commands for Bank B

1 0 Enables Read/Write

commands for Bank C

1 1 Enables Read/Write

commands for Bank D

Row

(Precharge command)

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13

(CAS strobes)

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13

Col.

Row

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CMOS Synchronous Dynamic RAM

7.Precharge

The precharge command can be asserted anytime after tRAS(min) is satisfied.

Soon after the precharge command is asserted, the precharge operation is performed and the synchronous DRAM

enters the idle state after tRP(min.) is satisfied. The parameter tRP is the time required to perform the precharge.

The earliest timing in a read cycle that a precharge command can be asserted without losing any data in the burst is

as follows.

PrechargeE

In order to write all data to the memory cell correctly, the asynchronous parameter ”tDPL” must be satis-

fied. The tDPL(min.) specification defines the earliest time that a precharge command can be asserted. The

minimum number of clocks can be calculated by dividing tDPL(min.) by the clock cycle time.

In summary, the precharge command can be asserted relative to the reference clock that indicates the

last data word is valid. In the following table, minus means clocks before the reference; plus means time

after the reference.

CAS latency Read Write

2-1 + tDPL(min.)

3-2 + tDPL(min.)

Burst lengh=4

CLK

Command

CAS latency = 2

DQ

Command

CAS latency = 3

DQ

CAS latency = 2 : One clock earlier than the last output data.

3 : Two clocks earlier than the last output data. (tRAS is satisfied)

Hi - Z

Q0 Q3

Q2

Q1

PRE

Q0 Q3Q2

Q1

Read

T0 T1 T2 T3 T4 T5 T6 T7

PRE

Hi - Z

Document : 1G5-0154 Rev.1 Page 18

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CMOS Synchronous Dynamic RAM

8.Auto Precharge

During a read or write command cycle, A10 controls whether auto precharge is selected. If A10 is high

in the read or write command (Read with Auto precharge command or Write with Auto precharge com-

mand), auto precharge is selected and begins automatically after the burst access.

In the write cycle, tDAL(min.) must be satisfied before asserting the next activate command to the bank

being precharged.

When using auto precharge in the read cycle, knowing when the precharge starts is important because

the next activate command to the bank being precharged cannot be executed until the precharge cycle

ends. Once auto precharge has started, an activate command to the bank can be asserted after tRP has

been satisfied.

A Read or Write command without auto - precharge can be terminated in the midst of a burst operation.

However, a Read or Write command with auto - precharge can not be interrupted by the same bank com-

mands before the entire burst operation is completed. Therefore use of the same bank Read, Write, Pre-

charge or Burst Stop command is prohibited during a read or write cycle with auto - precharge. It should be

noted that the device will not respond to the Auto - Precharge command if the device is programmed for full

page burst read or write cycles.

The timing when the auto precharge cycle begins depends both on both the CAS Iatency programmed

into the mode register and whether the cycle is read or write.

8.1 Read with Auto Precharge

During a READA cycle, the auto precharge begins one clock earlier (CL = 2) or two clocks earlier

(CL = 3) than the last word output.

READ with AUTO PRECHARGE

Burst lengh = 4

CLK

Command

CAS latency = 2

DQ

Command

CAS latency = 3

DQ

Remark READA means READ with AUTO PRECHARGE

Hi - Z

Auto precharge starts

QB0 QB3QB2

QB1

READA B

T0 T1 T2 T3

T4

T5 T6 T7

Auto precharge starts

Hi - Z

T8

QB0 QB3

QB2

QB1

No New Command to Bank B

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CMOS Synchronous Dynamic RAM

8.2 Write with Auto Precharge

During a write cycle, the auto precharge starts at the timing that is equal to the value of tDPL(min.)

after the last data word input to the device.

WRITE with AUTO PRECHRGE

In summary, the auto precharge cycle begins relative to a reference clock that indicates the last data

word is valid.

In the table below, minus means clocks before the reference; plus means clocks after the reference.

CAS latency Read Write

2-1 + tDPL(min.)

3-2 + tDPL(min.)

Burst lengh = 4

CLK

Command

CAS latency = 2

DQ

Command

CAS latency = 3

DQ

Remark WRITA means WRITE with AUTO Precharge

Hi - Z

DB0 DB3DB2

DB1

WRITA B

T0 T1 T2T3 T4 T5 T6 T7

Hi - Z_

T8

tDPL

DB0 DB3

DB2

DB1

AUTO PRECHARGE starts

No New Command to Bank B

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8.3 Multibank Operation- Read with Auto Precharge

During a READA cycle interrupted by a Read, Write command of another banks, the auto-pre-

charge scheduled time would not be changed.

CLK

Command

CAS latency=2

DQ

Command

CAS latency=3

DQ

Hi-Z

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14

READA A Read B

Burst lengh=8

Auto precharge bank A starts

QA0 QA1 QB0 QB2 QB3 QB4 QB5 QB6 QB7 QB1

Read B

Auto precharge bank A starts

Hi-Z

QA0 QA1 QB0 QB2 QB3 QB4 QB5 QB6 QB7 QB1

READA A

Multibank Operation

Similiar top.21

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CMOS Synchronous Dynamic RAM

8.4 Multibank Operation- Write with Auto Precharge

During a WRITEA cycle interrupted by a Read, Write command of another banks, the auto-pre-

charge scheduled time would not be changed.

CLK

Command

CAS latency=2

DQ

Command

CAS latency=3

DQ

Hi-Z

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10

Burst lengh=8

Auto precharge bank A starts

WRITA A Read B

DA0 DA1 DB0 DB1 DB2 DB3 DB4 DB5

Hi-Z

Auto precharge bank A starts

WRITA A Read B

DA0 DA1 DB0 DB1 DB2 DB3 DB4

CLK

Command

CAS latency=2

DQ

Command

CAS latency=3

DQ

Hi-Z

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11

Burst lengh=8

Auto precharge bank A starts

WRITA A Write B

DA0 DA1 DB0 DB1 DB2 DB3 DB4 DB6 DB7

Hi-Z

Auto precharge bank A starts

WRITA A Write B

DA0 DA1 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7

DB5

Multibank Operation

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9.Read/Write Command Interval

9.1 Read to Read command interval

During a read cycle when a new read command is asserted, it will be effective after the CAS latency,

even if the previous read operation has not completed. READ will be interrupted by another READ.

Each read command can be asserted in every clock without any restriction.

Burst lengh=4, CAS latency=2

CLK

Command

DQ

QA0 QB2QB1

QB0

Read A

T0 T1 T2 T3 T4 T5 T6 T7

Hi-Z_

T8

1 cycle

QB3

Read B

Burst lengh=4, CAS latency=2

CLK

Command

DQ QA0 QB2QB1

QB0

Write A

T0 T1 T2 T3 T4 T5 T6 T7

Hi-Z_

T8

1 cycle

QB3

Write B

WRITE to WRITE Command Interval

9.2 Write to Write Command Interval

During a write cycle, when a new Write command is asserted, the previous burst will terminated and the

new burst will begin with a new write command. WRITE will be interrupted by another WRITE.

Each write command can be asserted in every clock without any restriction.

READ to READ Command Interval

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CMOS Synchronous Dynamic RAM

9.3 Write to Read Command Interval

The write command to read command interval is also a minimum of 1 cycle. Only the write data before

the read command will be written. The data bus must be Hi-Z at least one cycle prior to the first DOUT.

WRITE to READ Command Interval

9.4 Read to Write Command Interval

During a read cycle, READ can be interrupted by WRITE.

DQM must be in High at least 3 clocks prior to the write command. There is a restriction to avoid a data

conflict. The data bus must be Hi-Z using DQM before Write.

Burst lengh=4

CLK

Command

CAS latency=2

DQ

Command

CAS latency=3

DQ

QB0 QB3QB2

QB1

WRITE A

Write A

T0 T1 T2 T3 T4 T5 T6 T7 T8

QB0 QB3

QB2

QB1

1 cycle

Read B

DA0

Read B

DA0 Hi-Z

Hi-Z

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CMOS Synchronous Dynamic RAM

READ to WRITE Command Interval

CAS latency=2

CLK

Command

DQM

DQ Hi-Z D0 D3D2

D1

Read

T0 T1 T2 T3 T4 T5 T6 T7 T8

1 cycle

Write

Burst length=8, CAS latency=2

CLK

Command

DQM

DQ Q0

Read

T0 T1 T2 T3 T4 T5 T6 T7 T8

Write

T9

necessary

Q2

Q1 D0 D2

D1

Hi-Z is

example: Burst length=4, CAS latency=3

CLK

Command

DQM

DQ

Read

T0 T1 T2 T3 T4 T5 T6 T7 T8

Write

necessary

D0 D2

D1

Hi-Z is

Q2

The minimum command interval = (4+1) cycles

Document : 1G5-0154 Rev.1 Page 25

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10.BURST Termination

There are two methods to terminate a burst operation other than using a read or a write command.

One is the burst stop command and the other is the precharge command.

10.1 BURST Stop Command

During a read burst. when the burst stop command is asserted, the burst read data are termi-

nated and the data bus goes to high-impedance after the CAS latency from the burst stop com-

mand.

During a write burst, when the burst stop command is asserted, any data provided at that cycle

will not be written. The burst write is effectively terminated and no further data can be written until a

new write command is asserted.

Burst Termination

Remark BST: Burst stop command

Remark BST: Burst command

Burst lengh=X, CAS Intency=2,3

CLK

Command

CAS latency=2

DQ

CAS latency=3

DQ

Q0 Q2

Q1

Read

T0 T1 T2 T3 T4 T5 T6 T7

BST

Hi-Z

Q0 Q2

Q1 Hi-Z

Burst lengh=X, CAS latency=2,3

CLK

Command

CAS latency=2,3

DQ Q0 Q2

Q1

Write

T0 T1 T2 T3 T4 T5 T6 T7

BST

Hi-Z_

Q0

Document : 1G5-0154 Rev.1 Page 26

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CMOS Synchronous Dynamic RAM

10.2 PRECHARGE TERMINATION

10.2.1 PRECHARGE TERMINATION in READ Cycle

During READ cycle, the burst read operation is terminated by a precharge command. When the

precharge command is asserted, the burst read operation is terminated and precharge starts.

The same bank can be activated again after tRP from the precharge command.

When CAS latency is 2,the read data will remain valid until one clock after the precharge com-

mand.

When CAS latency is 3, the read data will remain valid until two clocks after the precharge com-

mand.

Precharge Termination in READ Cycle

Burst lengh= X

CLK

Command

CAS latency=2

DQ Hi-Z

Read

T0 T1 T2 T3 T4 T5 T6 T7 T8

tRP

PRE ACT

DQ

Read PRE ACT

tRP

CAS latency=3

Q0 Q3

Q2

Q1 Hi-Z

Q0 Q3

Q2

Q1

command

Document : 1G5-0154 Rev.1 Page 27

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CMOS Synchronous Dynamic RAM

10.2.2 Precharge Termination in WRITE Cycle

During WRITE cycle, the burst write operation is terminated by a precharge com-

mand. When the precharge command is asserted, the burst write operation is termi-

nated and precharge starts.

The same bank can be activated again after tRP from the precharge command. The

DQM must be high to mask invalid data in.

During WRITE cycle, the write data written prior to the precharge command will be

correctly stored. However, invalid data may be written at the same clock as the pre-

charge command. To prevent this from happening, DQM must be high at the same

clock as the precharge command. This will mask the invalid data.

PRECHARGE TERMINATION in WRITE Cycle

Burst lengh = X

CLK

Command

CAS latency = 2

DQM

Hi - Z

Write

T0 T1 T2 T3 T4 T5 T6 T7 T8

t

RP

PRE ACT

DQ

Write PRE ACT

t

RP

CAS latency = 3

Hi - Z

D0 D3

D2

D1

D0 D3

D2

D1

DQM

D4

command

DQ

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,

Timing Diagram

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T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10

Mode Register Set

CLK

CKE

CS

RAS

CAS

WE

BS

A10

ADD

DQM

DQ

Command

Mode Register

Set

Command

All Banks

Precharge Command

tRP

tRSC

Hi-Z

Address Key

Document : 1G5-0154 Rev.1 Page 30

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T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

t

CH

t

CL

t

CKS

t

CMS

t

CMH

tAS tAH

Begin Auto Precharge

Bank A Begin Auto Precharge

Bank B t

CKH

t

CK2

AC Parameters for Write Timing (1 of 2)

CLK

CKE

CS

RAS

CAS

WE

BS

A10

ADD

DQM

DQ

tRCD

tRRD

tRC

tDAL

QAa0 QAa1 QAa2 QAa3 QBa0 QBa1 QBa2 QBa3 QAb0 QAb1 QAb2 QAb3

Activate

Command

Bank A

Write with

Auto Precharge

Command

Bank A

Activate

Command

Bank B

Write with

Auto Precharge

Command

Bank B

Activate

Command

Bank A

Write without

Auto Precharge

Command

Bank A

tDS

tDH tDPL RP

t

Precharge

Command

Bank A

Activate

Command

Bank A

Burst Length=4, CAS Latency=2

(Bank D)

Activate

Command

Bank B

(Bank D)

Document : 1G5-0154 Rev.1 Page 31

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T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23

t

CH

t

CL

t

CKS

t

CMS

t

CMH

tAS tAH

Begin Auto Precharge

Bank A Begin Auto Precharge

Bank B t

CKH

t

CK3

AC Parameters for Write Timing (2 of 2)

CLK

CKE

CS

RAS

CAS

WE

BS

A10

ADD

DQM

DQ

tRCD

tRRD

t

RC

tDAL

QAa0 QAa1 QAa2 QAa3 QBa0 QBa1 QBa2 QBa3 QAb0 QAb1 QAb2 QAb3

Activate

Command

Bank A

Write with

Auto Precharge

Command

Bank A

Activate

Command

Bank B

Write with

Auto Precharge

Command

Bank B

Activate

Command

Bank A

Write without

Auto Precharge

Command

Bank A

tDS

tDH

tDPL RP

t

Precharge

Command

Bank A

Activate

Command

Bank A

Burst Length=4, CAS Latency=3,4

(Bank D) (Bank D)

(Bank D)

Document : 1G5-0154 Rev.1 Page 32

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T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13

AC Parameters for Read Timing (1 of 2)

CLK

CKE

CS

RAS

CAS

WE

BS

A10

ADD

DQM

DQ

Burst Length=2, CAS Latency=2

tCH tCL tCK2

Begin Auto

Precharge

Bank B

tCKH

tCKS

tCMS

tCMH

tAH

tAS

tRRD tRAS tRC

tRCD

tAC2

tLZ tOH

tAC2 tOH

tHZ tRP tHZ

Hi-Z

Activate

Command

Bank A

Read

Command

Bank A

Activate

Command

Bank B

Read with

Auto Precharge

Bank B

Precharge

Command

Bank A

Activate

Command

Bank A

QAa0 QAa1 QBa0 QBa1

(Bank D) (Bank D)

(Bank D)

Command

Document : 1G5-0154 Rev.1 Page 33

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CMOS Synchronous Dynamic RAM

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15

AC Parameters for Read Timing (2 of 2)

CLK

CKE

CS

RAS

CAS

WE

BS

A10

ADD

DQM

DQ

Burst Length=2, CAS Latency=3

tLZ tHZ

Hi-Z

Activate

Command

Bank A

Read

Command

Bank A

Activate

Command

Bank B

Read with

Auto Precharge

Bank B

Precharge

Command

Bank A

Activate

Command

Bank A

tCHtCL

tCKS

tCK3

tCMS

tCMH

tAH

tAS

tRRD tRAS tRC

tRP

tRCD

tAC3 tOH

tAC3

QAa0 QAa1 QBa0 QBa1

tOH

tHZ

Command

tCKH

Begin Auto

Precharge

Bank B (Bank D)

(Bank D) (Bank D)

Document : 1G5-0154 Rev.1 Page 34

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CMOS Synchronous Dynamic RAM

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

Power on Sequence and Auto Refresh (CBR)

CLK

CKE

CS

RAS

CAS

WE

BS

A10

ADD

DQM

DQ

High level

is required Minimum of 2 Refresh Cycles are required tRSC

tRP

High Level is Necessary

tRC

Address Key

Inputs

be stable

for 100us

Precharge

All Banks

must Command 1st Auto

Command

Refresh 2nd Auto

Refresh

Command

Mode

Set Command Command

Register

Hi-Z

Document : 1G5-0154 Rev.1 Page 35

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T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

Clock Suspension During Burst Read (Using CKE) (1 of 2)

CLK

CKE

CS

RAS

CAS

WE

BS

A10

ADD

DQM

DQ

tHZ

Activate

Bank A

Command Read

Bank A

Command Clock

2 Cycles

Hi-Z

QAa0 QAa1 QAa2 QAa3

RAa CAa

RAa

tCK2

Clock

Suspended

1 Cycle Suspended Clock

3 Cycles

Suspended

Burst Length=4, CAS Latency=2

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CMOS Synchronous Dynamic RAM

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

Clock Suspension During Burst Read (Using CKE) (2 of 2)

CLK

CKE

CS

RAS

CAS

WE

BS

A10

ADD

DQM

DQ

tHZ

Activate

Bank A

Command Read

Bank A

Command Clock

2 Cycles

Hi-Z

QAa0 QAa1 QAa2 QAa3

RAa

tCK3

Clock

Suspended

1 Cycles Suspended Clock

3 Cycles

Suspended

Burst Length=4, CAS Latency=3

CAa

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T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

Clock Suspension During Burst Write (Using CKE) (1 of 2)

CLK

CKE

CS

RAS

CAS

WE

BS

A10

ADD

DQM

DQ

Activate

Bank A

Command Write

Bank A

Command

Clock

2 Cycles

Hi-Z

RAa CAa

RAa

tCK2

Clock

Suspended

1 Cycle Suspended Clock

3 Cycles

Suspended

Burst Length=4, CAS Latency=2

DAa0 DAa1 DAa2 DAa3

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T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

Clock Suspension During Burst Write (Using CKE) (2 of 2)

CLK

CKE

CS

RAS

CAS

WE

BS

A10

ADD

DQM

DQ

RAa

tCK

Burst Length=4, CAS Latency=3

CAa

Activate

Bank A

Command Write

Bank A

Command

Clock

2 Cycles

Hi-Z

Clock

Suspended

1 Cycle Suspended Clock

3 Cycles

Suspended

DAa0 DAa1 DAa2 DAa3

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VG36128161A

CMOS Synchronous Dynamic RAM

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

Power Down Mode and Clock Mask

CLK

CKE

CS

RAS

CAS

WE

BS

A10

ADD

DQM

DQ

RAa

tCK2

Burst Length=4, CAS Latency=2

Activate

Bank A

Command

Power Down

Mode Entry Power Down

Bank A

Hi-Z

ACTIVE

STANDBY Read

Clock Mask

CAa

tCKS

tCKH

VALID

tCKS

RAa

QAa0 QAa1 QAa2 QAa3

Mode Exit

Command

Start Clock Mask

End

tHZ

Precharge

Command

Power Down

Mode Entry

Precharge

Standby Power

Mode

Down

Exit Command

CLK can be Stopped

*

Document : 1G5-0154 Rev.1 Page 40

VIS VG36128401A

Preliminary VG36128801A

VG36128161A

CMOS Synchronous Dynamic RAM

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

Auto Refresh (CBR)

CLK

CKE

CS

RAS

CAS

WE

BS

A10

ADD

DQM

DQ

tCK2

Burst Length=4, CAS Latency=2

Precharge

All Banks

Command CBR Refresh

Hi-Z

CBR Refresh

Command

Activate

Command Read

RAa

CAa

RAa

Q0 Q1 Q2 Q3

Command Command

tRP tRC tRC

Document : 1G5-0154 Rev.1 Page 41

VIS VG36128401A

Preliminary VG36128801A

VG36128161A

CMOS Synchronous Dynamic RAM

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

Self Refresh (Entry and Exit)

CLK

CKE

CS

RAS

CAS

WE

BS

A10

ADD

DQM

DQ

tSRX

All Banks Self refresh

Hi-Z

Self Refresh

Exit Self Refresh

Entry Exit

tRC

tCKS

tSRX tCKS

tRC

must be idle Self Refresh

Entry Activate

Command

CLK can be Stopped

*

* Clock can be stopped at CKE=Low. If clock is stopped, it must be restarted/stable for 4 clock cycles before CKE=High

Document : 1G5-0154 Rev.1 Page 42

VIS VG36128401A

Preliminary VG36128801A

VG36128161A

CMOS Synchronous Dynamic RAM

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

Random Column Read (Page Within same Bank)(1 of 2)

CLK

CKE

CS

RAS

CAS

WE

BS

A10

ADD

DQM

DQ

tCK2

Burst Length=4, CAS Latency=2

Precharge

Bank A

Command Read

Hi-Z

Activate Read

RAa

QAd0

Command Command

RAa CAa

RAa

CAb CAc

RAd

RAd CAd

QAa0 QAa1 QAa2 QAa3 QAb0 QAb1 QAc0 QAc1 QAc2 QAc3 QAd1 QAd2 QAd3

Bank A

Read

Command

Bank A

Read

Command

Bank A

Precharge

Command

Bank A Bank A Command

Bank A

Document : 1G5-0154 Rev.1 Page 43

VIS VG36128401A

Preliminary VG36128801A

VG36128161A

CMOS Synchronous Dynamic RAM

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

Random Column Read (Page Within same Bank)(2 of 2)

CLK

CKE

CS

RAS

CAS

WE

BS

A10

ADD

DQM

DQ

tCK3

Burst Length=4, CAS Latency=3

Activate

Bank A

Command Read

Hi-Z

Activate Read

Command Command

RAa CAa CAb CAc RAd CAd

QAc2 QAc3

QAa0 QAa1 QAa2 QAa3 QAb0 QAb1 QAc0 QAc1

Bank A

Read

Command

Bank A

Precharge

Command

Bank A Bank A Command

Bank A

RAd

Read

Command

Bank A

RAa

Document : 1G5-0154 Rev.1 Page 44

VIS VG36128401A

Preliminary VG36128801A

VG36128161A

CMOS Synchronous Dynamic RAM

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

Random Column Write (Page Within same Bank) (1 of 2)

CLK

CKE

CS

RAS

CAS

WE

BS

A10

ADD

DQM

DQ

tCK2

Burst Length=4, CAS Latency=2

Activate

Bank B

Command Write

Hi-Z

Activate Write

Command Command

Ra Ca

Ra

Cb Cc Rd Cd

Dc2 Dc3

Da1 Da2 Da3 Db0 Db1 Dc0 Dc1

Bank B

Write

Command

Bank B

Precharge

Command

Bank B Bank B Command

Bank B

Write

Command

Bank B

Rd

Dd2 Dd3

Dd0 Dd1

Da0

(Bank D) (Bank D) (Bank D) (Bank D) (Bank D) (Bank D) (Bank D)

Document : 1G5-0154 Rev.1 Page 45

VIS VG36128401A

Preliminary VG36128801A

VG36128161A

CMOS Synchronous Dynamic RAM

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

Random Column Write (Page Within same Bank) (1 of 2)

CLK

CKE

CS

RAS

CAS

WE

BS

A10

ADD

DQM

DQ

tCK

Burst Length=4, CAS Latency=3

Activate

Bank B

Command Write

Hi-Z

Activate

Command

Ra Ca

Ra

Cb Cc Cd

Rd

Bank B

Write

Command

Bank B

Precharge

Command

Bank B Command

Bank B

Write

Command

Bank B

Rd

Write

Command

Bank B

Dc2 Dc3

Da1 Da2 Da3 Db0 Db1 Dc0 Dc1

Da0 Dd0 Dd1

(Bank D) (Bank D) (Bank D) (Bank D) (Bank D) (Bank D) (Bank D)

Document : 1G5-0154 Rev.1 Page 46

VIS VG36128401A

Preliminary VG36128801A

VG36128161A

CMOS Synchronous Dynamic RAM

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

Random Row Read (Interleaving Banks)(1 of 2)

CLK

CKE

CS

RAS

CAS

WE

BS

A10

ADD

DQM

DQ

tCK2

Burst Length=8, CAS Latency=2

Activate

Bank B

Command Read

Hi-Z

Command

QAa0 QAa1

QBa1 QBa2 QBa3 QBa4 QBa5 QBa6 QBa7

Bank B

Activate

Command

Bank A

Active

Command

Bank B

Read

Command

Bank A

QBb1

QBb0QBa0

Read

Command

Bank B

QAa3 QAa4 QAa5 QAa6 QAa7

QAa2

Precharge

Command

Bank B

tRCD tAC2 tRP

High

(Bank D) (Bank D) (Bank D) (Bank D) (Bank D)

Document : 1G5-0154 Rev.1 Page 47

VIS VG36128401A

Preliminary VG36128801A

VG36128161A

CMOS Synchronous Dynamic RAM

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

Random Row Read (Interleaving Banks) (2 of 3)

CLK

CKE

CS

RAS

CAS

WE

BS

A10

ADD

DQM

DQ

tCK3

Burs tLength=8, CAS Latency=3

Activate

Bank B

Command Read

Hi-Z

Command

QAa0 QAa1

QBa1 QBa2 QBa3 QBa4 QBa5 QBa6 QBa7

Bank B

Activate

Command

Bank A

Precharge

Command

Bank B

QBb0QBa0

Read

Command

Bank B

QAa3 QAa4 QAa5 QAa6 QAa7

QAa2

Read

Command

Bank A

tRCD tAC3 tRP

High

Activate

Bank B

Command Precharge

Command

Bank A

(Bank D) (Bank D) (Bank D) (Bank D) (Bank D)

Document : 1G5-0154 Rev.1 Page 48

VIS VG36128401A

Preliminary VG36128801A

VG36128161A

CMOS Synchronous Dynamic RAM

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

Random Row Write (Interleaving Banks) (1 of 2)

CLK

CKE

CS

RAS

CAS

WE

BS

A10

ADD

DQM

DQ

tCK2

Burst Length=8, CAS Latency=2

Activate

Bank A

Command Write

Hi-Z

Command

QBa0 QBa1

QAa1 QAa2 QAa3 QAa4 QAa5 QAa6 QAa7

Bank A

Activate

Command

Bank B

Active

Command

Bank A

Write

Command

Bank B

QAb3

QAb2QAa0

Write

Command

Bank A

QBa3 QBa4 QBa5 QBa6 QBa7

QBa2

Precharge

Command

Bank A

tRCD tRP

High

tDPL tDPL

QAb0 QAb1 QAb4

Precharge

Command

Bank B

(Bank D)

(Bank D) (Bank D)

Document : 1G5-0154 Rev.1 Page 49

VIS VG36128401A

Preliminary VG36128801A

VG36128161A

CMOS Synchronous Dynamic RAM

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

Random Row Write (Interleaving Banks) (2 of 2)

CLK

CKE

CS

RAS

CAS

WE

BS

A10

ADD

DQM

DQ

tCK

Burst Length=8, CAS Latency=3

Activate

Bank A

Command Write

Hi-Z

Command

QAa7 QBa0

QAa0 QAa1 QAa2 QAa3 QAa4 QAa5 QAa6

Bank A

Activate

Command

Bank B

QAb2

QAb1

Activate

Command

Bank A

QBa2 QBa3 QBa4 QBa5 QBa6

QBa1

Write

Command

Bank B

RBa

tRCD tRP

High

tDPL tDPL

QBb7 QAb0 QAb3

Write

Command

Bank A

Precharge

Command

Bank A

Precharge

Command

Bank B

(Bank D) (Bank D) (Bank D)

Document : 1G5-0154 Rev.1 Page 50

VIS VG36128401A

Preliminary VG36128801A

VG36128161A

CMOS Synchronous Dynamic RAM

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

Read and Write Cycle (1 of 2)

CLK

CKE

CS

RAS

CAS

WE

BS

A10

ADD

DQM

DQ

tCK2

Burst Length=4, CAS Latency=2

Activate

Bank A

Command Write

Hi-Z

Command

DAb3 QAc0

QAa0 QAa1 QAa2 QAa3 DAb0 DAb1

Bank A

Write

Command

Bank A

Read

Command

Bank A

QAc3

QAc1

The Read Data

The Write Data

is Masked with a

Zero Clock

RAa

RAa CAb CAc CAa

latency

is Masked with

Two Clocks

Latency

Document : 1G5-0154 Rev.1 Page 51

VIS VG36128401A

Preliminary VG36128801A

VG36128161A

CMOS Synchronous Dynamic RAM

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

Read and Write Cycle (2 of 2)

CLK

CKE

CS

RAS

CAS

WE

BS

A10

ADD

DQM

DQ

tCK3

Burst Length=4, CAS Latency=3

Activate

Bank A

Command Read

Hi-Z

Command

DAb3 QAc0

QAa0 QAa1 QAa2 QAa3 DAb0 DAb1

Bank A

Write

Command

Bank A

QAc3

QAc1

The Read Data

The Write Data

is Masked with a

Zero Clock

RAa

Latency

is Masked with

a Two Clock

Latency

RAa

CAb

CAa CAc

Read

Command

Bank A

Document : 1G5-0154 Rev.1 Page 52

VIS VG36128401A

Preliminary VG36128801A

VG36128161A

CMOS Synchronous Dynamic RAM

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

Interleaved Column Read Cycle (1 of 2)

CLK

CKE

CS

RAS

CAS

WE

BS

A10

ADD

DQM

DQ

tCK2

Burst Length=4, CAS Latency=2

Activate

Bank A

Command Read

Hi-Z

Command

QBb1 QBd0

QAa0 QAa1 QAa2 QAa3 QBa0 QBa1

Bank A

Read

Command

Bank B

QBd2

QBd1

Precharge

Ra Ra

Ra Cb Ra Ca Cb Cc Cb Cd

QAb1

QBc0 QBc1 QBd3

Activate

Command

Bank B

Read

Command

Bank B

QBb0 QAb0

Read

Command

Bank B

Read

Command

Bank A

Read

Command

Bank B

Precharge

Command

Bank A

Command

Bank B

tRCD tAC2

(Bank D) (Bank D) (Bank D) (Bank D) (Bank D) (Bank D)

Document : 1G5-0154 Rev.1 Page 53

VIS VG36128401A

Preliminary VG36128801A

VG36128161A

CMOS Synchronous Dynamic RAM

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

Interleaved Column Read Cycle (2 of 2)

CLK

CKE

CS

RAS

CAS

WE

BS

A10

ADD

DQM

DQ

tCK3

Burst Length=4, CAS Latency=3

Activate

Bank A

Command

Hi-Z QBb1 QAb2

QAa0 QAa1 QAa2 QAa3 QBa0 QBa1 QAb3

Precharge

Ra Ra

Ra Ca Ra Ca Cb Cc Cb

QAb1

QBc0 QBc1

Read

Command

Bank A

Read

Command

Bank B

QBb0 QAb0

Read

Command

Bank B

Read

Command

Bank B

Read

Command

Bank A

Precharge

Command

Bank B Command

Bank A

tRRD

Activate

Command

Bank B

tRCD tAC3

(Bank D)

(Bank D) (Bank D) (Bank D) (Bank D)

Document : 1G5-0154 Rev.1 Page 54

VIS VG36128401A

Preliminary VG36128801A

VG36128161A

CMOS Synchronous Dynamic RAM

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

Interleaved Column Write Cycle (1 of 2)

CLK

CKE

CS

RAS

CAS

WE

BS

A10

ADD

DQM

DQ

tCK2

Burst Length=4, CAS Latency=2

Activate

Bank A

Command

Hi-Z DBb1 DBd0

DAa0 DAa1 DAa2 DAa3 DBa0 DBa1 DBd1

Precharge

Ra Ra

Ra Ca Ra Ca Cb Cc Cb

DAb1

DBc0 DBc1

Write

Command

Bank A

Write

Command

Bank B

DBb0 DAb0

Command Write

Command

Bank B

Write

Command

Bank A

Precharge

Command

Bank A Command

Bank B

tRRD

Activate

Command

Bank B

tRCD tRP

Cb

DBd2 DBd3

Write

Bank B

tDPL

Write

Command

Bank B

(Bank D) (Bank D) (Bank D) (Bank D)

(Bank D)

Document : 1G5-0154 Rev.1 Page 55

VIS VG36128401A

Preliminary VG36128801A

VG36128161A

CMOS Synchronous Dynamic RAM

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

Interleaved Column Write Cycle (2 of 2)

CLK

CKE

CS

RAS

CAS

WE

BS

A10

ADD

DQM

DQ

tCK

Burst Length=4, CAS Latency=3

Activate

Bank A

Command

Hi-Z QBb1 QBd0

QAa0 QAa1 QAa2 QAa3 QBa0 QBa1 QBd1

Precharge

Ra Ra

Ra Ca Ra Ca Cb Cc Cb

QAb1

QBc0 QBc1

Write

Command

Bank A

Write

Command

Bank B

QBb0 QAb0

Write

Command

Bank B

Write

Command

Bank B

Write

Command

Bank A

Write

Command

Bank B

Command

Bank A

tRRD

Activate

Command

Bank B

tRCD

Cd

tDPL

tRP

QBd2 QBd3

tDPL

Precharge

Command

Bank B

(Bank D)

(Bank D) (Bank D) (Bank D) (Bank D) (Bank D)

Document : 1G5-0154 Rev.1 Page 56

VIS VG36128401A

Preliminary VG36128801A

VG36128161A

CMOS Synchronous Dynamic RAM

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

Auto Precharge after Read Burst (1 of 2)

CLK

CKE

CS

RAS

CAS

WE

BS

A10

ADD

DQM

DQ

tCK2

Burst Length=4, CAS Latency=2

Activate

Bank A

Command

Hi-Z QBa3 QBb0

QAa0 QAa1 QAa2 QAa3 QBa0 QBa1 QBb1

Read with

Ra Ra

Ca Ra Ca Cb Rb Cb

QAb3

QAb0 QAb1

Activate

Command

Bank B

QBa2 QAb2

Read with

Command

Bank A Activate

Command

Bank B

Read with

Command

Bank B

Activate

Command

Bank A

Command

Bank A

Read with

Auto Precharge

Bank B

Rc

QBb2 QBb3

Rb Rc

Ra Cc

QAc0 QAc2

Read

Bank A

Command Command

QAc1

Auto Precharge

Start Auto Precharge

Bank B Start Auto Precharge

Bank A Start Auto Precharge

Bank B

High (Bank D) (Bank D)

(Bank D) (Bank D)

Document : 1G5-0154 Rev.1 Page 57

VIS VG36128401A

Preliminary VG36128801A

VG36128161A

CMOS Synchronous Dynamic RAM

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

Auto Precharge after Write Burst (2 of 2)

CLK

CKE

CS

RAS

CAS

WE

BS

A10

ADD

DQM

DQ

tCK3

Burst Length=4, CAS Latency=3

Activate

Bank A

Command

Hi-Z QBa3

QAa0 QAa1 QAa2 QAa3 QBa0 QBa1

Ra Ra

Ra

QAb3

QAb0 QAb1

Read

Command

Bank A

Read with

Command

Bank B

QBa2 QAb2

Command

Bank A

Activate

Command

Bank B

QBb0

Ra Ca

Ca RBb

Cb

Auto Precharge

Start Auto Precharge

Bank B Start Auto

Bank A

Start Auto Precharge

Bank B

High

Rb

Cb

QBb1 QBb2

Activate

Command

Bank B

Write with

Auto Precharge Auto precharge

Command

Bank B

(Bank D) (Bank D) (Bank D) (Bank D)

Read with

Rb

Precharge

(Bank D) (Bank D)

Document : 1G5-0154 Rev.1 Page 58

VIS VG36128401A

Preliminary VG36128801A

VG36128161A

CMOS Synchronous Dynamic RAM

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

Auto Precharge after Write Burst (1 of 2)

CLK

CKE

CS

RAS

CAS

WE

BS

A10

ADD

DQM

DQ

tCK2

Burst Length=4, CAS Latency=2

Activate

Bank A

Command

Hi-Z QBa3 QBb0

QAa0 QAa1 QAa2 QAa3 QBa0 QBa1 QBb1

Ra Ra

Ra

QAb3

QAb0 QAb1

Write

Command

Bank A

Write with

Command

Bank B

QBa2 QAb2

Write with

Command

Bank A

Activate

Command

Bank B

Write with

Command

Bank B

Activate

Command

Bank B

QBb2 QBb3

Rb

Ra Ca Cb Ca Rb

Cb

Auto Precharge Auto Precharge

Auto Precharge

Start Auto Precharge

Bank B Start Auto Precharge

Bank A Start Auto Precharge

Bank B

High

Rc

Rc Cc

QAc0 QAc1 QAc2 QAc3

Activate

Command

Bank A Write with

Auto Precharge

Bank A

Start Auto

Precharge

Bank A

(Bank D) (Bank D) (Bank D)

(Bank D)

(Bank D) (Bank D)

Document : 1G5-0154 Rev.1 Page 59

VIS VG36128401A

Preliminary VG36128801A

VG36128161A

CMOS Synchronous Dynamic RAM

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

Auto Precharge after Write Burst (2 of 2)

CLK

CKE

CS

RAS

CAS

WE

BS

A10

ADD

DQM

DQ

tCK

Burst Length=4, CAS Latency=3

Activate

Bank A

Command

Hi-Z QBa3

QAa0 QAa1 QAa2 QAa3 QBa0 QBa1

Ra Ra

Ra

QAb3

QAb0 QAb1

Read

Command

Bank A

Read with

Command

Bank B

QBa2 QAb2

Command

Bank A

Activate

Command

Bank B

QBb0

Ra Ca

Ca RBb

Cb

Auto Precharge

Start Auto Precharge

Bank B Start Auto

Bank A

Start Auto Precharge

Bank B

High

Rb

Cb

QBb1 QBb2

Activate

Command

Bank B

Write with

Auto Precharge Auto precharge

Command

Bank B

(Bank D) (Bank D) (Bank D) (Bank D)

Read with

Rb

Precharge

QBb3

(Bank D)

Document : 1G5-0154 Rev.1 Page 60

VIS VG36128401A

Preliminary VG36128801A

VG36128161A

CMOS Synchronous Dynamic RAM

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

Full Page Read Cycle (1 of 2)

CLK

CKE

CS

RAS

CAS

WE

BS

A10

ADD

DQM

DQ

tCK2

Burst Length=Full Page, CAS Latency=2

Activate

Bank A

Command Read

Hi-Z

Command

Ra

QAa+1

Bank A

The burst counter wraps Burst Stop

Read

Command

Bank B

QAa

Full page burst operation does not

Ra Ca Rb

tRP

High

Activate

Command

Bank B

Ra Rb

Ca

QAa+2 QAa-2 QAa-1 QAa QAa+1 QBa QBa+1 QBa+2 QBa+3 QBa+4 QBa+51QBa+6

Activate

Command

Bank B

from the highest order

page address back to zero

during this time interval

terminate when the burst length is

satisfied; the burst counter

increments and continues bursting

beginning with the starting address

Command

Precharge

Command

Bank B

Ra

(Bank D) (Bank D) (Bank D) (Bank D)

Document : 1G5-0154 Rev.1 Page 61

VIS VG36128401A

Preliminary VG36128801A

VG36128161A

CMOS Synchronous Dynamic RAM

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

Full Page Read Cycle (2 of 2)

CLK

CKE

CS

RAS

CAS

WE

BS

A10

ADD

DQM

DQ

tCK3

Burst Length=Full Page, CAS Latency=3

Activate

Bank A

Command Read

Hi-Z

Command

Ra

QAa+1

Bank A

The burst counter wraps Burst Stop

Read

Command

Bank B

QAa

Full page burst operation

Ra Ca Rb

High

Activate

Command

Bank B

Ra Rb

Ca

QAa+2 QAa-2 QAa-1 QAa QAa+1 QBa0 QBa+1 QBa+2 QBa+3 QBa+4 QBa+5

Activate

Command

Bank B

from the highest order

page address back to zero

during this time interval

Command

Precharge

Command

Bank B

does not teminate when

the burst length is satisfied;

the burst counter increments

and continues bursting

beginning with the starting

address

Ra

(Bank D) (Bank D) (Bank D) (Bank D)

Document : 1G5-0154 Rev.1 Page 62

VIS VG36128401A

Preliminary VG36128801A

VG36128161A

CMOS Synchronous Dynamic RAM

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

Full Page Write Cycle (1 of 2)

CLK

CKE

CS

RAS

CAS

WE

BS

A10

ADD

DQM

DQ

tCK2

Burst Length=Full Page, CAS Latency=2

Activate

Bank A

Command Write

Hi-Z

Command

Ra

QAa+1

Bank A

The burst counter wraps Burst Stop

Write

Command

Bank B

QAa

Full page burst operation

Ra Ca Rb

tBDL

High

Activate

Command

Bank B

Ra Rb

Ca

QAa+2 QAa+3 QAa-1 QAa QAa+1 QBa QBa+1 QBa+2 QBa+3 QBa+4 QBa+5

Activate

Command

Bank B

from the highest order

page address back to zero

during this time interval

Command

Precharge

Command

Bank B

does not terminate when

the burst length is satisfied;

the burst counter increments

and continues bursting

beginning with the starting

address

QBa+6

Data is ignored

Ra

(Bank D) (Bank D) (Bank D) (Bank D)

Document : 1G5-0154 Rev.1 Page 63

VIS VG36128401A

Preliminary VG36128801A

VG36128161A

CMOS Synchronous Dynamic RAM

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

Full Page Write Cycle (2 of 2)

CLK

CKE

CS

RAS

CAS

WE

BS

A10

ADD

DQM

DQ

tCK

Burst Length=Full Page, CAS Latency=3

Activate

Bank A

Command Write

Hi-Z

Command

Ra

DAa+1

Bank A The burst counter wraps Burst Stop

Write

Command

Bank B

DAa

Full page burst operation

Ra

tBDL

High

Activate

Command

Bank B

DAa+2 DAa+3 DAa-1 DAa DAa+1 DBa DBa+1 DBa+2 DBa+3 DBa+4 DBa+5

Activate

Command

Bank B

from the highest order

page address back to zero

during this time interval Command

Precharge

Command

Bank B

does not terminate when

the burst length is satisfied;

the burst counter increments

and continues bursting

beginning with the starting

address

Ra Rb

Ca Ra Ca Rb

Data is ignored.

(Bank D) (Bank D) (Bank D) (Bank D)

Document : 1G5-0154 Rev.1 Page 64

VIS VG36128401A

Preliminary VG36128801A

VG36128161A

CMOS Synchronous Dynamic RAM

Hi-Z

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

Byte Write Operation

CLK

CKE

CS

RAS

CAS

WE

BS

A10

ADD

LDQM

UDQM

tCK2

Burst Length = 4, CAS Latency = 2

Hi-Z

RAa

High

Activate

CAa CAb CAz

DQ0~DQ7

Command

Bank A

Read

Command

Bank A

Upper Byte

is masked Lower Byte

is masked Write

Command

Bank A

Write Upper

is masked Read

Command

Bank A

Lower Byte

is masked Lower Byte

is masked

DQ8~DQ15

Document : 1G5-0154 Rev.1 Page 65

VIS VG36128401A

Preliminary VG36128801A

VG36128161A

CMOS Synchronous Dynamic RAM

Hi-Z

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

Burst Read and Single Write Operation

CLK

CKE

CS

RAS

CAS

WE

BS

A10

ADD

LDQM

UDQM

tCK2

Burst Length = 4, CAS Latency = 2

Hi-Z

RAa

High

Activate

CAa CAb CAd

DQ0~DQ7

Command

Bank A

Read

Command

Bank A

Single Write Single Write Read

Command

Bank A

Lower Byte

is masked

Upper Byte

is masked

DQ8~DQ15

CAc CAe

Command

Bank A Command

Bank A

Lower Byte

is masked

Single Write

Command

Bank A

Document : 1G5-0154 Rev.1 Page 66

VIS VG36128401A

Preliminary VG36128801A

VG36128161A

CMOS Synchronous Dynamic RAM

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

Full Page Random Column Read

CLK

CKE

CS

RAS

CAS

WE

BS

A10

ADD

DQM

DQ

tCK2

Burst Length=Full Page, CAS Latency=2

Activate

Bank A

Command Activate

Hi-Z

Command

Ra

QBa0

Bank B

Read

Command

Bank B

QAa0

Ra

Activate

Command

Bank B

QAb0 QAb1 QBb0 QBb1 QAc0 QAc1 QAc2 QBc0 QBc1 QBc2

Read

Command

Bank A

Precharge

Cc Cc Rb

Ra

Ra Ca Ca Cb Cb

Rb

tRP

Read

Command

Bank B

Read

Command

Bank A

Read

Command

Bank A

Read

Command

Bank B Command Bank B

(Precharge Termination)

(Bank D) (Bank D) (Bank D) (Bank D)

(Bank D)

Document : 1G5-0154 Rev.1 Page 67

VIS VG36128401A

Preliminary VG36128801A

VG36128161A

CMOS Synchronous Dynamic RAM

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

Full Page Random Column Write

CLK

CKE

CS

RAS

CAS

WE

BS

A10

ADD

DQM

DQ

tCK2

Burst Length=Full Page, CAS Latency=2

Activate

Bank A

Command Activate

Hi-Z

Command

Ra

QBa0

Bank B

Write

Command

Bank B

QAa0

Ra

Activate

Command

Bank B

QAb0 QAb1 QBb0 QBb1 QAc0 QAc1 QAc2 QBc0 QBc1 QBc2

Write

Command

Bank A

Precharge

Cc Cc Rb

Ra

Ra Ca Ca Cb Cb

Rb

tRP

Write

Command

Bank B

Write

Command

Bank A

Write

Command

Bank A

Write

Command

Bank B Command Bank B

(Precharge Termination)

Write Data

is masked

(Bank D) (Bank D) (Bank D) (Bank D)

(Bank D)

Document : 1G5-0154 Rev.1 Page 68

VIS VG36128401A

Preliminary VG36128801A

VG36128161A

CMOS Synchronous Dynamic RAM

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

Precharge Termination of a Burst (1 of 2)

CLK

CKE

CS

RAS

CAS

WE

BS

A10

ADD

DQM

DQ

tCK2

Burst Length=4,8 or Full Page, CAS Latency=2

Activate

Bank A

Command Write

Hi-Z

Command

RAa

Bank A

Activate

Command

Bank A

Read

Command

Bank A

RAc CAb

RAb

RAc

Precharge Termination

of a Write Burst. Write

data is masked.

Precharge

Command Read

Command

Bank A

Precharge

Command

Bank A

Precharge Termination

High

RAa CAcCAa

QAa1

QAa0 QAa2 Da3 QAb0 QAb1 QAb2 QAc0 QAc1 QAc2

tDPL tRP tRP tRP

Bank A

of a Read Burst.

Activate

Command

Bank A

Precharge

Command

Bank A

Document : 1G5-0154 Rev.1 Page 69

VIS VG36128401A

Preliminary VG36128801A

VG36128161A

CMOS Synchronous Dynamic RAM

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

Precharge Termination of a Burst (2 of 2)

CLK

CKE

CS

RAS

CAS

WE

BS

A10

ADD

DQM

DQ

tCK3

Burst Length=4,8 or Full Page, CAS Latency=3

Activate

Bank A

Command Write

Hi-Z

Command

RAa

Bank A

Activate

Command

Bank A

CAb

RAb

RAc

Precharge

Command Read

Command

Bank A

High

RAa RAcCAa

DAa1DAa0 QAb0 QAb1 QAb2 QAb3

tDPL tRP

Bank A

Activate

Command

Bank A

Activate

Command

Bank A

tRCD

tRP

Write Data

is masked Precharge Termination

of a Write Burst.

Precharge Termination

of a Read Burst.

t

RAS