NJU8716A/B PRELIMINARY Switching Driver with Regulator for Class-D Headphone Amplifier PACKAGE OUTLINE GENERAL DESCRIPTION The NJU8716A/B is switching driver with regulator for class-D headphone amplifier. It incorporates optimum regulator for the driver of headphone amplifier. The NJU8716A/B converts 1bit audio signals such as PWM/PDM to analog audio signals with simple external LC low-pass filter. The NJU8716A/B provides completed digital system and high power-efficiency with class-D operation. Therefore it is suitable for portable audio applications. NJU8716AV, NJU8716BV PIN CONFIGURATION FEATURES 2-channel 1bit Audio Signal Input Headphone Output Built-in Regulator for Driver Logic Operating Voltage 1.7~3.0V(VDD) Driver Operating Voltage 1.6~3.5V(VDDO1, VDDO2) Regulator Operating Voltage 4.0~5.75V(VREG1) 1.9~4.0V(VREG2) C-MOS Technology Package Outline SSOP16 VREGO CFB VREG1 VCONT VSS MCK VDD DIN2 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VREG2 VDDO2 OUT2 VSSO VSSO OUT1 VDDO1 DIN1 Version Lineup Version NJU8716A NJU8716B Data Latch The rising edge of MCK The falling edge of MCK VREGO CFB VREG2 VREG1 VCONT BLOCK DIAGRAM VDD VSS Low Voltage Detector VDD Regulator Low Voltage Detector VREGO VDDO1 DIN1 Level Shifter Pre Driver HP Amp Level Shifter VSSO MCK Level Shifter DIN2 Level Shifter OUT1 VDDO2 Pre Driver HP Amp OUT2 VSSO Ver.2005-03-09 -1- NJU8716A/B TERMINAL DESCRIPTION No. 1 2 3 16 4 5 SYMBOL VREGO CFB VREG1 VREG2 VCONT VSS I/O O I 6 MCK I 7 9 8 10 15 11 14 12 13 VDD DIN1 DIN2 VDDO1 VDDO2 OUT1 OUT2 VSSO FUNCTION Regulator Output Terminal Regulator Output Voltage Sense Terminal - Regulator Power Supply I - - Regulator Output Voltage Control Terminal Power GND:VSS=0V Master Clock Input Terminal Audio signals are latched on the edge of MCK. A Version: latched on the rising edge B version: latched on the falling edge Power Supply: VDD=2.0V I Audio Signal Input Terminal 1,2 - Driver Power Supply 1,2 O Output Terminal 1,2 - Driver GND: VSSO=0V INPUT TERMINAL STRUCTURE MCK, DIN1, DIN2 VDD Input Terminal Internal Circuit VSS -2- Ver.2005-03-09 NJU8716A/B NJU3555 FUNCTIONAL DESCRIPTION (1) Power Supply VDD : Power supply for input circuit and control logic. Keep the input logic level less than VDD. If VDD reaches less than sleep detection voltage, power consumption can be saved with halts of built-in regulator. VREG1 : Power supply for built-in regulator. Even after power-on, VREG1 line is shut off with transistor switch until VDD has been started up. VREG2 : Power supply for built-in regulator. Apply the required voltage with additional dropout voltage of regulator. By connecting VREGO (regulator output) to VDDO1, VDDO2 (Driver power supply), the power is provided at the drivers. And furthermore, the regulator output should be supplied to VDDO1 and VDDO2 by connecting de-coupling capacitor to get highly smoothed power supply. (2) Regulator Output Voltage Control Terminal (VCONT) VCONT is the control terminal for regulator output voltage. VREGO terminal generates double the voltage of supplied voltage to VCONT. (Shorted between VREGO-CFB) (3) Master Clock (MCK) Master clock (MCK) synchronizes the audio signal inputs (DIN1 and DIN2). The setup time and the hold time should be kept in the AC characteristics because DIN1 and DIN2 are fetched with the rising edge of MCK in A version, and the falling edge of MCK in B version. During the standby condition, MCK requires "L" level to avoid unnecessary power consumption. In addition, MCK requires jitter-free or jitter as small as possible because the jitter could lead to poor S/N ratio. (4) Signal Output (OUT1 / OUT2) OUT1 and OUT2 terminals keep the Hi-z condition if output voltage of VREGO is lower than detection voltage. Output signals are appeared as PWM signals through the use of VDDO1 and VDDO2 in the OUT1 and OUT2 terminals If the output voltage is over than detection voltage. Output signals will be converted to analog signals via 2nd-order or higher LC filter. POWER ON/DOWN SEQUENCE The pop-noise can be effectively suppressed with the following sequence when power ON and OFF. (1) Power ON Sequence 1) Start up VDD, VREG1 and VREG2. 2) Input the master clock (MCK) and audio signals (DIN1, DIN2) after the start-up of VDD, VREG1 and VREG2. At this time, audio signals must be input as "Sound-less data". 3) Increase VCONT. 4) Input the audio data after VCONT reaches a steady state. (2) Power Down Sequence The sequence must be executed in inverse order of the power ON sequence. VDD, VREG1, VREG2 VCONT MCK DIN1, DIN2 OUT1, OUT2 Ver.2005-03-09 Sound-less Data High impedance Audio Data Audio signal output Sound-less Data High impedance -3- NJU8716A/B ABSOLUTE MAXMUM RATINGS (Ta=25C) PARAMETER SYMBOL RATING UNIT VDD -0.3 ~ +4.0 V VDDO1, 2 -0.3 ~ +4.0 V VREG1 VREG2 ~ +6.0 V VREG2 -0.3 ~ +5.5 V Input Voltage Vin -0.3 ~ VDD+0.3 V Operating Temperature Ta -20 ~ +85 C Tstg -40 ~ +125 C PD 300 (SSOP16) mW Supply Voltage Storage Temperature Power Dissipation Note.1) The relations of "VDDO1,VDDO2<VREG1", "VREG2<VREG1", and "VDD<VREG1" must be maintained during operations. Note.2) All voltage are relative to "VSS= VSSO=0V" reference. Note.3) The LSI must be used inside of the "Absolute maximum ratings". Otherwise, a stress may cause permanent damage to the LSI. Note.4) De-coupling capacitors for "VDD-VSS", "VDDO1-VSSO" and "VDDO2-VSSO" should be connected for stable operation. ELECTRICAL CHARACTERISTIC (1) DC CHARACTERISTIC (Ta=25C, VDD=2.0V, VDDO1=VDDO2=1.8V, VREG2=2.15V, VREG1=5.0V, VSS=VSSO=0.0V, Load Impedance=16, fS=44.1kHz, unless otherwise noted) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT VDD 1.7 2.0 3.0 V VDDO 1.6 1.8 3.5 V Supply Voltage Output Driver High side Resistance RH OUT1, 2=VDDO-0.1V - 1.5 2 Output Driver Low side Resistance RL OUT1, 2=0.1V - 1.5 2 IDD - 0.05 0.10 IDDO No-load operating DIN1, DIN2=16fS MCK=256fS - 0.25 0.5 VIH MCK, DIN1, DIN2 0.7VDD - VDD V VIL MCK, DIN1, DIN2 0 - 0.3VDD V ILK MCK, DIN1, DIN2 - - 1 A Power Supply Current At Operating (Mute signal input) MA Digital Input Voltage Input Leakage Current -4- Ver.2005-03-09 NJU8716A/B NJU3555 (2) REGULATOR CHARACTERRITICS (Ta=25C, VDD=2.0V, VDDO1=VDDO2=1.8V, VREG2=2.15V, VREG1=5.0V, VSS=VSSO=0.0V, Load Impedance=16, fS=44.1kHz, unless otherwise noted) PARAMETER SYMBOL Power Supply MIN TYP MAX UNIT VREG1 4.0 - 5.75 V VREG2 1.9 - 4.0 V - 0.4 0.8 - 0.1 0.2 - - 1 A 0 - VREG2 V - - 1 A 1.9 2.0 2.1 V - - 0.1 V IREG2 Power Supply Current At Operating Off-Leakage Current CONDITIONS No-load IREG1 VDD=0.5V or lower IREG1OFF Input Voltage DIN1=L DIN2=L MCK=L VCONT Input Leakage Current ILK Output Voltage VCONT VREGO1 VREG2=2.5V, VCONT=1.0V VREGO2 VREG2=2.5V, VCONT=0V mA Output Current IOUT 70 - - mA Output Sink Current ISINK 60 - - mA VREG2-VREGO Dropout Voltage VIO - - 0.2 V Ripple Rejection RR 36 44 - dB Load Regulation Voltage VLR - 690 1228 Vrms 1.1 1.25 1.4 V 1.0 1.25 1.5 V 0.5 0.75 1.0 V Vr=0.1Vrms,Iout=70mA fr=1kHz VOUT1=VOUT2=-6dBm fOUT1=fOUT2=1kHz VDET1 VREGO Low Voltage Detection VDET2 Sleep Detection Voltage Ta=-20 ~+70C VDET3 Note.5) VLR (Load Regulation Voltage) is effective with our measurement PCB only. The following figure shows a representative example of VREGO versus VCONT at VREG2=2.5V. 3.0 Note.6) Output voltage of VREGO is maximum VREG2. In VDDO1 and VDDO2 terminals supplied from VREGO, please set VREG2 and VCONT not to exceed their operating voltage. VREGO (V) 2.5 2.0 1.5 1.0 0.5 0.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 VCONT (V) Ver.2005-03-09 -5- NJU8716A/B (3) AC CHARACTERISTICS (Ta=25C, VDD=2.0V, VDDO1=VDDO2=1.8V, VREG2=2.15V, VREG1=5.0V, VSS=VSSO=0.0V, Load Impedance=16, fS=44.1kHz, unless otherwise noted) PARAMETER SYMBOL CONDITION MIN TYP MAX UNIT MCK Frequency fMCKI 8 - 25 MHz MCK Pulse Width (H) tMCKH 12 - - ns MCK Pulse Width (L) tMCKL 12 - - ns DIN1, DIN2 Setup Time tDS 20 - - ns DIN1, DIN2 Hold Time tDH 20 - - ns tMCKH tMCKL tMCKL tMCKH MCK (A Version) MCK (B Version) tMCKI DIN1, DIN2 tDS -6- tDH Ver.2005-03-09 NJU8716A/B NJU3555 APPLICATION CIRCUIT 10F 0.1F 7 5 VREGO Control Voltage 4 Regulator Power 2 2.2F 16 10F Regulator Power 1 1F VSS VCONT VREG2 OUT2 14 CFB VREGO VDDO1 VSSO VDDO2 3 VREG1 1k 0.47F Headphone 220F 100H VDD 16 VSSO 1k Logic Power DIN2 0.47F 8 DIN1 2 1 10 1F Audio Signal OUT1 11 220F 12 15 1F 9 220F 100H MCK NJU8716A/B 6 Master Clock 13 Note.7) De-coupling capacitors must be connected between each power supply pin and GND. The capacitor value should be adjusted on the application circuit and the temperature. It may malfunction if capacity value is small. Note.8) A large-capacitance for the de-coupling capacitors for headphone speaker is recommended to improve a low-frequency characteristics. In addition, a low-ESR(Equivalent series resistance) capacitor is recommened for high power efficiency. Note.9) The above circuit shows only application example and does not guarantee the any electrical characteristics. Therefore, please test the circuit carafully to fit your application. [CAUTION] The specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. The application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights. Ver.2005-03-09 -7- Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: NJR: NJU8716BV-TE1 NJU8716AV-TE2