LM4125IM5-2.0/NOPB - Texas Instruments

LM4125

www.ti.com

SNVS238A –MAY 2004–REVISED APRIL 2013

LM4125 Precision Micropower Low Dropout Voltage Reference

Check for Samples: LM4125

1FEATURES DESCRIPTION

The LM4125 is a precision low power low dropout

2• Small SOT23-5 Package bandgap voltage reference with up to 5 mA output

• Low Dropout Voltage: 120 mV Typ @ 1 mA current source and sink capability.

• High Output Voltage Accuracy: 0.2% This series reference operates with input voltages as

• Source and Sink Current Output: ±5 mA low as 2V and up to 6V consuming 160 µA (Typ.)

• Supply Current: 160 μA Typ. supply current. In power down mode, device current

drops to less than 2 μA.

• Low Temperature Coefficient: 50 ppm/°C The LM4125 comes in two grades (A and Standard)

• Fixed Output Voltages: 2.048, 2.5,and 4.096 and three voltage options for greater flexibility. The

• Industrial Temperature Range: −40°C to +85°C best grade devices (A) have an initial accuracy of

• (For Extended Temperature Range, −40°C to 0.2%, while the standard have an initial accuracy of

125°C, Contact TI) 0.5%, both with a tempco of 50ppm/°C ensured from

−40°C to +125°C.

APPLICATIONS The very low dropout voltage, low supply current and

• Portable, Battery Powered Equipment power-down capability of the LM4125 makes this

product an ideal choice for battery powered and

• Instrumentation and Process Control portable applications.

• Automotive & Industrial The device performance is ensured over the industrial

• Test Equipment temperature range (−40°C to +85°C), while certain

• Data Acquisition Systems specs are ensured over the extended temperature

• Precision Regulators range (−40°C to +125°C). Please contact TI for full

specifications over the extended temperature range.

• Battery Chargers The LM4125 is available in a standard 5-pin SOT-23

• Base Stations package.

• Communications

• Medical Equipment

Connection Diagram

Figure 1. 5-Pin SOT-23 Surface Mount Package

See Package Number DBV

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

LM4125

SNVS238A –MAY 2004–REVISED APRIL 2013

www.ti.com

Absolute Maximum Ratings(1)(2)

Maximum Voltage on input or enable pins −0.3V to 8V

Output Short-Circuit Duration Indefinite

Power Dissipation (TA= 25°C)(3) DBV package − θJA 280°C/W

Power Dissipation 350 mW

ESD Susceptibility(4) Human Body Model 2 kV

Machine Model 200V

Lead Temperature: Soldering, (10 sec.) +260°C

Vapor Phase (60 sec.) +215°C

Infrared (15 sec.) +220°C

(1) “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for

which the device is intended to be functional, but do not ensure specific performance limits. For ensured specifications and test

conditions, see Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance

characteristics may degrade when the device is not operated under the listed test conditions.

(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and

specifications.

(3) Without PCB copper enhancements. The maximum power dissipation must be de-rated at elevated temperatures and is limited by TJMAX

(maximum junction temperature), θJ-A (junction to ambient thermal resistance) and TA(ambient temperature). The maximum power

dissipation at any temperature is: PDissMAX = (TJMAX −TA)/θJ-A up to the value listed in the Absolute Maximum Ratings.

(4) The human body model is a 100 pF capacitor discharged through a 1.5 kΩresistor into each pin. The machine model is a 200 pF

capacitor discharged directly into each pin.

Operating Range(1)

Storage Temperature Range −65°C to +150°C

Ambient Temperature Range −40°C to +85°C

Junction Temperature Range −40°C to +125°C

(1) “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for

which the device is intended to be functional, but do not ensure specific performance limits. For ensured specifications and test

conditions, see Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance

characteristics may degrade when the device is not operated under the listed test conditions.

Product Folder Links: LM4125

LM4125

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SNVS238A –MAY 2004–REVISED APRIL 2013

Electrical Characteristics — LM4125-2.048V and 2.5V

Unless otherwise specified VIN = 3.3V, ILOAD = 0, COUT = 0.01µF, TA= Tj= 25°C. Limits with standard typeface are for Tj=

25°C, and limits in boldface type apply over the −40°C ≤TA≤+85°C temperature range.

Min Typ Max

Symbol Parameter Conditions Units

(1) (2) (1)

Output Voltage Initial Accuracy

LM4125A-2.048 ±0.2 %

LM4125A-2.500

VOUT LM4125-2.048 ±0.5 %

LM4125-2.500

TCVOUT/°C Temperature Coefficient −40°C ≤TA≤+125°C 14 50 ppm/°c

ΔVOUT/ΔVIN Line Regulation 3.3V ≤VIN ≤6V 0.0007 0.008 %/V

0.01

0 mA ≤ILOAD ≤1 mA 0.03 0.08

0.17

1 mA ≤ILOAD ≤5 mA 0.01 0.04

ΔVOUT/ΔILOAD Load Regulation %/mA

0.1

−1 mA ≤ILOAD ≤0 mA 0.04 0.12

−5 mA ≤ILOAD ≤ −1 mA 0.01

ILOAD = 0 mA 45 65

100

ILOAD = +1 mA 120 150

VIN−VOUT Dropout Voltage(3) mV

200

ILOAD = +5 mA 180 210

300

VNOutput Noise Voltage(4) 0.1 Hz to 10 Hz 20 µVPP

10 Hz to 10 kHz 36 µVPP

ISSupply Current 160 257 µA

290

VIN = 3.3V, VOUT = 0 15

6 30

ISC Short Circuit Current mA

VIN = 6V, VOUT = 0 17

6 30

Hyst Thermal Hysteresis(5) −40°C ≤TA≤125°C 0.5 mV/V

ΔVOUT Long Term Stability(6) 1000 hrs. @ 25°C 100 ppm

(1) Limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlation using Statistical

Quality Control (SQC) methods. The limits are used to calculate Outgoing Quality Level (AOQL).

(2) Typical numbers are at 25°C and represent the most likely parametric norm.

(3) Dropout voltage is the differential voltage between VOUT and VIN at which VOUT changes ≤1% from VOUT at VIN = 3.3V for 2.0V, 2.5V

and 5V for 4.1V. A parasitic diode exists between input and output pins; it will conduct if VOUT is pulled to a higher voltage than VIN.

(4) Output noise voltage is proportional to VOUT. VNfor other voltage option is calculated using (VN(1.8V)/1.8) * VOUT. VN(2.5V) =

(36µVPP/1.8) * 2.5 = 46µVPP.

(5) Thermal hysteresis is defined as the change in +25°C output voltage before and after exposing the device to temperature extremes.

(6) Long term stability is change in VREF at 25°C measured continuously during 1000 hrs.

Product Folder Links: LM4125

LM4125

SNVS238A –MAY 2004–REVISED APRIL 2013

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Electrical Characteristics — LM4125-4.096V

Unless otherwise specified VIN = 5V, ILOAD = 0, COUT = 0.01µF, TA= Tj= 25°C. Limits with standard typeface are for Tj= 25°C,

and limits in boldface type apply over the −40°C ≤TA≤+85°C temperature range.

Min Typ Max

Symbol Parameter Conditions Units

(1) (2) (1)

Output Voltage Initial

Accuracy ±0.2 %

VOUT LM4125A-4.096

LM4125-4.096 ±0.5 %

TCVOUT/°C Temperature Coefficient −40°C ≤TA≤+125°C 14 50 ppm/°c

ΔVOUT/ΔVIN Line Regulation 5V ≤VIN ≤6V 0.0007 0.008 %/V

0.01

0 mA ≤ILOAD ≤1 mA 0.03 0.08

0.17

1 mA ≤ILOAD ≤5 mA 0.01 0.04

ΔVOUT/ΔILOAD Load Regulation %/mA

0.1

−1 mA ≤ILOAD ≤0 mA 0.04 0.12

−5 mA ≤ILOAD ≤ −1 mA 0.01

ILOAD = 0 mA 45 65

100

ILOAD = +1 mA 120 150

VIN−VOUT Dropout Voltage(3) mV

200

ILOAD = +5 mA 180 210

300

VNOutput Noise Voltage(4) 0.1 Hz to 10 Hz 20 µVPP

10 Hz to 10 kHz 36 µVPP

ISSupply Current 160 257 µA

290

VOUT = 0 15

6 30

ISC Short Circuit Current mA

VIN = 6V, VOUT = 0 17

6 30

Hyst Thermal Hysteresis(5) −40°C ≤TA≤125°C 0.5 mV/V

ΔVOUT Long Term Stability(6) 1000 hrs. @ 25°C 100 ppm

(1) Limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlation using Statistical

Quality Control (SQC) methods. The limits are used to calculate Outgoing Quality Level (AOQL).

(2) Typical numbers are at 25°C and represent the most likely parametric norm.

(3) Dropout voltage is the differential voltage between VOUT and VIN at which VOUT changes ≤1% from VOUT at VIN = 3.3V for 2.0V, 2.5V

and 5V for 4.1V. A parasitic diode exists between input and output pins; it will conduct if VOUT is pulled to a higher voltage than VIN.

(4) Output noise voltage is proportional to VOUT. VNfor other voltage option is calculated using (VN(1.8V)/1.8) * VOUT. VN(2.5V) =

(36µVPP/1.8) * 2.5 = 46µVPP.

(5) Thermal hysteresis is defined as the change in +25°C output voltage before and after exposing the device to temperature extremes.

(6) Long term stability is change in VREF at 25°C measured continuously during 1000 hrs.

Product Folder Links: LM4125

LM4125

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SNVS238A –MAY 2004–REVISED APRIL 2013

LM4125 Typical Operating Characteristics

Unless otherwise specified, VIN = 3.3V, VOUT = 2.5V, ILOAD = 0, COUT = 0.022µF and TA= 25°C.

Long Term Drift Typical Temperature Drift

Figure 2. Figure 3.

Short Circuit Current Dropout Voltage

vs vs

Temperature Output Error

Figure 4. Figure 5.

Dropout Voltage

Load Current Load Regulation

Figure 6. Figure 7.

Product Folder Links: LM4125

LM4125

SNVS238A –MAY 2004–REVISED APRIL 2013

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LM4125 Typical Operating Characteristics (continued)

Unless otherwise specified, VIN = 3.3V, VOUT = 2.5V, ILOAD = 0, COUT = 0.022µF and TA= 25°C.

GND Pin Current at No Load

GND Pin Current Temperature

Figure 8. Figure 9.

GND Pin Current

Load 0.1Hz to 10Hz output Noise

Figure 10. Figure 11.

Output Impedance PSRR

vs vs

Frequency Frequency

Figure 12. Figure 13.

Product Folder Links: LM4125

LM4125

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SNVS238A –MAY 2004–REVISED APRIL 2013

LM4125 Typical Operating Characteristics (continued)

Unless otherwise specified, VIN = 3.3V, VOUT = 2.5V, ILOAD = 0, COUT = 0.022µF and TA= 25°C.

Start-Up Response Load Step Response

Figure 14. Figure 15.

Load Step Response Line Step Response

Figure 16. Figure 17.

Thermal Hysteresis

Figure 18.

Product Folder Links: LM4125

LM4125

SNVS238A –MAY 2004–REVISED APRIL 2013

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PIN FUNCTIONS

Output (Pin 5): Reference Output.

Input (Pin 4): Positive Supply.

Ground (Pin 2): Negative Supply or Ground Connection.

APPLICATION HINTS

The standard application circuit for the LM4125 is shown in Figure 19. It is designed to be stable with ceramic

output capacitors in the range of 0.022µF to 0.1µF. Note that 0.022µF is the minimum required output capacitor.

These capacitors typically have an ESR of about 0.1 to 0.5Ω. Smaller ESR can be tolerated, however larger ESR

can not. The output capacitor can be increased to improve load transient response, up to about 1µF. However,

values above 0.047µF must be tantalum. With tantalum capacitors, in the 1µF range, a small capacitor between

the output and the reference pin is required. This capacitor will typically be in the 50pF range. Care must be

taken when using output capacitors of 1µF or larger. These application must be thoroughly tested over

temperature, line and load.

An input capacitor is typically not required. However, a 0.1µF ceramic can be used to help prevent line transients

from entering the LM4125. Larger input capacitors should be tantalum or aluminum.

The typical thermal hysteresis specification is defined as the change in +25°C voltage measured after thermal

cycling. The device is thermal cycled to temperature -40°C and then measured at 25°C. Next the device is

thermal cycled to temperature +125°C and again measured at 25°C. The resulting VOUT delta shift between the

25°C measurements is thermal hysteresis. Thermal hysteresis is common in precision references and is induced

by thermal-mechanical package stress. Changes in environmental storage temperature, operating temperature

and board mounting temperature are all factors that can contribute to thermal hysteresis.

Figure 19. Standard Application Circuit

INPUT CAPACITOR

Noise on the power-supply input can effect the output noise, but can be reduced by using an optional bypass

capacitor between the input pin and the ground.

PRINTED CIRCUIT BOARD LAYOUT CONSIDERATION

The mechanical stress due to PC board mounting can cause the output voltage to shift from its initial value.

References in SOT packages are generally less prone to assembly stress than devices in Small Outline (SOIC)

package.

To reduce the stress-related output voltage shifts, mount the reference on the low flex areas of the PC board

such as near to the edge or the corner of the PC board.

Product Folder Links: LM4125

LM4125

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SNVS238A –MAY 2004–REVISED APRIL 2013

Typical Application Circuits

Figure 20. Voltage Reference with Negative Output Figure 21. Precision High Current Low Dropout

Regulator

Figure 22. Precision High Current Negative Voltage Figure 23. Voltage Reference with Complimentary

Regulator Output

Figure 24. Precision High Current Low Droput Figure 25. Precision Voltage Reference with Force

Regulator and Sense Output

Product Folder Links: LM4125

LM4125

SNVS238A –MAY 2004–REVISED APRIL 2013

www.ti.com

Figure 26. Programmable Current Source Figure 27. Precision Regulator with Current

Limiting Circuit

Figure 28. Power Supply Splitter

Product Folder Links: LM4125

LM4125

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SNVS238A –MAY 2004–REVISED APRIL 2013

REVISION HISTORY

Changes from Original (April 2013) to Revision A Page

• Changed layout of National Data Sheet to TI format .......................................................................................................... 10

Product Folder Links: LM4125

PACKAGE OPTION ADDENDUM

www.ti.com 27-Oct-2016

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead/Ball Finish

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

LM4125AIM5-2.5/NOPB ACTIVE SOT-23 DBV 5 1000 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 R81A

LM4125IM5-2.0/NOPB ACTIVE SOT-23 DBV 5 1000 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 R80B

LM4125IM5-2.5/NOPB ACTIVE SOT-23 DBV 5 1000 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 R81B

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish

value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

PACKAGE OPTION ADDENDUM

www.ti.com 27-Oct-2016

Addendum-Page 2

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

LM4125AIM5-2.5/NOPB SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3

LM4125IM5-2.0/NOPB SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3

LM4125IM5-2.5/NOPB SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3

PACKAGE MATERIALS INFORMATION

www.ti.com 20-Dec-2016

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

LM4125AIM5-2.5/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0

LM4125IM5-2.0/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0

LM4125IM5-2.5/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 20-Dec-2016

Pack Materials-Page 2

www.ti.com

PACKAGE OUTLINE

TYP

0.22

0.08

0.25

3.0

2.6

2X 0.95

1.9

1.45 MAX

TYP

0.15

0.00

5X 0.5

0.3

TYP

0.6

0.3

TYP

1.9

3.05

2.75

1.75

1.45

(1.1)

SOT-23 - 1.45 mm max heightDBV0005A

SMALL OUTLINE TRANSISTOR

4214839/C 04/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. Refernce JEDEC MO-178.

0.2 C A B

INDEX AREA

PIN 1

GAGE PLANE

SEATING PLANE

0.1 C

SCALE 4.000

www.ti.com

EXAMPLE BOARD LAYOUT

0.07 MAX

ARROUND 0.07 MIN

ARROUND

5X (1.1)

5X (0.6)

(2.6)

(1.9)

2X (0.95)

(R0.05) TYP

4214839/C 04/2017

SOT-23 - 1.45 mm max heightDBV0005A

SMALL OUTLINE TRANSISTOR

NOTES: (continued)

4. Publication IPC-7351 may have alternate designs.

5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

SYMM

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:15X

PKG

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

DEFINED

EXPOSED METAL

METAL

SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

EXPOSED METAL

www.ti.com

EXAMPLE STENCIL DESIGN

(2.6)

(1.9)

2X(0.95)

5X (1.1)

5X (0.6)

(R0.05) TYP

SOT-23 - 1.45 mm max heightDBV0005A

SMALL OUTLINE TRANSISTOR

4214839/C 04/2017

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

7. Board assembly site may have different recommendations for stencil design.

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE:15X

SYMM

PKG

www.ti.com

PACKAGE OUTLINE

TYP

0.22

0.08

0.25

3.0

2.6

2X 0.95

1.9

1.45 MAX

TYP

0.15

0.00

5X 0.5

0.3

TYP

0.6

0.3

TYP

1.9

3.05

2.75

1.75

1.45

(1.1)

SOT-23 - 1.45 mm max heightDBV0005A

SMALL OUTLINE TRANSISTOR

4214839/C 04/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. Refernce JEDEC MO-178.

0.2 C A B

INDEX AREA

PIN 1

GAGE PLANE

SEATING PLANE

0.1 C

SCALE 4.000

www.ti.com

EXAMPLE BOARD LAYOUT

0.07 MAX

ARROUND 0.07 MIN

ARROUND

5X (1.1)

5X (0.6)

(2.6)

(1.9)

2X (0.95)

(R0.05) TYP

4214839/C 04/2017

SOT-23 - 1.45 mm max heightDBV0005A

SMALL OUTLINE TRANSISTOR

NOTES: (continued)

4. Publication IPC-7351 may have alternate designs.

5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

SYMM

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:15X

PKG

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

DEFINED

EXPOSED METAL

METAL

SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

EXPOSED METAL

www.ti.com

EXAMPLE STENCIL DESIGN

(2.6)

(1.9)

2X(0.95)

5X (1.1)

5X (0.6)

(R0.05) TYP

SOT-23 - 1.45 mm max heightDBV0005A

SMALL OUTLINE TRANSISTOR

4214839/C 04/2017

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

7. Board assembly site may have different recommendations for stencil design.

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE:15X

SYMM

PKG

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