PRELIMINARY FullFlexTM Synchronous SDR Dual-Port SRAM Features * True dual-ported memory allows simultaneous access to the shared array from each port * Synchronous pipelined operation with SDR operation on each port -- Single Data Rate (SDR) interface at 250 MHz -- Up to 36-Gb/s bandwidth (250 MHz * 72 bit * 2 ports) * Selectable pipeline or flow-through mode * Selectable 1.5V or 1.8V core power supply * Commercial and Industrial temperature * IEEE 1149.1 JTAG boundary scan * Available in 484-ball PBGA Packages and 256-ball FBGA packages * FullFlex72 family -- 36-Mbit: 512K x 72 (CYD36S72V18) -- Burst counters for sequential memory access -- Mailbox with interrupt flags for message passing -- Dual Chip Enables for easy depth expansion Functional Description The FullFlexTM Dual-Port SRAM families consist of 4-Mbit, 9-Mbit, 18-Mbit, and 36-Mbit synchronous, true dual-port static RAMs that are high-speed, low-power 1.8V/1.5V CMOS. Two ports are provided, allowing the array to be accessed simultaneously. Simultaneous access to a location triggers deterministic access control. For FullFlex72 these ports can operate independently with 72-bit bus widths and each port can be independently configured for two pipeline stages. Each port can also be configured to operate in pipeline or flow-through mode. Advanced features include built-in deterministic access control to manage address collisions during simultaneous access to the same memory location, variable impedance matching (VIM) to improve data transmission by matching the output driver impedance to the line impedance, and echo clocks to improve data transfer. -- 18-Mbit: 256K x 72 (CYD18S72V18) -- 9-Mbit: 128K x 72 (CYD09S72V18) -- 4-Mbit: 64K x 72 (CYD04S72V18) * FullFlex36 family -- 36-Mbit: 1M x 36 (CYD36S36V18) To reduce the static power consumption, chip enables can be used to power down the internal circuitry. The number of cycles of latency before a change in CE0 or CE1 will enable or disable the databus matches the number of cycles of read latency selected for the device. In order for a valid write or read to occur, both chip enable inputs on a port must be active. -- 18-Mbit: 512K x 36 (CYD18S36V18) -- 9-Mbit: 256K x 36 (CYD09S36V18) -- 4-Mbit: 128K x 36 (CYD04S36V18) * FullFlex18 family -- 36-Mbit: 2M x 18 (CYD36S18V18) Each port contains an optional burst counter on the input address register. After externally loading the counter with the initial address, the counter will increment the address internally. -- 18-Mbit: 1M x 18 (CYD18S18V18) -- 9-Mbit: 512K x 18 (CYD09S18V18) -- 4-Mbit: 256K x 18 (CYD04S18V18) * Built-in deterministic access control to manage address collisions -- Deterministic flag output upon collision detection -- Collision detection on back-to-back clock cycles -- First Busy Address readback * Advanced features for improved high-speed data transfer and flexibility -- Variable Impedance Matching (VIM) -- Echo clocks Cypress Semiconductor Corporation Document #: 38-06082 Rev. *C -- Selectable LVTTL (3.3V), Extended HSTL (1.4V-1.9V), 1.8V LVCMOS, or 2.5V LVCMOS I/O on each port * Additional features of this device include a mask register and a mirror register to control counter increments and wrap-around, counter-interrupt (CNTINT) flags to notify that the counter will reach the maximum value on the next clock cycle, readback of the burst-counter internal address, mask register address, and BUSY address on the address lines, retransmit functionality, mailbox interrupt flags for message passing, JTAG for boundary scan, and asynchronous Master Reset (MRST). The logic block diagram in Figure 1 displays these features. The FullFlex72 is offered in a 484-ball plastic BGA package. The FullFlex36 and FullFlex18 are offered in a 256-ball fine pitch BGA package. 198 Champion Court * San Jose, CA 95134-1709 * 408-943-2600 Revised October 11, 2005 FullFlex PRELIMINARY FTSELL FTSELR CQENL CONFIG Block PORTSTD[1:0]L CONFIG Block CQENR PORTSTD[1:0]R DQ[71:0]L BE [7:0]L CE0L CE1L OEL IO Control IO Control DQ [71:0]R BE [7:0]R CE0R CE1R OER R/WR R/WL CQ1L CQ1L CQ0L CQ0L CQ1R CQ1R CQ0R CQ0R Dual Ported Array VC_SEL BUSYL A [20:0]L CNT/MSKL ADSL CNTENL CNTRSTL RETL CNTINTL CL Collision Detection Logic Address & Counter Logic BUSYR Address & Counter Logic WRPL A [20:0]R CNT/MSKR ADSR CNTENR CNTRSTR RETR CNTINTR CR WRPR Mailboxes INTL INTR ZQ0L ZQ1L READYL LowSPDL JTAG RESET LOGIC TRST TMS TDI TDO TCK ZQ0R ZQ1R MRST READYR LowSPDR Figure 1. FullFlex72 18-Mbit (CYD18S72V18) Block Diagram[1, 2, 3] Notes: 1. The CYD36S18V18 device has 21 address bits. The CYD36S36V18 and the CYD18S18V18 devices have 20 address bits. The CYD36S72V18, CYD18S36V18, and the CYD09S18V18 devices have 19 address bits. The CYD18S72V18, CYD09S36V18, and the CYD04S18V18 devices have 18 address bits. The CYD09S72V18 and the CYD04S36V18 devices have 17 address bits. The CYD04S72V18 has 16 address bits. 2. The FullFlex72 family of devices has 72 data lines. The FullFlex36 family of devices has 36 data lines. The FullFlex18 family of devices has 18 data lines. 3. The FullFlex72 family of devices has eight byte enables. The FullFlex36 family of devices has four byte enables. The FullFlex18 family of devices has two byte enables. Document #: 38-06082 Rev. *C Page 2 of 48 FullFlex PRELIMINARY FullFlex72 SDR 484-ball BGA Pinout (Top View) 1 A NC 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 DQ61 DQ59 DQ57 DQ54 DQ51 DQ48 DQ45 DQ42 DQ39 DQ36 DQ36 DQ39 DQ42 DQ45 DQ48 DQ51 DQ54 DQ57 DQ59 DQ61 L L L L L L L L L L R R R R R R R R R R 22 NC B DQ63 DQ62 DQ60 DQ58 DQ55 DQ52 DQ49 DQ46 DQ43 DQ40 DQ37 DQ37 DQ40 DQ43 DQ46 DQ49 DQ52 DQ55 DQ58 DQ60 DQ62 DQ63 L L L L L L L L L L L R R R R R R R R R R R C DQ65 DQ64 VSS L L VSS DQ56 DQ53 DQ50 DQ47 DQ44 DQ41 DQ38 DQ38 DQ41 DQ44 DQ47 DQ50 DQ53 DQ56 VSS L L L L L L L R R R R R R R VSS DQ64 DQ65 R R DQ67 DQ66 VSS L L VSS LOW PORT ZQ0L[ BUSY CNTI PORT 4] SPDL STD0 L NTL STD1 L L VSS DQ66 DQ67 R R D VSS CQ1L CQ1L VSS NC CQ1R CQ1R VSS E DQ69 DQ68 VDDI VSS L L OL F DQ71 DQ70 CE1L CE0L VDDI VDDI VDDI VDDI VDDI VCO VCO VCO VCO VDDI VDDI VDDI VDDI VDDI CE0R CE1R DQ70 DQ71 L L OL OL OL OL OL RE RE RE RE OR OR OR OR OR R R G H J K L M N P R T VSS VDDI VDDI VDDI VDDI VDDI VTTL VTTL VTTL VDDI VDDI VDDI VDDI OL OL OL OL OL OR OR OR OR NC VSS VSS VDDI DQ68 DQ69 OR R R A0L A1L RETL BE4L VDDI VDDI VREF VSS OL OL L VSS VSS VSS VSS VSS VSS VSS VREF VDDI VDDI BE4R RETR A1R R OR OR A0R A2L A3L WRP BE5L VDDI VDDI VSS OL OL L VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDI VDDI BE5R WRP OR OR R A3R A2R A4L A5L READ BE6L VDDI VDDI VSS YL OL OL VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDI VDDI BE6R READ A5R OR OR YR A4R A6L A7L ZQ1L[ BE7L VTTL VCO 4] RE VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCO VDDI BE7R ZQ1R A7R [4] RE OR A6R A8L A9L OEL VTTL VCO RE VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCO VTTL OER RE A8R VSS BE3L VTTL VCO RE VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCO VTTL BE3R VSS A11R A10R RE A12L A13L ADSL BE2L VDDI VCO OL RE VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCO VTTL BE2R ADSR A13R A12R RE A14L A15L CNT BE1L VDDI VDDI VSS OL OL MSKL VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDI VDDI BE1R CNT A15R A14R OR OR MSK R A16L[ A17L[ CNTE BE0L VDDI VDDI VSS 7] 6] OL OL NL VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDI VDDI BE0R CNTE A17R[ A16R[ 6] 7] OR OR NR CNTR INTL VDDI VDDI VREF VSS STL OL OL L VSS VSS VSS VSS VSS VSS VSS VREF VDDI VDDI INTR CNTR R OR OR STR A10L A11L A18L[ 5] NC CL CR A9R NC A18R[ 5] U DQ35 DQ34 R/WL CQE VDDI VDDI VDDI VDDI VDDI VCO VCO VCO VCO VDDI VDDI VDDI VDDI VDDI CQE R/WR DQ34 DQ35 L L NL OL OL OL OL OL RE RE RE RE OR OR OR OR OR NR R R V DQ33 DQ32 FTSE VDDI L L OL LL W DQ31 DQ30 VSS MRST VSS CQ0L CQ0L VC_S PORT CNTI BUSY ZQ0R PORT LOW VSS CQ0R CQ0R VSS [4] L L EL STD1 NTR STD0 SPDR R R R Y DQ29 DQ28 VSS L L AA AB NC VDDI VDDI VDDI VDDI VTTL VTTL VTTL VDDI VDDI VDDI VDDI VDDI TRST VDDI FTSE DQ32 DQ33 OL OL OL OL OR OR OR OR OR OR R R LR TDI TDO DQ30 DQ31 R R VSS DQ20 DQ17 DQ14 DQ11 DQ8L DQ5L DQ2L DQ2R DQ5R DQ8R DQ11 DQ14 DQ17 DQ20 TMS L L L L R R R R TCK DQ28 DQ29 R R DQ27 DQ26 DQ24 DQ22 DQ19 DQ16 DQ13 DQ10 DQ7L DQ4L DQ1L DQ1R DQ4R DQ7R DQ10 DQ13 DQ16 DQ19 DQ22 DQ24 DQ26 DQ27 L L L L L L L L R R R R R R R R NC DQ25 DQ23 DQ21 DQ18 DQ15 DQ12 DQ9L DQ6L DQ3L DQ0L DQ0R DQ3R DQ6R DQ9R DQ12 DQ15 DQ18 DQ21 DQ23 DQ25 L L L L L L R R R R R R NC Notes: 4. Leaving this pin NC disables VIM 5. Leave this ball unconnected for CYD18S72V18, CYD09S72V18 and CYD04S72V18. 6. Leave this ball unconnected for CYD09S72V18 and CYD04S72V18 7. Leave this ball unconnected for CYD04S72V18 Document #: 38-06082 Rev. *C Page 3 of 48 FullFlex PRELIMINARY FullFlex36 SDR 484-ball BGA Pinout (Top View)[8] 1 2 3 4 5 18 19 20 21 22 NC NC NC NC NC DQ33 DQ30 DQ27 DQ24 DQ21 DQ18 DQ18 DQ21 DQ24 DQ27 DQ30 DQ33 L L L L L L R R R R R R NC NC NC NC NC NC NC NC NC NC DQ34 DQ31 DQ28 DQ25 DQ22 DQ19 DQ19 DQ22 DQ25 DQ28 DQ31 DQ34 L L L L L L R R R R R R NC NC NC NC NC NC NC VSS VSS NC DQ35 DQ32 DQ29 DQ26 DQ23 DQ20 DQ20 DQ23 DQ26 DQ29 DQ32 DQ35 L L L L L L R R R R R R NC VSS VSS NC NC NC NC VSS VSS VSS CQ1L CQ1L VSS CQ1R CQ1R VSS VSS VSS NC NC NC NC VDDI VSS OL VSS VDDI OR NC NC NC NC CE1L CE0L VDDI VDDI VDDI VDDI VDDI VCO VCO VCO VCO VDDI VDDI VDDI VDDI VDDI CE0R CE1R OL OL OL OL OL RE RE RE RE OR OR OR OR OR NC NC A0L A1L RETL BE2L VDDI VDDI VREF VSS OL OL L VSS VSS VSS VSS VSS VSS VSS VREF VDDI VDDI BE2R RETR A1R R OR OR A0R A2L A3L VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDI VDDI BE3R WRP OR OR R A3R A2R A4L A5L READ YL NC VDDI VDDI VSS OL OL VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDI VDDI OR OR NC READ A5R YR A4R A6L A7L ZQ1L[ NC VTTL VCO RE VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCO VDDI RE OR NC ZQ1R A7R A6R A8L A9L OEL VTTL VCO RE VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCO VTTL OER RE CR NC VTTL VCO RE VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCO VTTL RE NC VSS A11R A10R NC VDDI VCO OL RE VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCO VTTL RE NC ADSR A13R A12R A14L A15L CNT BE1L VDDI VDDI VSS OL OL MSKL VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDI VDDI BE1R CNT A15R A14R OR OR MSK R R A16L A17L CNTE BE0L VDDI VDDI VSS OL OL NL VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDI VDDI BE0R CNTE A17R A16R OR OR NR T A18L A19L CNTR INTL VDDI VDDI VREF VSS STL OL OL L VSS VSS VSS VSS VSS VSS VSS VREF VDDI VDDI INTR CNTR A19R A18R R OR OR STR A B C 6 7 8 D E F G H J K L M N P U V A10L A11L AA AB VSS A12L A13L ADSL 11 12 13 14 LOW PORT ZQ0L[ BUSY CNTI PORT 4] SPDL STD0 L NTL STD1 L L 15 NC 16 17 NC [4] A9R A8R NC NC R/WL CQE VDDI VDDI VDDI VDDI VDDI VCO VCO VCO VCO VDDI VDDI VDDI VDDI VDDI CQE R/WR NL OL OL OL OL OL RE RE RE RE OR OR OR OR OR NR NC NC NC NC FTSE VDDI OL LL NC NC NC NC VSS MRST VSS CQ0L CQ0L VC_S PORT CNTI BUSY ZQ0R PORT LOW VSS CQ0R CQ0R VSS [4] EL STD1 NTR STD0 SPDR R R R TDI TDO NC NC NC NC VSS VSS NC DQ17 DQ14 DQ11 DQ8L DQ5L DQ2L DQ2R DQ5R DQ8R DQ11 DQ14 DQ17 L L L R R R NC TMS TCK NC NC NC NC NC NC NC DQ16 DQ13 DQ10 DQ7L DQ4L DQ1L DQ1R DQ4R DQ7R DQ10 DQ13 DQ16 L L L R R R NC NC NC NC NC NC NC NC NC NC DQ15 DQ12 DQ9L DQ6L DQ3L DQ0L DQ0R DQ3R DQ6R DQ9R DQ12 DQ15 L L R R NC NC NC NC NC W Y CL 10 VSS VDDI VDDI VDDI VDDI VDDI VTTL VTTL VTTL VDDI VDDI VDDI VDDI OL OL OL OL OL OR OR OR OR WRP BE3L VDDI VDDI VSS OL OL L 4] 9 NC VDDI VDDI VDDI VDDI VTTL VTTL VTTL VDDI VDDI VDDI VDDI VDDI TRST VDDI FTSE OL OL OL OL OR OR OR OR OR OR LR Note: 8. Use this pinout only for device CYD36S36V18 of the FullFlex36 famiy. Document #: 38-06082 Rev. *C Page 4 of 48 FullFlex PRELIMINARY FullFlex18 SDR 484-ball BGA Pinout (Top View)[9] 1 2 3 4 5 6 7 8 15 16 17 18 19 20 21 22 NC NC NC NC NC NC NC NC DQ15 DQ12 DQ9L DQ9R DQ12 DQ15 L L R R NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC DQ16 DQ13 DQ10 DQ10 DQ13 DQ16 L L L R R R NC NC NC NC NC NC NC NC NC NC VSS VSS NC NC NC NC DQ17 DQ14 DQ11 DQ11 DQ14 DQ17 L L L R R R NC NC NC NC VSS VSS NC NC NC NC VSS VSS VSS CQ1L CQ1L VSS LOW PORT ZQ0L[ BUSY CNTI PORT 4] SPDL STD0 L NTL STD1 L L NC CQ1R CQ1R VSS VSS VSS NC NC NC NC VDDI VSS OL VSS VDDI OR NC NC NC NC CE1L CE0L VDDI VDDI VDDI VDDI VDDI VCO VCO VCO VCO VDDI VDDI VDDI VDDI VDDI CE0R CE1R OL OL OL OL OL RE RE RE RE OR OR OR OR OR NC NC A0L A1L RETL BE1L VDDI VDDI VREF VSS OL OL L VSS VSS VSS VSS VSS VSS VSS VREF VDDI VDDI BE1R RETR A1R R OR OR A0R A2L A3L WRP L NC VDDI VDDI VSS OL OL VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDI VDDI OR OR NC WRP R A3R A2R A4L A5L READ YL NC VDDI VDDI VSS OL OL VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDI VDDI OR OR NC READ A5R YR A4R A6L A7L ZQ1L[ NC VTTL VCO RE VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCO VDDI RE OR NC ZQ1R A7R A6R A8L A9L OEL VTTL VCO RE VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCO VTTL OER RE CR NC VTTL VCO RE VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCO VTTL RE NC VSS A11R A10R A12L A13L ADSL NC VDDI VCO OL RE VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCO VTTL RE NC ADSR A13R A12R A14L A15L CNT MSKL NC VDDI VDDI VSS OL OL VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDI VDDI OR OR NC CNT A15R A14R MSK R R A16L A17L CNTE BE0L VDDI VDDI VSS NL OL OL VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDI VDDI BE0R CNTE A17R A16R OR OR NR T A18L A19L CNTR INTL VDDI VDDI VREF VSS OL OL L STL VSS VSS VSS VSS VSS VSS VSS VREF VDDI VDDI INTR CNTR A19R A18R R OR OR STR A B C D E F G H J K L M N P 4] A10L A11L CL VSS 9 10 11 12 13 14 VSS VDDI VDDI VDDI VDDI VDDI VTTL VTTL VTTL VDDI VDDI VDDI VDDI OL OL OL OL OL OR OR OR OR NC [4] A9R A8R A20L NC R/WL CQE VDDI VDDI VDDI VDDI VDDI VCO VCO VCO VCO VDDI VDDI VDDI VDDI VDDI CQE R/WR NL OL OL OL OL OL RE RE RE RE OR OR OR OR OR NR NC A20R NC NC FTSE VDDI OL LL NC NC NC NC VSS MRST VSS CQ0L CQ0L VC_S PORT CNTI BUSY ZQ0R PORT LOW VSS CQ0R CQ0R VSS [4] EL STD1 NTR STD0 SPDR R R R TDI TDO NC NC Y NC NC VSS VSS NC NC NC NC DQ8L DQ5L DQ2L DQ2R DQ5R DQ8R NC NC NC NC TMS TCK NC NC AA NC NC NC NC NC NC NC NC DQ7L DQ4L DQ1L DQ1R DQ4R DQ7R NC NC NC NC NC NC NC NC AB NC NC NC NC NC NC NC NC DQ6L DQ3L DQ0L DQ0R DQ3R DQ6R NC NC NC NC NC NC NC NC U V W NC VDDI VDDI VDDI VDDI VTTL VTTL VTTL VDDI VDDI VDDI VDDI VDDI TRST VDDI FTSE OL OL OL OL OR OR OR OR OR OR LR Note: 9. Use this pinout only for device CYD36S18V18 of the FullFlex18 famiy. Document #: 38-06082 Rev. *C Page 5 of 48 FullFlex PRELIMINARY FullFlex36 SDR 256-Ball BGA (Top View) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A DQ32L DQ30L DQ28L DQ26L DQ24L DQ22L DQ20L DQ18L DQ18R DQ20R DQ22R DQ24R DQ26R DQ28R DQ30R DQ32R B DQ33L DQ31L DQ29L DQ27L DQ25L DQ23L DQ21L DQ19L DQ19R DQ21R DQ23R DQ25R DQ27R DQ29R DQ31R DQ33R C DQ34L DQ35L RETL INTL CQ1L CQ1L VC_SEL TRST MRST ZQ0R[4] CQ1R CQ1R INTR RETR DQ35R DQ34R D A0L A1L WRPL VREF FTSELL LOWSP DL VSS VTTL VTTL VSS LOWSP FTSELR DR VREF WRPR A1R A0R E A2L A3L CE0L CE1L VDDIOL VDDIOL VDDIOL VCORE VCORE VDDIOR VDDIOR VDDIOR CE1R CE0R A3R A2R F A4L A5L CNINTL BE3L VDDIOL VSS VSS VSS VSS VSS VSS VDDIOR BE3R CNINTR A5R A4R G A6L A7L BUSYL BE2L ZQ0L[4] VSS VSS VSS VSS VSS VSS VDDIOR BE2R BUSYR A7R A6R H A8L A9L CL VTTL VCORE VSS VSS VSS VSS VSS VSS VCORE VTTL CR A9R A8R J A10L A11L VSS PORTST VCORE D1L VSS VSS VSS VSS VSS VSS VCORE PORTST D1R VSS A11R A10R K A12L A13L OEL BE1L VDDIOL VSS VSS VSS VSS VSS VSS VDDIOR BE1R OER A13R A12R L A14L A15L ADSL BE0L VDDIOL VSS VSS VSS VSS VSS VSS VDDIOR BE0R ADSR A15R A14R M A16L A17L[11] R/WL R/WR A17R[11] A16R N A18L[10] NC CNTMS KL CNTMS KR NC A18R[10] P DQ16L DQ17L CNTENL CNTRST L CQ0L CQ0L DQ17R DQ16R R DQ15L DQ13L DQ11L DQ9L DQ7L T DQ14L DQ12L DQ10L DQ8L DQ6L CQENL VDDIOL VDDIOL VDDIOL VCORE VCORE VDDIOR VDDIOR VDDIOR CQENR VREF PORTST READYL ZQ1L[4] D0L ZQ1R[4] READY PORTST R D0R VTTL VTTL VREF TCK TMS TDO TDI CQ0R CQ0R DQ5L DQ3L DQ1L DQ1R DQ3R DQ5R DQ7R DQ9R DQ11R DQ13R DQ15R DQ4L DQ2L DQ0L DQ0R DQ2R DQ4R DQ6R DQ8R DQ10R DQ12R DQ14R CNTRST CNTEN R R Notes: 10. Leave this ball unconnected for CYD09S36V18 and CYD04S36V18. 11. Leave this ball unconnected for CYD04S36V18. Document #: 38-06082 Rev. *C Page 6 of 48 FullFlex PRELIMINARY FullFlex18 SDR 256-Ball BGA (Top View) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A NC NC NC DQ17L DQ16L DQ13L DQ12L DQ9L DQ9R DQ12R DQ13R DQ16R DQ17R NC NC NC B NC NC NC NC DQ15L DQ14L DQ11L DQ10L DQ10R DQ11R DQ14R DQ15R NC NC NC NC C NC NC RETL INTL CQ1L CQ1L VC_SEL TRST MRST ZQ0R[4] CQ1R CQ1R INTR RETR NC NC D A0L A1L WRPL VREF FTSELL LOWSP DL VSS VTTL VTTL VSS LOWSP FTSELR DR VREF WRPR A1R A0R E A2L A3L CE0L CE1L VDDIOL VDDIOL VDDIOL VCORE VCORE VDDIOR VDDIOR VDDIOR CE1R CE0R A3R A2R F A4L A5L CNINTL NC VDDIOL VSS VSS VSS VSS VSS VSS VDDIOR NC CNINTR A5R A4R G A6L A7L BUSYL NC ZQ0L[4] VSS VSS VSS VSS VSS VSS VDDIOR NC BUSYR A7R A6R H A8L A9L CL VTTL VCORE VSS VSS VSS VSS VSS VSS VCORE VTTL CR A9R A8R J A10L A11L VSS PORTST VCORE D1L VSS VSS VSS VSS VSS VSS VCORE PORTST D1R VSS A11R A10R K A12L A13L OEL BE1L VDDIOL VSS VSS VSS VSS VSS VSS VDDIOR BE1R OER A13R A12R L A14L A15L ADSL BE0L VDDIOL VSS VSS VSS VSS VSS VSS VDDIOR BE0R ADSR A15R A14R M A16L A17L R/WL R/WR A17R A16R N A18L[13] A19L[12] CNTMS KL P NC NC R NC NC NC T NC NC NC CQENL VDDIOL VDDIOL VDDIOL VCORE VCORE VDDIOR VDDIOR VDDIOR CQENR VREF CNTENL CNTRST L PORTST READYL ZQ1L[4] D0L VTTL VTTL ZQ1R[4] READY PORTST R D0R VREF CQ0L CQ0L TCK TMS TDO TDI CQ0R CQ0R NC DQ6L DQ5L DQ2L DQ1L DQ1R DQ2R DQ5R DQ6R NC DQ8L DQ7L DQ4L DQ3L DQ0L DQ0R DQ3R DQ4R DQ7R DQ8R CNTMS A19R[12] A18R[13] KR CNTRST CNTEN R R NC NC NC NC NC NC NC NC Notes: 12. Leave this ball unconnected for CYD09S18V18 and CYD04S18V18. 13. Leave this ball unconnected for CYD04S18V18. Document #: 38-06082 Rev. *C Page 7 of 48 FullFlex PRELIMINARY Table 1. Selection Guide fMAX -250[14, 15] -200[14] -167[14] -133[14] Unit 250 200 167 133 MHz Max. Access Time (Clock to Data) 2.64 3.3 4.0 4.5 ns Typical Operating Current ICC TBD TBD TBD TBD mA Typical Standby Current for ISB3 (Both Ports CMOS Level) TBD TBD TBD TBD mA Pin Definitions Left Port Right Port Description [1] A0L-A20L A0R-A20R Address Inputs. DQ0L-DQ71L DQ0R-DQ71R Data Bus Input/Output.[2] BE0L-BE7L BE0R-BE7R Byte Select Inputs.[3] Asserting these signals enables Read and Write operations to the corresponding bytes of the memory array. BUSYL BUSYR Port Busy Output. When there is an address match and both chip enables are active for both ports, an external BUSY signal is asserted on the fifth clock cycles from when the collision occurs. CL CR Clock Signal. Maximum clock input rate is fMAX. CE0L CE0R Active LOW Chip Enable Input. CE1L CE1R Active HIGH Chip Enable Input. CQENL CQENR Echo Clock Enable Input. Assert HIGH to enable echo clocking on respective port. CQ0L CQ0R Echo Clock Signal Output for DQ[35:0] for FullFlex72 devices. Echo Clock Signal Output for DQ[17:0] for FullFlex36 devices. Echo Clock Signal Output for DQ[8:0] for FullFlex18 devices. CQ0L CQ0R Inverted Echo Clock Signal Output for DQ[35:0] for FullFlex72 devices. Inverted Echo Clock Signal Output for DQ[17:0] for FullFlex36 devices. Inverted Echo Clock Signal Output for DQ[8:0] for FullFlex18 devices. CQ1L CQ1R Echo Clock Signal Output for DQ[71:36] for FullFlex72 devices. Echo Clock Signal Output for DQ[35:18] for FullFlex36 devices. Echo Clock Signal Output for DQ[17:9] for FullFlex18 devices. CQ1L CQ1R Inverted Echo Clock Signal Output for DQ[71:36] for FullFlex72 devices. Inverted Echo Clock Signal Output for DQ[35:18] for FullFlex36 devices. Inverted Echo Clock Signal Output for DQ[17:9] forFullFlex18 devices. ZQ[1:0]L[16] ZQ[1:0]R[16] VIM Output Impedance Matching Input. To use, connect a calibrating resistor between ZQ and ground. The resistor must be five times larger than the intended line impedance driven by the dual-port. Assert HIGH to disable Variable Impedance Matching. OEL OER Output Enable Input. This asynchronous signal must be asserted LOW to enable the DQ data pins during Read operations. INTL INTR Mailbox Interrupt Flag Output. The mailbox permits communications between ports. The upper two memory locations can be used for message passing. INTL is asserted LOW when the right port writes to the mailbox location of the left port, and vice versa. An interrupt to a port is deasserted HIGH when it reads the contents of its mailbox. LowSPDL LowSPDR Port Low Speed Select Input. Assert this pin LOW to disable the DLL. For operation at less than 100 MHz, assert this pin LOW. PORTSTD[1:0]L[17] PORTSTD[1:0]R[17] Port Clock/Address/Control/Data/Echo Clock/ I/O Standard Select Input. Assert these pins LOW/LOW for LVTTL, LOW/HIGH for HSTL, HIGH/LOW for 2.5V LVCMOS, and HIGH/HIGH for 1.8V LVCMOS, respectively. Connect these pins to a VTTL supply. R/WL R/WR Read/Write Enable Input. Assert this pin LOW to Write to, or HIGH to Read from the dual-port memory array. Notes: 14. SDR mode with two pipeline stages. 15. 250 MHz for HSTL and 1.8V LVCMOS I/O standards only 16. Leaving pins K3, K20 of the 484-ball BGA package and pin C10 of the 256-ball BGA package disables VIM. 17. For FullFlex72, pins D14 and W9 have an internal pull-down resistor. Document #: 38-06082 Rev. *C Page 8 of 48 FullFlex PRELIMINARY Pin Definitions (continued) Left Port Right Port Description READYL READYR Port DLL Ready Output. This signal will be asserted LOW when the DLL and Variable Impedance Matching circuits have completed calibration. This is a wired OR capable output. CNT/MSKL CNT/MSKR Port Counter/Mask Select Input. Counter control input. ADSL ADSR Port Counter Address Load Strobe Input. Counter control input. CNTENL CNTENR Port Counter Enable Input. Counter control input. CNTRSTL CNTRSTR Port Counter Reset Input. Counter control input. CNTINTL CNTINTR Port Counter Interrupt Output. This pin is asserted LOW one cycle before the unmasked portion of the counter is incremented to all "1s". WRPL WRPR Port Counter Wrap Input. When the burst counter reaches the maximum count, on the next counter increment WRP can be set LOW to load the unmasked counter bits to 0 or set HIGH to load the counter with the value stored in the mirror register. RETL RETR Port Counter Retransmit Input. Assert this pin LOW to reload the initial address for repeated access to the same segment of memory. VREFL VREFR Port External HSTL I/O Reference Input. VDDIOL VDDIOR Port Data I/O Power Supply. FTSELR Port Flow-Through Mode Select Input. Assert this pin LOW to select Flow-Through mode. Assert this pin HIGH to select Pipeline mode. FTSELL MRST Master Reset Input. MRST is an asynchronous input signal and affects both ports. Asserting MRST LOW performs all of the reset functions as described in the text. A MRST operation is required at power-up. This pin must be driven by a VDDIOL referenced signal. VC_SEL Core Power Supply Select. Assert this pin LOW to select 1.8V Core operation. Assert this pin HIGH to select 1.5V Core operation. This pin must be driven by a VTTL referenced signal. TMS JTAG Test Mode Select Input. It controls the advance of JTAG TAP state machine. State machine transitions occur on the rising edge of TCK. Operation for LVTTL or 2.5V LVCMOS. TDI JTAG Test Data Input. Data on the TDI input will be shifted serially into selected registers. Operation for LVTTL or 2.5V LVCMOS. TRST JTAG Reset Input. Operation for LVTTL or 2.5V LVCMOS. TCK JTAG Test Clock Input. Operation for LVTTL or 2.5V LVCMOS. TDO JTAG Test Data Output. TDO transitions occur on the falling edge of TCK. TDO is normally three-stated except when captured data is shifted out of the JTAG TAP. Operation for LVTTL or 2.5V LVCMOS. VSS VCORE VTTL Ground Inputs. Device Core Power Supply. LVTTL Power Supply. Selectable I/O Standard The FullFlex families of devices also offer the option of choosing one of four port standards for the device. Each port can independently select standards from single-ended HSTL class I, single-ended LVTTL, 2.5V LVCMOS, or 1.8V LVCMOS. The selection of the standard is determined by the PORTSTD pins for each port. These pins should be connected to either an LVTTL or 2.5V LVCMOS power suppy. This will determine the input clock, address, control, data, and Echo clock standard for each port as shown in Table 2. Document #: 38-06082 Rev. *C Table 2. Port Standard Selection PORTSTD1 PORTSTD0 I/O Standard VSS VSS LVTTL VSS VTTL HSTL VTTL VSS 2.5V LVCMOS VTTL VTTL 1.8V LVCMOS Operating mode with different IO standards combined with different core power supply will result in different maximum speed as shown in Table 3. Page 9 of 48 FullFlex PRELIMINARY Table 3. Speed vs. I/O Standard and Pipeline Stages Maximum Core Speed (MHz) Voltage (V) Latency Cycles I/O Standard 250[15] 1.8 HSTL/1.8V LVCMOS 2 200 1.8 LVTTL/2.5V LVCMOS 2 200 1.5 HSTL/LVTTL 2.5V LVCMOS 1.8V LVCMOS 2 clock in the address and control signals for a read operation. The dual-port retransmits the input clocks relative to the data output. The buffered clocks are provided on the CQ1/CQ1 and CQ0/CQ0 outputs. Each port has a pair of Echo clocks. Each clock is associated with half the data bits. The output clock will match the corresponding ports I/O configuration. To enable Echo clock outputs, tie CQEN HIGH. To disable Echo clock outputs, tie CQEN LOW. Input Clock Clocking Separate clocks synchronize the operations on each port. Each port has one clock input C. In this mode, all the transactions on the address, control, and data will be on the C rising edge. All transactions on the address, control, data input, output, and byte enables will occur on the C rising edge. Table 4. Data Pin Assignment Data Out Echo Clock Echo Clock Figure 2. SDR Echo Clock Delay Deterministic Access Control BE Pin Name Data Pin Name BE[7] DQ[71:63] BE[6] DQ[62:54] BE[5] DQ[53:45] BE[4] DQ[44:36] BE[3] DQ[35:27] BE[2] DQ[26:18] BE[1] DQ[17:9] BE[0] DQ[8:0] Deterministic Access Control is provided for ease of design. The circuitry detects when both ports are accessing the same location and provides an external BUSY flag to the port on which data may be corrupted. The collision detection logic saves the address in conflict (Busy Address) to a readable register. In the case of multiple collisions, the first Busy address will be written to the Busy Address register. Selectable Pipeline/Flow-Through Mode To meet data rate and throughput requirements, the FullFlex families offer selectable pipeline or flow-through mode. Echo clocks are not supported in flow-through mode and the DLL must be disabled. Flow-Through mode is selected by the FTSEL pin. Strapping this pin HIGH selects pipeline mode. Strapping this pin LOW selects flow-through mode. DLL The FullFlex familes of devices have an on-chip DLL. Enabling the DLL reduces the clock to data valid time allowing more set-up time for the receiving device. For operation below 100 MHz, the DLL must be disabled. This is selectable by strapping LowSPD low. For information on DLL lock and reset time, please see the Master Reset section below. Echo Clocking As the speed of data increases, on-board delays caused by parasitics make providing accurate clock trees extremely difficult. To counter this problem, the FullFlex families incorporate Echo Clocks. Echo Clocks are enabled on a per port basis. The dual-port receives input clocks that are used to If both ports are accessing the same location at the same time and only one port is doing a write, if tCCS is met, then the data being written to and read from the address is valid data. For example, if the right port is reading and the left port is writing and the left ports clock meets tCCS, then the data being read from the address by the right port will be the old data. In the same case, if the right ports clock meets tCCS, then the data being read out of the address from the right port will be the new data. In the above case, if tCCS is violated by the either ports clock with respect to the other port and the right port gets the external BUSY flag, the data from the right port is corrupted. Table 5 shows the tCCS timing that must be met to guarantee the data. Table 6 shows that, in the case of the left port writing and the right port reading, when an external BUSY flag is asserted on the right port, the data read out of the device will not be guaranteed. The value in the busy address register can be read back to the address lines. The required input control signals for this function are shown in Table 9. The value in the busy address register will be read out to the address lines tCA after the same amount of latency as a data read operation. After an initial address match, the address under contention is saved in the busy address register. All following address matches cause the BUSY flag to be generated, however, none of the addresses are saved into the busy address register. Once a busy readback is performed, the address of the first match which happens at least two clocks cycles after the busy readback, is saved into the busy address register. Table 5. tCCS Timing for All Operating Modes Port A--Early Arriving Port Port B--Late Arriving Port Mode Active Edge Mode Active Edge SDR C SDR C Document #: 38-06082 Rev. *C tCCS C Rise to Opposite C Rise Set-up Time for Non-corrupt Data tCYC(min) - 1 Unit ns Page 10 of 48 FullFlex PRELIMINARY Table 6. Deterministic Access Control Logic Left Port Right Port Left Clock Right Clock BUSYL BUSYR X H H No Collision Description Read Read X Write Read >tCCS 0 H H Read OLD Data 0 >tCCS H H Read NEW Data <tCCS 0 H H Read OLD Data H L Data Not Guaranteed H H Read NEW Data H L Data Not Guaranteed 0 Read Write <tCCS >tCCS 0 H H Read NEW Data 0 >tCCS H H Read OLD Data <tCCS 0 H H Read NEW Data L H Data Not Guaranteed H H Read OLD Data L H Data Not Guaranteed 0 Write <tCCS 0 >-tCCS & <tCCS L L Array Data Corrupted 0 >tCCS L H Array Stores Right Port Data >tCCS 0 H L Array Stores Left Port Data Write Variable Impedance Matching (VIM) Table 8. Variable Impedance Matching Operation Each port contains a Variable Impedance Matching circuit to set the impedance of the I/O driver to match the impedance of the on-board traces. The impedance is set for all outputs except JTAG and is done on a per port basis. To take advantage of the VIM feature, connect a calibrating resistor (RQ) that is five times the value of the intended line impedance from the ZQ pin to VSS. The output impedance is then adjusted to account for drifts in supply voltage and temperature every 1024 clock cycles. If a port's clock is suspended, the VIM circuit will retain its last setting until the clock is restarted where it will then resume periodic adjustment. In the case of a significant change in device temperature or supply voltage, the recalibration period is multiples of 1024 clock cycles. A Master Reset will initialize the VIM circuitry. Table 7 shows the VIM parameters and Table 8 describes the VIM operation modes. In order to disable VIM, the ZQ pin must be connected to VDDIO of the relative supply for the I/Os before a Master Reset. Table 7. Variable Impedance Matching Parameters Parameter Min. Max. Unit RQ Value 100 275 2% Output Impedance 20 55 15% Reset Time N/A 1024 Cycles N/A Update Time N/A 1024 Cycles N/A Document #: 38-06082 Rev. *C Tolerance RQ Connection Output Configuration 100 - 275 to VSS Output Driver Impedance = RQ/5 15% at Vout = VDDIO/2 ZQ to VDDIO VIM Disabled. Rout < 20 at Vout = VDDIO/2 Address Counter and Mask Register Operations[1] Each port of the FullFlex family contains a programmable burst address counter. The burst counter contains four registers: a counter register, a mask register, a mirror register, and a busy address register. The counter register contains the address used to access the RAM array. It is changed only by the master reset (MRST), Counter Reset, Counter Load, Retransmit, and Counter Increment operations. The mask register value affects the Counter Increment and Counter Reset operations by preventing the corresponding bits of the counter register from changing. It also affects the counter interrupt output (CNTINT). The mask register is only changed by Mask Reset, Mask Load, and MRST. The Mask Load operation loads the value of the address bus into the mask register. The mask register defines the counting range of the counter register. It divides the counter register into two or three consecutive regions. Zero or more "0s" define the masked region and one or more "1s" define the unmasked portion of the counter register. The counter register may only be divided into up to three regions. The region containing the least significant bits must be no more than two bits. Bits one and zero may be "10" respectively, masking the least significant counter bit and causing the counter to increment by two instead of one. If bits one and zero are "00", the two least significant bits are masked and the counter will increment by four instead of one. For example, in the case of a 256Kx72 Page 11 of 48 PRELIMINARY configuration, a mask register value of 003FC divides the mask register into three regions. With bit 0 being the least significant bit and bit 17 being the most significant bit, the two least significant bits are masked, the next eight bits are unmasked, and the remaining bits are masked. The mirror register is used to reload the counter register on retransmit operations (see "retransmit" below) and wrap functions (see "counter increment" below). The last value loaded into the counter register is stored in the mirror register. The mirror register is only changed by master reset (MRST), Counter Reset, and Counter Load. Table 9 summarizes the operations of these registers and the required input control signals. All signals except MRST are synchronized to the ports clock. Counter Load Operation[1] The address counter and mirror registers are both loaded with the address value presented on the address lines. This value ranges from 0 to 1FFFFF. Mask Load Operation[1] The mask register is loaded with the address value presented on the address bus. This value ranges from 0 to 1FFFFF though not all values permit correct increment operations. Permitted values are in the form of 2n-1, 2n-2, or 2n-4. The counter register can only be segmented in up to three regions. From the most significant bit to the least significant bit, permitted values have zero or more "0s", one or more "1s", and the least significant two bits can be "11", "10", or "00". Thus Document #: 38-06082 Rev. *C FullFlex 1FFFFE, 07FFFF, and 003FFC are permitted values but 02FFFF, 003FFA, and 07FFE4 are not. Counter Readback Operation The internal value of the counter register can be read out on the address lines. The address will be valid tCA after the selected number of latency cycles configured by FTSEL. The data bus (DQ) is tri-stated on the cycle that the address is presented on the address lines. Figure 3 shows a block diagram of the operation. Mask Readback Operation The internal value of the mask register can be read out on the address lines. The address will be valid tCA after the selected number of latency cycles configured by FTSEL. The data bus (DQ) is tri-stated on the cycle that the address is presented on the address lines. Figure 3 shows a block diagram of the operation. Counter Reset Operation All unmasked bits of the counter and mirror registers are reset to "0". All masked bits remain unchanged. A mask reset followed by a counter reset will reset the counter and mirror registers to 00000. Mask Reset Operation The mask register is reset to all "1s", which unmasks every bit of the burst counter. Page 12 of 48 FullFlex PRELIMINARY Table 9. Burst Counter and Mask Register Control Operation (Any Port) [18, 19] C MRST CNTRST CNT/MSK CNTEN ADS RET X L X X X X X Master Reset Operation Description H L H X X X Counter Reset Reset counter and mirror unmasked portion to all 0s. H L L X X X Mask Reset Reset mask register to all 1s. H H H L L X Counter Load Load burst counter and mirror with external address value presented on address lines. H H L L L X Mask Load Load mask register with value presented on the address lines. H H H L H L Retransmit Load counter with value in the mirror register H H H L H H Counter Increment Internally increment address counter value. H H H H H H Counter Hold Constantly hold the address value for multiple clock cycles. H H H H L H Counter Readback Read out counter internal value on address lines. H H L H L H Mask Readback Read out mask register value on address lines. H H L H H L Busy Address Readback Read out last busy address H H L L H X Reserved H H L H L L Reserved H H L H H H Reserved H H H H L L Reserved H H H H H L Reserved Reset address counter to all 0s, mask register to all 1s, and BUSY address to all 0's. Notes: 18. "X" = "Don't Care," "H" = HIGH, "L" = LOW. 19. Counter operation and mask register operation is independent of chip enables. Document #: 38-06082 Rev. *C Page 13 of 48 PRELIMINARY Increment Operation[1] Once the address counter is initially loaded with an external address, the counter can internally increment the address value and address the entire memory array. Only the unmasked bits of the counter register are incremented. In order for a counter bit to change, the corresponding bit in the mask register must be "1". If the two least significant bits of the mask register are "11", the burst counter will increment by one. If the two least significant bits are "10", the burst counter will increment by two, and if they are "00", the burst counter will increment by four. If all unmasked counter bits are incremented to "1" and WRP is deasserted, the next increment will wrap the counter back to the initially loaded value. The cycle before an increment will result in the unmasked counter bits being "1s", a counter interrupt flag (CNTINT) is asserted if the counter is continuously incrementing. The next increment will cause the counter to reach its maximum value and the second increment will return the counter register to its initial value which was stored in the mirror register when WRP is deasserted. When WRP is asserted, the second increment after CNTINT is asserted will load the unmasked counter bits with "0". The example shown in Figure 4 shows an example of the CYDD36S18V18 device with the mask register loaded with a mask value of 00007F unmasking the seven least significant bits. Setting the mask register to this value allows the counter to access the entire memory space. The address counter is then loaded with an initial value of 000005 assuming WRP is deasserted. The masked bits, the seventh address through the twenty-first address, do not increment in an increment operation. The counter address will start at address 000005 and will increment its internal address value until it reaches the mask register value of 00007F. The counter wraps around the memory block to location 000005 at the next count. CNTINT is issued when the counter reaches the maximum -1 count. Hold Operation The value of all three registers can be constantly maintained unchanged for an unlimited number of clock cycles. Such operation is useful in applications where wait states are needed, or when address is available a few cycles ahead of data in a shared bus interface. Retransmit Retransmit allows repeated access to the same block of memory without the need to reload the initial address. An internal mirror register stores the address counter value last Document #: 38-06082 Rev. *C FullFlex loaded. When the burst counter reaches its maximum value set by the mask register, it wraps back to the initial value stored in the mirror register as long as WRP is deasserted. The unmasked counter bits will be loaded with "0" If WRP is asserted. If the counter is configured to continuously be in increment mode, it increments once again to the maximum value and wraps back to the value initially stored in the mirror register as long as WRP is deasserted. While RET is asserted low, the counter will continue to wrap back to the value in the mirror register independent of the state of WRP. Counter Interrupt The counter interrupt (CNTINT) is asserted LOW one clock cycle before an increment operation that results in the unmasked portion of the counter register being all "1s". It is deasserted by counter reset, counter load, mask reset, mask load, and MRST. Counting by Two When the two least significant bits of the mask register are "10," the counter increments by two. Counting by Four When the two least significant bits of the mask register are "00", the counter increments by four. Mailbox Interrupts The upper two memory locations can be used for message passing and permit communications between ports. Table 10 shows the interrupt operation for both ports. The highest memory location is the mailbox for the right port and the maximum address - 1 is the mailbox for the left port. When one port Writes to the other port's mailbox, the INT flag of the port that the mailbox belongs to is asserted LOW. The INT flag remains asserted until the mailbox location is read by the other port. When a port reads its mailbox, the INT flag is deasserted high after one cycle of latency with respect to the input clock of the port to which the mailbox belongs and is independent of OE. Table 10 shows that in order to set the INTR flag, a Write operation by the left port to address 1FFFFF will assert INTR LOW. A valid Read of the 1FFFFF location by the right port will reset INTR HIGH after one cycle of latency with respect to the right port's clock. At least one byte enable has to be activated to set or reset the mailbox interrupt. Page 14 of 48 FullFlex PRELIMINARY CNT/MSK CNTEN Decode Logic A CNTRST RET MRST Bidirectional Address Lines Mask Register Counter/ Address Register Address Decode RAM Array C From Address Lines Load/Increment 21 Mirror From Mask Register Increment Logic Wrap 21 From Mask From Counter 21 To Readback and Address Decode 0 0 21 Counter 1 1 21 21 Bit 0 and 1 +1 Wrap Detect 1 +2 Wrap 0 1 +4 21 To Counter 0 Figure 3. Counter, Mask, and Mirror Logic Block Diagram[1] Document #: 38-06082 Rev. *C Page 15 of 48 FullFlex PRELIMINARY CNTINT Example: Load Counter-Mask H Register = 00007F 0 0 0s 220 219 0 1 1 1 H X X Xs 220 219 Max Address Value L H 1 1 Unmasked Address X 0 0 0 0 1 0 X X Xs X 1 1 1 1 Mask Register LSB 1 6 5 4 3 2 1 0 27 2 2 2 2 2 2 2 220 219 Max + 1 Address Value 1 6 5 4 3 2 1 0 27 2 2 2 2 2 2 2 Masked Address Load Address Counter = 000005 1 1 1 1 Address Counter LSB 6 5 4 3 2 1 0 27 2 2 2 2 2 2 2 X X Xs X 0 0 0 0 1 0 1 220 219 6 5 4 3 2 1 0 27 2 2 2 2 2 2 2 [1, 23] Figure 4. Programmable Counter-Mask Register Operation Table 10.Interrupt Operation Example[1, 19, 20, 21, 22] Left Port Function R/WL Right Port CEL A0L-21L INTL R/WR CER A0R-21R INTR Set Right INTR Flag L L Max. Address X X X X L Reset Right INTR Flag X X X X H L Max. Address H Set Left INTL Flag X X X L L L Max. Address-1 X Reset Left INTL Flag H L Max. Address-1 H X X X X Master Reset The FullFlex family of Dual-Ports undergo a complete reset by asserting MRST. The MRST can be asserted asynchronously to the clocks and must remain asserted for at least tRS. Once asserted MRST deasserts READY, initializes the internal burst counters, internal mirror registers, and internal Busy Addresses to zero, and initializes the internal mask register to all "1s". All mailbox interrupts (INT), Busy Address Outputs (BUSY), and burst counter interrupts (CNTINT) are deasserted upon master reset. Releasing MRST also signifies that the power supplies and all port clocks are stable. This begins calibration of the DLL and VIM circuits. READY will be asserted within 1024 clock cycles. READY is a wired OR capable output with a strong pull-up and weak pull-down. Up to four outputs may be connected together. For faster pull-down of the signal, connect a 250 Ohm resistor to VSS. If the DLL and VIM circuits are disabled for a port, the port will be operational within five clock cycles. However, the READY will be asserted within 160 clock cycles. IEEE 1149.1 Serial Boundary Scan (JTAG) The FullFlex families incorporate an IEEE 1149.1 serial boundary scan test access port (TAP). The TAP operates using JEDEC-standard 3.3V or 2.5V I/O logic levels depending on the VTTL power supply. It is composed of four input connections and one output connection required by the test logic defined by the standard. Notes: 20. CE is internal signal. CE = LOW if CE0 = LOW and CE1 = HIGH. For a single Read operation, CE only needs to be asserted once at the rising edge of the C and can be deasserted after that. Data will be out after the following C edge and will be tri-stated after the next C edge. 21. OE is "Don't Care" for mailbox operation. 22. At least one of BE0, BE1, BE2, BE3, BE4, BE5, BE6, or BE7 must be LOW. 23. The "X" in this diagram represents the counter upper bits. Document #: 38-06082 Rev. *C Page 16 of 48 FullFlex PRELIMINARY Table 12.Scan Registers Sizes Table 11.Identification Register Definitions Part Number Register Name Bit Size Configuration Value CYD36S72V18 512Kx72 0C022069h Instruction CYD36S36V18 1024Kx36 0C023069h Bypass 1 CYD36S18V18 2048Kx36 0C024069h Identification 32 CYD18S72V18 256Kx72 0C025069h Boundary Scan CYD18S36V18 512Kx36 0C026069h CYD18S18V18 1024Kx18 0C027069h CYD09S72V18 128Kx72 0C028069h CYD09S36V18 256Kx36 0C029069h CYD09S18V18 1024Kx18 0C02A069h CYD04S72V18 64Kx72 0C02B069h CYD04S36V18 128Kx36 0C02C069h CYD04S18V18 256Kx18 0C02D069h 4 n[24] Table 13.Instruction Identification Codes Instruction Code Description EXTEST 0000 Captures the Input/Output ring contents. Places the BSR between the TDI and TDO. BYPASS 1111 Places the BYR between TDI and TDO. IDCODE 1011 Loads the IDR with the vendor ID code and places the register between TDI and TDO. HIGHZ 0111 Places BYR between TDI and TDO. Forces all FullFlex72 and FullFlex36 output drivers to a High-Z state. CLAMP 0100 Controls boundary to 1/0. Places BYR between TDI and TDO. SAMPLE/PRELOAD 1000 Captures the input/output ring contents. Places BSR between TDI and TDO. RESERVED All other codes Other combinations are reserved. Do not use other than the above. Note: 24. Details of the boundary scan length can be found in the BSDL file for the device. Document #: 38-06082 Rev. *C Page 17 of 48 FullFlex PRELIMINARY Maximum Ratings Operating Range (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................ -65C to + 150C Range Ambient Temperature VCORE Commercial 0C to +70C 1.8V 100 mV 1.5V 80 mV Industrial -40C to +85C 1.8V 100 mV 1.5V 80 mV Ambient Temperature with Power Applied............................................ -55C to + 125C Supply Voltage to Ground Potential .............. -0.5V to + 4.1V DC Voltage Applied to Outputs in High-Z State......................-0.5V to VCORE + 0.5V Power Supply Requirements Min. Typ. Max. LVTTL VDDIO 3.0V 3.3V 3.6V 2.5V LVCMOS VDDIO 2.3V 2.5V 2.7V Static Discharge Voltage ...........................................> 2200V HSTL VDDIO 1.4V 1.5V 1.9V (JEDEC JESD8-6, JESD8-B) 1.8V LVCMOS VDDIO 1.7V 1.8V 1.9V Latch-up Current .....................................................> 200 mA 3.3V VTTL 3.0V 3.3V 3.6V 2.5V VTTL 2.3V 2.5V 2.7V HSTL VREF 0.68V 0.75V 0.95V DC Input Voltage............................... -0.5V to VCORE + 0.5V Output Current into Outputs (LOW) ............................ 20 mA Electrical Characteristics Over the Operating Range -250[15] Parameter VOH VOL Description VIL Min. Typ. -200 Max. [25] Min. LVTTL (VCORE=Min., IOH=-4 mA) HSTL (DC)[26] VDDIO - 0.4[25] VDDIO - 0.4[25] V (VCORE=Min., IOH=-4 mA) (AC)[26] 0.5[25] 0.5[25] V HSTL 2.4 VDDIO - 2.4 Typ. Max. Unit [25] Output HIGH Voltage (VCORE=Min., IOH=-8 mA) VDDIO - 1.7[25] (VCORE=Min., IOH=-6 mA) 2.5V LVCMOS (VCORE=Min., IOH=-4 mA) 1.8V LVCMOS VDDIO - 0.45[25] V 1.7[25] V VDDIO - 0.45[25] V Output HIGH Voltage (VCORE=Min., IOL= 8 mA) LVTTL 0.4[25] (VCORE=Min., IOL= 4 mA) HSTL (DC)[26] 0.4[25] 0.4[25] V (VCORE=Min., IOL= 4 mA) HSTL (AC)[26] 0.5[25] 0.5[25] V (VCORE=Min., IOL= 6 mA) 2.5V LVCMOS 0.7[25] 0.7[25] V 1.8V LVCMOS 0.2[25] 0.2[25] V (VCORE=Min., IOL= 4 mA) VIH Configuration Input HIGH Voltage Input LOW Voltage V LVTTL 2 VDDIO + 0.3 2 VDDI O+ 0.3 V HSTL (DC)[26] VREF + 0.1 VDDIO + 0.3 VREF + 0.1 VDDI O+ 0.3 V HSTL (AC)[26] VREF + 0.2 VREF + 0.2 V 2.5V LVCMOS 1.7 1.7 V 1.8V LVCMOS 1.26 1.26 V LVTTL -0.3 0.8 -0.3 0.8 V -0.3 VREF - 0.1 -0.3 VREF - 0.1 V VREF - 0.2 V HSTL (DC)[26] HSTL (AC)[26] Document #: 38-06082 Rev. *C 0.4[25] VREF - 0.2 2.5V LVCMOS 0.7 0.7 V 1.8V LVCMOS 0.36 0.36 V Page 18 of 48 FullFlex PRELIMINARY Electrical Characteristics Over the Operating Range (continued) -250[15] Parameter READY VOH Description Configuration Min. Output HIGH Voltage (VCORE = Min., IOH = -24 mA) LVTTL 2.7[25] Max. Min. Typ. Max. Unit 2.7[25] V (VCORE = Min., IOH = -12 mA) HSTL (DC)[26] VDDIO - 0.4[25] VDDIO - 0.4[25] V [26] [25] VDDIO - 0.5[25] V (VCORE = Min., IOH = -12 mA) HSTL (AC) (VCORE = Min., IOH = -15 mA) 2.5V LVCMOS (VCORE = Min., IOH = -12 mA) 1.8V LVCMOS READY VOL Typ. -200 VDDIO - 0.5 2.0 [25] [25] 2.0 VDDIO - 0.45[25] V VDDIO - 0.45[25] V Output HIGH Voltage (VCORE = Min., IO = 0.12 mA) LVTTL 0.4[25] 0.4[25] V (VCORE = Min., IOL = 0.12 mA) HSTL (DC) 0.4[25] 0.4[25] V HSTL (AC) 0.5[25] 0.5[25] V (VCORE = Min., IOL = 0.15 mA) 2.5V LVCMOS 0.7[25] 0.7[25] V (VCORE = Min., IOL = 0.08 mA) 1.8V LVCMOS 0.2[25] 0.2[25] V (VCORE = Min., IOL = 0.12 mA) IOZ Output Leakage Current -10 10 -10 10 A IIX1 Input Leakage Current Except TDI, TMS, MRST -10 10 -10 10 A IIX2 Input Leakage Current TDI, TMS, MRST -300 10 -300 10 A IIX3 Input Leakage Current PORTSTD, DDRON, VC_SEL -10 300 -10 300 A ICC Operating Current (VCORE = Max.,IOUT = 0 mA) Outputs Disabled 512Kx72 TBD TBD TBD TBD TBD TBD mA 1024Kx36 TBD TBD TBD TBD TBD TBD mA 2048Kx18 TBD TBD TBD TBD TBD TBD mA 256Kx72 TBD TBD TBD TBD TBD TBD mA 512Kx36 TBD TBD TBD TBD TBD TBD mA 1024x18 TBD TBD TBD TBD TBD TBD mA 128Kx72 TBD TBD TBD TBD TBD TBD mA 256Kx36 TBD TBD TBD TBD TBD TBD mA 512x18 TBD TBD TBD TBD TBD TBD mA 64Kx72 TBD TBD TBD TBD TBD TBD mA 128Kx36 TBD TBD TBD TBD TBD TBD mA 256x18 TBD TBD TBD TBD TBD TBD mA Notes: 25. These parameters are met with VIM disabled. 26. The (DC) specifications are measured under steady state conditions. The (AC) specifications are measured while switching at speed. Document #: 38-06082 Rev. *C Page 19 of 48 FullFlex PRELIMINARY Electrical Characteristics Over the Operating Range (continued) -250[15] Parameter ISB1 ISB2 ISB3 -200 Description Configuration Min. Typ. Max. Min. Typ. Max. Unit Standby Current (Both Ports TTL Level) CEL and CER VIH, f = fMAX 512Kx72 TBD TBD TBD TBD TBD TBD mA 1024Kx36 TBD TBD TBD TBD TBD TBD mA 2048Kx18 TBD TBD TBD TBD TBD TBD mA 256Kx72 TBD TBD TBD TBD TBD TBD mA 512Kx36 TBD TBD TBD TBD TBD TBD mA 1024x18 TBD TBD TBD TBD TBD TBD mA 128Kx72 TBD TBD TBD TBD TBD TBD mA 256Kx36 TBD TBD TBD TBD TBD TBD mA 512x18 TBD TBD TBD TBD TBD TBD mA Standby Current (One Port TTL Level) CEL | CER VIH, f = fMAX Standby Current (Both Ports CMOS Level) CEL and CER VCORE - 0.2V, f=0 Document #: 38-06082 Rev. *C 64Kx72 TBD TBD TBD TBD TBD TBD mA 128Kx36 TBD TBD TBD TBD TBD TBD mA 256x18 TBD TBD TBD TBD TBD TBD mA 512Kx72 TBD TBD TBD TBD TBD TBD mA 1024Kx36 TBD TBD TBD TBD TBD TBD mA 2048Kx18 TBD TBD TBD TBD TBD TBD mA 256Kx72 TBD TBD TBD TBD TBD TBD mA 512Kx36 TBD TBD TBD TBD TBD TBD mA 1024x18 TBD TBD TBD TBD TBD TBD mA 128Kx72 TBD TBD TBD TBD TBD TBD mA 256Kx36 TBD TBD TBD TBD TBD TBD mA 512x18 TBD TBD TBD TBD TBD TBD mA 64Kx72 TBD TBD TBD TBD TBD TBD mA 128Kx36 TBD TBD TBD TBD TBD TBD mA 256x18 TBD TBD TBD TBD TBD TBD mA 512Kx72 TBD TBD TBD TBD TBD TBD mA 1024Kx36 TBD TBD TBD TBD TBD TBD mA 2048Kx18 TBD TBD TBD TBD TBD TBD mA 256Kx72 TBD TBD TBD TBD TBD TBD mA 512Kx36 TBD TBD TBD TBD TBD TBD mA 1024x18 TBD TBD TBD TBD TBD TBD mA 128Kx72 TBD TBD TBD TBD TBD TBD mA 256Kx36 TBD TBD TBD TBD TBD TBD mA 512x18 TBD TBD TBD TBD TBD TBD mA 64Kx72 TBD TBD TBD TBD TBD TBD mA 128Kx36 TBD TBD TBD TBD TBD TBD mA 256x18 TBD TBD TBD TBD TBD TBD mA Page 20 of 48 FullFlex PRELIMINARY Electrical Characteristics Over the Operating Range (continued) -250[15] Parameter ISB4 Description Standby Current (One Port CMOS Level) CEL | CER VIH, f = fMAX -200 Configuration Min. Typ. Max. Min. Typ. Max. Unit 512Kx72 TBD TBD TBD TBD TBD TBD mA 1024Kx36 TBD TBD TBD TBD TBD TBD mA 2048Kx18 TBD TBD TBD TBD TBD TBD mA 256Kx72 TBD TBD TBD TBD TBD TBD mA 512Kx36 TBD TBD TBD TBD TBD TBD mA 1024x18 TBD TBD TBD TBD TBD TBD mA 128Kx72 TBD TBD TBD TBD TBD TBD mA 256Kx36 TBD TBD TBD TBD TBD TBD mA 512x18 TBD TBD TBD TBD TBD TBD mA 64Kx72 TBD TBD TBD TBD TBD TBD mA 128Kx36 TBD TBD TBD TBD TBD TBD mA 256x18 TBD TBD TBD TBD TBD TBD mA Electrical Characteristics Over the Operating Range -167 Parameter VOH Description Configuration Min. Output HIGH Voltage (VCORE = Min., IOH = -8 mA) LVTTL 2.4[25] 2.4 [25] V (VCORE = Min., IOH = -4 mA) HSTL (DC) VDDIO - 0.4[25] VDDIO - 0.4[25] V HSTL (AC) 0.5[25] VDDIO - 0.5[25] V 1.7[25] V (VCORE = Min., IOH = -4 mA) (VCORE = Min., IOH = -6 mA) 2.5V LVCMOS VDDIO - Typ. -133 Max. 1.7[25] (VCORE = Min., IOH = -4 mA) 1.8V LVCMOS VDDIO - 0.45[25] VOL VIL Typ. Max. VDDIO - 0.45[25] Unit V [25] 0.4 0.4[25] V Output HIGH Voltage (VCORE = Min., IOH = -8 mA) LVTTL (VCORE = Min., IOH = -4 mA) HSTL (DC) 0.4[25] 0.4[25] V HSTL (AC) 0.5[25] 0.5[25] V [25] [25] 0.7 V 0.2[25] V (VCORE = Min., IOH = -4 mA) VIH Min. (VCORE = Min., IOH = -6 mA) 2.5V LVCMOS 0.7 (VCORE = Min., IOH = -4 mA) 1.8V LVCMOS 0.2[25] Input HIGH Voltage Input LOW Voltage LVTTL 2 VDDIO + 0.3 2 VDDIO + 0.3 V HSTL (DC) VREF + 0.1 VDDIO + 0.3 VREF + 0.1 VDDIO + 0.3 V HSTL (AC) VREF + 0.2 VREF + 0.2 V 2.5V LVCMOS 1.7 1.7 V 1.8V LVCMOS 1.26 LVTTL -0.3 0.8 -0.3 0.8 V HSTL (DC) -0.3 VREF - 0.1 -0.3 VREF - 0.1 V VREF - 0.2 V HSTL (AC) Document #: 38-06082 Rev. *C 1.26 VREF - 0.2 V 2.5V LVCMOS 0.7 0.7 V 1.8V LVCMOS 0.36 0.36 V Page 21 of 48 FullFlex PRELIMINARY Electrical Characteristics Over the Operating Range (continued) -167 Parameter READY VOH Description Configuration Min. Output HIGH Voltage (VCORE = Min., IOH = -24 mA) LVTTL 2.7[25] Typ. -133 Max. (VCORE = Min., IOH = -12 mA) HSTL (DC)[26] VDDIO - 0.4[25] (VCORE = Min., IOH = -12 mA) HSTL (AC) [26] (VCORE = Min., IOH = -15 mA) 2.5V LVCMOS (VCORE = Min., IOH = -12 mA) 1.8V LVCMOS READY VOL [25] VDDIO - 0.5 2.0 [25] Min. Typ. Max. V VDDIO - 0.4[25] V VDDIO - 0.5[25] V [25] 2.0 VDDIO - 0.45[25] Unit 2.7[25] V VDDIO - 0.45[25] V Output HIGH Voltage (VCORE = Min., IOL = 0.12 mA) LVTTL 0.4[25] 0.4[25] V (VCORE = Min., IOL = 0.12 mA) HSTL (DC) 0.4[25] 0.4[25] V HSTL (AC) 0.5[25] 0.5[25] V (VCORE = Min., IOL = 0.15 mA) 2.5V LVCMOS 0.7[25] 0.7[25] V (VCORE = Min., IOL = 0.08 mA) 1.8V LVCMOS 0.2[25] 0.2[25] V (VCORE = Min., IOL = 0.12 mA) IOZ Output Leakage Current -10 10 -10 10 A IIX1 Input Leakage Current Except TDI, TMS, MRST -10 10 -10 10 A IIX2 Input Leakage Current TDI, TMS, MRST -300 10 -300 10 A IIX3 Input Leakage Current PORTSTD, DDRON, VC_SEL -10 300 -10 300 A ICC Operating Current (VCORE = Max., IOUT = 0 mA) Outputs Disabled Document #: 38-06082 Rev. *C 512Kx72 TBD TBD TBD TBD TBD TBD mA 1024Kx36 TBD TBD TBD TBD TBD TBD mA 2048Kx18 TBD TBD TBD TBD TBD TBD mA 256Kx72 TBD TBD TBD TBD TBD TBD mA 512Kx36 TBD TBD TBD TBD TBD TBD mA 1024x18 TBD TBD TBD TBD TBD TBD mA 128Kx72 TBD TBD TBD TBD TBD TBD mA 256Kx36 TBD TBD TBD TBD TBD TBD mA 512x18 TBD TBD TBD TBD TBD TBD mA 64Kx72 TBD TBD TBD TBD TBD TBD mA 128Kx36 TBD TBD TBD TBD TBD TBD mA 256x18 TBD TBD TBD TBD TBD TBD mA Page 22 of 48 FullFlex PRELIMINARY Electrical Characteristics Over the Operating Range (continued) -167 Parameter ISB1 ISB2 ISB3 -133 Description Configuration Min. Typ. Max. Min. Typ. Max. Unit Standby Current (Both Ports TTL Level) CEL and CER VIH, f = fMAX 512Kx72 TBD TBD TBD TBD TBD TBD mA 1024Kx36 TBD TBD TBD TBD TBD TBD mA 2048Kx18 TBD TBD TBD TBD TBD TBD mA 256Kx72 TBD TBD TBD TBD TBD TBD mA 512Kx36 TBD TBD TBD TBD TBD TBD mA 1024x18 TBD TBD TBD TBD TBD TBD mA 128Kx72 TBD TBD TBD TBD TBD TBD mA 256Kx36 TBD TBD TBD TBD TBD TBD mA 512x18 TBD TBD TBD TBD TBD TBD mA Standby Current (One Port TTL Level) CEL | CER VIH, f = fMAX Standby Current (Both Ports CMOS Level) CEL and CER VCORE - 0.2V, f=0 Document #: 38-06082 Rev. *C 64Kx72 TBD TBD TBD TBD TBD TBD mA 128Kx36 TBD TBD TBD TBD TBD TBD mA 256x18 TBD TBD TBD TBD TBD TBD mA 512Kx72 TBD TBD TBD TBD TBD TBD mA 1024Kx36 TBD TBD TBD TBD TBD TBD mA 2048Kx18 TBD TBD TBD TBD TBD TBD mA 256Kx72 TBD TBD TBD TBD TBD TBD mA 512Kx36 TBD TBD TBD TBD TBD TBD mA 1024x18 TBD TBD TBD TBD TBD TBD mA 128Kx72 TBD TBD TBD TBD TBD TBD mA 256Kx36 TBD TBD TBD TBD TBD TBD mA 512x18 TBD TBD TBD TBD TBD TBD mA 64Kx72 TBD TBD TBD TBD TBD TBD mA 128Kx36 TBD TBD TBD TBD TBD TBD mA 256x18 TBD TBD TBD TBD TBD TBD mA 512Kx72 TBD TBD TBD TBD TBD TBD mA 1024Kx36 TBD TBD TBD TBD TBD TBD mA 2048Kx18 TBD TBD TBD TBD TBD TBD mA 256Kx72 TBD TBD TBD TBD TBD TBD mA 512Kx36 TBD TBD TBD TBD TBD TBD mA 1024x18 TBD TBD TBD TBD TBD TBD mA 128Kx72 TBD TBD TBD TBD TBD TBD mA 256Kx36 TBD TBD TBD TBD TBD TBD mA 512x18 TBD TBD TBD TBD TBD TBD mA 64Kx72 TBD TBD TBD TBD TBD TBD mA 128Kx36 TBD TBD TBD TBD TBD TBD mA 256x18 TBD TBD TBD TBD TBD TBD mA Page 23 of 48 FullFlex PRELIMINARY Electrical Characteristics Over the Operating Range (continued) -167 Parameter Description ISB4 -133 Configuration Min. Typ. Max. Min. Typ. Max. Unit 512Kx72 TBD TBD TBD TBD TBD TBD mA 1024Kx36 TBD TBD TBD TBD TBD TBD mA 2048Kx18 TBD TBD TBD TBD TBD TBD mA 256Kx72 TBD TBD TBD TBD TBD TBD mA 512Kx36 TBD TBD TBD TBD TBD TBD mA 1024x18 TBD TBD TBD TBD TBD TBD mA 128Kx72 TBD TBD TBD TBD TBD TBD mA 256Kx36 TBD TBD TBD TBD TBD TBD mA 512x18 TBD TBD TBD TBD TBD TBD mA Standby Current (One Port CMOS Level) CEL | CER VIH, f = fMAX 64Kx72 TBD TBD TBD TBD TBD TBD mA 128Kx36 TBD TBD TBD TBD TBD TBD mA 256x18 TBD TBD TBD TBD TBD TBD mA Table 14.Capacitance Parameter CIN[27] COUT[27, 29] Description Test Conditions Input Capacitance TA = C, f = MHz, VCORE = 3 dV[28] Output Capacitance Max. Unit 10 pF 12 pF AC Test Load and Waveforms V V REF V T H = 1 .5 V fo r L V T T L V T H = 5 0 % V D D IO fo r 2 .5 V C M O S V T H = 5 0 % V D D IO fo r 1 .8 V C M O S = 0V REF 50 O hm 50 O hm O u tp u t T e s t P o in t R=250 O hm READY VTH ZQ D e v ic e u n d e r te s t C = 10pF RQ =250 O hm Figure 5. Output Test Load for LVTTL/CMOS V T H V V R E F = 5 0 % V D D IO = 0 .7 5 V R E F 5 0 O h m 5 0 O h m O u tp u t R = 2 5 0 O h m T e s t P o in t R E A D Y Z Q D e v ic e u n d e r te s t V T H C = 1 0 p F fo r S D R R Q = 2 5 0 O h m Figure 6. Output Test Load for HSTL Notes: 27. Capacitance for the 36M x18 device is 20 pF, capacitance for all other 36M or x18 devices is 12 pF. 28. Input and Output switch from 0V to 3V or from 3V to 0V. 29. Cout also references to CI/O. Document #: 38-06082 Rev. *C Page 24 of 48 FullFlex PRELIMINARY Switching Characteristics Over the Operating Range Table 15.SDR Mode with DLL Enabled (LOWSPD-HIGH)[32] -250[15} Parameter Description fMAX (PIPELINED) Maximum Operating Frequency for Pipelined mode Max. Min. Max. Min. Max. Unit 100 250 100 200 100 167 100 133 MHz 55.6 MHz 10.00 ns 100 4.00 tCYC C Clock Cycle Time for (FLOW-THROUGH) Flow-through mode 10.00 tSD Data Input Set-up Time to C Rise -133 Min. tCYC (PIPELINED) C Clock Cycle Time for Pipelined mode C Clock Duty Time -167 Max. fMAX[33] Maximum Operating Frequency (FLOW-THROUGH) for Flow-through mode tCKD -200 Min. 45 10.00 77 5.00 10.00 13.00 55 45 66.7 6.00 10.00 15.00 55 45 7.00 18.00 55 45 1.20[31] 1.50[31] 1.70[31] 1.80[31] [31] [31] [31] [31] ns 55 % ns tHD Data Input Hold Time after C Rise 0.50 tSAC Address & Control Input Setup Time to C Rise 1.20 1.50 1.70 1.80 ns tHAC Address & Control Input Hold Time after C Rise 0.50 0.50 0.60 0.70 ns tOE Output Enable to Data Valid tOLZ[30] tOHZ[30] OE to Low Z tCD1 C Rise to DQ Valid for Flow-through Mode (LowSPD = 1) tCD2 C Rise to DQ Valid for Pipelined mode (LowSPD = 1) tCA1 OE to High Z 0.50 3.40[31] 1.00 0.50 4.40[31] 1.00 0.50 5.00[31] 1.00 ns 5.50[31] 1.00 ns ns 1.00[31] 3.40[31] 1.00[31] 4.40[31] 1.00[31] 5.00[31] 1.00[31] 5.50[31] ns 7.20 9.00 11.00 13.00 ns 2.64[31] 3.30[31] 4.00[31] 4.50[31] ns C Rise to Address Readback Valid for flow-through mode 7.20 9.00 11.00 13.00 ns tCA2 C Rise to Address Readback Valid for pipelined mode 4.00 5.00 6.00 7.50 ns tDC DQ Output Hold after C Rise 1.00 tCCQ C Rise to CQ Rise 1.00 tCQHQV Echo Clock (CQ) High to Output Valid tCQHQX Echo Clock (CQ) High to Output Hold -0.66 tCKHZ1[30] C Rise to DQ Output High Z in Flow-Through Mode 1.00 tCKLZ1[30] C Rise to DQ Output Low Z in Flow-Through Mode 1.00 tCKHZ2[30] C Rise to DQ Output High Z in Pipelined Mode tCKLZ2[30] C Rise to DQ Output Low Z in Pipelined Mode 1.00 1.00 1.00 1.00 ns tAC Address Output Hold after C Rise 1.00 1.00 1.00 1.00 ns 1.00 2.64 1.00 0.70[31] 1.00 3.30 -0.72 7.20 1.00 0.76[31] 1.00 1.00 1.00 4.00 -0.76 9.00 1.00 0.80[31] 1.00 1.00 ns 4.50 ns 0.90[31] ns -0.90 11.00 1.00 ns 13.00 1.00 ns ns 1.00[31] 2.64[31] 1.00[31] 3.30[31] 1.00[31] 4.00[31] 1.00[31] 4.50[31] ns Notes: 30. Parameters specified with the load capacitance in Figure 5 and Figure 6. 31. For the x18 devices, add 200 ps to this parameter in the table above. 32. Test conditions assume a signal transition time of 2 V/ns. 33. Flow-Through Mode operates at this frequency regardless of DLL being enabled or disabled Document #: 38-06082 Rev. *C Page 25 of 48 FullFlex PRELIMINARY Table 15.SDR Mode with DLL Enabled (LOWSPD-HIGH)[32] (continued) -250[15} -200 -167 -133 Description Min. Max. Min. Max. Min. Max. Min. Max. Unit [30] C Rise to Address Output High Z for Flow-Through Mode 1.00 7.20 1.00 9.00 1.00 11.00 1.00 13.00 ns tCKHZA2[30] C Rise to Address Output High Z for Pipelined Mode 1.00 4.00 1.00 5.00 1.00 6.00 1.00 7.50 ns tCKLZA[30] C Rise to Address Output Low Z 1.00 tSCINT C Rise to CNTINT Low 1.00 2.64 1.00 3.30 1.00 4.00 1.00 4.50 ns tRCINT C Rise to CNTINT High 1.00 2.64 1.00 3.30 1.00 4.00 1.00 4.50 ns tSINT C Rise to INT Low 0.50 6.00 0.50 7.00 0.50 8.00 0.50 8.50 ns tRINT C Rise to INT High 0.50 6.00 0.50 7.00 0.50 8.00 0.50 8.50 ns tBSY C Rise to BUSY Valid 1.00 2.64 1.00 3.30 1.00 4.00 1.00 4.50 ns Parameter tCKHZA1 1.00 1.00 1.00 ns Table 16. SDR Mode with DLL Disabled (LOWSPD-LOW)[32] -100 Parameter fMAX (PIPELINED) Description Min. Maximum Operating Frequency for Pipelined mode fMAX (FLOW-THROUGH)[33] Maximum Operating Frequency for Flow-through mode tCYC (PIPELINED) C Clock Cycle Time for Pipelined mode 7.00 tCYC (FLOW-THROUGH) C Clock Cycle Time for Flow-through mode 18.00 45 Max. Unit 100 MHz 55.6 MHz 10.00 ns ns tCKD C Clock Duty Time tSD Data Input Set-up Time to C Rise 1.80[31] 55 % tHD Data Input Hold Time after C Rise 0.50[31] ns tSAC Address & Control Input Setup Time to C Rise 1.80 ns tHAC Address & Control Input Hold Time after C Rise 0.70 tOE Output Enable to Data Valid tOLZ[30] tOHZ[30] OE to Low Z 1.00 OE to High Z 1.00[31] tCD1 C Rise to DQ Valid for Flow-through Mode (LowSPD = 0) tCD2 C Rise to DQ Valid for Pipelined mode (LowSPD = 0) tCA1 tCA2 tDC DQ Output Hold after C Rise 1.00 tCCQ C Rise to CQ Rise 1.00 ns ns 5.50[31] ns 5.50[31] ns ns 13.00 ns 6.00[31] ns C Rise to Address Readback Valid for flow-through mode 13.00 ns C Rise to Address Readback Valid for pipelined mode 7.50 ns ns 6.00 0.90[31] tCQHQV Echo Clock (CQ) High to Output Valid tCQHQX Echo Clock (CQ) High to Output Hold -0.90 tCKHZ1[30] C Rise to DQ Output High Z in Flow-through Mode 1.00 tCKLZ1[30] C Rise to DQ Output Low Z in Flow-Through Mode 1.00 [31] ns ns ns 13.00 ns ns [31] [30] C Rise to DQ Output High Z in Pipelined Mode tCKLZ2[30] C Rise to DQ Output Low Z in Pipelined Mode 1.00 tAC Address Output Hold after C Rise 1.00 tCKHZA1[30] C Rise to Address Output High Z for Flow-Through mode 1.00 13.00 ns 7.50 ns tCKHZ2 tCKHZA2 [30] 1.00 6.00 ns ns ns C Rise to Address Output High Z for Pipelined mode 1.00 tCKLZA[30] C Rise to Address Output Low Z 1.00 tSCINT C Rise to CNTINT Low 1.00 4.50 ns tRCINT C Rise to CNTINT High 1.00 4.50 ns Document #: 38-06082 Rev. *C ns Page 26 of 48 FullFlex PRELIMINARY Table 16. SDR Mode with DLL Disabled (LOWSPD-LOW)[32] -100 Parameter Description Min. Max. Unit 0.50 8.50 ns tSINT C Rise to INT Low tRINT C Rise to INT High 0.50 8.50 ns tBSY C Rise to BUSY Valid 1.00 4.50 ns Master Reset Timing -250[15] Parameter Description Min. Max. -200 Min. -167 Max. Min. -133 Max. Min. Max. Unit tPUP Power-Up Time 1 1 1 1 ms tRS Master Reset Pulse Width 5 5 5 5 cycles tRSR Master Reset Recovery Time 5 tRSF Master Reset to Outputs Inactive/Hi Z 10 10 10 10 ns tRDY Master Reset Release to Port Ready 1024 1024 1024 1024 cycles tCORDY[35] C Rise to Port Ready 8 9.5 11 13 ns Max. Unit 20 MHz [34] 5 5 5 cycles Table 17.JTAG Timing -250[15] Parameter Description Min. Max. -200 Min. -167 Max. Min. -133 Max. Min. fJTAG JTAG TAP Controller Frequency tTCYC TCK Cycle Time 50 50 50 50 ns tTH TCK High Time 20 20 20 20 ns tTL TCK Low Time 20 20 20 20 ns tTMSS TMS Set-up to TCK Rise 10 10 10 10 ns tTMSH TMS Hold to TCK Rise 10 10 10 10 ns tTDIS TDI Set-up to TCK Rise 10 10 10 10 ns tTDIH TDI Hold to TCK Rise 10 10 10 10 ns tTDOV TCK Low to TDO Valid tTDOX TCK Low to TDO Invalid tJXZ TCK Low to TDO High Z 15 15 15 15 ns tJZX TCK Low to TDO Active 15 15 15 15 ns 20 20 10 0 20 10 0 10 0 10 0 ns ns Notes: 34. READY is a wired OR capable output with a weak pull-down. For a decreased falling delay, connect a 250-Ohm resistor to VSS. 35. Add this propagation delay after tRDY for all Master Reset Operations. Document #: 38-06082 Rev. *C Page 27 of 48 FullFlex PRELIMINARY Switching Waveforms JTAG Timing tTH Test Clock TCK tTMSS tTL tTCYC tTMSH Test Mode Select TMS tTDIS tTDIH Test Data-In TDI Test Data-Out TDO tTDOX tTDOV Master Reset[34] ~ VCORE tPUP tRS MRST ~ C ~ tRDY READY All Address & Data tRSF tCORDY ~ ~ tRSR All Other Inputs Document #: 38-06082 Rev. *C ~ Page 28 of 48 FullFlex PRELIMINARY Switching Waveforms (continued) READ Cycle for Pipelined Mode tCYC C CE OE tSAC tHAC R/W A An An+1 2 pipeline stages DQ DQx-1 An+2 DQx DQn An+3 DQn+1 tDC An+4 An+5 An+6 DQn+2 DQn+3 DQn+4 tCD2 WRITE Cycle for Pipelined and Flow-Through Modes tCYC C CE R/W A An An+1 An+2 An+3 An+4 An+5 An+6 DQn+1 DQn+2 DQn+3 DQn+4 DQn+5 DQn+6 2 pipeline stages DQ DQn tSD Document #: 38-06082 Rev. *C tHD Page 29 of 48 FullFlex PRELIMINARY Switching Waveforms (continued) READ with Address Counter Advance for Pipelined Mode tCYC C An A Internal Address An An+1 An+2 An+3 ADS CNTEN DQ DQx-1 DQx DQn DQn+1 DQn+2 DQn+3 READ with Address Counter Advance for Flow-Through Mode tCYC C tSAC tHAC A An ADS tSAC t HAC CNTEN t CD1 DQ DQx DQn DQn + 1 DQn + 2 DQn + 3 DQn + 4 t DC R EAD EXTERNAL ADDRESS Document #: 38-06082 Rev. *C READ W ITH CO UN TER C OUN TER H OLD READ W ITH CO UNTER Page 30 of 48 FullFlex PRELIMINARY Switching Waveforms (continued) Port-to-Port WRITE-READ for Pipelined Mode tCYC Left Port CL An AL R/WL DQL DQn Right Port CR tCCS tCYC AR An R/WR tSAC tHAC DQR DQn tCD2 tDC Chip Enable READ for Pipelined Mode tCYC C CE0 CE1 R/W tSAC tHAC A An An+1 An+3 An+4 tCD2 An+5 An+6 DQn+3 DQn DQ Document #: 38-06082 Rev. *C An+2 tDC tCKLZ2 Page 31 of 48 FullFlex PRELIMINARY Switching Waveforms (continued) OE Controlled WRITE for Pipelined Mode tCYC C A Ax+1 Ax+2 Ax+3 An An+1 An+2 An+3 DQn DQn+1 DQn+2 DQn+3 An An+1 An+2 An+3 DQn DQn+1 DQn+2 DQn+3 R/W OE tOHZ DQx+1 DQ DQx-1 DQx OE Controlled WRITE for Flow-Through Mode tCYC C A Ax+1 Ax+2 Ax+3 R/W OE tOHZ DQx+2 DQ DQx DQx+1 Document #: 38-06082 Rev. *C Page 32 of 48 FullFlex PRELIMINARY Switching Waveforms (continued) Byte-Enable READ for Pipelined Mode tCYC C A An An+1 An+2 An+3 R/W BE7 BE6 BE5 BE4 BE3 BE2 BE1 BE0 tCKLZ2 t DQn+1(63:71) CKHZ2 DQ63:71 DQ54:62 DQn+1(54:62) DQn+2(45:53) DQ45:53 DQn+2(36:44) DQ36:44 DQn+1(27:35) DQ27:35 DQ18:26 DQ9:17 DQ0:8 Document #: 38-06082 Rev. *C DQn+2(18:26) DQn+3(9:17) DQn+3(0:8) Page 33 of 48 FullFlex PRELIMINARY Switching Waveforms (continued) Port-to-Port WRITE-to-READ for Flow-Through Mode CL R/W L t SAC AL t H AC MATCH NO MAT CH t SD t HD VALID DQ L t CCS CR t CD1 R/W R t H AC t SAC AR N O MATCH MATCH t CD1 VALID DQ R VALID t DC t DC Busy Address Readback for Pipelined and Flow-Through Modes[36] tCYC ~ C Internal Amatch+2 Address Amatch+3 BUSY CNTEN ADS External Address Amatch+4 ~ ~ ~ ~ ~ Amatch tCA tAC Note: 36. Amatch is the matching address which will be reported on the address bus of the losing port. The counter operation selected for reporting the address is "Busy Address Readback." Document #: 38-06082 Rev. *C Page 34 of 48 FullFlex PRELIMINARY Switching Waveforms (continued) Read Cycle for Flow-Through Mode t CYC C CE 0 tSAC tHAC CE 1 BEn R/W tSAC A tHAC An + 1 An tCD1 An + 2 An + 3 tCKHZ1 t DC DQ DQn DQn + 1 tCKLZ1 DQn + 2 tDC t OLZ tOHZ OE tOE READ-to-WRITE for Pipelined Mode (OE = VIL)[37,38,39] tCYC tCL C A tCH Ax An An+1 tSAC tHAC R/W DQ An+2 tSAC tHAC tCKLZ2 DQx-2 DQx-1 tCD2 DQx tDC DQn tCKHZ2 DQn+1 DQn+2 tSD tHD Notes: 37. When OE = VIL, the last read operation is allowed to complete before the DQ bus is tri-stated and the user is allowed to drive write data. 38. Two dummy writes should be issued to accomplish bus turnaround. The 3rd instruction is the first valid write. 39. Chip enable or all byte enables should be held inactive during the two dummy writes to avoid data corruption. Document #: 38-06082 Rev. *C Page 35 of 48 FullFlex PRELIMINARY Switching Waveforms (continued) READ-to-WRITE for Pipelined Mode (OE Controlled)[40,41] tCYC C A Ax Ax+1 Ax+2 An An+1 An+2 An+3 DQn+1 DQn+2 DQn+3 tSAC tHAC R/W OE DQ tOHZ DQx-2 DQx-1 DQx tSD tHD DQn Notes: 40. OE should be deasserted and tOHZ allowed to elapse before the first write operation is issued. 41. Any write scheduled to complete after OE is deasserted will be preempted. Document #: 38-06082 Rev. *C Page 36 of 48 FullFlex PRELIMINARY Switching Waveforms (continued) Read-to-Write-to-Read for Flow-Through Mode (OE = LOW) tCYC C tSAC tHAC CE 0 CE 1 BEn t SAC t HAC R/W A An An + 1 An + 2 An + 2 tSD DQ IN An + 3 An + 4 tHD DQn + 2 tCD1 tCD1 DQn DQ OUT tCD1 DQn + 1 t CD1 DQn + 3 t CKHZ1 tCKLZ1 tDC READ Document #: 38-06082 Rev. *C tDC NOP W RITE READ Page 37 of 48 FullFlex PRELIMINARY Switching Waveforms (continued) Read-to-Write-to-Read for Flow-Through Mode (OE Controlled) tCYC C tSAC tHAC CE0 CE1 BEn tSAC tHAC R/W A An An + 1 An + 2 tSD DQIN DQOUT An + 4 An + 5 tHD DQn + 2 tCD1 An + 3 DQn + 3 tDC tOE tCD1 tCD1 DQn DQn + 4 tCKLZ1 tOHZ tDC OE READ Document #: 38-06082 Rev. *C WRITE READ Page 38 of 48 FullFlex PRELIMINARY Switching Waveforms (continued) BUSY Timing, WRITE-WRITE Collision for Pipelined and Flow-Through Modes, Clock Timing Violates tCCS. (Flag Both Ports) Port A C A R/W BUSY < tCCS tBSY tBSY Port B C A R/W tBSY BUSY tBSY BUSY Timing, WRITE-WRITE Collision for Pipelined and Flow-Through Modes, Clock Timing Meets tCCS. (Flag Losing Port) Losing Port C A R/W BUSY tccs tBSY tBSY Winning Port C A Match R/W BUSY Document #: 38-06082 Rev. *C Page 39 of 48 FullFlex PRELIMINARY Switching Waveforms (continued) Read with Echo Clock for Pipelined and Flow-Through Modes (CQEN = HIGH) C tSAC tHAC R/W A An An+1 An+2 An+3 An+4 An+5 An+6 CQ0 CQ0 tCCQ CQ1 CQ1 tCQHQX tCQHQV DQ DQx-1 DQx Document #: 38-06082 Rev. *C DQn DQn+1 DQn+2 DQn+3 DQn+4 Page 40 of 48 FullFlex PRELIMINARY Switching Waveforms (continued) Mailbox Interrupt Output tCYC CL AL AMAX R/WL DQL INTR tSINT tRINT CR AR AMAX R/WR DQR Document #: 38-06082 Rev. *C DQMAX Page 41 of 48 PRELIMINARY FullFlex Ordering Information 512K x 72 (36 Mbit) 1.8V Synchronous CYD36S72V18 Dual-Port SRAM Speed (MHz) Ordering Code Package Name Package Type Operating Range 200 CYD36S72V18-200BBC BY484 484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (PBGA) Commercial 167 CYD36S72V18-167BBC BY484 484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (PBGA) Commercial CYD36S72V18-167BBI BY484 484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (PBGA) Industrial 133 CYD36S72V18-133BBC BY484 484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (PBGA) Commercial CYD36S72V18-133BBI BY484 484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (PBGA) Industrial 256K x 72 (18 Mbit) 1.8V Synchronous CYD18S72V18 Dual-Port SRAM Speed (MHz) Ordering Code Package Name Package Type Operating Range 250 CYD18S72V18-250BBC BY484 484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (PBGA) Commercial 200 CYD18S72V18-200BBC BY484 484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (PBGA) Commercial CYD18S72V18-200BBI BY484 484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (PBGA) Industrial CYD18S72V18-167BBC BY484 484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (PBGA) Commercial CYD18S72V18-167BBI BY484 484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (PBGA) Industrial 167 128K x 72 (9 Mbit) 1.8V Synchronous CYD09S72V18 Dual-Port SRAM Speed (MHz) Ordering Code Package Name Package Type Operating Range 250 CYD09S72V18-250BBC BY484 484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (PBGA) Commercial 200 CYD09S72V18-200BBC BY484 484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (PBGA) Commercial CYD09S72V18-200BBI BY484 484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (PBGA) Industrial CYD09S72V18-167BBC BY484 484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (PBGA) Commercial CYD09S72V18-167BBI BY484 484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (PBGA) Industrial 167 64K x 72 (4 Mbit) 1.8V Synchronous CYD04S72V18 Dual-Port SRAM Speed (MHz) Ordering Code Package Name Package Type Operating Range 250 CYD04S72V18-250BBC BY484 484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (PBGA) Commercial 200 CYD04S72V18-200BBC BY484 484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (PBGA) Commercial CYD04S72V18-200BBI BY484 484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (PBGA) Industrial 167 CYD04S72V18-167BBC BY484 484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (PBGA) Commercial CYD04S72V18-167BBI BY484 484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (PBGA) Industrial 1024K x 36 (36 Mbit) 1.8V Synchronous CYD36S36V18 Dual-Port SRAM Speed (MHz) Ordering Code Package Name Package Type Operating Range 200 CYD36S36V18-200BBC BY484 484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (PBGA) Commercial 167 CYD36S36V18-167BBC BY484 484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (PBGA) Commercial CYD36S36V18-167BBI BY484 484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (PBGA) Industrial 133 CYD36S36V18-133BBC BY484 484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (PBGA) Commercial CYD36S36V18-133BBI BY484 484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (PBGA) Industrial Document #: 38-06082 Rev. *C Page 42 of 48 PRELIMINARY FullFlex Ordering Information (continued) 512K x 36 (18 Mbit) 1.8V Synchronous CYD18S36V18 Dual-Port SRAM Speed (MHz) Ordering Code 250 CYD18S36V18-250BBC 200 167 Package Name Package Type Operating Range BW256C 256-ball Grid Array 19 mm x 19 mm with 1.0 mm pitch (FBGA) Commercial CYD18S36V18-200BBC BW256C 256-ball Grid Array 19 mm x 19 mm with 1.0 mm pitch (FBGA) Commercial CYD18S36V18-200BBI BW256C 256-ball Grid Array 19 mm x 19 mm with 1.0 mm pitch (FBGA) Industrial CYD18S36V18-167BBC BW256C 256-ball Grid Array 19 mm x 19 mm with 1.0 mm pitch (FBGA) Commercial CYD18S36V18-167BBI BW256C 256-ball Grid Array 19 mm x 19 mm with 1.0 mm pitch (FBGA) Industrial 256K x 36 (9 Mbit) 1.8V Synchronous CYD09S36V18 Dual-Port SRAM Speed (MHz) Ordering Code Package Name Package Type Operating Range 250 CYD09S36V18-250BBC BB256 256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (FBGA) Commercial 200 CYD09S36V18-200BBC BB256 256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (FBGA) Commercial CYD09S36V18-200BBI BB256 256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (FBGA) Industrial 167 CYD09S36V18-167BBC BB256 256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (FBGA) Commercial CYD09S36V18-167BBI BB256 256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (FBGA) Industrial 128K x 36 (4 Mbit) 1.8V Synchronous CYD04S36V18 Dual-Port SRAM Speed (MHz) Ordering Code Package Name Package Type Operating Range 250 CYD04S36V18-250BBC BB256 256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (FBGA) Commercial 200 CYD04S36V18-200BBC BB256 256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (FBGA) Commercial CYD04S36V18-200BBI BB256 256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (FBGA) Industrial 167 CYD04S36V18-167BBC BB256 256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (FBGA) Commercial CYD04S36V18-167BBI BB256 256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (FBGA) Industrial 2048K x 18 (36 Mbit) 1.8V Synchronous CYD36S18V18 Dual-Port SRAM Speed (MHz) Ordering Code Package Name Package Type Operating Range 200 CYD36S18V18-200BBC BY484 484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (PBGA) Commercial 167 CYD36S18V18-167BBC BY484 484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (PBGA) Commercial CYD36S18V18-167BBI BY484 484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (PBGA) Industrial CYD36S18V18-133BBC BY484 484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (PBGA) Commercial CYD36S18V18-133BBI BY484 484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (PBGA) Industrial 133 1024K x 18 (18 Mbit) 1.8V Synchronous CYD18S18V18 Dual-Port SRAM Speed MHz) Ordering Code 250 CYD18S18V18-250BBC 200 167 Package Name Package Type Operating Range BW256C 256-ball Grid Array 19 mm x 19 mm with 1.0 mm pitch (FBGA) Commercial CYD18S18V18-200BBC BW256C 256-ball Grid Array 19 mm x 19 mm with 1.0 mm pitch (FBGA) Commercial CYD18S18V18-200BBI BW256C 256-ball Grid Array 19 mm x 19 mm with 1.0 mm pitch (FBGA) Industrial CYD18S18V18-167BBC BW256C 256-ball Grid Array 19 mm x 19 mm with 1.0 mm pitch (FBGA) Commercial CYD18S18V18-167BBI BW256C 256-ball Grid Array 19 mm x 19 mm with 1.0 mm pitch (FBGA) Industrial Document #: 38-06082 Rev. *C Page 43 of 48 PRELIMINARY FullFlex Ordering Information (continued) 512K x 18 (9 Mbit) 1.8V Synchronous CYD09S18V18 Dual-Port SRAM Speed (MHz) Ordering Code Package Name Package Type Operating Range 250 CYD09S18V18-250BBC BB256 256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (FBGA) Commercial 200 CYD09S18V18-200BBC BB256 256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (FBGA) Commercial CYD09S18V18-200BBI BB256 256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (FBGA) Industrial CYD09S18V18-167BBC BB256 256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (FBGA) Commercial CYD09S18V18-167BBI BB256 256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (FBGA) Industrial 167 256K x 18 (4 Mbit) 1.8V Synchronous CYD04S18V18 Dual-Port SRAM Speed (MHz) Ordering Code Package Name Package Type Operating Range 250 CYD04S18V18-250BBC BB256 256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (FBGA) Commercial 200 CYD04S18V18-200BBC BB256 256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (FBGA) Commercial CYD04S18V18-200BBI BB256 256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (FBGA) Industrial 167 CYD04S18V18-167BBC BB256 256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (FBGA) Commercial CYD04S18V18-167BBI BB256 256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (FBGA) Industrial Document #: 38-06082 Rev. *C Page 44 of 48 FullFlex PRELIMINARY Package Diagrams TOP VIEW 256-Ball FBGA (17 x 17 mm) BB256 BOTTOM VIEW O0.05 M C O0.25 M C A B PIN 1 CORNER O0.450.05(256X)-CPLD DEVICES (37K & 39K) PIN 1 CORNER 1 2 3 4 5 6 7 8 9 +0.10 -0.05 O0.50 (256X)-ALL OTHER DEVICES 10 11 12 13 14 15 16 16 15 14 13 12 11 10 9 8 7 6 5 4 2 1 A B B C C D D 1.00 A E E F F G H J K H 15.00 17.000.10 G J K L M 7.50 L M N N P P R R T T 1.00 7.50 0.15 C 0.700.05 B 0.25 C 3 15.00 A 17.000.10 A 0.20(4X) SEATING PLANE +0.10 -0.05 C A1 0.36 0.56 REFERENCE JEDEC MO-192 51-85108-*F 0.35 A1 A 1.40 MAX. 1.70 MAX. Document #: 38-06082 Rev. *C Page 45 of 48 FullFlex PRELIMINARY Package Diagrams (continued) 256 FBGA (19 x 19 x 1.7 mm) BW256C BOTTOM VIEW TOP VIEW A1 CORNER O0.05 M C O0.25 M C A B PIN A1 CORNER 1 O0.50 (256 X) 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 B C C D D E E F F G G 19.00 +/- 0.10 H J K L 1.00 (REF) A B 15.00 (REF) A H J K L M M N N P P R R T T 1.00 (REF) -B- 15.00 (REF) -A- 19.00 +/- 0.10 Package Weight - 1.1 grams 0.15 C 0.70 (REF) 0.25 C 0.15(4X) 001-00915-*A Document #: 38-06082 Rev. *C 1.70 MAX. 0.35 +0.10/-0.05 SEATING PLANE 0.56 (REF) -C- Jedec Outline - Design Guide 4.14 Page 46 of 48 FullFlex PRELIMINARY Package Diagrams (continued) 484-ball PBGA (23 mm x 23 mm x 2.03 mm) BY484 O0.50~O0.70(484X) PIN #1 CORNER 1 3 2 5 4 7 6 9 8 15 13 11 10 12 14 19 17 16 18 21 20 21 22 22 O1.00(3X) REF. 18 14 9 11 13 15 16 12 10 7 8 1 3 5 6 4 2 A B C D E F G H J K L M N P R T U V W Y AA AB 21.00 23.000.20 20.00 REF. 1.00 A B C D E F G H J K L M N P R T U V W Y AA AB 17 19 20 1.00 -B- 21.00 3.20*45(4x) -A20.00 REF. 23.000.20 0.35 C 0.20 C f 0.25 C 30 TYP. f 0.97 REF. 0.20(4X) 2.03 0.13 0.40~0.60 SEATING PLANE 0.56 REF. -C- Package Weight - 2.0 grams Jedec Outline - Design Guide 4.14 51-85218-** FullFlex is a trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this document are trademarks of their respective holders. Document #: 38-06082 Rev. *C Page 47 of 48 PRELIMINARY FullFlex Document History Page Document Title: FullFlexTM Synchronous SDR Dual-Port SRAM Document Number: 38-06082 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 302411 See ECN YDT New data sheet *A 334036 See ECN YDT Corrected typo on page 1 Reproduced PDF file to fix formatting errors *B 395800 See ECN SPN Added statement about no echo clocks for flow-through mode Updated electrical characteristics Added note 16 and 17 (1.5V timing) Added note 33 (timing for x18 devices) Updated input edge rate (note 34) Updated table 5 on deterministic access control logic Added description of busy readback in deterministic access control section Changed dummy write descriptions Updated ZQ pins connection details Updated note 24, B0 to BE0 Added power supply requirements to MRST and VC_SEL Added note 4 (VIM disable) Updated supply voltage to ground potential to 4.1V Updated parameters on table 15 Updated and added parameters to table 16 Updated x72 pinout to SDR only pinout Updated 484 PBGA pin diagram Updated the pin definition of MRST Updated the pin definition of VC_SEL Updated READY description to include Wired OR note Updated master reset to include wired OR note for READY Updated minimum VOH value for the 1.8V LVCMOS configuration Updated electrical characteristics to include IOH and IOL values Updated electrical characteristics to include READY Added IIX3 Updated maximum input capacitance Added Note 33 Added Note 34 Removed Notes 15 and 17 Updated Pin Definitions for CQ0, CQ0, CQ1, and CQ1 Removed -100 Speed bin from Table.1 Selection Guide Changed voltage name from VDDQ to VDDIO Changed voltage name from VDD to VCORE Moved the Mailbox Interrupt Timing Diagram to be the final timing diagram Updated the Package Type for the CYD36S18V18 parts Updated the Package Type for the CYD36S18V18 parts Updated the Package Type for the CYD18S18V18 parts Updated the Package Type for the CYD18S36V18 parts Included the Package Diagram for the 256-Ball FBGA (19 x 19 mm) BW256 Included an OE Controlled Write for Flow-Through Mode Switching Waveform Included a Read with Echo Clock Switching Waveform Updated Figure 5 and Figure 6 Updated Electrical Characteristics for READY VOH and READY V Updated Electrical Characteristics for VOH and VOL for the -167 and -133 speeds Included a Unit column for Table 5 Removed Switching Characteristic tCA from chart Included tOHZ in Switching Waveform OE Controlled Write for Pipelined Mode Included tCKLZ2 in Waveform Read-to-Write-to-Read for Flow-Through Mode *C 402238 SEE ECN KGH Updated AC Test Load and Waveforms Included FullFlex36 SDR 484-ball BGA Pinout (Top View) Included FullFlex18 SDR 484-ball BGA Pinout (Top View) Included Timing Parameter tCORDY Document #: 38-06082 Rev. *C Page 48 of 48