1
®
FN9079.1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 |Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002, 2004. All Rights Reserved
Intellitrip™ is a trademark of Intersil Americas Inc.
ISL6141, ISL6151
Negative Voltage Hot Plug Controller
The ISL6141 is an 8-pin, negative v oltage hot plug controller
that allows a board to be safely inserted and removed from a
live bac kplane. Inrush current is limited to a programmable
value by controlling the gate voltage of an external N-
channel pass transistor. The pass transistor is turned off if
the input voltage is less than the Under-Voltage threshold, or
greater than the Over-Voltage threshold. The IntelliTripTM
electronic circuit break er and programmable current limit
features protect the system against short circuits. When the
Over-Current threshold is exceeded, the output current is
limited for 600µs before the circuit breaker shuts down the
FET. If the fault disappears before the 600µs time-out,
nor mal operation resumes. In addition, the IntelliTripTM
electronic circuit breaker has a fast Hard F ault shutdown with
a threshold set at 4 times the current limit value. When
activated, the GATE is immediately turned off and then
slowly turned back on for a single retry (soft-start). The
active low PWRGD signal can be used to directly enable a
power module (with a low enable input). The ISL6151 is the
same device but has an active high PWRGD output.
Typical Application (RL, CL are the Load)
Features
• Operates from -20V to -80V (-100V Absolute Max Rating)
• Programmable Inrush Current
• Programmable Over-Voltage Protection
• Programmable Under-Voltage Protection
- 135mV of hysteresis
- Equals ~4.6V of hysteresis at the power supply
• UVLO (Under-Voltage Lock-Out) ~ 16.5V
• Programmable Current Limit with 600µs time-out
• IntelliTripTM electronic circuit breaker distinguishes
between Over-Current and Hard Fault conditions
- Fast shutdown for Hard Faults with a single retry (fault
current > 4X current limit value).
• Pin Compatible with ISL6140/50.
• Power Good Control Output
- Monitors both the DRAIN (voltage drop across the FET)
and the GATE voltage; once both are OK, the Power
Good output is latched in the active state.
- PWRGD active high: ISL6151 (H version)
-PWRGD
active low: ISL6141 (L version)
• Pb-free available
Applications
• VoIP (Voice over Internet Protocol) Servers
• Telecom systems at -48V
• Negative Power Supply Control
• +24V Wireless Base Station Po wer
Related Literature
• ISL6140/41 EVAL1 Board Set, Document # AN9967
• ISL6142/52 EVAL1 Board Set, Document # AN1000
• ISL6140/50 Hot Plug Control l er, Document # FN9039
• ISL6116 Hot Plug Controller, Document # FN4778
NOTE: See www.intersil.com/hotplug for more information.
Pinout ISL6141 OR ISL6151 (8 LEAD SOIC)
ISL6141 has active low (L version) PWRGD output pin
ISL6151 has active high (H version) PWRGD output pin
R1 = 0.02Ω (1%)
R2 = 10Ω (5%)
R3 = 18kΩ (5%)
R4 = 549kΩ (1%)
R5 = 6.49kΩ (1%)
R6 = 10kΩ (1%)
C1 = 150nF (25V)
C2 = 3.3nF (100V)
Q1 = IRF530 (100V, 17A, 0.11Ω)
CL = 100µF (100V)
RL = equivalent load
ISL6141
VDD
UV
OV
VEE SENSE GATE DRAIN
PWRGD
R4
R5
R6
R1
R2 R3 C2
C1
Q1
CL
GND GND
-48V IN -48V OUT
RL
(LOAD)
OV
VEE 5
7
6
4
3
2
GATE
DRAIN
UV
SENSE
PWRGD/PWRGD 1VDD
8
TOP VIEW
Data Sheet July 2004
2
Ordering Information
PART NO. TEMP. RANGE (oC) PACKAGE PKG.
DWG. #
ISL6141CB 0 to 70 8 Lead SOIC M8.15
ISL6141CBZA
(See Note) 0 to 70 8 Lead SOIC
(Pb-free) M8.15
ISL6151CB 0 to 70 8 Lead SOIC M8.15
ISL6151CBZA
(See Note) 0 to 70 8 Lead SOIC
(Pb-free) M8.15
ISL6141IB -40 to 85 8 Lead SOIC M8.15
ISL6141IBZA
(See Note) -40 to 85 8 Lead SOIC
(Pb-free) M8.15
ISL6151IB -40 to 85 8 Lead SOIC M8.15
ISL6151IBZA
(See Note) -40 to 85 8 Lead SOIC
(Pb-free) M8.15
*Add “-T” suffix to part number for tape and reel packaging.
NOTE: Intersil Pb-free products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which is compatible with both SnPb and
Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J Std-020B.
Ordering Information (Continued)
PART NO. TEMP. RANGE (oC) PACKAGE PKG.
DWG. #
C1
Q1
R2
R1
CL RL
-48V IN -48V OUT
LOAD
C2
R3
+
-
+
-
VEE
1.255V
+
-
+
-
VEE
50mV
+
-
+
-VEE
1.255V
+
-
+
-
VEE
11.1V
+
-
VEE
210mV
+
-
+
-
VEE
1.265V
+
-
+
-
VEE
1.3V
R4
R5
R6
GND
GND
LOGIC
TIMING
GATE DRIVE
REGULATOR,
REFERENCES
PWRGD
LATCH
LOGIC
UV
OV
VEE SENSE
VDD
PWRGD
GATE DRAIN
UVLO
UV
OV
CURRENT
LIMIT
HARD
GATE
GATE
13V
600µs
TIMER
PWRGD
FIGURE 1. BLOCK DIAGRAM
FAULT
(ISL6141)
(ISL6151)
PWRGD
OUTPUT
DRIVE
REGULATOR
VEE
+
-
ISL6141, ISL6151
3
Pin Descriptions
PWRGD (ISL6141; L Version) Pin 1
This digital output is an open-dr a in pull-d o wn device. Du ring
start-up the DRAIN and GATE v oltages are monitored w ith
two separate comparators. The first compara tor looks at the
DRAIN pin v o ltage compared to the inte rnal VPG reference
(VPG is nominal 1.3V); this measures the v oltage drop across
the e xternal FET and sense resistor. When the DRAIN to V EE
v oltage drop is less than 1.3V, the first of two conditions
required for the pow e r to be considered good are met. In
addition, the GATE voltage monitored b y the se con d
comparator must be within app roximately 2.5V of its normal
operating voltage (1 3.6V). When both criteria are met the
PWRGD output will transition from high to lo w, enab lin g a
pow er module in some applications. The output is latched in
the low state until an y of th e signals that sh ut off the GATE
occur (Over-Voltage, Under-Voltage , Under-V oltage Loc k-Out,
Ov er-Current Time-Out, or po w ering down). An y of these
conditions will re-set the latch and the PWRGD output will
transition fro m lo w to high in dicating power is n o longer g ood.
In this case the output pull-do wn device shuts off, and the pin
becomes high impedance . Typically an ex ternal pull-up of
some kind is used to pull the pin high (many brick regul ators
have a pull-up function built in).
PWRGD (ISL6151; H Version) Pin 1 - This digital
output is used to provide an active high signal to enable an
exter nal module. The Power Good comparators are the
same as described above, but the active state of the output
is reversed (reference Figure 33).
If the latch is reset (GATE turns off), the internal DMOS
device (Q3) is turned off, and Q2 (NPN) turns on to clamp
the output one diode drop above the DRAIN voltage to
produce a logic low.
Once the latch is set (both DRAIN and GATE are normal), the
DMOS de vice (Q3) turns on and sinks current to VEE through
a 6.2KΩ resistor. The base of Q2 is clamped to VEE to turn it
off . If the external pull-up current is high enough (>1mA, for
e xamp le), the voltage drop across the re sistor will be large
enough to produce a l ogic high output (in this e xample , 1mA *
6.2kΩ = 6.2V) and enable the external module.
Note that for all H versions , although this is a digital pin
functionally, the logic high lev el is determined b y the external
pull-up device, and the power supply to which it is
connected; the IC will not clamp it below the VDD voltage.
Therefore, if the external device does not have its own
clamp, or if it would be damaged by a high voltage, an
exter nal clamp might be necessary.
OV (Over-Voltage) Pin 2 - This analog input compares the
voltage on the pin to an internal voltage reference of 1.255V
(nominal). When the input goes above the reference (low to
high transition) an Over-Voltage condition is detected and
the GATE pin is immediatel y pulled low to shut off the
external FET. The built in 25mV hysteresis will keep the
GATE off until the OV pin drops below 1.230V, which is the
nominal high to low threshold. A typica l application will use
an external resistor divider from VDD to VEE to set the OV
le vel as desired. A three-resistor divider can be used to set
both OV and UV trip points.
UV (Under-Voltage) Pin 3 - This analog input compares the
voltage on the pin to an internal comparator with a built in
hysteresis of 135mV. When the UV input goes below the
nominal reference (high to low transition) voltage of 1.120V,
the GATE pin is immediately pulled low to shut off the
external FET. Since the comparator has a built in 135mV
h ysteresis the GATE will remain off until the UV pin rises
above a 1.255V low to high threshold. A typical application
will use an external resistor divider from VDD to VEE to set
the UV level as desired. A three-resistor divider can be used
to set both OV and UV trip points.
The UV pin is also used to reset the Over-Current latch. The
pin must be cycled below 1.120V (nominal) and then above
1.255V (nominal) to clear the latch and initiate a normal
power-up sequence.
VEE Pin 4 - This is the most negative supply voltage, such
as in a -48V system. Most of the other signals are ref erenced
relative to this pin, ev en though it ma y be far awa y from what
is considered a GND reference.
SENSE Pin 5 - This analog input monitors the voltage drop
across the external sense resistor (between SENSE and
VEE) to determine if the current exceeds the programmed
Over-Current trip point, equal to 50mV / Rsense. If the load
current exceeds the Over-Current threshold, the circuit will
regulate the current to maintain the nomin al voltage drop
(50mV) across the sensing resistor R1 (Rsense). If current is
limited for more than 600µs, the Ov er-Cu rrent shutdown
(also called electronic circuit breaker) will quickly turn off the
FET and latch the GATE pin off.
A Hard Fault comparator is employed to detect and respond
quickly to severe short circuits. The threshold of this
comparator is set approximately four times higher (210mV)
than the Over-Current trip point. When its threshold is
exceeded the GATE is immediately (10µs typical) shut off,
the timer is reset, and a single retry (soft start) is attempted
before latching the GATE off (assuming the fault remains).
During the retry, if the fault disappears pr ior to the Over-
Current Time-Out period (600µs) the FET will remain on as
normal. If the GATE is latched off , the user must either toggle
the UV pin below then above its threshold, or reduce the
supply voltage below the VDD UVLO trip point and then
above it. This will clear the latch and initiate a normal power-
up sequence.
ISL6141, ISL6151
4
GATE Pin 6 - This analog output drives the gate of the
ex ternal FET used as a pass transistor . The GATE pin is high
(FET is on) when the following conditions are met:
• UVLO is above its trip point (~16.5V)
• Voltage on the UV pin is abov e its trip point (1.255V)
• Voltage on the OV pin is below its trip point (1.255V)
• No Over-Current conditions are present.
If any of the 4 conditions are violated, the GATE pin will be
pulled low to shut off or regulate current through the FET.
The GATE is latched off only wh en the 600µs Over-Current
Time-Out per iod is exceeded.
The GATE is driven high by a weak (-50µA nominal) pul l -up
current source, in order to slowly turn on the FET. It is driven
low by a 70mA nominal pull-down device for three of the
abov e shut-off conditions. A larger (350mA nominal) pull-
down current shuts off the FET very quic kly in the event of a
hard fault where the sense pin voltage exceeds
appro ximately 210mV.
DRAIN Pin 7 - This is the analog input to one of two
comparators that control the PWRGD (ISL6141) or PWRGD
(ISL6151) outputs. It compares the voltage of the external
FET DRAIN to a 1.3V internal reference (VPG). The DRAIN
voltage is criticized only until the PWRGD or PWRGD
outputs are latched into their active low or high states. The
latch is reset when any of the conditions that turn off the
GATE occur (UVLO, OV, UV, OC Time-Out). Note that the
comparator does NOT itself turn off the GATE.
VDD Pin 8 - This is the most positive po wer supply pin. It can
range from the Under-Voltage Lock-Out threshold (16.5V) to
+80V (Relative to VEE).
ISL6141, ISL6151
5
.
Absolute Maximum Ratings Thermal Info rmation
Supply Voltage (VDD to VEE). . . . . . . . . . . . . . . . . . . .-0.3V to 100V
DRAIN, PWRGD, PWRGD Voltage . . . . . . . . . . . . . . .-0.3V to 100V
UV, OV Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to 60V
SENSE, GATE Voltage . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to 20V
ESD Rating
Human Body Model (Per MIL-STD-883 Method 3015.7) . . .2000V
Operating Conditions
Temperature Range (Industrial). . . . . . . . . . . . . . . . . -40oC to 85oC
Temperature Range (Commercial). . . . . . . . . . . . . . . . . 0oC to 70oC
Supply Voltage Range (Typical). . . . . . . . . . . . . . . . . . . 36V to 72V
Thermal Resistance (Typical, Note 1) θJA (oC/W)
8 Lead SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC
Maximum Storage Temperature Range. . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditi ons above those indicated in the operational sections of this specification is not implied.
NOTES:
1. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
2. PWRGD is referenced to DRAIN; VPWRGD-VDRAIN = 0V.
Electrical Specifications VDD = +48V, VEE = +0V Unless Otherwise Specified. All tests are over the full temperature range; either
Commercial (0oC to 70oC) or Industrial (-40oC to 85oC). Typical specs are at 25oC.
PARAMETER SYMBOL
TEST CONDITIONS MIN TYP MAX Units
DC PARAMETERS
VDD PIN
Supply Operating Range VDD 20 - 80 V
Supply Current IDD UV = 3V; OV = VEE; SENSE = VEE; VDD =
80V 2.4 4.5 mA
UVLO High VUVLOH VDD Low to High transition 15 16.7 19 V
UVLO Low VUVLOL VDD High to Low transition 13 14.8 17 V
UVLO hysteresis 1.9 V
GATE PIN
GATE Pin Pull-Up Current IPU GATE Drive on, VGATE = VEE -30 -50 -60 µA
GATE Pin Pull-Down Current IPD1 GATE Drive off, UV or OV false 70 mA
GATE Pin Pull-Down Current IPD2 GATE Drive off, Over-Current Time-Out 70 mA
GATE Pin Pull-Down Current IPD3 GATE Drive off; Hard Fault (Vsense > 210mV) 350 mA
External GATE Drive (VDD = 20V, 80V) ∆ VGATE (VGATE - VEE), 20V <=VDD <=80V 12 13.6 15 V
GATE High Threshold (PWRGD/PWRGD
active) VGH ∆VGATE - VGATE 2.5 V
SENSE PIN
Current Limit Trip Voltage VCL VCL = (VSENSE - VEE)405060mV
Hard Fault Trip Voltage VHFT VHFTV = (VSENSE - VEE) 210 mV
SENSE Pin Current ISENSE VSENSE = 50mV -1.3 -4.0 µA
UV PIN
UV Pin High Threshold Voltage VUVH UV Low to High Transition 1.240 1.255 1.270 V
UV Pin Low Threshold Voltage VUVL UV High to Low Transition 1.105 1.120 1.145 V
UV Pin Hysteresis VUVHY 135 mV
ISL6141, ISL6151
6
UV Pin Input Current IINUV VUV = VEE -0.05 -0.5 µA
OV pin
OV Pin High Threshold Voltage VOVH OV Low to High Transition 1.235 1.255 1.275 V
OV Pin Low Threshold Voltage VOVL OV High to Low Transition 1.215 1.230 1.255 V
OV Pin Hysteresis VOVHY 25 mV
OV Pin Input Current IINOV VOV = VEE -0.05 -0.5 µA
DRAIN Pin
Power Good Threshold (PWRGD/PWRGD
active) VPG VDRAIN - VEE 0.80 1.30 2.00 V
DRAIN Input Bias Current IDRAIN VDRAIN = 48V 38 60 µA
ISL6141 (PWRGD Pin: L Version)
PWRGD Output Low Voltage VOL1
VOL5 (VDRAIN - VEE) < VPG; IOUT = 1mA - 0.30 1.0 V
(VDRAIN - VEE) < VPG; IOUT = 5mA - 1.50 3.0 V
Output Leakage IOH VDRAIN = 48V, V PWRGD = 80V - 0.05 10 µA
ISL6151 (PWRGD Pin: H Version)
PWRGD Output Low Voltage (PWRGD-DRAIN) VOL VDRAIN = 5V, IOUT = 1mA - 0.85 1.0 V
PWRGD Output Impedance ROUT (VDRAIN - VEE) < VPG 3.5 6.2 9.0 kΩ
AC Timing
OV High to GATE Low tPHLOV Figures 2A, 3A 0.6 1.3 3.0 µs
OV Low to GATE High tPLHOV Figures 2A, 3A 1.0 4.5 12.0 µs
UV Low to GATE Low tPHLUV Figures 2A, 3B 0.6 0.90 3.0 µs
UV High to GATE High tPLHUV Figures 2A, 3B 1.0 5.0 12.0 µs
SENSE High to GATE Low tPHLSENSE Figures 2A, 6 0.35 3 µs
Current Limit to GATE Low (O.C. Time-out) tPHLCB Figures 2B, 8 600 µs
Hard Fault to GATE Low (200mV comparator)
Typical GATE shutdown based on application
ckt. Guaranteed by design.
tPHLHF Figures 7, 23, 27 (zero Ω short to VDD)10µs
ISL6141 (L Version)
DRAIN Low to PWRGD Low tPHLDL Figures 2A, 4A (note 2) 3.0 5.0 µs
GATE High to PWRGD Low tPHLGH Figures 2A, 5A (note 2) 1.0 3.0 µs
ISL6151 (H Version)
DRAIN Low to (PWRGD-DRAIN) High tPLHDL Figures 2A, 4B (note 2) 3.0 5.0 µs
GATE High to (PWRGD-DRAIN) High tPLHGH Figures 2A, 5B (note 2) 0.4 3.0 µs
Electrical Specifications VDD = +48V, VEE = +0V Unless Otherwise Specified. All tests are over the full temperature range; either
Commercial (0oC to 70oC) or Industrial (-40oC to 85oC). Typical specs are at 25oC. (Continued)
PARAMETER SYMBOL
TEST CONDITIONS MIN TYP MAX Units
ISL6141, ISL6151
7
Test Circuit and Timing Diagrams
FIGURE 2A. TYPICAL TEST CIRCUIT FIGURE 2B. TEST CIRCUIT FOR 600µs TIME-OUT
FIGURE 3A. OV TO GATE TIMING FIGURE 3B. UV TO GATE TIMING
FIGURE 3. OV AND UV TO GATE TIMING
FIGURE 4A. DRAIN TO PWRGD TIMING (ISL6141) FIGURE 4B. DRAIN TO PWRGD TIMING (ISL6151)
FIGURE 4. DRAIN TO PWRGD/PWRGD TIMING
FIGURE 5A. GATE TO PWRGD (ISL6141) FIGURE 5B. GATE TO PWRGD (ISL6151)
FIGURE 5. GATE TO PWRGD/PWRGD TIMING
OV
VEE 5
7
6
4
3
2
GATE
DRAIN
UV
SENSE
PWRGD 1
VDD
8
5V
VOV
VUV
48V
VDRAIN
VSENSE
ISL6141
ISL6151
R = 5K
+
-
.
OV
VEE 5
7
6
4
3
2
GATE
DRAIN
UV
SENSE
PWRGD 1
VDD
8
5V
VOV
VUV
48V
VDRAIN
ISL6141
ISL6151
R = 5K
+
-
0.1KΩ
0.9KΩ
9.0KΩ
GATE
tPHLOV tPLHOV
0V
2V
1V
1.255V 1.230V
1V
0V
13.6V
OV Pin
GATE
tPHLUV tPLHUV
2V
0V
1V
1.120V 1.255V
1V
13.6V
0V
UV Pin
tPHLDL
DRAIN
PWRGD
1.3V
1.0V
VEE
VPG
PWRGD
tPHLDL
1.3V
1.0V
DRAIN
VEE
VPG
tPHLGH
2.5V
1.0V
GATE
PWRGD
∆VGATE - VGATE = 0V
VGH
tPLHGH
GATE
PWRGD
2.5V
1.0V
VPWRGD - VDRAIN = 0V
∆VGATE - VGATE = 0V
VGH
ISL6141, ISL6151
8
FIGURE 6. SENSE TO GATE TIMING FIGURE 7. SENSE TO GATE (Hard Fault) TIMING
FIGURE 8. CURRENT LIMIT TO GATE TIMING
Test Circuit and Timing Diagrams (Continued)
SENSE
GATE
tPHLSENSE
~4V (depends on FET threshold)
50mV SENSE
GATE
tPHLHF
VEE
210mV
13.6V
0V
tPHLCB
UV
1.0V 1.0V
GATE
Typical Performance Curves
FIGURE 9. SUPPLY CURRENT VS. SUPPLY VOLTAGE (25oC) FIGURE 10. SUPPLY CURRENT VS. TEMPERATURE, VDD = 48V
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
10 20 30 40 50 60 70 80 90 100
Supply Voltage (VDD)
IDD (mA)
1.95
2
2.05
2.1
2.15
2.2
2.25
2.3
-40-20 0 20406080100
Temperature (C)
IDD (mA)
ISL6141, ISL6151
9
FIGURE 11. SUPPLY CURRENT VS TEMPERATURE, VDD = 80V FIGURE 12. GATE VOLTAGE VS SUPPLY VOLTAGE (25oC)
FIGURE 13. GATE VOLTAGE VS TEMPERATURE, VDD = 48V FIGURE 14. GATE VOLTAGE VS TEMPERATURE, VDD = 80V
FIGURE 15. GATE VOLTAGE VS TEMPERATURE, VDD = 20V FIGURE 16. GATE PULL-UP CURRENT VS TEMPERATURE
Typical Performance Curves (Continued)
2.1
2.15
2.2
2.25
2.3
2.35
2.4
2.45
-40-20 0 20406080100
Temperature (C)
IDD (mA)
0
2
4
6
8
10
12
14
16
10 20 30 40 50 60 70 80 100
Supply Voltage (VDD)
Gate Voltage (V)
13.3
13.4
13.5
13.6
13.7
13.8
13.9
14
-40-20 0 20406080100
Temperature (C)
Gate Voltage (V)
13.4
13.5
13.6
13.7
13.8
13.9
14
-40 -20 0 20 40 60 80 100
Temperature (C)
Gate Voltage (V)
13.4
13.5
13.6
13.7
13.8
13.9
14
-40-200 20406080100
Temperature (C)
Gate Voltage (V)
41
42
43
44
45
46
47
48
49
50
-40 -20 0 20 40 60 80 100
Temperature (C)
Gate Current (uA)
ISL6141, ISL6151
10
FIGURE 17. GATE PULL-DOWN CURRENT
(UV/OV/TIME-OUT) VS TEMPERATURE FIGURE 18. HARD F A ULT GATE PULL-DO WN CURRENT
(200mV COMPARATOR) VS TEMPERATURE
FIGURE 19. O VER-CURRENT TRIP V OL TAGE VS
TEMPERATURE FIGURE 20. PWRGD (ISL6141) VOL VS TEMPERATURE
FIGURE 21. PWRGD (ISL6151) IMPED ANCE VS
TEMPERATURE FIGURE 22. DRAIN to PWRGD / PWRGD TRIP VOLTAGE (VPG)
VS TEMPERATURE
Typical Performance Curves (Continued)
0
10
20
30
40
50
60
70
80
90
-40 -20 0 20 40 60 80 100
Temperature (C)
Gate Pull Down Current (mA)
0
50
100
150
200
250
300
350
400
450
-40-20 0 20406080100
Temperature (C)
Gate Pull Down Current (mA)
40
42
44
46
48
50
52
54
-40 -20 0 20 40 60 80 100
Temperature (C)
Trip Voltage (mv)
(1 ma)
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
-40 -20 0 20 40 60 80 100
Temperature (C)
Output Low Voltage (V)
5mA
1mA
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
-40-20 0 20406080100
Temperature (C)
Impedance (KOhms)
0
0.5
1
1.5
2
-40-20 0 20406080100
Temperature (C)
Trip Voltage (V)
ISL6141, ISL6151
11
Applications Information
Typica l Values for a represent at iv e sy st em ; wh ich
assumes:
• 43V to 71V supply range; 48 nominal; UV = 43V;
OV = 71V
• 1Amp of typical current draw; 2.5 Amp Over-Current
• 100µF of load capacitance (CL); equ ivalent RL of 48Ω
(R = V/I = 48V/1A)
R1: 0.02Ω (1%)
R2: 10Ω (5%)
R3: 18kΩ (5%)
R4: 549kΩ (1%)
R5: 6.49kΩ (1%)
R6: 10kΩ (1%)
C1: 150nF (25V)
C2: 3.3nF (100V)
Q1: IRF530 (100V, 17A, 0.11 Ω)
Quick Guide to Choosing Component
Values
(See fig 23 for refere nce)
This section will describe the minimum components needed
for a typical application, and will show how to select
component values. (Note that “typical” values may on ly be
good for this application; the user may have to select
alter nate component values to optimize performance for
other applications). Each block will then have more detailed
explanation of how the device works, and alternatives.
R4, R5, R6 - togethe r set the Under-Voltage (UV) and Over-
Voltage (OV) trip points. When the power supply ramps up
and down, these trip points (and their hysteresis) will
deter mine when the GATE is allowed to turn on and off (UV
and OV do not control the PWRGD / PWRGD output). The
input power supply is divided down such that when the
voltage on the OV pin is below its threshold and the UV pin is
above its threshold their comparators will be in the proper
state signaling the supply is within its desired range, allo wing
the GATE to turn on. The equation s below define the
comparator thresholds for an increasing (in magnitude)
supply voltage.
The values of R4 = 549K, R5 = 6.49K, and R6 = 10K shown
in figure 23 set the Under-Voltage turn-on threshold to 43V,
and the Over-Voltage turn off threshold to 71V. The Under-
Voltage (UV) comparator has a hysteresis of 135mV (4.6V of
hysteresis on the supply) which correlates to a 38.4V turn off
voltage. The Over-Voltage comparator has a 25mV
hysteresis which translates to a turn on voltage (supply
decreasing) of approximately 69.6V.
Q1 - is the FET that connects the input supply voltage to the
output load, when properly enabled. It needs to be selected
based on several criteria:
• Maximum voltage expected on the input supply (including
transients) as well as transients on the output side.
• Maximum current and power dissipation expected during
nor m al operation, usually at a level just below the current
limit threshold.
• Power dissipation and/or safe-operating-area
considerations during current limiting and single retry
events.
• Other considerations include the GATE voltage threshold
which affects the rDS(ON) (which in turn, affects the
voltage drop across the FET during normal operation),
and the maximum GATE voltage allowed (the ICs GATE
output is clamped to ~14V).
ISL6141
V
DD
UV
OV
V
EE
SENSE GATE DRAIN
PWRGD
R4
R5
R6
R1
R2 R3 C2
C1
Q1
CL
GND
-48V IN
-48V OUT
RL
(LOAD)
FIGURE 23. TYPICAL APPLICATION WITH MINIMUM COMPONENTS
VUV R4R5R6
++〈〉
R5R6
+()
-----------------------------------------1.255×=(EQ. 1)
VOV R4R5R6
++〈〉
R6
()
-----------------------------------------1.255×=(EQ. 2)
ISL6141, ISL6151
12
R1 - Is the Ov er-Current sense resistor . If the input current is
high enough, such that the voltage drop across R1 exceeds
the SENSE comparator trip point (50mV nominal), the GATE
pin will be pulled lower (to ~4V) and current will be regulated
to 50mV/Rsense for appro ximately 600µs. The Ov er-Current
threshold is de fi n e d in Equation 3 bel ow. If the 600µs time-
out period is e xceeded the Over-Current latch will be set and
the FET will be turned off to protect the load from excessive
current. A typical value for R1 is 0.02Ω, which sets an Over-
Current trip poi nt of; IOC = V/R = 0.05/0.02 = 2.5 Amps. To
select the appropriate value for R1, the user must first
deter mine at what level of current it should trip, take into
account worst case variations for the trip point (50mV
±10mV = ±20%), and the tolerances of the resistor (typically
1% or 5%). Note that the Over-Current threshold should be
set above the inrush current level plus the expected load
current to avoid activating the current limit and time-out
circuitr y during start-up. If the power good output is used to
enable an external module, the desired inrush current only
needs to be considered. One rule of thumb is to set the
Over-Current threshold 2-3 times higher than the normal
operating current.
Physical layout of R1 SENSE resistor is critical to avoid
the possibility of false over current events. Since it is in the
main input-to-output path, the traces should be wide enough
to support both the normal current, and up to the over-
current trip point. Id eally trace routing between the R1
resistor and the ISL6141/51 (pin 4 (VEE) and pin 5 (SENSE)
is direct and as short as possible with zero current in the
sense lines. (See Figure 24).
CL - is the sum of all load capacitances, including the load’s
input capacitance itself. Its value is usually deter m ined by
the needs of the load circuitry, and not the hot plug (although
there can be interaction). For example, if the load is a
regulator , then the capacitance ma y be chosen based on the
input requirements of that circuit (holding regulation under
current spikes or loading, filtering noise, etc.) The value
chosen will affect the peak inrush cu rrent. Note that in the
case of a regulator , there ma y be capacitors on the output of
that circuit as well; these need to be added into the
capacitance calculation during inrush (unless the regulator is
delayed from operation by the PWRGD signal).
RL - is the equiv alent resistive value of the load and
determines the nor m al operation current delivered through
the FET. It also affects some dynamic conditions (such as
the discharge time of the load capacitors during a power-
down). A typical value might be 48Ω (I = V/R = 48/48 = 1A).
R2, C1, R3, C2 - are related to the GATE driver, as it
controls the inrush current.
R2 prevents high frequency oscillations; 10Ω is a typical
value. R2 = 10Ω.
R3 and C2 act as a feedback network to control the inrush
current as shown in equation 4 below, where CL is the load
capacitance (including module input capacitance), and IPU is
the GATE pin charging current, nominally 50µA.
Begin by choosing a value of acceptable inrush current for
the system, and then solve for C2.
C1 and R3 prevent Q1 from turning on momentarily when
power is first applied. Without them, C2 would pull the gate
of Q1 up to a voltage roughly equal to VEE*C2/Cgs(Q1)
(where Cgs is the FET gate-source capacitance) before the
ISL6141/2 could power up and actively pull the gate low.
Place C1 in parallel with the gate capacitance of Q1; isolate
them from C2 by R3.
C1= [(Vinmax - Vth)/Vth] * (C2+Cgd) - where Vth is the
FET’s minimum gate threshold, Vinmax is the maximum
operating input voltage, and Cgd is the FET gate-drain
capacitance.
R3 - its value is not critical, a typical value of 18kΩ is
recommended but values down to 1KΩ can be used. Lower
values of R3 will add delay to the gate turn-on for hot
insertion and the single retry event following a hard fault.
Note that although this IC was designed for -48V systems, it
can also be used as a low-side switch for positive 48V
systems; the operation and components are usually similar.
One possible difference is the kind of level shifting that may
be needed to interface logic signals to the UV input (to reset
the latch) or PWRGD output. For example, many of the IC
functions are referenced to the IC substrate, connected to
the VEE pin. But this pin may be considered -48V or GND,
depending upon the polarity of the system. And input or
output logic (r unning at 5V or 3.3V or even lower) might be
externally referenced to either VDD or VEE of the IC, instead
of GND.
IOC 50mv
Rsense
--------------------= (EQ. 3)
CORRECT
To SENSE
CURRENT
SENSE RESISTOR
INCORRECT
and V
EE
FIGURE 24. SENSE RESISTOR LAYOUT GUIDELINES
Iinrush IPU CL
C2
-------
×=(EQ. 4)
ISL6141, ISL6151
13
Inrush Current Control
The primary function of the ISL6141 hot plug controller is to
control the inrush current. When a board is plugged into a
live backplane, the input capacitors of the board’s po wer
supply circuit can produce large current transie nts as they
charge up. This can cause glitches on the system power
supply (which can affect other boards!), as well as possibly
cause some per m anent damage to the power supply.
The key to allowing boards to be inser ted into a live
backplane is to turn on the power to the board in a controlled
manner, usually by limiting the current allowed to flow
through a FET switch, until the input capacitors are fully
charged. At that point, the FET is fully on, for the smallest
voltage drop across it. Figure 25 below illustrates the typical
inrush current response resulting from a hot insertion for the
f ollowing conditions:
•V
EE = -48V, Rsense = 0.02Ω (2.5A current limit)
• C1 = 150nF, C2 = 3.3nF, R3 = 18kΩ
•I
Inrush = 50µA (100µF/3.3nF) = 1.5A
•C
L = 100uF, RL = 150Ω (48V/150Ω = 320mA)
After the contact bounce subsides the UVLO and UV criteria
are quickly met and the GATE begi ns to ramp up. As the
GATE reaches approximately 4V with respect to the source,
the FET begins to turn on allowing current to charge the load
capacitor. As the drain to source voltage begins to drop, the
feedback network of C2 and R3 hold the GATE constant, in
this case limiting the current to approximately 1.3A. When
the DRAIN voltage completes its ramp down the load current
remains constant at 320mA as the GATE voltage increases
to its final v alue .
Electronic Circuit Breaker/Current Limit
The ISL6141/51 f eatures prog rammable curre nt limiting with a
fix ed 600µs time-out period to protect against e xcessive
supply or f aul t currents . The IntelliTripTM electronic circuit
breaker is capa b le of detecting both hard faults , a nd less
severe Over-Current conditions.
The Ov er-Current trip point is determined by R1 (Eq . #3) also
ref erred to as Rsense . When the voltage across this resistor
e xceeds 50mV, the current limit regulator will turn on, and the
GATE will be pulled low er (to ~4V) to regulate curren t through
the FET at 50mV/Rsense. If the fault persists and current
limiting exceeds the 600µs time-out period, the FET will be
turned off by discharging the GATE pin to VEE. This will
enable the Over-Current latch and the PWRGD/PWRGD
output will transi tion to the in active state to indicate power is
no longer good. To clear the latch and initiate a normal power-
up sequence, the user m ust eith er power do w n the syste m
(below the UVLO voltage), or toggle the UV pin below and
abov e its threshold (usually with an e xternal transistor). Figure
26 below shows the Ov er-Curre nt shut down and current
limiting response f or a 10Ω short to ground on the output. With
a 10Ω short and a -48V supply, the initial fault current is
approximately 4.8A, producing a voltage drop across the
0.02Ω sense resistor o f 95mV, roughly two times the Ov er-
Current threshold of 50mV. This enables the 600 µs timer and
the GATE is quick ly pulled lo w to limit the cu rrent to 2.5A
(50mV/Rsense). The f ault condition persists f or the duration of
the time-out period and the GATE is latched off in about
670µs . There is a short filter (3µs n ominal) on the comparator,
so current transients shorter than this will be ignored. Longer
transients will initiate the GATE pull do wn, current limiting, and
the timer. If the fault current goes a wa y before the ti me -out
period expires the device will exit the current limiting mode
and resume normal operation.
FIGURE 25. INRUSH CURRENT LIMITING FOR A HO T
INSERTION
FIGURE 26. CURRENT LIMITING AND TIMEOUT
ISL6141, ISL6151
14
In addition to the above current limit and 600µs time -out,
there is a Hard Fault comparator to respond to short circuits
with an immediate GATE shutdown (typically 10µs) and a
single retry. The trip point of this comparator is set ~4 times
(210mV) higher than the Over-Current threshold of 50mV. If
the Hard F ault compar ator trip point is e xceeded, a hard pull
down current (350mA) is enabled to quickly pull down the
GATE and momentarily turn off the FET. The fast shutdown
resets the 600µs timer and is followed by a soft start, single
retry e v ent. If the f ault is still present after the GATE is slowly
tur ned on, the current-limit regulator will trip (sense pin
voltage > 50mV), turn on the timer, and limit the current to
50mV/Rsense for 600µs before latching the GATE pin low.
Note: Since the 600µs timer starts when the SENSE pin
e xceeds the 50mV threshold, then depending on the speed of
the current transient exceeding 200mV, it’s possible that the
current limit time-out an d shutdown can occur bef ore the H ard
F ault comparator trips (and thus no retry). Figure 27 illustrates
the Hard Fault response with a zero ohm short circuit at the
output.
As in the Over-Current response discussed previously the
supply is set at -48V and the current limit is set at 2.5A. After
the initial gate shutdown (10µs) a soft start is initiated with
the short circuit still present. As the GATE slowly turns on the
current ramps up and exceeds the Over-Current threshold
(50mV) enabling the timer and current limiting. The fault
remains for the duration of the time-out period and the GATE
pin is quickly pulled low and latched off requiring a UVLO or
UV reset to resume normal operation (assuming the fault
has gone away).
Applications: OV and UV
The UV and O V pins can be used to detect Over-Voltage and
Under-Voltage conditions on the input supply and quickly
shut down the external FET. Each pin is tied to an internal
comparator with a nominal reference of 1.255V. A resistor
divider between the VDD (gnd) and VEE is typically used to
set the trip points on the UV and OV pins . If the voltage on
the UV pin is above its threshold and the voltage on the OV
pin is below its threshold, the supply is within its operating
range and the GATE will be allow ed to turn on, or remain on.
If the UV pin voltage drops below its high to low threshold, or
the O V pin v oltage increases abov e its low to high threshold,
the GATE pin will be pulled low, turning off the FET until the
supply is back within tolerance.
The OV and UV inputs are high impedance, so the value of
the external resistor divider is not critical with respect to input
current. Therefore , the next consideration is total current; the
resistors will always draw current, equal to the supply
voltage divided by the total resistance of the divider
(R4+R5+R6) so the values should be chosen high enough to
get an acceptable current. However, to the extent that the
noise on the power supply can be transmitted to the pins, the
resistor values might be chosen to be lo wer . A filter capacitor
from UV to VEE or OV to VEE is a possibility, if certain
transients need to be filtered. (Note that even some
transients which will momentarily shut off the GATE might
recov er fast enough such that the GATE or the output current
does not even see the interruption).
Finally, take into account whether the resistor values are
readily available, or need to be custom ordered. Tol erances
of 1% are recommended f or accuracy. Note that for a typical
48V system (with a 43V to 72V range), the 43V or 72V is
being divided down to 1.255V, a significant scaling factor . F or
UV, the ratio is roughly 35 times; every 3mV change on the
UV pin represents roughly 0.1V change of power supply
vo ltage. Conv ersely, an error of 3mV (due to the resistors, for
example) results in an error of 0.1V for the supply trip point.
The OV ratio is around 60. So the accuracy of the resistors
comes into play.
The hysteresis of the comparators is also multiplied by the
scale factor of 35 for the UV pin (35 * 135mV = 4.7V of
hysteresis at the power supply) and 60 for the OV pin (60 *
25mV = 1.5V of hysteresis at the power supply).
With the three resistors, the UV equation is based on the
simple resistor divider:
1.255 = VUV * (R5 + R6)/(R4 + R5 + R6) or
VUV = 1.255 (R4 + R5 + R6)/(R5 + R6)
Similarly, f or OV :
1.255 = VOV * (R6)/(R4 + R5 + R6) or
VOV = 1.255 (R4 + R5 + R6)/(R6)
Note that there are tw o eq uations , but 3 unkn o wns . Beca use
of the scale f actor, R4 has to be much bigge r than the other
two; chose its v alue first, to set the current (for example , 50V /
500kΩ dr a ws 100µA), and then the other tw o will b e in the
10kΩ range. Solve the two equati ons for tw o unkn o wn s . Note
that some iteration may be necessary to select values that
FIGURE 27. HARD FAULT SHUTDOWN AND RETRY
ISL6141, ISL6151
15
meet the requirement, and are also rea dily a v ailable standard
v alues .
The three resistor divider (R4, R5, R6) is the recommended
approach for most cases. But if acceptable values can’t be
f ound, then consider 2 separate resistor dividers (one for
each pin, both from VDD to VEE). This also allows the user to
adjust or trim either trip point independentl y. Some
applications employ a short pin ground on the connector tied
to R4 to ensure the hot plug device is fully powered up
before the UV and OV pins (tied to the short pin ground) are
biased. This ensures proper control of the GATE is
maintained during power up . This is not a requirement for the
ISL6141/51 however the circuit will perform properly if a
short pin scheme is implemented (reference Figure 34).
Supply ramping
As pre viously mentioned the UV and OV pins can be used to
detect under and Over-Voltage cond itions on the input
supply. Figures 28 and 29 illustrate the GATE shutdown
response and the UV/OV hysteresis as a typical power
supply is ramped from 0 to 80V, and then from 80V to 0V.
As the supply ramps up, the UV threshold is reached at
43.6V and the FET begins to turn on. Within 40ms the GATE
is fully on and the device is operating normally. As the supply
continues to ramp up the Over-Voltage threshold is
exceeded at approximately 70.5V and the GATE is quickly
shut down as expected. In figure 29 the GATE voltage
begins in the off state as the supply voltage is above the OV
set point. As the supply voltage decreases the GATE turns
on at about 69V (roughly a 1.5 volt h ysteresis). Some 800ms
later (a characteristic of the supply used) the UV high to low
threshold is met at approximately 38.5 volts (about 5.0V of
hysteresis) and the GATE is shut off.
Applications: PWRGD/PWRGD
The PWRGD/PWRGD outputs are typically used to directly
enable a power module, such as a DC/DC conv erter. The
PWRGD (ISL6141) is used for modules with active low
enable (L version), and PWRGD (ISL6151) for those with
active high enable (H version). The modules usually have a
pull-up device b uilt-in, as well as an internal clamp. If not, an
external pull-up resistor may be needed. If the pin is not
used, it can be left open.
For both versions at initial start-up, when the DRAIN to VEE
voltage differential is less than 1.3V and the GATE voltage is
within 2.5V (VGH) of its normal operating voltage (13.6V),
power is considered good and the PWRGD/PWRGD pins
will go active. At this point the output is latched and the
DRAIN is no longer criticized. The latch is reset b y any of the
signals that shut off the GATE (Ov er-Voltage, Under-Voltage;
Under-Voltage-Lock-Out; Over-Current Time-Out or
powering down). In this case the PWRGD/PWRGD output
will go inactive, indicating power is no longer good.
ISL6141 (L version; Figure 30): Under normal conditions
(DRAIN voltage - VEE < VPG, and ∆VGATE - VGATE < VGH)
the Q2 DMOS will turn on, pulling PWRGD low, enabling the
module.
FIGURE 28. SUPPLY RAMP-UP
FIGURE 29. SUPPLY RAMP-DOWN
+
-VEE
VGH
PWRGD
DRAIN
VDD
+
VIN+
VIN-
ON/OFF
VOUT+
VOUT-
CL
Q2 ACTIVE LOW
ENABLE
MODULE
(SECTION OF) ISL6141
(L VERSION)
FIGURE 30. ACTIVE LOW ENABLE MODULE
+
-
VEE
GATE
∆VGATE
+
+
-
-
LOGIC
+
LATCH
VPG
ISL6141, ISL6151
16
When any of the 4 conditions occur that turn off the GATE
(OV, UV, UVLO, Over-Current Time-Out) the PWRGD latch
is reset and the Q2 DMOS device will shut off (high
impedance). The pin will quickly be pulled high by the
ex ternal module (or an optional pull-up resistor or equiv alent)
which in turn will disable it. If a pull-up resistor is used, it can
be connected to any supply voltage that doesn’t exceed the
IC pin maximum ratings on the high end, but is high enough
to give acceptable logic le v els to whate v er signal it is driving.
An external clamp may be used to limit the voltage range.
The PWRGD can also drive an opto-coupler (such as a
4N25), as shown in Figure 31 or LED (Figure 32). In both
cases, they are on (active) when power is good. Resistors
R12 or R13 are chosen, based on the supply voltage, and
the amount of current needed by the loads.
ISL6151 (H version; Figure 33): Under normal condition s
(DRAIN voltage - VEE < VPG, and ∆VGATE - VGATE < VGH),
the Q3 DMOS will be on, shorting the bottom of the inte rnal
resistor to VEE, and turning Q2 off . If the pull-up current from
the external module is high enough, the voltage drop across
the 6.2kΩ resistor will look like a logic high (relative to
DRAIN). Note that the module is only referenced to DRAIN,
not VEE (but under normal conditions, the FET is on, and the
DRAIN and VEE are almost the same voltage).
When any of the 4 conditions occur that tur n off the GATE,
the Q3 DMOS turns off, and the resistor and Q2 clamp the
PWRGD pin to one diode drop (~0.7V) above the DRAIN
pin. This should be able to pull low against the module pull-
up current, and disable the module.
Applications: GATE pin
To help protect the external FET, the output of the GATE pin
is internally clamped; up to an 80V supply and will not be any
higher than 15V. Under normal operation when the supply
voltage is abov e 20V, the GATE v oltage will be regulated to a
nominal 13.6V above VEE.
Applications: “Brick” Regulators
One of the typical loads used are DC/DC regulators, some
commonly known as “brick” regulators, (partly due to their
shape, and because it can be considered a “building block”
of a system). For a given input voltage range, there are
usually whole families of different output voltages and
current ranges. There are also various standardized sizes
and pinouts, starting with the original “full” brick, and since
getting smaller (half-bricks and quarter-bricks are now
common).
Other common f eatures may include: all components (e xcept
some filter capacitors) are self-contained in a molded plastic
package; external pins for connections; and often an
ENABLE input pin to turn it on or off. A hot plug IC, such as
the ISL6141 is often used to gate power to a brick, as well as
turn it on.
Many bricks ha ve both logic polarities av ailable (Enable Hi or
Lo input); select the ISL6141 (L version) and ISL6151 (H
version) to match. There is little difference between them,
although the L version output is usually simpler to interface.
The Enable input often has a pull-up resistor or current
source, or equivalent built in; care must be taken in the
ISL6151 (H version) output that the given current will create
a high enough input voltage (remember that current through
the RPG 6.2kΩ resistor generates the high voltage lev el; see
Figure 33).
The input capacitance of the brick is chosen to match its
system requirements, such as filtering noise, and
maintaining regulation under varying loads. Note that this
input capacitance appears as the load capacitance of the
ISL6141/51.
OPTO
PWRGD
FIGURE 31. ACTIVE LOW ENABLE OPTO-ISOLATOR
R12
+
-
VEE
VPG
VDD
Q2
(SECTION OF) ISL6141
(L VERSION)
+
-
VEE
GATE
∆VGATE PWRGD
DRAIN
+
-
+
-
LOGIC
+
LATCH
VGH
LED (GREEN
)
R13
FIGURE 32. ACTIVE LOW ENABLE WITH LED
+
-
VEE
VPG
VDD
Q2
(SECTION OF) ISL6141
(L VERSION)
+
-
VEE
GATE
∆VGATE PWRGD
DRAIN
+
+
-
-
LOGIC
+
LATCH
VGH
VEE
PWRGD
DRAIN
VDD
+
VIN+
VIN-
ON/OFF
VOUT+
VOUT-
CL
Q3
Q2
RPG
6.2K
ACTIVE HIGH
ENABLE
MODULE
(SECTION OF) ISL6151
(H VERSION)
FIGURE 33. ACTIVE HIGH ENABLE MODULE
+
-
VPG
+
-
VEE
GATE
∆VGATE
+
-
+
-
LOGIC
+
LATCH
VGH
ISL6141, ISL6151
17
The bric k’s output capacitance is also determined by the
system, including load regulation considerations. Howe v er , it
can affect the ISL6141/51, depending upon how it is
enabled. For example, if the PWRGD signal is not used to
enable the brick, the follo wing could occur . Sometime during
the inrush current time, as the main power supply starts
charging the brick input capacitors, the brick itself will start
working, and start charging its output capacitors and load;
that current has to be added to the inrush current. In some
cases, the sum could exceed the Over-Current shutdown,
which would shut down the whole system! Therefore,
whenever practical, it is advantageous to use the PWRGD
output to keep the brick off at least until the input caps are
charged up, and then start-up the brick to charge its output
caps.
Typical brick regulators include models such as Lucent
JW050A1-E or Vicor VI-J30-CY. These are nominal -48V
input, and 5V outputs, with some isolation between the input
and output.
Applications: Optional Components
In addition to the typical application, and the variations
already mentioned, there are a few other possible
components that might be used in specific cases. See Figure
34 for some possibilities.
If the input power supply exceeds the 100V absolute
maximum rating, ev en for a short transient, that could cause
per manent damage to the IC, as well as other components
on the board. If this cannot be guaranteed, a voltage
suppressor (such as the SMAT70A, D1) is recommended.
When placed from VDD to VEE on the board, it will clamp the
voltage.
If transients on the input power supply occur when the
supply is near either the OV or UV trip points, the GATE
could turn on or off momentarily. One possible solution is to
add a filter cap C4 to the VDD pin, through isolation resistor
R10. A large value of R10 is better for the filtering, but be
aware of the voltage drop across it. For example, a 1kΩ
resistor, with 2.4mA of IDD would have 2.4V across it and
dissipate 2.4mW. Since the UV and OV comparators are
referenced with respect to the VEE supply, they should not
be affected. But the GATE clamp voltage could be offset by
the voltage across the extra resistor.
The switch SW1 is shown as a simple push button. It can be
replaced by an active switch, such as an NPN or NFET; the
principle is the same; pull the UV node bel ow its trip point,
and then release it (toggle low). To connect an NFET, for
e xample, the DRAIN goes to UV ; the source to VEE, and the
GATE is the input; if it goes high (relative to VEE), it turns the
NFET on, and UV is pulled low. Just make sure the NFET
resistance is low compared to the resistor divider, so that it
has no problem pulling down against it.
R8 is a pull-up resistor for PWRGD, if there is no other
component acting as a pull-up device. The value of R8 is
determined by how much current is needed when th e pin is
pulled low ( al so affected by the VDD voltage); and it should
be pulled low enough for a good logic low level. An LED can
also be placed in series with R8, if desired. In that case, the
criteria is the LED brightness versus current.
ISL6141 (L)
V
DD
UV
OV V
EE
SENSE GATE DRAIN
PWRGD
R1 Q1
C1 R2
R3
C2
R4
D1*
SW1*
R8*
CL*
C4*
GND GND
-V IN -V OUT
R10*
R5
R6
GND
(SHORT PIN)
G
NFET*
(INSTEAD
OF SW1)
FIGURE 34. ISL6141/51 OPTIONAL COMPONENTS (SHOWN WITH *)
ISL6141, ISL6151ISL6141, ISL6151
18
Applications: Layout Considerations
For the minimum application, there are only 6 resistors, 2
capacitors, one IC and one FET. A sample lay out is shown in
Figure 35. It assumes the IC is 8-SOIC; the FET is in a
D2PAK (or similar SMD-220 package).
Although GND planes are common with multi-lev el PCBs, f or
a -48V system, the -48V rails (both input and output) act
more like a GND than the top 0V rail (mainly because the IC
signals are mostly referenced to the lower rail). So if
separate planes f or each voltage are not an option, consider
prioritizing the bottom rails first.
Note that with the placement shown, most of the signal lines
are short, and there should not be minimal interaction
between them.
Although decoupling capacitors across the IC supply pins
are often recommended in general, this application may not
need one, nor e v en tolerate one. F or one thing, a decoupling
cap would add to (or be swamped out by) any other input
capacitance; it also needs to be charged up when power is
applied. But more importantly, there are no high speed (or
any) input signals to the IC that need to be conditioned. If still
desired, consider the isolation resistor R10, as shown in
Figure 34.
NOTES:
1. Lay out scale is appro ximate; routing lines are just for illustration
purposes; they do not necessarily conform to normal PCB
design rules. High current buses are wider, shown with parallel
lines.
2. Approximate size of the above layout is 1.6 x 0.6 inches; almost
half of the area is just the FET (D2PAK or similar SMD-220
package).
3. R1 sense resistor is size 2512; all other R’s and C’s shown are
0805; they can all potentially use smaller footprints, if desired.
4. The RL and CL are not shown on the layout.
5. R4 uses a via to connect to GND on the bottom of the board; all
other routing can be on top level. (It’s even possible to eliminate
the via, for an all top-level route).
6. PWRGD signal is not used here.
BOM (Bill Of Materials)
R1 = 0.02Ω (5%)
R2 = 10Ω (5%)
R3 = 18kΩ (5%)
R4 = 549kΩ (1%)
R5 = 6.49kΩ (1%)
R6 = 10kΩ (1%)
C1 = 150nF (25V)
C2 = 3.3nF (100V)
Q1 = IRF530 (100V, 17A, 0.11Ω)
G 6
D 7
VDD 8
2 OV
3 UV
4 VEE
1 PG
S 5
U1
R1
R5
G
S
DRAIN
FET
R4
R3
C2
R2
R6
C1
-48V IN
GND GND
-48V OUT
ISL6141
VDD
UV
OV
VEE SENSE GATE DRAIN
PWRGD
R4
R5
R6
R1
R2 R3 C2
C1
Q1
CL
GND GND
-48V IN -48V OUT
RL
(LOAD)
FIGURE 35. ISL6141/51 SAMPLE LAYOUT (NOT TO SCALE)
ISL6141, ISL6151
19
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
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ISL6141, ISL6151
Small Outline Plastic Packages (SOIC)
INDEX
AREA E
D
N
123
-B-
0.25(0.010) C AMBS
e
-A-
L
B
M
-C-
A1
A
SEATING PLANE
0.10(0.004)
h x 45o
C
H
µ
0.25(0.010) BM M
α
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
M8.15 (JEDEC MS-012-AA ISSUE C)
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC
PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A0.0532 0.0688 1.35 1.75 -
A1 0.0040 0.0098 0.10 0.25 -
B0.013 0.020 0.33 0.51 9
C0.0075 0.0098 0.19 0.25 -
D0.1890 0.1968 4.80 5.00 3
E0.1497 0.1574 3.80 4.00 4
e 0.050 BSC 1.27 BSC -
H0.2284 0.2440 5.80 6.20 -
h0.0099 0.0196 0.25 0.50 5
L0.016 0.050 0.40 1.27 6
N8 87
α0o8o0o8o-
Rev. 0 12/93
ISL6141, ISL6151
