CAT5251YI-50TE13 - Catalyst Semiconductor, Inc.

DESCRIPTION

The CAT5251 is four Digitally Programmable

Potentiometers (DPPs™) integrated with control logic

and 16 bytes of NVRAM memory. Each DPP consists of

a series of resistive elements connected between two

externally accessible end points. The tap points between

each resistive element are connected to the wiper outputs

with CMOS switches. A separate 8-bit control register

(WCR) independently controls the wiper tap switches for

each DPP. Associated with each wiper control register

are four 8-bit non-volatile memory data registers (DR)

used for storing up to four wiper settings. Writing to the

wiper control register or any of the non-volatile data

CAT5251

Quad Digitally Programmable Potentiometer (DPP™) with

256 Taps and SPI Interface

FEATURES

■ Four linear-taper digitally programmable

potentiometers

■256 resistor taps per potentiometer

■End to end resistance 50kΩ or 100kΩ

■Potentiometer control and memory access via

SPI interface

■Low wiper resistance, typically 100ΩΩ

ΩΩ

Ω

■Nonvolatile memory storage for up to four wiper

settings for each potentiometer

■Automatic recall of saved wiper settings at

power up

■2.5 to 6.0 volt operation

■Standby current less than 1µA

■1,000,000 nonvolatile WRITE cycles

■100 year nonvolatile memory data retention

■24-lead SOIC and 24-lead TSSOP

■Industrial temperature range

PIN CONFIGURATION FUNCTIONAL DIAGRAM

Characteristics subject to change without notice Document No. 2017, Rev. D

registers is via a SPI serial bus. On power-up, the

contents of the first data register (DR0) for each of the

four potentiometers is automatically loaded into its

respective wiper control register.

The CAT5251 can be used as a potentiometer or as a

two terminal, variable resistor. It is intended for circuit

level or system level adjustments in a wide variety of

applications. It is available in the -40°C to 85°C industrial

operating temperature range and offered in a 24-lead

SOIC and TSSOP package.

CAT

5251

RW3

RH3

RL3

VCC

RL0

RH0

RW0

HOLD

SCK

RL2

RH2

RW2

GND

RW1

RH1

RL1

SOIC/TSSOP Package (J, W/U, Y)

H1 H2 H3

R RR

L0 L1 L2 L3

R RR

WIPER

CONTROL

REGISTERS

NONVOLATILE

DATA

REGISTERS

SPI BUS

INTERFACE

CONTROL

LOGIC

SCK

HOLD

CAT5251

Document No. 2017, Rev. D

being initiated. A low to high transition on CS after a valid write sequence is what initiates an internal write cycle.

WPWP

WP: Write Protect

WP is the Write Protect pin. The Write Protect pin will allow normal read/write operations when held high. When WP is tied low, all

non-volatile write operations to the Data registers are inhibited (change of wiper control register is allowed). WP going low while

CS is still low will interrupt a write to the registers. If the internal write cycle has already been initiated, WP going low will have no

effect on any write operation.

HOLDHOLD

HOLD: Hold

The HOLD pin is used to pause transmission to the CAT5251 while in the middle of a serial sequence without having to re-

transmit entire sequence at a later time. To pause, HOLD must be brought low while SCK is low. The SO pin is in a high imped-

ance state during the time the part is paused, and transitions on the SI pins will be ignored. To resume communication, HOLD is

brought high, while SCK is low. (HOLD should be held high any time this function is not being used.) HOLD may be tied high

directly to VCC or tied to VCC through a resistor.

PIN DESCRIPTION

(SOIC/TSSOP) Name Function

1 SO Serial Data Output

2 A0 Device Address, LSB

W3 Wiper Terminal for Potentiometer 3

H3 High Reference Terminal

for Potentiometer 3

L3 Low Reference Terminal

for Potentiometer 3

6 NC No Connect

7 VCC Supply Voltage

L0 Low Reference Terminal

for Potentiometer 0

H0 High Reference Terminal

for Potentiometer 0

10 RW0 Wiper Terminal for Potentiometer 0

11 CS Chip Select

12 WP Write Protection

13 SI Serial Input

14 A1 Device Address

15 RL1 Low Reference Terminal

for Potentiometer 1

16 RH1 High Reference Terminal

for Potentiometer 1

17 RW1 Wiper Terminal for Potentiometer 1

18 GND Ground

19 NC No Connect

20 RW2 Wiper Terminal for

Potentiometer 2

21 RH2 High Reference Terminal

for Potentiometer 2

22 RL2 Low Reference Terminal

for Potentiometer 2

23 SCK Bus Serial Clock

24 HOLD Hold

PIN DESCRIPTIONS

SI: Serial Input

SI is the serial data input pin. This pin is used to

input all opcodes, byte addresses and data to be

written to the CAT5251. Input data is latched on the

rising edge of the serial clock.

SO: Serial Output

SO is the serial data output pin. This pin is used to

transfer data out of the CAT5251. During a read

cycle, data is shifted out on the falling edge of the

serial clock.

SCK: Serial Clock

SCK is the serial clock pin. This pin is used to

synchronize the communication between the

microcontroller and the CAT5251. Opcodes, byte

addresses or data present on the SI pin are latched

on the rising edge of the SCK. Data on the SO pin is

updated on the falling edge of the SCK.

A0, A1: Device Address Inputs

These inputs set the device address when address-

ing multiple devices. A total of four devices can be

addressed on a single bus. A match in the slave

address must be made with the address input in

order to initiate communication with the CAT5251.

RH, RL: Resistor End Points

The four sets of RH and RL pins are equivalent to the

terminal connections on a mechanical potentiometer.

RW: Wiper

The four RW pins are equivalent to the wiper terminal

of a mechanical potentiometer.

CSCS

CS:Chip Select

CS is the Chip select pin. CS low enables the

CAT5251 and CS high disables the CAT5251. CS

high takes the SO output pin to high impedance and

forces the devices into a Standby mode (unless an

internal write operation is underway). The CAT5251

draws ZERO current in the Standby mode. A high to

low transition on CS is required prior to any sequence

CAT5251

Document No. 2017, Rev. D

DEVICE OPERATION

The CAT5251 is four resistor arrays integrated with an

SPI serial interface logic, four 8-bit wiper control registers

and sixteen 8-bit, non-volatile memory data registers.

Each resistor array contains 255 separate resistive

elements connected in series. The physical ends of

each array are equivalent to the fixed terminals of a

mechanical potentiometer (RH and RL). RH and RL are

symmetrical and may be interchanged. The tap positions

between and at the ends of the series resistors are

connected to the output wiper terminals (RW) by a

CMOS transistor switch. Only one tap point for each

potentiometer is connected to its wiper terminal at a time

and is determined by the value of the wiper control

registers or the non-volatile memory data registers via

the SPI bus. Additional instructions allow data to be

transferred between the wiper control registers and

each respective potentiometer's non-volatile data

registers. Also, the device can be instructed to operate

in an "increment/decrement" mode.

SERIAL BUS PROTOCOL

The CAT5251 supports the SPI bus data transmission

protocol. The synchronous Serial Peripheral Interface

(SPI) helps the CAT5251 to interface directly with many

of today's popular microcontrollers. The CAT5251

contains an 8-bit instruction register .The instruction set

and the operation codes are detailed in the instruction

set table 3 on page 9.

After the device is selected with CS going low the first

byte will be received. The part is accessed via the SI pin,

with data being clocked in on the rising edge of SCK. The

first byte contains one of the six op-codes that define the

operation to be performed.

CAT5251

Document No. 2017, Rev. D

Note:

(1) This parameter is tested initially and after a design or process change that affects the parameter.

(2) Absolute linearity is utilitzed to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a potentiometer.

(3) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a

potentiometer. It is a measure of the error in step size.

(4) LSB = RTOT / 255 or (RH - RL) / 255, single pot

(5) n = 0, 1, 2, ..., 255

ABSOLUTE MAXIMUM RATINGS*

Temperature Under Bias ..................-55°C to +125°C

Storage Temperature........................-65°C to +150°C

Voltage on any Pin with

Respect to VSS(1)(2) ................ -2.0V to +VCC +2.0V

VCC with Respect to Ground ................ -2.0V to +7.0V

Package Power Dissipation

Capability (TA = 25°C)................................... 1.0W

Lead Soldering Temperature (10 secs) ............ 300°C

Wiper Current.................................................... +6mA

Note:

(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC voltage on output

pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns.

(2) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to VCC +1V.

*COMMENT

Stresses above those listed under “Absolute Maximum Ratings” may cause permanent

damage to the device. These are stress ratings only, and functional operation of the

device at these or any other conditions outside of those listed in the operational sections

of this specification is not implied. Exposure to any absolute maximum rating for extended

periods may affect device performance and reliability.

Recommended Operating Conditions:

VCC = +2.5V to +6.0V

Temperature Min Max

Industrial -40°C85°C

POTENTIOMETER CHARACTERISTICS

Over recommended operating conditions unless otherwise stated.

Symbol Parameter Test Conditions Min Typ Max Units

RPOT Potentiometer Resistance (-00)100 kΩ

RPOT Potentiometer Resistance (-50)50 kΩ

Potentiometer Resistance +20 %

Tolerance

RPOT Matching 1 %

Power Rating 25°C, each pot 50 mW

IWWiper Current +3 mA

RWWiper Resistance IW = +3mA @ VCC =3V 200 300 Ω

RWWiper Resistance IW = +3mA @ VCC = 5V 100 150 Ω

VTERM Voltage on any RH or RL Pin VSS = 0V GND VCC V

VNNoise (1) nV/ Hz

Resolution 0.4 %

Absolute Linearity (2) Rw(n)(actual)-R(n)(expected)(5) +1 LSB (4)

Relative Linearity (3) Rw(n+1)-[Rw(n)+LSB](5) +0.5 LSB (4)

TCRPOT Temperature Coefficient of RPOT (1) +300 ppm/°C

TCRATIO Ratiometric Temp. Coefficient (1) 20 ppm/°C

CH/CL/CWPotentiometer Capacitances (1) 10/10/25 pF

fc Frequency Response RPOT = 50kΩ(1) 0.4 MHz

CAT5251

Document No. 2017, Rev. D

D.C. OPERATING CHARACTERISTICS

Over recommended operating conditions unless otherwise stated.

Symbol Parameter Test Conditions Min Typ Max Units

ICC1 Power Supply Current fSCK = 2.5 MHz, SO Open 1 mA

VCC = 6 V Inputs = GND

ICC2 Power Supply Current fsck = 2.5 MHz, SO = Open 5 mA

Non-volatile Write VCC = 6 V Inputs = GND

ISB Standby Current (VCC = 5.0V) VIN = GND or VCC; SO Open 1 µA

ILI Input Leakage Current VIN = GND to VCC 10 µA

ILO Output Leakage Current VOUT = GND to VCC 10 µA

VIL Input Low Voltage -1 VCC x 0.3 V

VIH Input High Voltage VCC x 0.7 VCC + 1.0 V

VOL1 Output Low Voltage (VCC = 3 V) IOL = 3 mA 0.4 V

VOH1 Output High Voltage (VCC = 6 V) IOH = -1.6mA VCC-0.8 V

PIN CAPACITANCE (1)

Applicable over recommended operating range from TA=25˚C, f=1.0 MHz, VCC=+5.0V (unless otherwise noted).

Symbol Test Conditions Min Typ Max Units Conditions

COUT Output Capacitance (SO) 8 pF VOUT=0V

CIN Input Capacitance (CS, SCK, SI, WP, HOLD,6pFV

IN=0V

A0, A1)

Note:

(1) This parameter is tested initially and after a design or process change that affects the parameter.

CAT5251

Document No. 2017, Rev. D

Test

SYMBOL PARAMETER Min Typ Max UNITS Conditions

tSU Data Setup Time 50 ns

tHData Hold Time 50 ns

tWH SCK High Time 125 ns

tWL SCK Low Time 125 ns

fSCK Clock Frequency DC 3 MHz

tLZ HOLD to Output Low Z 50 ns

tRI(1) Input Rise Time 2 µs

tFI(1) Input Fall Time 2 µs

tHD HOLD Setup Time 100 ns

tCD HOLD Hold Time 100 ns

tVOutput Valid from Clock Low 200 ns

tHO Output Hold Time 0 ns

tDIS Output Disable Time 250 ns

tHZ HOLD to Output High Z 100 ns

tCS CS High Time 250 ns

tCSS CS Setup Time 250 ns

tCSH CS Hold Time 250 ns

NOTE:

(1) This parameter is tested initially and after a design or process change that affects the parameter.

A.C. CHARACTERISTICS

Over recommended operating conditions unless otherwise stated.

CL = 50pF

POWER UP TIMING (1)(2)

Over recommended operating conditions unless otherwise stated.

Symbol Parameter Min Typ Max Units

tPUR Power-up to Read Operation 1 ms

tPUW Power-up to Write Operation 1 ms

NOTE:

(1) This parameter is tested initially and after a design or process change that affects the parameter.

(2) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.

XDCP TIMING

Symbol Parameter Min Max Units

tWRPO Wiper Response Time After Power Supply Stable 5 10 µs

tWRL Wiper Response Time After Instruction Issued 5 10 µs

CAT5251

Document No. 2017, Rev. D

WRITE CYCLE LIMITS

Over recommended operating conditions unless otherwise stated.

Symbol Parameter Min Typ Max Units

tWR Write Cycle Time 5 ms

Figure 1. Sychronous Data Timing

Figure 2. HOLDHOLD

HOLDHOLD

HOLD Timing

Note:

(1) This parameter is tested initially and after a design or process change that affects the parameter.

RELIABILITY CHARACTERISTICS

Over recommended operating conditions unless otherwise stated.

Symbol Parameter Reference Test Method Min Typ Max Units

NEND(1) Endurance MIL-STD-883, Test Method 1033 1,000,000 Cycles/Byte

TDR(1) Data Retention MIL-STD-883, Test Method 1008 100 Years

VZAP(1) ESD Susceptibility MIL-STD-883, Test Method 3015 2000 Volts

ILTH(1) Latch-Up JEDEC Standard 17 100 mA

SCK

HOLD

tCD

tHD

tCD

tLZ

tHZ

HIGH IMPEDANCE

Note: Dashed Line= mode (1, 1)

VALID IN

VIH

VIL

VIH

VIL

VIH

VIL

VOH

VOL

HI-Z

tSU tH

tWH tWL

tCS

tCSH

tHO tDIS

HI-Z

SCK

tRI

tFI

tCSS

CAT5251

Document No. 2017, Rev. D

INSTRUCTION AND REGISTER

DESCRIPTION

DEVICE TYPE / ADDRESS BYTE

The first byte sent to the CAT5251 from the master/

processor is called the Device Address Byte. The most

significant four bits of the Device Type address are a

device type identifier. These bits for the CAT5251 are

fixed at 0101[B] (refer to Table 1).

The two least significant bits in the slave address byte,

A1 - A0, are the internal slave address and must match

the physical device address which is defined by the state

of the A1 - A0 input pins for the CAT5251 to successfully

continue the command sequence. Only the device which

slave address matches the incoming device address

sent by the master executes the instruction. The A1 - A0

inputs can be actively driven by CMOS input signals or

tied to VCC or VSS. The remaining two bits in the device

address byte must be set to 0.

INSTRUCTION BYTE

The next byte sent to the CAT5251 contains the instruction

and register pointer information. The four most significant

bits used provide the instruction opcode I3-I0. The R1

and R0 bits point to one of the four data registers of each

associated potentiometer. The least two significant bits

point to one of four Wiper Control Registers. The format

is shown in Table 2.

Table 1. Identification Byte Format

ID3 ID2 ID1 ID0 0 0 A1 A0

0101

(MSB) (LSB)

Device Type

Identifier Slave Address

Table 2. Instruction Byte Format

I3 I2 I1 I0 R1 R0 P1 P0

(MSB) (LSB)

Instruction Data Register WCR/Pot Selection

Opcode Selection

Data Register Selected R1 R0

DR0 0 0

DR1 0 1

DR2 1 0

DR3 1 1

Data Register Selection

CAT5251

Document No. 2017, Rev. D

Table 3. Instruction Set

WIPER CONTROL AND DATA REGISTERS

Wiper Control Register (WCR)

The CAT5251 contains four 8-bit Wiper Control

Registers, one for each potentiometer. The Wiper

Control Register output is decoded to select one of

256 switches along its resistor array. The contents of

the WCR can be altered in four ways: it may be written

by the host via Write Wiper Control Register instruction;

it may be written by transferring the contents of one of

four associated Data Registers via the XFR Data

time by the Increment/decrement instruction (see

Instruction section for more details). Finally, it is

loaded with the content of its data register zero (DR0)

upon power-up.

The Wiper Control Register is a volatile register that

loses its contents when the CAT5251 is powered-down.

Although the register is automatically loaded with the

value in DR0 upon power-up, this may be different from

the value present at power-down.

Data Registers (DR)

Each potentiometer has four 8-bit non-volatile Data

Registers. These can be read or written directly by the

host. Data can also be transferred between any of the

four Data Registers and the associated Wiper Control

is a non-volatile operation and will take a maximum of

5ms.

If the application does not require storage of multiple

settings for the potentiometer; the Data Registers can be

used as standard memory locations for system

parameters or user preference data.

Write in Process

The contents of the Data Registers are saved to

nonvolatile memory when the CS input goes HIGH after

a write sequence is received. The status of the internal

write cycle can be monitored by issuing a Read Status

command to read the Write in Process (WIP) bit.

INSTRUCTIONS

Five of the ten instructions are three bytes in length.

These instructions are:

—Read Wiper Control Register - read the current

wiper position of the selected potentiometer in the WCR

—Write Wiper Control Register - change current

wiper position in the WCR of the selected potentiometer

—Read Data Register - read the contents of the

selected Data Register

Note: 1/0 = data is one or zero

Instruction

Instruction Set

Operation

I3 I2 I1 I0 R1 R0 WCR1/

Read Wiper Control

Write Wiper Control Register 101000 1/0 1/0Write new value to the Wiper Control

Read Data Register 10111/01/01/0 1/0Read the contents of the Data Register

pointed to by P1-P0 and R1-R0

Write Data Register 11001/01/01/0 1/0Write new value to the Data Register

pointed to by P1-P0 and R1-R0

XFR Data Register to Wiper

Control Register 11011/01/01/0 1/0Transfer the contents of the Data Register

pointed to by P1-P0 and R1-R0 to its

associated Wiper Control Register

XFR Wiper Control Register

to Data Register 11101/01/01/0 1/0Transfer the contents of the Wiper Control

Global XFR Data

Registers

to Wiper Control Registers 00011/01/0 0 0 Transfer the contents of the Data Registers

pointed to by R1-R0 of all four pots to their

respective Wiper Control Register

Global XFR Wiper Control

Registers to Data Register 10001/01/0 0 0 Transfer the contents of both Wiper Control

Registers to their respective data Registers

pointed to by R1-R0 of all four pots

Increment/Decrement Wiper

Control Register 001000 1/0 1/0Enable Increment/decrement of the Control

Latch pointed to by P1-P0

WCR0/

Read Status (WIP bit) 010100 0 1 Read WIP bit to check internal

write cycle status

CAT5251

Document No. 2017, Rev. D

—Write Data Register - write a new value to the

selected Data Register

—Read Status - Read the status of the WIP bit which

when set to "1" signifies a write cycle is in progress.

The basic sequence of the three byte instructions is

illustrated in Figure 8. These three-byte instructions

exchange data between the WCR and one of the Data

Registers. The WCR controls the position of the wiper.

The response of the wiper to this action will be delayed

by tWRL. A transfer from the WCR (current wiper position),

to a Data Register is a write to non-volatile memory and

takes a minimum of tWR to complete. The transfer can

occur between one of the four potentiometers and one

of its associated registers; or the transfer can occur

between all potentiometers and one associated register.

Four instructions require a two-byte sequence to

complete, as illustrated in Figure 7. These instructions

transfer data between the host/processor and the

CAT5251; either between the host and one of the data

registers or directly between the host and the Wiper

Control Register. These instructions are:

—XFR Data Register to Wiper Control Register

This transfers the contents of one specified Data

—XFR Wiper Control Register to Data Register

This transfers the contents of the specified Wiper

Control Register to the specified associated

Data Register.

—Global XFR Data Register to Wiper

Control Register

This transfers the contents of all specified Data

Registers to the associated Wiper Control

Registers.

—Global XFR Wiper Counter Register to

Data Register

This transfers the contents of all Wiper Control

Registers to the specified associated Data

Registers.

INCREMENT/DECREMENT COMMAND

The final command is Increment/Decrement (Figure 9

and 10). The Increment/Decrement command is differ-

ent from the other commands. Once the command is

issued the master can clock the selected wiper up and/

or down in one segment steps; thereby providing a fine

tuning capability to the host. For each SCK clock pulse

(tHIGH) while SI is HIGH, the selected wiper will move one

resistor segment towards the RH terminal. Similarly, for

each SCK clock pulse while SI is LOW, the selected

wiper will move one resistor segment towards the RL

terminal.

See Instructions format for more detail.

Figure 7. Two-Byte Instruction Sequence

Figure 8. Three-Byte Instruction Sequence

Figure 9. Increment/Decrement Instruction Sequence

0101

A2 A0 I2 I1 I0 R1 R0 P1

ID3 ID2 ID1 ID0 P0

Device ID Internal Instruction

Opcode

Address Register

Address Pot/WCR

Address

A3 I3

I3 I2 I1 I0 R1 R0

ID3 ID2

ID1

ID0

Device ID Internal Instruction

Opcode

Address Data

Address

Pot/WCR

Address WCR[7:0]

Data Register D[7:0]

010100

A2 A1 A0 P1 P0

D7 D6 D5 D4 D3 D2 D1 D0

I3 I2 I1 I0

ID3 ID2 ID1ID0

Device ID Internal Instruction

Opcode

Address Data

Address

Pot/WCR

Address

010100

A2 A1 A0 R0 P1 P0

CAT5251

Document No. 2017, Rev. D

Figure 10. Increment/Decrement Timing Limits

INSTRUCTION FORMAT

Read Wiper Control Register (WCR)

Write Wiper Control Register (WCR)

Read Data Register (DR)

Write Data Register (DR)

DEVICE ADDRESSES INSTRUCTION DATA

0 1 0 1 0 0 A A 1 0 0 1 0 0 P P 7 6 5 4 3 2 1 0

10 10

CS CS

DEVICE ADDRESSES INSTRUCTION DATA

0 1 0 1 0 0 A A 1 0 1 0 0 0 P P 7 6 5 4 3 2 1 0

10 10

CS CS

DEVICE ADDRESSES INSTRUCTION DATA

0 1 0 1 0 0 A A 1 1 0 0 R R P P 7 6 5 4 3 2 1 0

10 1010

CS CS

DEVICE ADDRESSES INSTRUCTION DATA

0 1 0 1 0 0 A A 1 0 1 1 R R P P 7 6 5 4 3 2 1 0

10 1010

CS CS High Voltage

Write Cycle

Read (WIP) Status

DEVICE ADDRESSES INSTRUCTION DATA

0 1 0 1 0 0 A A 0 1 0 1 0 0 0 1 7 6 5 4 3 2 1

1 0 0 0 0 0 0 0 0

CS CS

SCK

INC/DEC

Command

Issued

Voltage Out

WRL

CAT5251

Document No. 2017, Rev. D

DEVICE ADDRESSES INSTRUCTION DATA

0 1 0 1 0 0 A A 0 0 1 0 0 0 P P I/D I/D I/D I/D

1 0 1 0

CS CS

Global Transfer Wiper Control Register (WCR) to Data Register (DR)

INSTRUCTION FORMAT (continued)

Transfer Wiper Control Register (WCR) to Data Register (DR)

Transfer Data Register (DR) to Wiper Control Register (WCR)

Notes:

(1) Any write or transfer to the Non-volatile Data Registers is followed by a high voltage cycle after a STOP has been issued.

Global Transfer Data Register (DR) to Wiper Control Register (WCR)

Increment (I)/Decrement (D) Wiper Control Register (WCR)

DEVICE ADDRESSES INSTRUCTION

0 1 0 1 0 0 A A 0 0 0 1 R R 0 0

10 10

CS CS

DEVICE ADDRESSES INSTRUCTION

0 1 0 1 0 0 A A 1 0 0 0 R R 0 0

10 10

CS CS

DEVICE ADDRESSES INSTRUCTION

0 1 0 1 0 0 A A 1 1 1 0 R R P P

10 1010

CS CS

DEVICE ADDRESSES INSTRUCTION

0 1 0 1 0 0 A A 1 1 0 1 R R P P

10 1010

CS CS

• • •

High Voltage

Write Cycle

High Voltage

Write Cycle

CAT5251

Document No. 2017, Rev. D

Notes:

(1) The device used in the above example is a CAT5251JI-50-TE13 (SOIC, Industrial Temperature, 50kohm, Tape & Reel)

ORDERING INFORMATION

24-LEAD 300 MIL WIDE SOIC (J)

0.2914 (7.40)

0.2992 (7.60) 0.394 (10.00)

0.419 (10.65)

0.0926 (2.35)

0.1043 (2.65)

0.0040 (0.10)

0.0118 (0.30)

0.050 (1.27) BSC 0.013 (0.33)

0.020 (0.51)

0—8

0.0091 (0.23)

0.0125 (0.32)

0.010 (0.25)

0.029 (0.75) X 45

0.016 (0.40)

0.050 (1.27)

0.5985 (15.20)

0.6141 (15.60)

PACKAGING INFORMATION

Prefix Device # Suffix

5251 J

Product

Number

CAT

Optional

Company ID

I-TE13

Tape & Reel

TE13: 2000/Reel

-50

Resistance

-50: 50kohm

-00: 100kohm

Package

J: SOIC

U: TSSOP

W: SOIC (Lead free, Halogen free)

Y: TSSOP (Lead free, Halogen free)

All Dimensions in inches (mm).

CAT5251

Document No. 2017, Rev. D

PACKAGING INFORMATION CON'T

24 Lead TSSOP (U)

6.4

(0.9)

7.8 + 0.1

4.4 + 0.1

PIN #1 INDENT.

-A-

-B-

0.2 C B A

3.2

ALL LEAD TIPS

7.72 TYP

4.16 TYP

(1.78 TYP)

0.42 TYP

0.65 TYP

LAND PATTERN RECOMMENDATION

0.10 + 0.05 TYP

0.19 - 0.30 TYP

1.1 MAX TYP 0.1 C

ALL LEAD TIPS

-C-

0.65 TYP

0.3 M A B S C S

SEE DETAIL A

0.09 - 0.20 TYP

0.6+0.1 SEATING PLANE

GAGE PLANE

0.25

- 8

DETAIL A

All Dimensions in mm.

Catalyst Semiconductor, Inc.

Corporate Headquarters

1250 Borregas Avenue

Sunnyvale, CA 94089

Phone: 408.542.1000

Fax: 408.542.1200

www.catalyst-semiconductor.com

Publication #: 2017

Revison: D

Issue date: 5/6/04

Type: Advance

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DPP ™ AE2 ™

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issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000.

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typical semiconductor applications and may not be complete.

Date Rev. Reason

11/11/2003 C Eliminated BGA package in all areas

Eliminated Commercial temperature range

5/6/2004 D Updated Functional Diagram

Updated wiper resistance from 50Ω to 100Ω

Updated notes in Absolute Max Ratings

Eliminated Commercial temp range in all areas

Updated Potentiometer Characteristics table

Updated DC Characteristics table

Updated AC Characteristics table

Added XDCP Timing Table on page 6

Corrected Sychronous Data Timing (Figure 1) drawing

REVISION HISTORY