KM681002C/CL, KM681002CI/CLI CMOS SRAM
PRELIMINARY
Revision 2.0
- 1 - March 2000
PRELIMINARY
Document Title
128Kx8 Bit High-Speed CMOS Static RAM(5V Operating).
Operated at Commercial and Industrial Temperature Ranges.
Revision History
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
Rev. No.
Rev. 0.0
Rev. 1.0
Rev. 2.0
Remark
Preliminary
Final
Final
History
Initial release with Preliminary.
Release to Final Data Sheet.
1.1. Delete Preliminary.
2.2. Added Data Retention Characteristics.
Add 10ns part.
Draft Data
Aug. 5. 1998
Mar. 3. 1999
Mar. 3. 2000
KM681002C/CL, KM681002CI/CLI CMOS SRAM
PRELIMINARY
Revision 2.0
- 2 - March 2000
PRELIMINARY
128K x 8 Bit High-Speed CMOS Static RAM(5.0V Operating)
GENERAL DESCRIPTIONFEATURES
• Fast Access Time 10,12,15,20ns(Max.)
• Low Power Dissipation
Standby (TTL) : 30mA(Max.)
(CMOS) : 5mA(Max.)
0.5mA(Max.) L-ver. only
Operating KM681002C/CL-10 : 80mA(Max.)
KM681002C/CL-12 : 75mA(Max.)
KM681002C/CL-15 : 73mA(Max.)
KM681002C/CL-20 : 70mA(Max.)
• Single 5.0V±10% Power Supply
• TTL Compatible Inputs and Outputs
• I/O Compatible with 3.3V Device
• Fully Static Operation
- No Clock or Refresh required
• Three State Outputs
• 2V Minimum Data Retention; L-ver. only
• Center Power/Ground Pin Configuration
• Standard Pin Configuration
KM681002C/CLJ : 32-SOJ-400
KM681002C/CLT : 32-TSOP2-400CF
KM681002C/CL-10/12/15/20 Commercial Temp.
KM681002CI/CLI-10/12/15/20 Industrial Temp.
ORDERING INFORMATION
Clk Gen.
I/O1~I/O8
CS
WE
OE
FUNCTIONAL BLOCK DIAGRAM
Row Select
Data
Cont. Column Select
CLK
Gen.
Pre-Charge Circuit
Memory Array
512 Rows
256x8 Columns
I/O Circuit
PIN FUNCTION
Pin Name Pin Function
A0 - A16 Address Inputs
WE Write Enable
CS Chip Select
OE Output Enable
I/O1 ~ I/O8Data Inputs/Outputs
VCC Power(+5.0V)
VSS Ground
N.C No Connection
The KM681002C is a 1,048,576-bit high-speed Static Random
Access Memory organized as 131,072 words by 8 bits. The
KM681002C uses 8 common input and output lines and has an
output enable pin which operates faster than address access
time at read cycle. The device is fabricated using SAMSUNG′s
advanced CMOS process and designed for high-speed circuit
technology. It is particularly well suited for use in high-density
high-speed system applications. The KM681002C is packaged
in a 400mil 32-pin plastic SOJ or TSOP2 forward.
PIN CONFIGURATION(Top View)
SOJ/
TSOP2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A16
A15
A14
A13
OE
I/O8
I/O7
Vss
Vcc
I/O6
I/O5
A12
A11
A10
A9
A8
A0
A1
A2
A3
CS
I/O1
I/O2
Vcc
Vss
I/O3
I/O4
WE
A4
A5
A6
A7
A10 A11 A12 A13 A14 A15
A0
A1
A2
A3
A4
A5
A6
A7
A9A16
A8
KM681002C/CL, KM681002CI/CLI CMOS SRAM
PRELIMINARY
Revision 2.0
- 3 - March 2000
PRELIMINARY
ABSOLUTE MAXIMUM RATINGS*
* Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Parameter Symbol Rating Unit
Voltage on Any Pin Relative to VSS VIN, VOUT -0.5 to Vcc+0.5V V
Voltage on VCC Supply Relative to VSS VCC -0.5 to 7.0 V
Power Dissipation Pd1W
Storage Temperature TSTG -65 to 150 °C
Operating Temperature Commercial TA0 to 70 °C
Industrial TA-40 to 85 °C
RECOMMENDED DC OPERATING CONDITIONS*(TA=0 to 70°C)
* The above parameters are also guaranteed at industrial temperature range.
** VIL(Min) = -2.0V a.c(Pulse Width ≤ 8ns) for I ≤ 20mA.
*** VIH(Max) = VCC + 2.0V a.c (Pulse Width ≤ 8ns) for I ≤ 20mA.
Parameter Symbol Min Typ Max Unit
Supply Voltage VCC 4.5 5.0 5.5 V
Ground VSS 000V
Input High Voltage VIH 2.2 -VCC + 0.5*** V
Input Low Voltage VIL -0.5** -0.8 V
CAPACITANCE*(TA=25°C, f=1.0MHz)
* Capacitance is sampled and not 100% tested.
Item Symbol Test Conditions MIN Max Unit
Input/Output Capacitance CI/O VI/O=0V -8pF
Input Capacitance CIN VIN=0V -6pF
DC AND OPERATING CHARACTERISTICS*(TA=0 to 70°C, Vcc=5.0V±10%, unless otherwise specified)
* The above parameters are also guaranteed at industrial temperature range.
** VCC=5.0V±5%, Temp.=25°C.
Parameter Symbol Test Conditions Min Max Unit
Input Leakage Current ILI VIN = VSS to VCC -2 2µA
Output Leakage Current ILO CS=VIH or OE=VIH or WE=VIL
VOUT=VSS to VCC -2 2µA
Operating Current ICC Min. Cycle, 100% Duty
CS=VIL, VIN=VIH or VIL,
IOUT=0mA
10ns -80 mA
12ns -75
15ns -73
20ns -70
Standby Current ISB Min. Cycle, CS=VIH -30 mA
ISB1 f=0MHz, CS ≥VCC-0.2V,
VIN≥VCC-0.2V or VIN≤0.2V Normal -5mA
L-ver. -0.5
Output Low Voltage Level VOL IOL=8mA -0.4 V
Output High Voltage Level VOH IOH=-4mA 2.4 -V
VOH1** IOH1=-0.1mA -3.95 V
KM681002C/CL, KM681002CI/CLI CMOS SRAM
PRELIMINARY
Revision 2.0
- 4 - March 2000
PRELIMINARY
TEST CONDITIONS*
* The above test conditions are also applied at industrial temperature range.
Parameter Value
Input Pulse Levels 0V to 3V
Input Rise and Fall Times 3ns
Input and Output timing Reference Levels 1.5V
Output Loads See below
AC CHARACTERISTICS(TA=0 to 70°C, VCC=5.0V±10%, unless otherwise noted.)
READ CYCLE*
* The above parameters are also guaranteed at industrial temperature range.
Parameter Symbol KM681002C-10 KM681002C-12 KM681002C-15 KM681002C-20 Unit
Min Max Min Max Min Max Min Max
Read Cycle Time tRC 10 -12 -15 -20 -ns
Address Access Time tAA -10 -12 -15 -20 ns
Chip Select to Output tCO -10 -12 -15 -20 ns
Output Enable to Valid Output tOE -5-6-7-9ns
Chip Enable to Low-Z Output tLZ 3-3-3-3-ns
Output Enable to Low-Z Output tOLZ 0-0-0-0-ns
Chip Disable to High-Z Output tHZ 0 5 0 6 0 7 0 9 ns
Output Disable to High-Z Output tOHZ 0 5 0 6 0 7 0 9 ns
Output Hold from Address tOH 3-3-3-3-ns
Chip Selection to Power Up Time tPU 0-0-0-0-ns
Chip Selection to Power Down- tPD -10 -12 -15 -20 ns
Output Loads(B)
DOUT
5pF*
480Ω
255Ω
for tHZ, tLZ, tWHZ, tOW, tOLZ & tOHZ
+5.0V
* Including Scope and Jig Capacitance
Output Loads(A)
DOUT RL = 50Ω
ZO = 50Ω
VL = 1.5V
30pF*
* Capacitive Load consists of all components of the
test environment.
KM681002C/CL, KM681002CI/CLI CMOS SRAM
PRELIMINARY
Revision 2.0
- 5 - March 2000
PRELIMINARY
WRITE CYCLE*
* The above parameters are also guaranteed at industrial temperature range.
Parameter Symbol KM681002C-10 KM681002C-12 KM681002C-15 KM681002C-20 Unit
Min Max Min Max Min Max Min Max
Write Cycle Time tWC 10 -12 -15 -20 -ns
Chip Select to End of Write tCW 7-8-9-10 -ns
Address Set-up Time tAS 0-0-0-0-ns
Address Valid to End of Write tAW 7-8-9-10 -ns
Write Pulse Width(OE High) tWP 7-8-9-10 -ns
Write Pulse Width(OE Low) tWP1 10 -12 -15 -20 -ns
Write Recovery Time tWR 0-0-0-0-ns
Write to Output High-Z tWHZ 05060709ns
Data to Write Time Overlap tDW 5-6-7-8-ns
Data Hold from Write Time tDH 0-0-0-0-ns
End Write to Output Low-Z tOW 3-3-3-3-ns
Address
Data Out Previous Valid Data Valid Data
TIMMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH)
tAA
tRC
tOH
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)
CS
Address
OE
Data out
tAA
tOLZ
tLZ(4,5)
tOH
tOHZ
tRC
tOE
tCO
tPU tPD
Valid Data
tHZ(3,4,5)
50%
50%
VCC
Current
ICC
ISB
KM681002C/CL, KM681002CI/CLI CMOS SRAM
PRELIMINARY
Revision 2.0
- 6 - March 2000
PRELIMINARY
NOTES(READ CYCLE)
1. WE is high for read cycle.
2. All read cycle timing is referenced from the last valid address to the first transition address.
3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to VOH or
VOL levels.
4. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to
device.
5. Transition is measured ±200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested.
6. Device is continuously selected with CS=VIL.
7. Address valid prior to coincident with CS transition low.
8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.
TIMING WAVEFORM OF WRITE CYCLE(1) (OE= Clock)
Address
CS
tWP(2)
tDW tDH
Valid Data
WE
Data in
Data out
tWC
tWR(5)
tAW
tCW(3)
High-Z(8)
High-Z
OE
tOHZ(6)
tAS(4)
TIMING WAVEFORM OF WRITE CYCLE(2) (OE=Low Fixed)
Address
CS
tWP1(2)
tDW tDH
tOW
tWHZ(6)
Valid Data
WE
Data in
Data out
tWC
tAS(4)
tWR(5)
tAW tCW(3)
(10) (9)
High-Z(8)
High-Z
KM681002C/CL, KM681002CI/CLI CMOS SRAM
PRELIMINARY
Revision 2.0
- 7 - March 2000
PRELIMINARY
NOTES(WRITE CYCLE)
1. All write cycle timing is referenced from the last valid address to the first transition address.
2. A write occurs during the overlap of a low CS and WE. A write begins at the latest transition CS going low and WE going low ;
A write ends at the earliest transition CS going high or WE going high. tWP is measured from the beginning of write to the end of
write.
3. tCW is measured from the later of CS going low to end of write.
4. tAS is measured from the address valid to the beginning of write.
5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high.
6. If OE, CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase
of the output must not be applied because bus contention can occur.
7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.
8. If CS goes low simultaneously with WE going or after WE going low, the outputs remain high impedance state.
9. Dout is the read data of the new address.
10. When CS is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be
applied.
TIMING WAVEFORM OF WRITE CYCLE(3) (CS = Controlled)
Address
CS
tAW
tDW tDH
Data Valid
WE
Data in
Data out High-Z High-Z(8)
tCW(3)
tWP(2)tAS(4)
tWC
tWR(5)
High-Z
High-Z
tLZ tWHZ(6)
FUNCTIONAL DESCRIPTION
* X means Don′t Care.
CS WE OE Mode I/O Pin Supply Current
HXX* Not Select High-Z ISB, ISB1
LH H Output Disable High-Z ICC
LHLRead DOUT ICC
L L XWrite DIN ICC
KM681002C/CL, KM681002CI/CLI CMOS SRAM
PRELIMINARY
Revision 2.0
- 8 - March 2000
PRELIMINARY
DATA RETENTION CHARACTERISTICS*(TA=0 to 70°C)
* The above parameters are also guaranteed at industrial temperature range.
Data Retention Characteristic is for L-ver only.
Parameter Symbol Test Condition Min. Typ. Max. Unit
VCC for Data Retention VDR CS≥VCC-0.2V 2.0 -5.5 V
Data Retention Current IDR VCC=3.0V, CS≥VCC-0.2V
VIN≥VCC-0.2V or VIN≤0.2V - - 0.4 mA
VCC=2.0V, CS≥VCC-0.2V
VIN≥VCC-0.2V or VIN≤0.2V - - 0.3
Data Retention Set-Up Time tSDR See Data Retention
Wave form(below) 0- - ns
Recovery Time tRDR 5- - ms
DATA RETENTION WAVE FORM
CS controlled
VCC
4.5V
VIH
VDR
CS
GND
Data Retention Mode
CS≥VCC - 0.2V
tSDR tRDR
KM681002C/CL, KM681002CI/CLI CMOS SRAM
PRELIMINARY
Revision 2.0
- 9 - March 2000
PRELIMINARY
#1
32-SOJ-400
#32
20.95 ±0.12
0.825 ±0.005
10.16
0.400
+0.10
MAX
21.36
0.841
0.20 -0.05
+0.004
0.008 -0.002
9.40 ±0.25
0.370 ±0.010
MAX
0.148
3.76
MIN
0.69
0.027
1.30
( )
0.051
1.30
( )
0.051
0.95
( )
0.0375
+0.10
0.43 -0.05
+0.004
0.017 -0.002
+0.10
0.71 -0.05
+0.004
0.028 -0.002
1.27
0.050
#16
#17
0.004
0.10 MAX
11.18 ±0.12
0.440 ±0.005
PACKAGE DIMENSIONS Units:millimeters/Inches
32-TSOP2-400CF
#32
20.95 ±0.10
0.825 ±0.004
MAX
21.35
0.841
MAX
1.00 ±0.10
0.039 ±0.004 1.20
0.047
MIN
0.002
0.05
0.004 MAX
0.10 MAX
#1
0.95
( )
0.037
10.16
0.400
+0.10
0.15 -0.05
+0.004
0.006 -0.002
11.76 ±0.20
0.463 ±0.008
#17
#16
0.50
( )
0.020
0.45 ~0.75
0.018 ~ 0.030
0.25
( )
0.010
1.27
0.050
0.40 ±0.10
0.016 ±0.004
0~8°
