COP404LSN-5 National | Semiconductor COP404LSN-5 ROMless N-Channel Microcontrollers General Description The COP404LSN-5 ROMiess Microcontroller is a member of the COPS family, fabricated using N-channel, silicon gate MOS technology. The COP404LSN-5 contains CPU, RAM, I/O and is identical to a COP444L device except the ROM has Deen removed and pins have been added to out- put the ROM address and to input the ROM data. In a sys- tem the COP404LSNN-5 will perform exactly as the COP444L. This important benefit facilitates development and debug of a COP program prior to masking the final part. The COP404LSN-5 is also appropriate in low volume appli- cations, or when the program might be changing. The COP404LSN-5 may be used to emulate the COP444L, COP445L, COP420L, and the COP421L. Use COP404LSN-5 in volume applications. For extended temperature range (40C to +85C), COPSO4L is avail- able on a special order basis. Features m Exact circuit equivalent of COP444L mg Low cost @ Powerful instruction set m 128 x 4 RAM, addresses 2048 x 8 ROM @ True vectored interrupt, plus restart @ Three-level subroutine stack @ 16 ys instruction time @ Single supply operation (4.5V-5.5V) @ Low current drain (16 mA max) @ Internal time-base counter for real-time processing @ Internal binary counter register with MICROWIRET compatible serial 1/O @ General purpose outputs m LSTTL/CMOS compatible in and out @ Direct drive of LED digit and segment lines m Software/hardware compatible with other members of COP400 family Block Diagram Ay DATA IPs Py IP, IPs IP, Ps iP; iP; Pa Pa SKIP/P yy 2 cxo IW IN2 1M) INg GIVIGER q REGISTER 14 cK 2 CLOCK GENERATOR D3 02 Sg SK 50 micacme 5/0 81 $103 $102 HO, 0g SERIAL 0 REGISTER g REGISTER BUFFER 4 (7 tp by kg Ly by by lg TL/DD/8817-1 FIGURE 1 1-302Absolute Maximum Ratings if Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Total Source Current 120 mA Total Sink Current 140 mA Note: Adso/ute maximum ratings indicate limits beyond which damage to the device may occur. DC and AC electri- cal specifications are not ensured when operating the de- vice at absolute maximum ratings. Voltage at Any Pin Relative to GND 0.5V to + 10V Ambient Operating Temperature OC to +70C Ambient Storage. Temperatura 65C to + 150C Lead Temperature (Soldering, 10 sec.) 300C Power Dissipation 0.75W at 25C 0.4W at 70C DC Electrical Characteristics 4.5V < Voc < 5.5V;0C < Ta < 70C Parameter Conditions Min Max Units Operating Voltage (Voc) (Note 2) 45 5.5 v Power Supply Ripple Peak to Peak 0.5 v Operating Supply Current All Inputs and Outputs Open 16 mA Input Voltage Levels CKI Input Levels Crystal Input Logic High (Vj) 2.0 v Logic Low (Vil) -0.3 0.4 Vv RESET input Levels Schmitt Trigger Input Logic High 0.7 Voc Vv Logic Low 0.3 0.6 Vv IPO-IP7, SI Input Levels Logic High Voc = 5.5V 2.4 Vv Logic High Voc = 5 +5% 2.0 v Logic Low 0.3 0.8 Vv All Other Inputs Logic High High Trip Levet Options 3.6 Vv Logic Low Selected 0.3 1.2 Vv Input Capacitance 7 pF Output Voltage Levels . LSTTL Operation Voc = 5V 10% Logic High (Von) lon = 25 pA 2.7 Vv Logic Low (Vo) loL = 0.36 mA 0.4 Vv IPO-IP7, P8, P9, SKIP/P10 (Note 1) Logic High loH = 80 pA 2.4 Vv Logic Low lor = 720 pA 0.4 v Output Current Levels Output Sink Current SO and SK Outputs (Io1) Veco = 4.5V, Vo. = 0.4V 0.9 mA LgL7 Outputs Voc = 4.5V, VoL = 0.4V 0.4 mA Go-Gg3 and Dg-D3 Outputs Voc = 4.5V, Voy = 1.0V 75 mA CKO Voc = 4.5V, Vo_ = 0.4V 0.2 mA Output Source Current Do-D3, GoGg Outputs (lon) Voc = 4.5V, Vou = 2.0V 30 250 pA SO and SK Outputs (Ion) Voc = 4.5V, Vou = 1.0V -1.2 mA Lo-L7 Outputs Voc = 5.5V, Von = 2.0V 14 25 mA 1-303 S-NS 1P0%dODCOP404LSN-5 DC Electrical Characteristics (Continued OC < Ta < +70C, 4.5V < Voc < 5.5V unless otherwise noted Parameter Conditions Min Max Units Input Load Source Current (IL) Voc = 5.0V, Vi_ = OV 10 140 BA Total Sink Current Allowed All Outputs Combined 140 mA D, G Ports 120 mA L7-L4 4 mA Lg-Ly 4 mA All Other Pins 1.8 mA Tota! Sources Current Allowed All |O Combined - 120 mA L7-La 60 mA Lg-Lo 60 mA Each L Pin 30 mA All Other Pins 1.5 mA AC Electrical Characteristics oc < T, < 70C, 4.5V < Voc < 5.5V unless otherwise specified Parameter Conditions Min Max Units Instruction Cycle Time 16 40 BS CKI Input Frequency, f (+32 Mode) 0.8 2 MHz Duty Cycie 30 60 % Rise Time f, = 2.0 MHz 120 ns Fall Time 80 ns INPUTS: SI, IP7-IPO tseTuP 2.0 BS tHOLD 1.0 BS IN3-INo, G3g-Go, L7-Lo tseTup 8.0 ws tHoLD 1.3 BS OUTPUT PROPAGATION DELAY Test Condition: C_ = 50 pF, Vout = 1.5 SO, SK Outputs AL = 20 kn tpat, tedo 40 BS Dy-Dg, Gg-Gg, L7-Lo Ri = 20kn toa1) togo 5.6 ws IP7-IPO, P8, P9, SKIP RL = kn tod. tado 7.2 ps P10 RA, = 5ko tpd1, tpao 6.0 ps Note 1: COP404LSN-5 has Push-Pull drivers on these outputs. Note 2: Voc voltage change must be less than 0.5V in a 1 ms period to maintain proper operation. 1-304Connection Diagram Dual-In-Line Package cxo =| 1 40 === DO cKi 42 39 = Dt Ir] 3 38 == bz RESET =q 4 37 D3 P31 5 36 f IPS 1P2 16 35 Pe Ih 77 Mp Ps Po 8 33 AD/DATA pT 9 22 = SKIP/P10 ips 9 10 COPADALSN-5 31 G3 un 30 j G2 Lg my 12 28 G1 Ls oy 13 28 cp Lu 14 27 per IN int 4 15 26 p INO In2 7 16 26 == SK Veo sy 17 24 p= 50 Lj] 18 2 si 21 19 22 } GND li] 20 21/ Lo TL/DD/B817-2 Top View FIGURE 2 Order Number COP404LSN-5 See NS Package Number N40A Timing Diagram Pin Descriptions Pin Description L7-Lo 8 bidirecitonal I/O ports with TRI-STATE G3-Go D3-Do INg-INg Sl so SK AD/DATA CKI cKO RESET Voc GND IP7-IPO P86, P9 SKIP/P10 A ATANNANAARATAN AT AANATIUUANNANAANNAN. CYCLE TIME (tJ >| 4 bidirectional I/O ports 4 general purpose outputs 4 general purpose outputs Serial input (or counter input Serial output (or general purpose output) Logic-controlled clock (or general purpose out- put) Address out/data in flag System oscillator input System oscillator output (COP404LSN-5) System reset input Power supply Ground 8 bidirectional ROM address and data ports 2 ROM address outputs Instruction skip output and most significant ROM address bit output ck mits if oe (AS A CLOCK) |+tserur+} +}Woun Lu. 0,8 TU ln M...._ AM oa | tae + Kyat + tog er 2: a wr oe en = PPS-IP7, P8, PS OUTPUTS TL/DD/8817-3 FIGURE 3. Input/Output 1-305 S"NS 1P0%dODCOP404LSN-5 Functional! Description A block diagram of the COP404LSN-5 is given in Figure 7. Data paths are illustrated in simplitied form to depict how the various logic elements communicate with each other in implementing the instruction set of the device. Positive logic is used, When a bit is set, it is a logic 1 (greater than 2V). When a bit is reset, it is a logic 0 (less than 0.8V). PROGRAM MEMORY Program Memory consists of a 2048 byte external memory. As can be seen by an examination of the COP404LSN-5 instruction set, these words may be program instructions, program data or ROM addressing data. Because of the spe- cial characteristics associated with the JP, JSAP, JID and LAID instructions, ROM must often be thought of as being organized into 32 pages of 64 words each. ROM addressing is accomplished by an 11-bit PC register. Its binary value selects one of the 2048 8-bit words con- tained in ROM. A new address is loaded into the PC register during each instruction cycle. Unless the instruction is a transfer of control instruction, the PC register is loaded with the next sequential 11-bit binary count value. Three levels of subroutine nesting are implemented by the 11-bit subroutine saves registers, SA, SB, and SC, providing a last-in, first-out (LIFO) hardware subroutine stack. ROM instruction words are fetched, decoded and executed by the Instruction Decode, Control and Skip Logie circuitry. DATA MEMORY Data memory consists of a 512-bit RAM, organized as 8 data registers of 16 4-bit digits. RAM addressing is imple- mented by a 7-bit B register whose upper 3 bits (Br) select 1 of 8 data registers and lower 4 bits (Bd) select 1 of 16 4-bit digits in the selected data register. While the 4-bit contents of the selected RAM digit (M) is usually loaded into or from, or exchanged with, the A register (accumulator), it may also be loaded into or from the latches or loaded from the L ports. RAM addressing may also be performed directly by the LDD and XAD instructions based upon the 7-bit con- tents of the operand field of these instructions. The Bd reg- ister also serves as a source register for 4-bit data sent directly to the D outputs. INTERNAL LOGIC The 4-bit A register (accumulator) is the source and destina- tion register for most I/O, arithmetic, logic and data memory access operations. It can also be used to load the Br and Bd portions of the B registar, to load and input 4 bits of the 8-bit Q latch data, to input 4 bits of the 8-bit L 1/O port data and to perform data exchanges with the SIO register. A 4-bit adder performs the arithmetic and logic functions, storing its results in A. It also outputs a carry bit to the 1-bit CG register, most often employed to indicate arithmetic over- flow. The C register, in conjunction with the XAS instruction and the EN register, also serves to control the SK output. C can be outputted directly to SK or can enable SK to be a sync clock each instruction cycle time. (See XAS instruction and EN register description, below). Four general-purpose inputs, INgINo, are provided. The D register provides 4 general-purpose outputs and is used as the destination register for the 4-bit contents of Bd. The D outputs can be directly connected to the digits of a multiplexed LED display. The G register contents are outputs to 4 general-purpose bidirectional I/O ports. G I/O ports can be directly connect- ed to the digits of a multiplexed LED display. The register is an internal, latched, 8-bit register, used to hold data loaded to or from M and A, as well as 8-bit data from ROM. Its contents are output to the L I/O ports when the L drivers are enabled under program controi. (See LEI instruction.) The 8 L drivers, when enabled, output the contents of latched Q data to the L I/O ports. Also, the contents of L may be read directly into A and M. L I/O ports can be direct- ly connected to the segments of a multiplexed LED display (using the LED Direct Drive output configuration option) with Q data being outputted to the Sa-Sg and decimal point segments of the display. The SIO register functions as a 4-bit serial-in/serial-out shift register or as a binary counter depending on the contents of the EN register. (See EN register description, below.) Its contents can be exchanged with A, allowing it to input or output a continuous serial data stream. SIO may also be used to provide additional parallel |1/O by connacting SO to external serial-in/parallel-out shift registers. The XAS instruction copies C into the SKL latch. In the counter mode, SK is the output of SKL; in the shift register mode, SK outputs SKL ANDed with the clock. The EN register is an internal 4-bit register loaded under program control by the LEI instruction. The state of each bit of this register selects or deselscts the particular feature associated with each bit of the EN register (EN3-ENg). 1. The least significant bit of the enable register, ENp, se- lects the SiO register as either a 4-bit shift register or a 4- bit binary counter. With ENo set, SIO is an asynchronous binary counter, decrementing its value by one upon each low-going pulse (1" to 0) occurring on the SI input. Each pulse must be at least two instruction cycles wide. SK outputs the value of SKL. The SO output is equal to the value of EN3. With ENg reset, SIO is a serial shift register shifting left each instruction cycle time. The data present at SI goes into the least significant bit of SIO. SO can be enabled to output the most significant bit of SIO each cycle time. (See 4 below.) The SK output becomes a logic-controlled clock. 2. With EN, set the IN, input is enabled as an interrupt in- put. Immediately foliowing an interrupt, EN, is reset to disable further interrupts. 3. With ENp set, the L drivers are enabled to output the data in Q to the L I/O ports. Resetting ENe disables the L drivers, placing the L I/O ports in a high-impedance input state. 1-306Functional Description (Continued 4. ENg, in conjunction with ENp, affects the SO output. With ENg set (binary counter option selected) SO will output the value loaded into ENg. With ENp reset (serial shift register option selected), setting ENg enables SO as the output of the SIO shift register, outputting serial shifted data each instruction time. Resetting ENg with the serial shift register option selected disables SO as the shift reg- ister output; data continues to be shifted through SIO and can be exchanged with A via an XAS instruction but SO remains reset to 0. The table below provides a summa- ry of the modes associated with ENg and ENo. INTERRUPT The following features are associated with the IN, interrupt procedure and protocol and must be considered by the pro- grammer when utilizing interrupts. a. The interrupt, once acknowledged as explained below, pushes the next sequential program counter address (PC+1) ante the stack, pushing in turn the contents of the other subrautine-save registers to the next lower level (PC+1 SA SB SC). Any previous contents of SC are lost. The program counter is set to hex address OFF (the last word of page 3) and EN; is reset. b. An interrupt will be acknowledged only after the following conditions are met: 1. EN, has been set. 2. A low-going pulse (1 to 0) at least two instruction cycles wide occurs on the IN input. 3. A currently executing instruction has been completed. 4. Ali successive transfer of control instructions and suc- cessive LBls have bean completed (e.g., if the main program is executing a JP instruction which transfers program control to another JP instruction, the interrupt will not ba acknowledged until the second JP instruc- tion has been executed. c. Upon acknowledgement of an interrupt, the skip logic status is saved and later restored upon popping of the stack. For example, if an interrupt occurs during the exe- cution of ASC (Add with Carry, Skip on Carry) instruction which results in carry, the skip logic status is saved and program control is transferred to the interrupt servicing routine at hex address OFF. At the end of the interrupt routine, a RET instruction is executed to pop the stack and return program control to the instruction following the original ASC. Af this time, the skip logic is enabled and skips this instruction because of the previous ASC carry. Subroutines and LQID instructions should not be nested within the interrupt service routine, since their popping the stack will enable any previously saved main program skips, interfering with the orderly execution of the inter- rupt routine. d. The first instruction of the interrupt routine at hax address OFF must be a NOP. 6. A LEI instruction can be put immediately before the RET to re-enable interrupts. INITIALIZATION The Reset Logic will initialize (clear) the device upon power- up if the power supply rise time is less than 1 ms and great- er than 1 ps. If the power supply rise time is greater than 1 ms, the user must provide an external RC network and diode to the RESET pin as shown below. The RESET pin is configured as a Schmitt trigger input. If the RC network is not used, the RESET pin should be left open. Initialization will occur whenever a logic 0 is applied to the RESET input, provided it stays low for at least three instruction cycle times. <r 2vVCH BmSBOV ~~ << + = a m mi = < QQ o TL/DD/8817-4 RC = 5 < Power Supply Rise Time (R > 40k) Upon initialization, the PC register is cleared to 0 (ROM ad- dress 0) and the A, B, C, D, EN, and G registers are cleared. The SK output is enabled as a SYNC output, providing a pulse each instruction cycle time. Data Memory (RAM) is not cleared upon initialization. The first instruction at ad- dress 0 must be a CLRA. EXTERNAL MEMORY INTERFACE The COP404LSN-5 is designed for use with an external Pro- gram Memory. This memory may be implemented using any devices having the following characteristics: 1. random addressing 2. TTL-compatible TRI-STATE outputs 3. TTL-compatible inputs 4. access time = 5 ws max. Typically these requirements are met using bipolar or MOS PROMs. During operation, the address of the next instruction is sent out on P10, P9, PB, and IP7 through IPO during the time that AD/DATA is high (logic 1 = address mode). Address data on the IP lines is stored into an external latch on the high-to-ow transition of the AD/DATA line; P9 and P8 are Enable Register Modes Bits ENg and ENo EN; ENo SIO so SK 0 0 Shift Register Input to Shift Register 0 lf SKL = 1,SK = CLOCK lf SKL = 0,SK = 0 1 0 Shift Register Input to Shift Register Serial Out lf SKL = 1, SK = CLOCK lf SKL = 0, SK = 0 0 1 Binary Counter Input to Binary Counter 0 lf SKL = 1,SK = 1 if SKL = 0,SK = 0 1 1 Binary Counter Input to Binary Counter 1 if SKL = 1,SK = 1 If SKL = 0,SK = 0 S-NS 1P07dODCOP404LSN-5 Functional Description (continued) dedicated address outputs, and do not need to be latched. SKIP/P10 outputs address data when AD/DATA is low. When AD/DATA is low {logic 0 = data mode), the output of the memory is gated onto IP7 through iPO, forming the input bus. Note that the AD/DATA output has a period of one instruction time, a duty cycle of approximately 50%, and specifies whether the IP lines are used for address out- put or instruction input. OSCILLATOR The basic clock oscillator configurations is shown in Figure 4 Crystal Controlled OsclilatorCKI and CKO are connect- ed to an external crystal. The instruction cycle time equals the crystal frequency divided by 32. COPAGALS CKI cxo AAA vvy 1 < 2.007MHz 4 ued UY x = t 56 pF TL/OD/8817-5 FIGURE 4. Oscillator tNPUT/OUTPUT CONFIGURATIONS COP404LSN-5 outputs have the following configurations, il- lustrated in Figure 5: a. Standardan enhancement mode device to ground in conjunction with a depletion-mode device to Vcc, com- patible with LSTTL and CMOS input requirements. (Used on D and G outputs.) TL/DD/8817-8 a. Standard Output DISABLE TL/DD/6817~8 d. L Output (LED) mg b. Open-Drain Output b. Open-Drainan enhancement-mode device to ground only, allowing external pull-up as required by the user's application. c. Push-Pullan enhancement-mode device to ground in conjunction with a depletion-mode device paralleled by an enhancement-mode device to Voc. This configuration has been provided to allow for fast rise and fall times when driving capacitive loads. d. LED Direct Drivean enhancement-mode device to ground and to Voc, meeting the typical current sourcing requirements of the segments of an LED display. The sourcing device is clamped to limit current fiow. These devices may be turned off under program control (see Functional Description, EN Register), placing the outputs in a high-impedance state to provide required LED seg- ment blanking for a multiplexed display. (Used on L out- puts.) COP404LSN-5 inputs have an on-chip depletion load device to Voc. The above input and output configurations share common enhancement-mode and depletion-mode devices. Specifi- cally, all configurations use one or more of six devices (numbered 1-6, respectively). Minimum and maximum cur- rent (lour and Vout) curves are given in Figure 6 for each of these devices to allow the designer to effectively use these 1/O configurations in designing a system. An important point to remember is that even when the L drivers are disabled, the depletion load device will source a smalt amount of current (see Figure 6, device 2); however, when the L-lines are used as inputs, the disabled depletion device can not be relied on to source sufficient current to pull an input to a logic 1. TL/DD/8817-7 TL/OD/e817-8 c. Push-Pull Output Vec #6 a INPUT: [ TL/DD/8817-10 e. Input with Load (4 is Depletion Device) FIGURE 5. Output ContigurationsTypical Performance Characteristics Input Current for Lg through Current for inputs with L7 when Output Programmed Load Device 100 Otf by Software DEVICES #8 =#0 4 150 ~~ 3 70 = a 60 3 10 ~ & 50 * NL a evel=eav 5-0 0 =30 ~20 hye @ Voc4.5 10 0 O 10 20 3D 40 50 60 70 80 9D *5 10 20 Vg (VOLTS) 1/0 (VOLTS) Source Current for SO and SK L Output Source Current 15 =40 Tala #2 AND 44 =30 10 z hakx @ eg=4.5 ? 20 huax @ Yoo=5.5 3 = 0s \ L ha og24.5 =10 ee 0 0 0123456788 1 0123456789 10 You (VOLTS) You (VOLTS) LED Output Drive Segment Output Sink Current for SO Drive and SK - DEVICE d DEVICE a #t #2 AND #4 /| B#t AND oh 3 4 | Peeve 8 z 2 UY 5 3 han OVog=4.5 1 0 o 1 2 3 4 5 Voy (VOLTS) Output Sink Current Go-G3 Source Current for Standard Output Configuration low id) geesees 3s =100 0125 45 67 8 $ You (VOLTS) LED Output Direct Segment and Digit Drive DEVICE d g2 AND #4 | AND DEVICE ft I 4 hax ONE SEGMENTS senter> <0 toy (nA) ~20 1 bao 10 | Tax ecu TS ON coer ry Vog (VOLTS) Output Sink Current for Ly through L7 I | DEVICE aponen, | onl.te OR g#t | iar Voge. S | Sf han @ Vop=4.5V Igy (rma) 0 1 2 3 4 5 Voy (VOLTS) Output Sink Current iPO-IP7, top BN Do-Ds 3p PB: PS, SKIP/P10, AD/DATA agi AND bat hyax @ 100 Vo 4.S m0 mt z 60 1a 3 5 an @ Vocus BV 2 0 on 012345678 %10 on 05 10 Vo. (WOLTS) Voyr (VOLTS) TL/DD/9817-11 FIGURE 6, COP404LSN-5 |/O Characteristics 1-309 S-NS1P0FdODCOP404LSN-5 COP404LSN-5 Instruction Set Tabie | is a symbol table providing internal architecture, in- struction operand and operational symbols used in the in- Table Il provides the mnemonic, operand, machine code, data flow, skip conditions, and description associated with struction set table. each instruction in the COP404LSN-5 instruction set. TABLE |. COP404LSN-5 instruction Set Table Symbols Symbol Definition Symbol Betinition INTERNAL ARCHITECTURE SYMBOLS INSTRUCTION OPERAND SYMBOLS A 4-bit Accumulator d 4-bit Operand Field, 0-15 binary (RAM Digit Select) B 10-bit RAM Address Register r 3-bit Operand Field, 0-7 binary (RAM Register Br Upper 3 bits of B (register address) Select) Bd Lower 4 bits of B (digit address) a 11-bit Operand Field, O-2047 binary (ROM Address) Cc 1-bit Carry Register y 4-bit Operand Fiald, 0-15 binary (Immediate Data) D 4-bit Data Output Port RAM(s) Contents of RAM tocation addressed by s EN 4-bit Enable Register ROM(t) Contents of ROM location addressed by t G 4-bit Register to latch data for G I/O Port IL ine mM -bit latches associated with the INg or INg OPERATIONAL SYMBOLS IN 4-bit Input Port + Plus IP 8-bit bidirectional ROM address and Data Port - Minus L 8-bit TR!I-STATE I/O Port Replaces M 4-bit contents of RAM Memory pointed to by B +> _ Is exchanged with Register = Is equal to P 3-bit ROM Address Register Port A The ones complement of A PC 11-bit ROM Address Register (program counter) Exclusive-OR Q 8-bit Register to latch data for L I/O Port : Range of values SA 11-bit Subroutine Save Register A 58 11-bit Subroutine Save Register B sc 11-bit Subroutine Save Register C slo 4-bit Shift Register and Counter SK Logic-Controlled Clock Output TABLE Il. COP404L5N-5 Instruction Set Hex Machine Mnemonic Operand Language Code Data Flow Skip Conditions Description Code (Binary) ARITHMETIC INSTRUCTIONS ASC 30 0011 | 0000 | A+C-+ RAM(B) A Carry Add with Carry, Skip on Carry > C Carry ADD 31 [0011 |0001 A + RAM(B) A None Add RAM to A ADT 4A 0100/1010 A+ 1019 > A None Add Ten to A AISC y 5- 0101| y Aty-A Carry Add Immediate, Skip on Carry (y # 0) CASC 10 0001 | 0000 A+ RAM(B)+C A Cary Complement and Add with Carry > Carry, Skip on Carry CLRA 00 {0000 | 0000 Oo-A None Clear A COMP 40 0100 | 0000 AA None Ones complement of A to A NOP 44 0100 | 0100 None None No Operation Rc 32 0011 |0010 "Oo" C None Reset C sc 22 0010 |0010 "1" + C None Set C XOR 02 0000 | 0010 A RAM(B) A None Exclusive-OR RAM with A 1-310TABLE ll. COP404LSN-5 Instruction Set (Continued) Hex Machine Mnemonic Operand Cod Language Code Data Flow Skip Conditions Description le (Binary) TRANSFER OF CONTROL INSTRUCTIONS JID FF 1111]1111 ROM (PC19-3, A.M) > None dump Indirect (Note 2) PC7-9 JMP a 6- [0110] 0 jaio8|} a > PC None Jump -< 47:0 JP a -- 1 ago | | a PCEo None Jump within Page (pages 2,3 only) (Note 4) or -- 11 a P&s.o (all other pages) JSAP a -- 10| as. PC +1 SA SB None Jump to Subroutine Page sc (Note 5) 00010 > PCio a > PC5.9 JSR a 6- [0110] 1 |ajo.3}}PC +1 SA SB None Jump to Subroutine -- Lazo =| | > SC a PC RET 46 0100/1000; | SC SB SA PC None Return from Subroutine RETSK 49 0100/1001; | SC SB SA PC Always Skip on Return Return from Subroutine then Skip MEMORY REFERENCE INSTRUCTIONS CAMQ 33 0011 |0011 A> O74 None Copy A, RAM ta O 3C 0011/1100 RAM(B) Q5:9 CQMA 33 0011/0011 Q7.4 > RAM(B) None Copy Q to RAM, A 2C 0010/1100 Q3.9 > A LD r -5 [00 | r|0101 RAM(B) A None Load RAM into A, (r = 0:3} Br@r Br Exclusive-OR Br with r LDD rd 23 0010/0011 RAM(r,d) > A None Load A with RAM pointed -- Oj rid to directly by rd LQID BF 1011/1111] | ROM(PC1o:3,A,M) -> Q None Load Q Indirect (Note 3) SB SC RMB 0 4c 0100] 1100 0 RAM(B)p None Reset RAM Bit 1 45 0100/0101 0 RAM(8), 2 42 0100/0010 0 RAM(B)2 3 43 0100/0011 0 RAM(B)3 SMB 0 4D 0100/1101 1 RAM(B)p None Set RAM Bit 1 47 0100/0111 1 RAM(B), 2 46 0100/0140 1 RAM(B)o 3 4B 0100 | 1011 1 > RAM(B)3 STil y 7- 0111| y y RAM(B) None Store Memory Immediate Bd+1 Bd and Increment Bd x t -6 00|r|0110 RAM(B) <> A None Exchange RAM with A, (r = 9:3) Br@r-> Br Exclusive-OR Br with r XAD rd 23 0010|0011 RAM(r,d) <> A None Exchange A with RAM -- 1jr|d pointed to directly by (r,d) XDS. r -7 00(r(/0111 RAM(B) <> A Bd decrements pastO Exchange RAM with A (r = 0:3) Bad 1 Bd and Decrement Bd, Br@r Br Exclusive-OR Br withr 1-344 S"NS 1h0%dO9DCOP404LSN-5 TABLE Il. COP404LSN-5 Instruction Set (Continued) Hex Machine Mnemonic Operand Code Language Code Data Flow Skip Conditions Description (Binary) MEMORY REFERENCE INSTRUCTIONS (Continued) xis r -4 00 |r| Ot00) RAM(B) <> A Bd increments past 15 Exchange RAM with A (r = 0:3) Bd+1 Bd and Increment Bd, Bre@r Br Exclusive-OR Br with r REGISTER REFERENCE INSTRUCTIONS CAB 50 0401 {0000 A Bd None Copy A to Bd CBA 4E 0100 | 1110 Bd > A None Copy BdtoA LBi rd -- 00jr|(d-1) rdsB Skip until not a LBI Load B Immediate with (r = 0:3; d = 0, 9:15) r,d (Note 6) or 33 0011 |0011| ~=< iri] df (any r, any d) LEI y 33 0011 |0011| y EN None Load EN Immediate 6- 0110| y (Note 7) XABR 12 | 0001 |0010] A <> Br(0 Ag) None Exchange A with Br TEST INSTRUCTIONS SKC 20 [0010 | 0000 c="1" Skip if C is True SKE 21 [0010 | 0001 A = RAM(B) Skip if A Equals RAM SKGZ 33 0011| 0011 G0 = 0 Skip if Gis Zero 21 0010/0001 (all 4 bits) SKGBZ 33 0011/0011 ist byte Skip if G Bit is Zero 0 01 0000 | 0001 Go = 0 1 11 0007 | 0001 2nd byte G;=0 2 03 0000| 001+ | Go =0 a 13 0001/0017 G3 =0 SKMBZ 0 01 [0000/0001 RAM(B)y = 0 Skip if RAM Bit is Zero 1 11 [0001 [0001 RAM(B); = 0 2 03 0000/0011 | RAM(B)2 = 0 3 13 0001 {0011 | RAM(B)3 = 0 SKT 41 0100 |0001 A time-base counter Skip on Timer (Note 2) carry has occurred . since last test INPUT/OUTPUT INSTRUCTIONS ING 33 0011/0011 Goa None Input G Ports to A 2A 0010/1010 ININ 33 0011 | 0011 IN>A None Input IN Inputs to A 28 0010 | 1000 INIL 33 0011/0011 | ILg, GKO, 0, ILg > A None Input IL Latches to A 29 0010/1001 | (Note 2) INL 33 0011/0011! Ly.4 > RAM(B) None Input L Ports to RAM, A 2E 0010/1110) Lg A OBD 33 0011/0011 Bd D None Output Bd to D Outputs 3E |00+1|1110) 1-312TABLE II. COP404LSN-5 Instruction Set (Continued) Hex Machine Mnemonic Operand Language Code Data Flow Skip Conditions Description Code (Binary) INPUT/OUTPUT INSTRUCTIONS (Continued) OGI y 33 [0011 | 0011 yoG None Output to G Ports Immediate 5- o0101/ y OMG 33 [0011 [0014 RAM(B) G None Output RAM to G Ports 3A 0011 | 1010 XAS 4F 01001111 A <> SIO,C -> SKL None Exchange A with SIO (Note 2) Note 1: All subscripte for alphabetical symbols indicate bit numbers unless explicitly defined (6.9., Br and Bd are explicitly defined). Bits are numbered 0 to N where O signifies the least significant bit (low-order, right-most bit). For example, Ag indicates the most significant (laft-most) bit of the 4-bit A register. Note 2: Fer additional information on the operation of the XAS, JID, LOQID, INIL, and SKT instructions, see below. Note 3: The JP instruction aliows a jump, while in subroutine pages 2 or 3, to any ROM location within the two-page boundary of pages 2 or 3. The JP instruction, otherwise, permits a jump to a ROM location within the current 64-word page. JP may not jump to the last word of a page. Note 4: A JSRP transfers program control to subroutine page 2 (0010 is loaded into the upper 4 bits of P}. A JSAP may not be used when in pages 2 or 3. JSRP may not jump to the last word in page 2. Note 6: LB! is a single-byte instruction if d = 0, 9, 10, 11, 12, 13, 14, or 15. Tha machine code for the lower 4 bits equals the binary value of the a data minus 7, 9.g., to load the lower four bits of 8 (Bd) with the value 9 (10019), the lower 4 bits of the LBI instruction equal 8 (10002). To load 0, the lowar 4 bits of tha LBI instruction should equal 15 (11113). Note 6: Machine code for operand field y for LEI instruction should equal the binary value to be latched into EN, where a "1" or 0 in each bit of EN cormespands to the selection or deselection of a particular function associated with each bit. (See Functional Description, EN Register.) Description of Selection Instructions The following information is provided to assist the user in fuf in recognizing pulses of short duration or pulses which understanding the operation of several unique instructions occur too efien to be read conveniently by an ININ instruc- and to provide notes useful to programmers in writing tion. COP404LSN-5 programs. Note: IL latches are not cleared on reset. XAS INSTRUCTIONS LQID INSTRUCTION XAS (Exchange A with SIO) exchanges the 4-bit contents of LQID (Load Q Indirect) toads the 8-bit Q register with the the accumulator with the 4-bit contents of the SIO register. contents of ROM pointed to by the 11-bit word PC19, PCs, The contents of SIO will contain serial-in/serial-out shift reg- PCg, A, M. LQID can be used for table lookup or code con- ister or binary counter data, depending on the value of the version such as BCD to seven-segment. The LQID instruc- EN register. An XAS instruction will also affect the SK out- tion pushes the stack (PC + 1 SA SB - SC) put. (See Functional Description, EN Register.) If SIO is se- and replaces the least significant 8 bits of PC as follows: fected as a shift register, an XAS instruction must be per- A ~> PC;7.4, RAM(B) PC3.o, leaving PGi, PCg and formed once every 4 instruction cycles to effect a continu- PCg unchanged. The ROM data pointed to by the new ad- ous data stream. dress is fetched and loaded into the Q latches. Next, the stack is popped (SC SB SA PC), restoring JID INSTRUCTION : : , . oo oo. . the saved value of PG to continue sequential program exe- JID (Jump Indirect) is an indirect addressing instruction, cution. Since LQID pushes SB > SC, the previous con- transterring program control to a new ROM location pointed tents of SC are lost. Also, when LQID pops the stack, the to indirectly by A and M. It loads the lower 8 bits of the ROM previously pushed contents of SB are left in SC. The net address register PC with the contents of ROM addressed by result is that the contents of SB are placed in SC (SB > the 11-bit word, PC10.5, A, M. PC49, PCg and PCg are not SC). affected by this instruction. Note: JID requires 2 instruction cycles to execute. INIL INSTRUCTION INIL (Input IL Latches to A} inputs 2 latches, ILg and iLy (see Figure 7) and CKO into A. The lig and !Lp latches are set if a low-going pulse (1 to 0") has occurred on the {Ng and INg/IN3 > : INo inputs since the last INIL instruction, provided the input wal pulse stays low for at least two instruction times. Execution ac of an INIL inputs ILg and Ila into A3 and AO respectively, SET arcn and resets these iatches to allow them to respond to subse- uy quent low-going pulses on the INg and No lines. iNIL will input 1 into A2 on the COP404LSN-5. A 0 is always Init placed in A1 upon the execution of an INIL. The general Purpose inputs IN3-INo are input to A upon execution of an TLDo/e817~12 ININ instruction. (See Table Il, ININ instruction.) INIL is use- FIGURE 7. INIL Hardware Implementation Note: LQID takes two instruction cycle times to execute. CcorapaL RESET 1-313 S-NS71h0tdODCOP404LSN-5 Description of Selected Instructions (Continued) SKT INSTRUCTION The SKT (Skip On Timer) instruction tests the state of an internal 10-bit time-base counter. This counter divides the instruction cycle clock frequency by 1024 and provides a latched indication of counter overflow. The SKT instruction tests this latch, executing the next program instruction if the latch is not set. If the latch has been set since the previous test, the next program instruction is skipped and the latch is reset. The features associated with this instruction, there- fore, allow the COP404LSN-5 to generate its own time-base for real-time processing rather than relying on an external input signal. For example, using a 2.097 MHz oscillator as the time-base to the clock generator, the instruction cycle clock frequency will be 65 kHz (crystal frequency + 32) and the binary coun- ter output pulse frequency will be 64 Hz. For time-of-day or similar real-time processing, the SKT instruction can call a routine which increments a seconds counter every 64 ticks. INSTRUCTION SET NOTES a. The first word of a COP404LSN-5 program (ROM ad- dress 0) must be a CLRA (Clear A) instruction. b. Although skipped instructions are not executed, one in- struction cycle time is devoted to skipping each byte of the skipped instruction. Thus ail program paths except JID and LOID take the same number of cycle times whether instructions are skipped or executed. JID and LOID instructions take 2 cycles if executed and 1 cycle if skipped. COP404LSN-5 Mask Options c. The ROM is organized into 32 pages of 64 words each. The Program Counter is an 14-bit binary counter, and will count through page boundaries. If a JP, JSRP, JID or LQID instruction is located in the last word of a page, the instruction operates as if it were in the next page. For example: a JP located in the last word of a page will jump to a location in the next page. Also, a LQID or JID locat- ed in the last word of page 3, 7, 11, 15, 19, 23 or 27 will access data in the next group of four pages. Typical Applications PROM-BASED SYSTEM The COP404LSN-5 may be used to exactly emulate the COP444L. Figure & shows the interconnect to implement a COP444L hardware emulation. This connection uses a MM2716 EPROM as external memory. Cther memory can be used such as bipolar PROM or RAM. Pins IP7--IPO are bidirectional inputs and outputs. When the AD/DATA clocking output turns on, the EPROM drivers are disabled and !P7-IPO output addresses. The 8-bit latch (MM74LS373) latches the addresses to drive the memory. When AD/DATA turns off, tha EPROM is enabled and the IP7-IPO pins will input the memory data. P&, P9 and SKIP/ P10 output the most significant address bits to the memory. (SKIP output may be used for program debug if needed.) The other 28 pins of the COP404LSN-5 may be configured exactly the same as a COP444L. The COP4G4LSN-5 Voc can vary from 4.5V to 5.5V. However, 5V is used for the memory. For In-Circuit emulation, see also COP444LP. The following COP444L options have been implemented on the COP404LSN-5. Option Value Comment Option 1 = 0 Ground, no option available Option 2 = 0 CKO is clock generator output to crystal/resonator Option3 = 0 CK is oscillator input (divide by 32) Option 4 = 0 RESET pin has load device to Voc Option 5 = 2 L7 Option 6 = 2 Le have LED direct-drive Option? = 2 Ls] output Option 8 = 2 La Option 9 = 0 IN1 has load device to Voc Option 10 = 0 IN2 has load device to Voc Option 11 = 1 Voc 4.5V to 5.5V operation Option 12 = 2 Ls Option 13 = 2 Lo have LED direct-drive Option 14 = 2 Ly output Option 15 = 2 Lo Option 16 = 0 SI has load to Voc Option 17 = 2 SO has push-pull output Option Value Comment Option 18 = 2 SK has push-pull output Option 19 = 0 INO has load device to Vcc Option 20 = 0 IN3 has load device to Voo Option 21 = 0 Go Option 22 = 0 Gy have high current Option 23 = 0 Ge standard output Option 24 = 0 G3 Option 25 = 0 Dg Option 26 = 0 De| have high current Option 27 = 0 Dy standard output Option 28 = 0 Do Option 29 = 1 L Option 30 = 1 n| have higher voltage Option 31 = 1 G input levels Option 32 = 0 SI has standard input level Option 33 = 0 RESET has Schmitt trigger input Option 34 = 0 CKO has standard input levels - Option 35 = N/A 40-pin package 1-314Typical Applications (Continued) +5V Ar Ag As Aa MM2716 Avo 2048 x @ EPROM A3 Ag Ap Ap Ay OE cE Oo Lr) O7 04 02 04 VWPGP ISP MPs] 14, 107 9 WOU 1EP 5p t2) 9) GES} 2 +5 20 Vcc GND DM74LS373 ! OUTPUT DIS 1 $110 IPz IP IPs 149 15 5 16 | 17 19 25 | 26 | 27 | 28 | 29) 30 La INT IN2 Vec L3 Le by Lo Si SO SK INo IN3 Gc G Gz Gy Dy De Oy Oy 12 3 4 5 7 B 9 16 11 12 13 14 15 16 17 18 19 20 21 22 23 2425 26 27 28 FIGURE 8. COP404LSN-5 System Diagram COPa44L PINOUT TL/DD/8817-13 1-315 S-NS1h0rd09