1
LTC1473
Dual PowerPathTM
Switch Driver
■
Power Path Management for Systems with Multiple
DC Sources
■
All N-Channel Switching to Reduce Power Losses and
System Cost
■
Switches and Isolates Sources Up to 30V
■
Adaptive High Voltage Step-Up Regulator for N-Channel
Gate Drive
■
Capacitor Inrush and Short-Circuit Current Limited
■
User-Programmable Timer to Limit Switch Dissipation
■
Small Footprint: 16-Pin Narrow SSOP
The LTC
®
1473 provides a power management solution for
single and dual battery notebook computers and other
portable equipment. The LTC1473 drives two sets of back-
to-back N-channel MOSFET switches to route power to the
input of the main system switching regulator. An internal
boost regulator provides the voltage to fully enhance the
logic level N-channel MOSFET switches.
The LTC1473 senses current to limit surge currents both
into and out of the batteries and the system supply
capacitor during switch-over transitions or during fault
conditions. A user-programmable timer monitors the time
the MOSFET switches are in current limit and latches them
off when the programmed time is exceeded.
A unique “2-diode mode” logic ensures system start-up
regardless of which input receives power first.
■
Notebook Computers
■
Portable Instruments
■
Handi-Terminals
■
Portable Medical Equipment
■
Portable Industrial Control Equipment PowerPath is a trademark of Linear Technology Corporation.
, LTC and LT are registered trademarks of Linear Technology Corporation.
IN1
IN2
DIODE
TIMER
V+
VGG
SW
GND
GA1
SAB1
GB1
SENSE+
SENSE–
GA2
SAB2
GB2
LTC1473
COUT
RSENSE
0.04Ω
1µF
1µF
MMBD914LTI
1mH*
Si9926DY
MMBD2838LTI
1473 TA01
BAT1
DCIN
BAT2
INPUT OF SYSTEM
HIGH EFFICIENCY DC/DC
SWITCHING REGULATOR
(LTC1735, ETC)
FROM POWER
MANAGEMENT
µP
CTIMER
4700pF
MBRD340
Si9926DY
*COILCRAFT 1812LS-105XKBC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
FEATURES
DESCRIPTIO
U
APPLICATIO S
U
TYPICAL APPLICATION
U
2
LTC1473
ABSOLUTE MAXIMUM RATINGS
W
WW
U
DCIN, BAT1, BAT2 Supply Voltage .............. –0.3 to 32V
SENSE
+
, SENSE
–
, V
+
.................................. –0.3 to 32V
GA1, GB1, GA2, GB2 ................................... –0.3 to 42V
SAB1, SAB2 ................................................. – 0.3 to 32V
SW, V
GG
...................................................... – 0.3 to 42V
IN1, IN2, DIODE........................................–0.3V to 7.5V
Junction Temperature (Note 2)............................. 125°C
Operating Temperature Range
Commercial ............................................. 0°C to 70°C
Industrial ........................................... –40°C to 85°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
ORDER PART
NUMBER
PACKAGE/ORDER INFORMATION
W
UU
LTC1473CGN
LTC1473IGN
TOP VIEW
GN PACKAGE
16-LEAD NARROW PLASTIC SSOP
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
IN1
IN2
DIODE
TIMER
V
+
V
GG
SW
GND
GA1
SAB1
GB1
SENSE
+
SENSE
–
GA2
SAB2
GB2
T
JMAX
= 125°C, θ
JA
= 150°C/ W
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
+
Supply Operating Range 4.75 30 V
I
S
Supply Current V
IN1
= V
DIODE
= 5V, V
IN2
= 0V, V
SENSE+
= V
SENSE–
= 20V ●100 200 µA
V
GS
V
GS
Gate Supply Voltage V
GS
= V
GG
– V
+
●7.5 8.5 9.5 V
V
+UVLO
V
+
Undervoltage Lockout Threshold V
+
Ramping Down 2.7 3.1 3.5 V
V
+UVLOHYS
V
+
Undervoltage Lockout Hysteresis 0.75 1 1.25 V
V
HIDIGIN
Digital Input Logic High ●2 1.6 V
V
LODIGIN
Digital Input Logic Low ●1.5 0.8 V
I
IN
Input Current V
IN1
= V
IN2
= V
DIODE
= 5V ±1µA
V
GS(ON)
Gate-to-Source ON Voltage I
GA1
= I
GA2
= I
GB1
= I
GB2
= –1µA, V
SAB1
= V
SAB2
= 20V ●5.0 5.7 7.0 V
V
GS(OFF)
Gate-to-Source OFF Voltage I
GA1
= I
GA2
= I
GB1
= I
GB2
= 100µA, V
SAB1
= V
SAB2
= 20V ●00.4 V
I
BSENSE+
SENSE
+
Input Bias Current V
SENSE+
= V
SENSE–
= 20V ●24.56.5µA
V
SENSE+
= V
SENSE–
= 0V (Note 3) ●–300 –160 –100 µA
I
BSENSE–
SENSE
–
Input Bias Current V
SENSE+
= V
SENSE–
= 20V ●24.56.5µA
V
SENSE+
= V
SENSE–
= 0V (Note 3) ●–300 –160 –100 µA
V
SENSE
Inrush Current Limit Sense Voltage V
SENSE–
= 20V (V
SENSE+
– V
SENSE–
)●0.15 0.20 0.25 V
V
SENSE–
= 0V (V
SENSE+
– V
SENSE–
) 0.10 0.20 0.30 V
I
PDSAB
SAB1, SAB2 Pull-Down Current V
IN1
= V
IN2
= V
DIODE
= 0.8V 5 20 35 µA
V
IN1
= V
IN2
= 0.8V, V
DIODE
= 2V 30 200 350 µA
I
TIMER
Timer Source Current V
IN1
= 0.8V, V
IN2
= V
DIODE
= 2V, V
TIMER
= 0V, ●35.59 µA
V
SENSE+
– V
SENSE–
= 300mV
V
TIMER
Timer Latch Threshold Voltage V
IN1
= 0.8V, V
IN2
= V
DIODE
= 2V ●1.1 1.2 1.3 V
t
ON
Gate Drive Rise Time C
GS
= 1000pF, V
SAB1
= V
SAB2
= 0V (Note 4) 33 µs
t
OFF
Gate Drive Fall Time C
GS
= 1000pF, V
SAB1
= V
SAB2
= 20V (Note 4) 2 µs
t
D1
Gate Drive Turn-On Delay C
GS
= 1000pF, V
SAB1
= V
SAB2
= 0V (Note 4) 22 µs
t
D2
Gate Drive Turn-Off Delay C
GS
= 1000pF, V
SAB1
= V
SAB2
= 20V (Note 4) 1 µs
f
OVGG
V
GG
Regulator Operating Frequency 30 kHz
ELECTRICAL CHARACTERISTICS
Test circuit, V+ = 20V, unless otherwise specified.
Consult factory for Military grade parts.
(Note 1)
The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C.
GN PART MARKING
1473
1473I
3
LTC1473
TYPICAL PERFORMANCE CHARACTERISTICS
UW
DC Supply Current
vs Supply Voltage
SUPPLY VOLTAGE (V)
0
SUPPLY CURRENT (µA)
80
120
40
1473 G01
40
010 20 30
515 25 35
160
60
100
20
140 V
DIODE
= V
IN1
= 5V
V
IN2
= 0V
V
DIODE
= 5V
V
IN1
= V
IN2
= 0V
V
SENSE+
= V
SENSE–
= V
+
DC Supply Current vs VSENSE
DC Supply Current
vs Temperature
TEMPERATURE (°C)
–50
50
SUPPLY CURRENT (µA)
60
80
90
100
0
140
1473 G02
70
–25 25 50 75 100 125
110
120
130
V
+
= 20V
V
DIODE
= V
IN1
= 5V
V
IN2
= 0V
V
DIODE
= 5V
V
IN1
= V
IN2
= 0V
VGS Gate-to-Source ON Voltage
vs Temperature
TEMPERATURE (°C)
–50
5.1
V
GS
GATE-TO-SOURCE ON VOLTAGE (V)
5.2
5.4
5.5
5.6
0
6.0
1473 G04
5.3
–25 25 50 75 100 125
5.7
5.8
5.9
V
+
= V
SAB
=20V
TEMPERATURE (°C)
–50
1.0
SUPPLY VOLTAGE (V)
1.5
2.5
3.0
3.5
0
5.5
1473 G05
2.0
–25 25 50 75 100 125
4.0
4.5
5.0 START-UP
THRESHOLD
SHUTDOWN
THRESHOLD
Undervoltage Lockout Threshold (V+)
vs Temperature
Note 4: Gate turn-on and turn-off times are measured with no inrush
current limiting, i.e., V
SENSE
= 0V. Gate rise times are measured from 1V to
4.5V and fall times are measured from 4.5V to 1V. Delay times are
measured from the input transition to when the gate voltage has risen or
fallen to 3V.
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: T
J
is calculated from the ambient temperature T
A
and power
dissipation P
D
according to the following formula:
T
J
= T
A
+ (P
D
)(150°C/W)
Note 3: I
S
increases by the same amount as I
BSENSE+
+ I
BSENSE–
when
their common mode falls below 5V.
ELECTRICAL CHARACTERISTICS
VGS Gate Supply Voltage
vs Temperature
TEMPERATURE (°C)
–50
8.1
V
GS
GATE SUPPLY VOLTAGE (V)
8.2
8.4
8.5
8.6
0
9.0
1473 G03
8.3
–25 25 50 75 100 125
8.7
8.8
8.9
V
+
= 20V
V
GS =
V
GG
– V
+
|V
SENSE
| COMMON MODE(V)
0
SUPPLY CURRENT (µA)
20
1473 • TPC02.5
510 15
2.5 7.5 12.5 17.5
500
450
400
350
300
250
200
150
100
V
+
= 20V
V
DIODE
= V
IN1
= 5V
V
IN2
= 0V
V
SENSE+
– V
SENSE–
= 0V
4
LTC1473
TYPICAL PERFORMANCE CHARACTERISTICS
UW
Logic Input Threshold Voltage
vs Temperature
TEMPERATURE (°C)
–50
1.0
LOGCI INPUT THRESHOLD VOLTAGE (V)
1.1
1.3
1.4
1.5
0
1.9
1473 G11
1.2
–25 25 50 75 100 125
1.6
1.7
1.8
V
HIGH
V
LOW
V
+
= 20V
Logic Input Threshold Voltage
vs Temperature
TEMPERATURE (°C)
–50
1.0
LOGIC INPUT THRESHOLD VOLTAGE (V)
1.1
1.3
1.4
1.5
0
1.9
1473 G10
1.2
–25 25 50 75 100 125
1.6
1.7
1.8
V
HIGH
V
LOW
V
+
= 5V
Timer Latch Threshold Voltage
vs Temperature
TEMPERATURE (°C)
–50
1.10
TIMER LATCH THRESHOLD VOLTAGE (V)
1.12
1.16
1.18
1.20
0
1.28
1473 G12
1.14
–25 25 50 75 100 125
1.22
1.24
1.26
V
+
= 20V
Timer Source Current
vs Temperature
TEMPERATURE (°C)
–50
4.0
TIMER SOURCE CURRENT (µA)
4.5
5.5
6.0
6.5
0
8.5
1473 G13
5.0
–25 25 50 75 100 125
7.0
7.5
8.0
V
+
= 20V
TIMER = 0V
Turn-On Delay and Gate Rise Time
vs Temperature
TEMPERATURE (°C)
–50
0
TURN-ON DELAY AND GATE RISE TIME (µs)
5
15
20
25
0
45
1473 G06
10
–25 25 50 75 100 125
30
35
40 GATE RISE
TIME
V
+
= 20V
C
LOAD
= 1000pF
V
SAB
= 0V
TURN-ON
DELAY
Turn-Off Delay and Gate Fall Time
vs Temperature
TEMPERATURE (°C)
–50
0.4
TURN-OFF DELAY AND GATE FALL TIME (µs)
0.6
1.0
1.2
1.4
0
2.2
1473 G07
0.8
–25 25 50 75 100 125
1.6
1.8
2.0
GATE FALL
TIME
V
+
= 20V
C
LOAD
= 1000pF
V
SAB
= 20V
TURN-OFF
DELAY
Rise and Fall Time
vs Gate Capacitive Loading
GATE CAPACITIVE LOADING (pF)
10
20
RISE AND FALL TIME (µs)
30
40
100 1000 10000
1473 G08
10
5
25
35
15
0
RISE TIME
V
SAB
= 0V
FALL TIME
V
SAB
= 20V
Sense Pin Source Current
IBSENSE vs VSENSE
V
SENSE
(V)
0
SENSE PIN CURRENT (µA)
20
1473 • TPC14
510 15
2.5 7.5 12.5 17.5
175
150
125
100
75
50
25
0
–25
V
+
= 20V
V
DIODE
= V
IN1
= 5V
V
IN2
= 0V
V
SENSE+
– V
SENSE–
= 0V
5
LTC1473
PIN FUNCTIONS
UUU
IN1 (Pin 1): Logic Input of Gate Drivers GA1 and GB1. IN1
is disabled when IN2 is high or DIODE is low.
IN2 (Pin 2): Logic Input of Gate Drivers GA2 and GB2. IN2
is disabled when IN1 is high or DIODE is low.
DIODE (Pin 3): “2-Diode Mode” Logic Input. DIODE over-
rides IN1 and IN2 by forcing the two back-to-back
external N-channel MOSFET switches to mimic two
diodes.
TIMER (Pin 4): Fault Timer. A capacitor connected from
this pin to GND programs the time the MOSFET switches
are allowed to be in current limit. To disable this function,
Pin 4 can be grounded.
V
+
(Pin 5): Input Supply. Bypass this pin with at least a 1µF
capacitor.
V
GG
(Pin 6): Gate Driver Supply. This high voltage supply
is intended only for driving the internal micropower gate
drive circuitry.
Do not load this pin with any external
circuitry
. Bypass this pin with at least 1µF.
SW (Pin 7): Open Drain of an internal N-Channel MOSFET
Switch. This pin drives the bottom of the V
GG
switching
regulator inductor which is connected between this pin
and the V
+
pin.
GND (Pin 8): Ground.
GA2, GB2 (Pins 11, 9): Switch Gate Drivers. GA2 and GB2
drive the gates of the second back-to-back external
N-channel switches.
SAB2 (Pin 10): Source Return. The SAB2 pin is connected
to the sources of SW A2 and SW B2. A small pull-down
current source returns this node to 0V when the switches
are turned off.
SENSE
–
(Pin 12): Inrush Current Input. This pin should be
connected directly to the bottom (output side) of the low
value current sense resistor in series with the two input
power selector switch pairs, SW A1/B1 and SW A2/B2, for
detecting and controlling the inrush current into and out of
the power supply sources and the output capacitor.
SENSE
+
(Pin 13): Inrush Current Input. This pin should be
connected directly to the top (switch side) of the low value
current sense resistor in series with the two input power
selector switch pairs, SW A1/B1 and SW A2/B2, for
detecting and controlling the inrush current into and out of
the power supply sources and the output capacitor. Cur-
rent limit is invoked when (V
SENSE +
– V
SENSE –
) exceeds
±0.2V.
GA1, GB1 (Pins 16, 14): Switch Gate Drivers. GA1 and
GB1 drive the gates of the first back-to-back external
N-channel switches.
SAB1 (Pin 15): Source Return. The SAB1 pin is connected
to the sources of SW A1 and SW B1. A small pull-down
current source returns this node to 0V when the switches
are turned off.
6
LTC1473
FUNCTIONAL DIAGRA
UU
W
GA1
SAB1
GB1
GA2
SAB2
GB2
1473 FD
SENSE+
SENSE–
IN1
IN2
DIODE
V+
TIMER
V+
SW
TO
GATE
DRIVERS
VGG
GND
1.20V
VGG
SWITCHING
REGULATOR
INRUSH
CURRENT
SENSE
900k
5.5µA
LATCH
R
S
–
+
SW A1/B1
GATE
DRIVERS
SW A2/B2
GATE
DRIVERS
16
15
14
13
12
11
10
9
8
6
5
4
3
2
1
7
7
LTC1473
The LTC1473 is responsible for low-loss switching and
isolation at the “front end” of the power management
system, where up to two battery packs can be connected
and disconnected seamlessly. Smooth switching between
input power sources is accomplished with the help of
lowloss N-channel switches. They are driven by special
gate drive circuitry which limits the inrush current in and
out of the battery packs and the system power supply
capacitors.
All N-Channel Switching
The LTC1473 drives external back-to-back N-channel
MOSFET switches to direct power from two sources: the
primary battery and the secondary battery or a battery and
a wall unit. (N-channel MOSFET switches are more cost
effective and provide lower voltage drops than their P-
channel counterparts.)
Gate Drive (V
GG
) Power Supply
The gate drive for the low-loss N-channel switches is
supplied by an internal micropower boost regulator which
is regulated at approximately 8.5V above V
+
, up to 37V
maximum. In two battery systems, the LTC1473 V
+
pin is
diode ORed through three external diodes connected to
the three main power sources, DCIN, BAT1 and BAT2.
Thus, V
GG
is regulated at 8.5V above the highest power
source and will provide the overdrive required to fully
enhance the MOSFET switches.
For maximum efficiency the top of the boost regulator
inductor is connected to V
+
as shown in Figure 1. C1
provides filtering at the top of the 1mH switched inductor,
L1, which is housed in a small surface mount package. An
internal diode directs the current from the 1mH inductor to
the V
GG
output capacitor C2.
Inrush and Short-Circuit Current Limiting
The LTC1473 uses an adaptive inrush current limiting
scheme to reduce current flowing in and out of the two
main power sources and the following system’s input
capacitor during switch-over transitions. The voltage across
a single small valued resistor, R
SENSE
, is measured to
ascertain the instantaneous current flowing through the
Figure 2. SW A1/B1 Inrush Current Limiting
V
SENSE+
V
SENSE–
GA1 GB1
SAB1
SW A1 SW B1 R
SENSE
1473 F02
BAT1
+
OUTPUT
LOAD
C
OUT
V
GG
LTC1473
6V 6V ± 200mV
THRESHOLD
SW A/B
GATE
DRIVERS
BIDIRECTIONAL
INRUSH CURRENT
SENSING AND
LIMITING
BAT1 BAT2DCIN
V
+
SW
GND
1473 F01
V
GG
L1
1mH
C1
1µF
50V
TO GATE
DRIVERS
(8.5V + V
+
)
LTC1473
C2
1µF
50V
V
GG
SWITCHING
REGULATOR
Figure 1. VGG Switching Regulator
two switch pairs, SW A1/B1 and SW A2/B2, during the
transitions.
Figure 2 shows a block diagram of a switch driver pair, SW
A1/B1. A bidirectional current sensing and limiting circuit
determines when the voltage drop across R
SENSE
reaches
±200mV. The gate-to-source voltage, V
GS
, of the appro-
priate switch is limited during the transition period until
the inrush current subsides, generally within a few milli-
seconds, depending upon the value of the following
system’s input capacitor.
This scheme allows capacitors and MOSFET switches of
differing sizes and current ratings to be used in the same
system without circuit modifications.
OPERATION
U
8
LTC1473
After the transition period, the V
GS
of both MOSFETs in the
selected switch pair rises to approximately 5.6V. The gate
drive is set at 5.6V to provide ample overdrive for standard
logic-level MOSFET switches without exceeding their
maximum V
GS
rating.
In the event of a fault condition the current limit loop will
limit the inrush current into the short. At the instant the
MOSFET switch is in current limit, i.e., when the voltage
drop across R
SENSE
is ±200mV, a fault timer will start
timing. It will continue to time as long as the MOSFET
switch is in current limit. Eventually the preset time will
lapse and the MOSFET switch will latch off. The latch is
reset by deselecting the gate drive input. Fault time-out is
programmed by an external capacitor connected between
the TIMER pin and ground.
POWER PATH SWITCHING CONCEPTS
Power Source Selection
The LTC1473 drives low-loss switches to direct power in
the main power path of a single or dual rechargeable
battery system, the type found in many notebook comput-
ers and other portable equipment.
Figure 3 is a conceptual block diagram that illustrates the
main features of an LTC1473 dual battery power manage-
ment system starting with the three main power sources
and ending at the output load (i.e.: system DC/DC
regulator).
Switches SW A1/B1 and SW A2/B2 direct power from
either batteries to the input of the DC/DC switching regu-
lator. Each of the switches is controlled by a TTL/CMOS
compatible input that can interface directly with a power
management system µP.
Using Tantalum Capacitors
The inrush (and “outrush”) current of the system DC/DC
regulator input capacitor is limited by the LTC1473, i.e.,
the current flowing both in and out of the capacitor during
transitions from one input power source to another is
limited. In many applications, this inrush current limiting
makes it feasible to use smaller tantalum surface mount
capacitors in place of larger aluminum electrolytics.
Note: The capacitor manufacturer should be consulted for
specific inrush current specifications and limitations and
some experimentation may be required to ensure compli-
ance with these limitations under all possible operating
conditions.
Back-to-Back Switch Topology
The simple SPST switches shown in Figure 3 actually
consist of two back-to-back N-channel switches. These
low-loss N-channel switch pairs are housed in 8-pin SO
and SSOP packaging and are available from a number of
manufacturers. The back-to-back topology eliminates the
problems associated with the inherent body diodes in
power MOSFET switches and allows each switch pair to
APPLICATIONS INFORMATION
WUUU
Figure 3. LTC1473 PowerPath Conceptual Diagram
BAT1
BAT2
INRUSH
CURRENT
LIMITING
SW A1/B1
SW A2/B2
+
HIGH
EFFICIENCY
DC/DC
SWITCHING
REGULATOR
5V
3.3V
1473 F03
12V
C
IN
DCIN
POWER
MANAGEMENT
µP
OUTPUT LOAD
LTC1473
9
LTC1473
APPLICATIONS INFORMATION
WUUU
block current flow in either direction when both switches
are turned off.
The back-to-back topology also allows for independent
control of each half of the switch pair which facilitates
bidirectional inrush current limiting and the so-called
“2-diode mode” described in the following section.
The 2-Diode Mode
Under normal operating conditions, both halves of each
switch pair are turned on and off simultaneously. For
example, when the input power source is switched from
BAT1 to BAT2 in Figure 4, both gates of switch pair SW
A1/B1 are normally turned off and both gates of switch pair
SW A2/B2 are turned on. The back-to-back body diodes in
switch pair, SW A1/B1, block current flow in or out of the
BAT1 input connector.
In the “2-diode mode,” only the first half of each power
path switch pair, i.e., SW A1 and SW A2, are turned on; and
the second half, i.e., SW B1 and SW B2 are turned off.
These two switch pairs now act simply as two diodes
connected to the two main input power sources as illus-
trated in Figure 4. The power path diode with the highest
input voltage passes current through to the output load
(i.e. input of the DC/DC converter) to ensure that the power
management µP is powered even under start-up or abnor-
mal operating conditions. (An undervoltage lockout circuit
defeats this mode when the V
+
pin drops below approxi-
mately 3.2V. The supply to V
+
comes from the main power
sources, DCIN, BAT1 and BAT2 through three external
diodes as shown in Figure 1.)
The 2-diode mode is asserted by applying an active low to
the DIODE input.
COMPONENT SELECTION
N-Channel Switches
The LTC1473 adaptive inrush current limiting circuitry
permits the use of a wide range of logic-level N-Channel
MOSFET switches. A number of dual, low R
DS(ON)
N-channel switches in 8-lead surface mount packages are
available that are well suited for LTC1473 applications.
The maximum allowable drain-source voltage, V
DS(MAX)
,
of the two switch pairs, SW A1/B1 and SW A2/B2 must be
high enough to withstand the maximum DC supply volt-
age. If the DC supply is in the 20V to 28V range, use 30V
MOSFET switches. If the DC supply is in the 10V to 18V
range, and is well regulated, then 20V MOSFET switches
will suffice.
Figure 4. LTC1473 PowerPath Switches in 2-Diode Mode
BAT1
DCIN
BAT2
SW A2
SW B2
ON OFF
R
SENSE
HIGH
EFFICIENCY
DC/DC
SWITCHING
REGULATOR
5V
3.3V
1473 F04
12V
POWER
MANAGEMENT
µP
+
C
IN
SW A1
SW B1
ON OFF
LTC1473
OUTPUT LOAD
10
LTC1473
APPLICATIONS INFORMATION
WUUU
As a general rule, select the switch with the lowest R
DS(ON)
and able to withstand the maximum allowable V
DS
. This
will minimize the heat dissipated in the switches while
increasing the overall system efficiency. Higher switch
resistances can be tolerated in some systems with lower
current requirements, but care should be taken to ensure
that the power dissipated in the switches is never allowed
to rise above the manufacturers’ recommended level.
Inrush Current Sense Resistor, R
SENSE
A small valued sense resistor (current shunt) is used by
the two switch pair drivers to measure and limit the inrush
or short-circuit current flowing through the conducting
switch pair.
The inrush current limit should be set at approximately 2×
or 3× the maximum required output current. For example,
if the maximum current required by the DC/DC converter
is 2A, an inrush current limit of 6A is set by selecting a
0.033Ω sense resistor, R
SENSE
, using the following for-
mula:
R
SENSE
= (200mV)/I
INRUSH
Note that the voltage drop across the resistor in this
example is only 66mV under normal operating conditions.
Therefore, the power dissipated in the resistor is ex-
tremely small (132mW), and a small 1/4W surface mount
resistor can be used in this application (the resistor will
tolerate the higher power dissipation during current limit
for the duration of the fault time-out). A number of small
valued surface mount resistors are available that have
been specifically designed for high efficiency current
sensing applications.
Programmable Fault Timer Capacitor, C
TIMER
A fault timer capacitor, C
TIMER
, is used to program the time
duration the MOSFET switches are allowed to be in con-
tinuous current limit.
In the event of a fault condition, the MOSFET switch is
driven into current limit by the inrush current limit loop.
The MOSFET switch operating in current limit is in a high
dissipation mode and can fail catastrophically if not
promptly terminated.
The fault time delay is programmed with an external
capacitor between the TIMER pin and GND. At the instant
the MOSFET switch enters current limit, a 5.5µA current
source starts charging C
TIMER
through the TIMER pin.
When the voltage across C
TIMER
reaches 1.2V an internal
latch is set and the MOSFET switch is turned off. To reset
the latch, the logic input of the MOSFET gate driver is
deselected.
The fault time delay should be programmed as large as
possible, at least 3× to 5× the maximum switching transi-
tion period, to avoid prematurely tripping the protection
circuit. Conversely, for the protection circuit to be effec-
tive, the fault time delay must be within the safe operating
area of the MOSFET switches, as stated in the
manufacturer’s data sheet.
The maximum switching transition period happens during
a cold start, when a fully charged battery is connected to
an unpowered system. The inrush current charging the
system supply capacitor to the battery voltage determines
the switching transition period.
The following example illustrates the calculation of C
TIMER.
Assume the maximum battery voltage is 20V, the system
supply capacitor is 68µF, the inrush current limit is 6A and
the maximum current required by the DC/DC converter is
2A. Then, the maximum switching transition period is
calculated using the following formula:
t
SW(MAX)
=
(V
BAT(MAX)
)(C
IN(DC/DC)
)
I
INRUSH
– I
LOAD
t
SW(MAX)
= = 340µs
(20)(68µF)
6A – 2A
Multiplying 3 by 340µs gives 1.02ms, the minimum fault
delay time. Make sure this delay time does not fall outside
of the safe operating area of the MOSFET switch dissipat-
ing 60W (6A • 20V/2). Using this delay time the C
TIMER
can
be calculated using the following formula:
C
TIMER
= 1.02ms = 4700pF
5.5µA
1.20V
)
)
Therefore, C
TIMER
should be 4700pF.
11
LTC1473
APPLICATIONS INFORMATION
WUUU
V
GG
Regulator Inductor and Capacitors
The V
GG
regulator provides a power supply voltage 8.5V
higher than any of the three main power source voltages
to allow the control of N-channel MOSFET switches. This
micropower, step-up voltage regulator is powered by the
highest potential available from the three main power
sources for maximum regulator efficiency.
BAT1 BAT2DCIN
VGG
SWITCHING
REGULATOR
V+
SW
GND
1473 F05
VGG
L1*
1mH
C1
1µF
50V
C2
1µF
50V
TO GATE
DRIVERS
(8.5V + V+)
LTC1473
*COILCRAFT 1812LS-105 XKBC. (708) 639-6400
Figure 5. VGG Step-Up Switching Regulator
Three external components are required by the V
GG
regu-
lator: L1, C1 and C2, as shown in Figure 5.
L1 is a small, low current, 1mH surface mount inductor. C1
provides filtering at the top of the 1mH switched inductor
and should be at least 1µF to filter switching transients.
The V
GG
output capacitor, C2, provides storage and filter-
ing for the V
GG
output and should be at least 1µF and rated
for 50V operation. C1 and C2 can be ceramic capacitors.
12
LTC1473
TYPICAL APPLICATIONS
U
L1*
1mH
CTIMER
4700pF
CTIMER
4700pF
POWER MANAGEMENT µP
RSENSE
0.033Ω
SMBus
BAT2
8.4V
Li-Ion
BAT1
12V
NiCd
750k
BATTERY CHARGER
DCIN
MBRD340
MMBD914LT1
* COILCRAFT 1812LS-105XKBC
C7
1µFC8
1µF
500k TIMER
V+
VGG
SW
GND
GA1
SAB1
GB1
SENSE+
SENSE–
GA2
SAB2
GB2
LTC1473
Si9926DYSi9926DY
MMBD2838LT1
1473 TA02
16
15
14
13
12
11
10
9
4
5
6
7
8
TIMER
V+
VGG
SW
GND
GA1
SAB1
GB1
SENSE+
SENSE–
GA2
SAB2
GB2
LTC1473
16
15
14
13
12
11
10
9
4
5
6
7
8
Si9926DY
Si9926DY
IN1
IN2
1
2
3
DIODE
1
2
3
IN1
IN2
DIODE
RSENSE
0.033Ω
HIGH EFFICIENCY
DC/DC SWITCHING
REGULATOR
Input Power Routing Circuit for Microprocessor Controlled Dual Battery Dual Chemistry System
13
LTC1473
TYPICAL APPLICATIONS
U
R
SENSE
0.015Ω
Q1
Si4412DY
C4
0.1µF
D1
CMDSH-3
C3
4.7µF
16V D2
MBRS140T3
C
IN
22µF
35V
× 2
C
OUT
100µF
10V
× 3
V
OUT
5V/3.5A
Q2
Si4412DY
+
+
R1
105k
1%
L1*
10µH
SGND
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
C1
100pF C5
1000pF
C
SS
, 0.1µF
C
C2
, 51pF
C
OSC
57pF
R
C
, 10k
C
C
330pF
+
C6
100pF
C2, 0.1µF
R2
20k
1%
4700pF
C
TIMER
C7
1µFC8
1µF
GND
SW
BOOST
GND
GND
UV
GND
OVP
CLP
CLN
COMP1
SENSE
GND
GND
V
CC1
V
CC2
V
CC3
PROG
V
C
UVOUT
GND
COMP2
BAT
SPIN
LT
®
1511
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
DCIN
OUT A
V
–
IN
+
A
IN
–
B
OUT B
V
+
REF
HYST
LTC1442
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
1
2
3
4
8
7
6
5
74C00
12
3
45
6
13
12
11
14
MMBD2838LT1
D5
MBRD340
C11
0.47µF
D6
MBR0540T
D4
MBRD340
L3***
20µH
2,3
1,4
C10
1µF
R13
5.1k
1%
R12
3k
1%
C16
220pF
R
SENSE
0.033Ω
R20
395k
0.1%
R21
164k
0.1%
C17
10µF
8.4V
Li-Ion
BATTERY
R19
200Ω
1%
R15
1k
C15
0.33µF
R16
300Ω
C14
1µF
R17
4.93k
C12
10µF
C13
10µF
R
SENSE
0.033Ω
R14
510Ω
R6
900k
1%
R7
130k
1%
R9
113k
1%
R8
427k
1%
R10
50k
1%
R11
1132k
1%
C9
0.1µF
R5
500k
7
L2**
1mH
R18, 200Ω, 1%
1473 TA03
*SUMIDA CDRH125-10
**COILCRAFT 1812LS-105XKBC
***COILTRONICS CTX20-4
10
9
8
Si9926DY
R
SENSE
0.033Ω
IN1
IN2
DIODE
TIMER
V
+
V
GG
SW
GND
GA1
SAB1
GB1
SENSE
+
SENSE
–
GA2
SAB2
GB2
LTC1473
Si9926DY
D3
6.8V
TG
BOOST
SW
V
IN
INTV
CC
BG
PGND
EXTV
CC
C
OSC
RUN/SS
I
TH
SFB
SGND
V
OSENSE
SENSE
–
SENSE
+
LTC1735
8
+
V
OUT
Complete Front End Including Battery Charger and DC/DC Converter with Automatic Switchover Between Battery and DCIN
14
LTC1473
TYPICAL APPLICATION
U
Protected Automatic Switchover Between Two Supplies
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
IN1
IN2
DIODE
TIMER
V
+
V
GG
SW
GND
GA1
SAB1
GB1
SENSE
+
SENSE
–
GA2
SAB2
GB2
LTC1473
+
L1*, 1mH
C5
1µF
+
C7
1µF
C6
4700pF
–
+
5
6
7
–
+
3
2
1
8
4
1M
1M
10k
10k
1M
SUPPLY V2
SUPPLY V1
1M
1µF
5V 18
3
LT1121-5
D1
MMBD2838LT1
Q1
Si9926DY
Q2
Si9926DY
R3
0.033ΩOUT
*1812LS-105XKBC, COILCRAFT
1473 TA04
LT1490
15
LTC1473
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
GN Package
16-Lead Plastic SSOP (Narrow 0.150)
(LTC DWG # 05-08-1641)
Dimensions in inches (millimeters) unless otherwise noted.
PACKAGE DESCRIPTION
U
GN16 (SSOP) 1098
* DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
12
345678
0.229 – 0.244
(5.817 – 6.198)
0.150 – 0.157**
(3.810 – 3.988)
16 15 14 13
0.189 – 0.196*
(4.801 – 4.978)
12 11 10 9
0.016 – 0.050
(0.406 – 1.270)
0.015 ± 0.004
(0.38 ± 0.10) × 45°
0° – 8° TYP
0.007 – 0.0098
(0.178 – 0.249)
0.053 – 0.068
(1.351 – 1.727)
0.008 – 0.012
(0.203 – 0.305)
0.004 – 0.0098
(0.102 – 0.249)
0.0250
(0.635)
BSC
0.009
(0.229)
REF
16
LTC1473
1473fas, sn1473 LT/TP 0400 REV A 2K • PRINTED IN
USA
LINEAR TECHNOLOGY CORPORATION 1997
RELATED PARTS
PART NUMBER DESCRIPTION COMMENTS
LTC1155 Dual High Side Micropower MOSFET Driver Internal Charge Pump Requires No External Components
LTC1161 Quad Protected High Side MOSFET Driver Rugged, Designed for Harsh Environment
LTC1473L Dual PowerPath Switch Driver Low Voltage Version of the LTC1473; Operates with 3.3V Input
LTC1479 PowerPath Controller for Dual Battery Systems Designed to Interface with a Power Management µP
LT1505 Synchronous Constant-Voltage/Constant-Current Up to 6A Charge Current; High Efficiency; Adaptive Current Limiting
Battery Charger
LT1510 Constant-Voltage/Constant-Current Battery Charger Up to 1.5A Charge Current for Lithium-Ion, NiCd and NiMH Batteries
LT1511 3A Constant-Voltage/Constant-Current Battery Charger High Efficiency, Minimal External Components to Fast Charge
Lithium, NiMH and NiCd Batteries
LTC1628 2-Phase Dual Synchronous Step-Down Controller Minimum Input Capacitors; 4.5V ≤ V
IN
≤ 36V
LTC1735 High Efficiency Synchronous Switching Regulator Constant Frequency, V
IN
≤ 36V, Fault Protection
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
●
FAX: (408) 434-0507
●
www.linear-tech.com
TYPICAL APPLICATIONS
U
Protected Hot Swap
TM
Switchover Between Two Supplies
Hot Swap is a trademark of Linear Technology Corporation.
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
IN1
IN2
DIODE
TIMER
V
+
V
GG
SW
GND
GA1
SAB1
GB1
SENSE
+
SENSE
–
GA2
SAB2
GB2
LTC1473
L1*, 1mH
C5
1µF
C7
1µF
100k
100k
C6
4700pF
SUPPLY V2
12V
SUPPLY V1
5V
D1
MMBD2838LT1
Q1
Si4936DY
Q2
Si4936DY
R3
0.1ΩOUT
5V
DOCKING
CONNECTOR
ON
LONG PIN
LONG PIN
SHORT PIN
*1812LS-105XKBC,
COILCRAFT
1473 • TA05
OTHER 5V
LOGIC
SUPPLY