LTC4260IUH#TR - Linear Technology

LTC4260

4260fa

, LTC and LT are registered trademarks of Linear Technology Corporation.

■

Allows Safe Insertion into Live Backplane

■

8-Bit ADC Monitors Current and Voltage

■

/SMBus Interface

■

Wide Operating Voltage Range: 8.5V to 80V

■

High Side Drive for External N-Channel MOSFET

■

Input Overvoltage/Undervoltage Protection

■

Optional Latchoff or Autoretry After Faults

■

Alerts Host After Faults

■

Foldback Current Limiting

■

Available in 24-Lead SO, 24-Lead Narrow

SSOP and 32-Lead (5mm × 5mm) QFN Packages

Positive High Voltage

Hot Swap Controller with

C Compatible Monitoring

■

Electronic Circuit Breakers

■

Live Board Insertion

■

Computers, Servers Hot Swap is a trademark of Linear Technology Corporation.

All other trademarks are the property of their respective owners.

The LTC

4260 Hot Swap

controller allows a board to be

safely inserted and removed from a live backplane. Using

an external N-channel pass transistor, the board supply

voltage can be ramped up at an adjustable rate. An I

interface and onboard ADC allow monitoring of board

current, voltage and fault status.

The device features adjustable analog foldback current

limit with latch off or automatic restart after the LTC4260

remains in current limit beyond an adjustable time-out

delay.

The controller has additional features to interrupt the host

when a fault has occurred, notify when output power is

good, detect insertion of a load card and power-up in either

the on or off state.

BACKPLANE PLUG-IN

CARD

2.67k

1.74k

49.9k

48V

SDA

SCL

ALERT

GND

SENSE

LTC4260

INTV

100k

FDB3632

0.010Ω

10Ω

6.8nF

43.5k

3.57k

OUT

48V

24k

68nF

*DIODES INC. SMBT70A

0.1µF

GATE

TIMER GND

BD_PRST

ADIN

GPIO

4260 TA01

SOURCE

SDAO

SDAI

SCL

ALERT

CONNECTOR 1

CONNECTOR 2

FEATURES

DESCRIPTIO

APPLICATIO S

TYPICAL APPLICATIO

50V/DIV

OUT

50V/DIV

GPIO

5V/DIV

25ms/DIV

4260 TA02

2A/DIV

= 1000µF

Power Up Waveforms

3A, 48V Card Resident Application

LTC4260

4260fa

ORDER

PART NUMBER

ORDER

PART NUMBER

ORDER

PART NUMBER

UH PART

MARKING

Supply Voltages (V

) ............................ – 0.3V to 100V

Input Voltages

SENSE ............................ V

– 10V or –0.3V to V

SOURCE .......................... GATE – 5V to GATE + 0.3V

BD_PRST, FB, ON, OV, UV ................... –0.3V to 12V

ADR0-ADR2, TIMER, ADIN ..... –0.3V to INTV

+ 0.3V

SCL, SDAI ........................................... –0.3V to 6.5V

Output Voltages

GPIO ................................................... –0.3V to 100V

GATE (Note 3) ..................................... –0.3V to 100V

(Notes 1, 2)

ABSOLUTE AXI U RATI GS

WWWU

PACKAGE/ORDER I FOR ATIO

ALERT, SDAO ........................................... –0.3V to 6.5V

Supply Voltage (INTV

) ......................... –0.3V to 6.2V

Operating Temperature Range

LTC4260C ............................................... 0°C to 70°C

LTC4260I............................................. –40°C to 85°C

Storage Temperature Range

GN, SW Packages............................. – 65°C to 150°C

UH Package ...................................... – 65°C to 125°C

Lead Temperature (Soldering, 10 sec)

GN, SW Packages Only..................................... 300°C

TOP VIEW

GN PACKAGE

24-LEAD PLASTIC SSOP

SENSE

VDD

GND

SCL

SDAI

SDAO

ALERT

TIMER

GATE

SOURCE

GPIO

INTVCC

ADR2

ADR1

ADR0

BD_PRST

ADIN

LTC4260CSW

LTC4260ISW

LTC4260CGN

LTC4260IGN

JMAX

= 125°C, θ

= 85°C/W

TOP VIEW

SW PACKAGE

24-LEAD PLASTIC SO

SENSE

GND

SCL

SDAI

SDAO

ALERT

TIMER

GATE

SOURCE

GPIO

INTV

ADR2

ADR1

ADR0

BD_PRST

ADIN

JMAX

= 125°C, θ

= 75°C/W

32 31 30 29 28 27 26 25

9 10 11 12

TOP VIEW

UH PACKAGE

32-LEAD (5mm × 5mm) PLASTIC QFN

13 14 15 16

1NC

GND

SCL

GPIO

INTV

ADR2

DDK

SENSE

GATE

SOURCE

SDAI

SDAO

ALERT

TIMER

ADIN

BD_PRST

ADR0

ADR1

JMAX

= 125°C, θ

= 34°C/W

EXPOSED PAD (PIN 33) PCB ELECTRICAL CONNECTION OPTIONAL

LTC4260CUH

LTC4260IUH

ELECTRICAL CHARACTERISTICS

The ● denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C. VDD = 48V, unless otherwise noted.

4260

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

General

Input Supply Range ●8.5 80 V

Input Supply Current ●25 mA

DD(UVL)

Supply Undervoltage Lockout V

Falling ●7 7.45 7.9 V

Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF

Lead Free Part Marking: http://www.linear.com/leadfree/

Consult LTC Marketing for parts specified with wider operating temperature ranges.

LTC4260

4260fa

ELECTRICAL CHARACTERISTICS

The ● denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C. VDD = 48V, unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

INTV

CC(UVL)

Supply Undervoltage Lockout INTV

Falling ●3.4 3.8 4.2 V

INTV

Internal Regulator Voltage ●5 5.5 6 V

Gate Drive

Turn-On Delay ●50 100 150 ms

∆V

GATE

External N-Channel Gate Drive V

= 20V to 80V ●10 14 18 V

GATE

– V

SOURCE

= 8.5V to 20V ●4.5 6 18 V

GATE(UP)

External N-Channel Pull-Up Current Gate Drive On, V

GATE

= 0V ●–14 –18 –22 µA

GATE(FST)

External N-Channel Fast Pull-Down Fast Turn Off, V

GATE

= 48V, V

SOURCE

= 38V ●400 600 1000 mA

GATE(DN)

External N-Channel Pull-Down Current Gate Drive Off, V

GATE

= 58V, V

SOURCE

= 48V ●0.7 1 1.4 mA

SOURCE

SOURCE Pin Input Current SOURCE = 48V ●200 400 600 µA

Input Pins

ON(TH)

ON Pin Threshold Voltage V

Rising ●1.19 1.235 1.27 V

∆V

ON(HYST)

ON Pin Hysteresis ●60 130 200 mV

ON(IN)

ON Pin Input Current V

= 1.2V ●0±1µA

OV(TH)

OV Pin Threshold Voltage V

Rising ●3.43 3.5 3.56 V

∆V

OV(HYST)

OV Pin Hysteresis ●70 90 120 mV

OV(IN)

OV Pin Input Current V

= 3.5V ●0±1µA

UV(TH)

UV Pin Threshold Voltage V

Rising ●3.43 3.5 3.56 V

∆V

UV(HYST)

UV Pin Hysteresis ●310 380 440 mV

UV(IN)

UV Pin Input Current V

= 3.5V ●0±2µA

UV(RTH)

UV Pin Reset Threshold Voltage V

Falling ●1.18 1.235 1.27 V

∆V

UV(RHYST)

UV Pin Reset Threshold Hysteresis ●80 160 250 mV

∆V

SENSE(TH)

Current Limit Sense Voltage Threshold V

= 3.5V ●45 50 55 mV

– V

SENSE

= 0V ●10 20 30 mV

SENSE(IN)

SENSE Pin Input Current V

SENSE

= 48V ●70 100 130 µA

Foldback Pin Power Good Threshold FB Rising ●3.43 3.5 3.56 V

∆V

FB(HYST)

FB Pin Power Good Hysteresis ●80 100 120 mV

Foldback Pin Input Current FB = 3.5V ●0±2µA

BD_PRST(TH)

BD_PRST Input Threshold V

BD_PRST

Rising ●1.2 1.235 1.27 V

∆V

BD_PRST(HYST)

BD_PRST Hysteresis ●70 130 190 mV

BD_PRST

BD_PRST Pullup Current BD_PRST = 0V ●–7 –10 –16 µA

GPIO(TH)

GPIO Pin Input Threshold V

GPIO

Rising ●1.6 1.8 2 V

∆V

GPIO(HYST)

GPIO Pin Hysteresis 80 mV

GPIO(OL)

GPIO Pin Output Low Voltage I

GPIO

= 2mA ●0.25 0.5 V

GPIO(IN)

GPIO Pin Input Leakage Current V

GPIO

= 80V ●0±10 µA

ADIN

ADIN Pin Input Resistance V

ADIN

= 1.28V ●210 MΩ

ADIN

ADIN Pin Input Current V

ADIN

= 2.56V ●0±1µA

Timer

TIMER(H)

TIMER Pin High Threshold V

TIMER

Rising ●1.2 1.235 1.28 V

TIMER(L)

TIMER Pin Low Threshold V

TIMER

Falling ●0.1 0.2 0.3 V

TIMER(UP)

TIMER Pin Pull-Up Current V

TIMER

= 0V ●–80 –100 –120 µA

TIMER(DN)

TIMER Pin Pull-Down Current V

TIMER

= 1.3V ●1.4 2 2.6 µA

TIMER(RATIO)

TIMER Pin Current Ratio ●1.6 2 2.7 %

TIMER(DN)

TIMER(UP)

LTC4260

4260fa

ELECTRICAL CHARACTERISTICS

The ● denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C. VDD = 48V, unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Note 1: Absolute Maximum Ratings are those values beyond which the life

of the device may be impaired.

Note 2: All currents into pins are positive, all voltages are referenced to

GND unless otherwise specified.

AC Parameters

PLH(GATE)

Input High (ON) to GATE High C

GATE

= 1pF ●13 µs

Propagation Delay

PHL(GATE)

Input High (OV, BD_PRST), Input Low C

GATE

= 1pF ●0.5 3 µs

(ON, UV) to GATE Low Propagation Delay

PHL(SENSE)

– SENSE) High to GATE Low V

– SENSE = 200mV, C

GATE

= 10nF ●0.4 1 µs

ADC

Resolution (No Missing Codes) (Note 4) ●8 Bits

Integral Nonlinearity V

– SENSE (Note 5) ●±0.5 ±2LSB

SOURCE ●±0.2 ±1.25 LSB

ADIN ●±0.2 ±1.25 LSB

Offset Error V

– SENSE ●±1.5 LSB

SOURCE ●±1LSB

ADIN ●±1LSB

Full Scale Error (Note 6) ●±5LSB

Total Unadjusted Error (Note 6) ●±5LSB

Full Scale Voltage (Code 255) V

– SENSE (Note 6) ●75 76.5 78 mV

SOURCE ●100 10.2 104 V

ADIN ●2.50 2.55 2.60 V

Conversion Rate 10 Hz

C Interface

ADR(H)

ADR0 to ADR2 Input High Voltage ●INTV

INTV

Threshold – 0.6 – 0.45 – 0.25

ADR(L)

ADR0 to ADR2 Input Low Voltage Threshold ●0.25 0.45 0.65 V

ADR(IN)

ADR0 to ADR2 Input Current ADR0 to ADR2 = 0V, 5.5V ●–80 80 µA

SDAI,SCL(TH)

SDAI, SCL Input Threshold ●1.6 1.8 2 V

SDAI,SCL(IN)

SDAI, SCL Input Current SCL, SDAI = 5V ●0±1µA

SDAO(OL)

SDAO Output Low Voltage I

SDAO

= 5mA ●0.2 0.4 V

ALERT(OL)

ALERT Output Low Voltage I

ALERT

= 5mA ●0.2 0.4 V

SDAO,ALERT(IN)

SDAO, ALERT Input Current SDAO, ALERT = 5V ●0±1µA

C Interface Timing (Note 4)

SCL(MAX)

Maximum SCL Clock Frequency Operates with f

SCL

≤ f

SCL(MAX)

400 kHz

BUF(MIN)

Minimum Bus Free Time Between 0.12 1.3 µs

Stop/Start Condition

SU,STA(MIN)

Minimum Repeated Start Condition 30 600 ns

Set-Up Time

HD,STA(MIN)

Minimum Hold Time After (Repeated) Start 140 600 ns

Condition

SU,STO(MIN)

Minimum Stop Condition Set-Up Time 30 600 ns

SU,DAT(MIN)

Minimum Data Set-Up Time Input 30 100 ns

HD,DATI(MIN)

Minimum Data Hold Time Input –100 0 ns

HD,DATO(MIN)

Minimum Data Hold Time Output 300 500 900 ns

SP(MAX)

Maximum Suppressed Spike Pulse Width 50 110 250 ns

SCL, SDA Input Capacitance SDAI Tied to SDAO 5 10 pF

LTC4260

4260fa

ELECTRICAL CHARACTERISTICS

TYPICAL PERFOR A CE CHARACTERISTICS

IDD vs VDD

(V)

(mA)

2.0

85°C25°C

2.5

4260 G01

1.5

1.0 20 40 60 100

3.0

–40°C

TEMPERATURE (°C)

–50

3.46

UV LOW-HIGH THRESHOLD (V)

3.48

3.50

3.52

3.54

–25 0 25 50

4260 G02

75 100

TEMPERATURE (°C)

–50

0.34

UV HYSTERESIS (V)

0.35

0.36

0.37

0.38

0.39

–25 02550

4260 G03

75 100

UV Low-High Threshold

vs Temperature

UV Hysteresis vs Temperature

ON, BD_PRST Low-High

Threshold vs Temperature

TEMPERATURE (°C)

–50

1.220

ON, BD_PRST LOW-HIGH THRESHOLD (V)

1.225

1.230

1.235

1.240

1.245

–25 02550

4260 G04

75 100

ON, BD_PRST Hysteresis

vs Temperature

TEMPERATURE (°C)

–50

0.10

ON, BD_PRST HYSTERESIS (V)

0.11

0.12

0.13

0.14

0.16

–25 02550

4260 G05

75 100

0.15

TA = 25°C, VDD = 48V unless otherwise noted.

Note 3:

Limits on maximum rating is defined as whichever limit occurs

first. An internal clamp limits the GATE pin to a minimum of 10V above

source. Driving this pin to voltages beyond the clamp may damage the

device.

Note 4: Guaranteed by design and not subject to test.

Note 5: Integral nonlinearity is defined as the deviation of a code from a

precise analog input voltage. Maximum specifications are limited by the

LSB step size and the single shot measurement. Typical specificatons are

measured from the 1/4, 1/2 and 3/4 areas of the quantization band.

Note 6: For the V

-sense channel, full-scale is at code 255 but codes

above 200 may be discarded by offset cancellation. Full scale error and

total unadjusted error are evaluated over the 0-200 code range. Full scale

voltage corresponds to the theorectical code 255, and is extrapolated from

a code 200 measurement.

INT VCC vs ILOAD

LOAD

(mA)

INTV

(V)

–4 –8

4260 G18

–2 –6 –10

= 48V

= 12V

MAX I

LOAD

= 4.5 mA

CAUTION: DRAWING CURRENT

FROM INTV

INCREASES POWER

DISSIPATION AND T

LTC4260

4260fa

TYPICAL PERFOR A CE CHARACTERISTICS

Current Limit Sense Voltage

vs FB Voltage

Current Limit Propagation Delay

vs Sense Voltage

IGATE Pull Up vs Temperature

TA = 25°C, VDD = 48V unless otherwise noted.

FB VOLTAGE (V)

CURRENT LIMIT SENSE VOLTAGE (VDD – VSENSE) (mV)

12 34

4260 G07

0.5 1.5 2.5 3.5

CURRENT LIMIT SENSE VOLTAGE (V

– V

SENSE

) (mV)

0.1

CURRENT LIMIT PROPAGATION DELAY (µs)

100

1000

50 100 150 200

4260 G08

250 300 350

TEMPERATURE (°C)

–50

–10

IGATE PULL UP (µA)

–15

–20

–25

–25 0 25 50

4260 G09

75 100

Gate Drive vs IGATE

Gate Drive vs Temperature

GATE

(µA)

GATE DRIVE (V

GATE

– V

SOURCE

) (V)

–20

4260 G10

0–5 –10 –15

= 80V

= 48V

= 12V

Gate Drive vs VDD

(V)

GATE DRIVE (V

GATE

– V

SOURCE

) (V)

20 30

4260 G11

10 15 25 35

85°C

25°C

–40°C

TEMPERATURE (°C)

–50

GATE DRIVE (VGATE – VSOURCE) (V)

–25 02550

4260 G12

75 100

ADC Total Unadjusted Error

vs Code (ADIN Pin)

CODE

ADC TOTAL UNADJUSTED ERROR (LSB)

256

4260 G14

–1

–2 64 128 192

TIMER Pull-Up Current

vs Temperature

TEMPERATURE (°C)

–50

–90

TIMER PULL-UP CURRENT (µA)

–95

–100

–105

–110

–25 0 25 50

4260 G06

75 100

GPIO VOUT Low vs ILOAD

LOAD

(mA)

030 50

4260 G13

10 20 40 60

GPIO V

OUT

LOW (V)

LTC4260

4260fa

PI FU CTIO S

ADIN: ADC Input. A voltage between 0V and 2.56V applied

to this pin can be measured by the onboard ADC. Tie to

ground if unused.

ADR0 to ADR2: Serial Bus Address Inputs. Tying these

pins to ground, open or INTV

configures one of 27 pos-

sible addresses. See Table 1 in Applications Information.

ALERT: Fault Alert Output. Open-drain logic output that

can be pulled to ground when a fault occurs to alert the

host controller. A fault alert is enabled by the ALERT

protocol. See Applications Information. Tie to ground if

unused.

BD_PRST: Board Present Input. Ground this pin to enable

the N-channel FET to turn on after 100ms debounce delay.

When this pin is high, the FET is off. An internal 10µA

current source pulls up this pin. Transitions on this pin will

be recorded in the FAULT register. A high-to-low transition

activates the logic to read the state of the ON pin and clear

Faults. See Applications Information.

Exposed Pad (Pin 33, UH Package): Exposed Pad may be

left open or connected to device ground.

FB: Foldback and Power Good Input. A resistive divider

from the output voltage is tied to this pin. When the voltage

at this pin drops below 3.41V, the output power is consid-

ered bad and the current limit is reduced. The power bad

condition can be indicated with the GPIO pin and a power

bad fault can be logged in this condition. See Applications

Information.

GATE: Gate Drive for External N-Channel FET. An internal

18µA current source charges the gate of the external

N-channel MOSFET. A resistor and capacitor network

from this pin to ground sets the turn-on rate and compen-

sates the active current limit. During turn-off there is a

1mA pull-down current. During a short circuit or under-

voltage lockout (V

or INTV

), a 600mA pull-down

current source between GATE and SOURCE is activated.

GND: Device Ground.

TYPICAL PERFOR A CE CHARACTERISTICS

TA = 25°C, VDD = 48V unless otherwise noted.

ADC INL vs Code (ADIN Pin)

CODE

ADC INL (LSB)

0.25

256

4260 G16

–0.25

–0.50 64 128 192

0.50

ADC DNL vs Code (ADIN Pin)

CODE

ADC DNL (LSB)

0.25

256

4260 G17

–0.25

–0.50 64 128 192

0.50

ADC Full-Scale Error

vs Temperature (ADIN Pin)

TEMPERATURE (°C)

–50

–2

ADC FULL-SCALE ERROR (LSB)

–1

–25 0 25 50

3708 G15

75 100

LTC4260

4260fa

GPIO: General Purpose Input/Output. Open-drain logic

output and logic input. Defaults to pull low to indicate

power is bad. Configure according to Table 3.

NC: No Connect. Unconnected pins. These pins provide

extra distance between high and low voltage pins.

ON: On Control Input. A rising edge turns on the external

N-channel FET and a falling edge turns it off. This pin is

also used to configure the state of the FET ON bit (and

hence the external FET) at power up. For example if the ON

pin is tied high, then the FET ON control bit (A3) will go high

100ms after power-up. Likewise if the ON pin is tied low

then the part will remain off after power-up until the FET

ON control bit is set high using the I

C bus. A high-to-low

transition on this pin will clear faults.

OV (GN/UH Packages): Overvoltage Comparator Input.

Connect this pin to an external resistive divider from V

If the voltage at this pin rises above 3.5V, an overvoltage

fault is detected and the switch turns off. Tie to GND if

unused.

SCL: Serial Bus Clock Input. Data at the SDA pin is shifted

in or out on rising edges of SCL. This is a high impedance

pin that is generally driven by an open-collector output

from a master controller. An external pull-up resistor or

current source is required.

SDAI: Serial Bus Data Input. A high impedance input used

for shifting in address, command or data bits. Normally

tied to SDAO to form the SDA line.

SDAO: Serial Bus Data Output. Open-drain output used for

sending data back to the master controller or acknowledg-

ing a write operation. Normally tied to SDAI to form the

SDA line. An external pull-up resistor or current source is

required.

SENSE: Current Sense Input. Connect this pin to the

output of the current sense resistor. The current limit

circuit controls the GATE pin to limit the sense voltage

between the V

and SENSE pins to 50mV or less depend-

ing on the voltage at the FB pin. This pin is used as an input

to the 8-bit ADC.

SOURCE: N-Channel MOSFET Source Connection and

ADC Input. Connect this pin to the source of the external

N-channel MOSFET switch. This pin also serves as the

ADC input to monitor output voltage. The pin provides a

return for the gate pull-down circuit and as a supply for the

charge pump circuit.

TIMER: Timer Input. Connect a capacitor between this

pin and ground to set a 12ms/µF duration for current limit

before the switch is turned off. The duration of the off

time is 518ms/µF when autoretry during current limit is

enabled. A minimum value of 0.1nF must be connected

to this pin.

UV: Undervoltage Comparator Input. Connect this pin to

an external resistive divider from V

. If the voltage at this

pin falls below 3.12V, an undervoltage fault is detected and

the switch turns off. Pulling this pin below 1.2V resets all

faults and allows the switch to turn back on. Tie to INTV

if unused.

: Supply Voltage and Current Sense Input. This pin has

an undervoltage lockout threshold of 7.45V.

INTV

: Internal Low Voltage Supply Decoupling Output.

Connect a 0.1µF capacitor from this pin to ground. This pin

can be used to drive the other pins to logic high and has an

undervoltage lockout threshold of 3.8V.

DDK

(UH Package): Same as V

. Connect this pin to

. V

DDK

tied to V

internally with 18Ω.

PI FU CTIO S

LTC4260

4260fa

FU CTIO AL DIAGRA

–

3.5V

UVS

OVS

RESET

ONS

UVLO

3.5V

1.235V

INTV

1.235V

7.45V

SOURCE

– SENSE

C ADDR

–

3.5V

–

PWRGD FET ON

–

RST

–

BOARD

PRESENT

–

1.235V

–

0.2V

LOGIC

TM2

UVLO2

–

UVLO1

GN/UH ONLY

BD_PRST

10µA

SDAI

SDAO

SCL

ALERT

ADR0 ADR1 ADR2 GND

UH ONLY

EXPOSED

PAD

ADIN

1 OF 27

3.8V

UVLO

4260 BD

INTV

TIMER

GPIO

INTV

100µA

1.8V

2µA

A/D CONVERTER

5.5V

GEN

TM1

SOURCE

GATE

–

DDK

18Ω

SENSE

UH ONLY

INTERNAL

POWER CHARGE

PUMP

AND

GATE

DRIVER

FOLDBACK

20mV TO

50mV

+–

LTC4260

4260fa

OPERATIO

The Functional Diagram displays the main functional areas

of this device. The LTC4260 is designed to turn a board’s

supply voltage on and off in a controlled manner, allowing

the board to be safely inserted or removed from a live

backplane. During normal operation, the charge pump and

gate driver turn on the external N-channel pass FET’s gate

to pass power to the load. The gate driver uses a charge

pump that derives its power from the SOURCE pin. When

the SOURCE pin is at ground, the charge pump is powered

from an internal 12V supply derived from V

. This results

in a 200µA current load on the SOURCE pin when the gate

is up. Also included in the gate driver is an internal 15V

gate-to-source clamp.

The current sense (CS) amplifier monitors the load current

using the difference between the V

and SENSE pin

voltage. The CS amplifier limits the current in the load by

reducing the GATE-to-SOURCE voltage in an active con-

trol loop. The CS amplifier requires 100µA input bias

current from both the V

and the SENSE pins.

A short circuit on the output to ground causes significant

power dissipation during active current limiting. To limit

this power, the foldback amplifier reduces the current limit

value from 50mV to 20mV (referred to the V

minus

SENSE voltage) in a linear manner as the FB pin drops

below 2V (see Typical Performance curves).

If an overcurrent condition persists, the TIMER pin ramps

up with a 100µA current source until the pin voltage

exceeds 1.2V (comparator TM2). This indicates to the

logic that it is time to turn off the pass FET to prevent

overheating. At this point the TIMER pin ramps down

using the 2µA current source until the voltage drops below

0.2V (comparator TM1) which tells the logic that the pass

transistor has cooled and it is safe to turn it on again.

The output voltage is monitored using the FB pin and the

PG comparator to determine if the power is available for

the load. The power good condition is signalled by the

GPIO pin using an open-drain pull-down transistor. The

GPIO pin can also be used as a general purpose input (GP

comparator) or output pin.

The Functional Diagram shows the monitoring blocks of

the LTC4260. The group of comparators on the left side

includes the UV, OV, RST, BP and ON comparators. These

comparators are used to determine if the external condi-

tions are valid prior to turning on the FET. But first the two

undervoltage lockout circuits UVLO1 and UVLO2 must

validate the input supply and the internally generated 5.5V

supply (INTV

) and generate the power up initialization to

the logic circuits.

Included in the LTC4260 is an 8-bit A/D converter. The

converter has a 3-input mux to select between the ADIN

pin, the SOURCE pin and the V

– SENSE voltage.

An I

C interface is provided to read the A/D registers. It

also allows the host to poll the device and determine if

faults have occurred. If the ALERT line is used as an

interrupt, the host can respond to a fault in real time. The

typical SDA line is divided into an SDAI (input) and SDAO

(output). This simplifies applications using an optoisolator

driven directly from the SDAO output. The I

C device

address is decoded using the ADR0, ADR1 and ADR2 pins.

These inputs have three states each that decode into a total

of 27 device addresses.

TI I G DIAGRA

UWW

tSU, DAT

tSU, STO

tSU, STA tBUF

tHD, STA

tSP

tHD, DATO,

tHD, DATI

tHD, STA

START

CONDITION

STOP

CONDITION

REPEATED START

CONDITION

START

CONDITION

4260 TD01

SDAI/SDAO

SCL

LTC4260

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The typical LTC4260 application is in a high availability

system that uses a positive voltage supply to distribute

power to individual cards. The device measures card

voltages and currents and records past and present fault

conditions. The system queries each LTC4260 over the I

periodically and reads the stored information.

The basic LTC4260 application circuit is shown in Fig-

ure 1. External component selection is discussed in detail

in the Design Example section.

Turn-On Sequence

The power supply on a board is controlled by placing an

external N-channel pass transistor (Q1) in the power path.

Note that sense resistor (R

) detects current and capacitor

C1 controls the GATE slew rate. Resistor R6 compensates

the current control loop while R5 prevents high frequency

oscillations in Q1. Resistors R1, R2 and R3 provide

undervoltage and overvoltage sensing.

Several conditions must be present before the external

switch can be turned on. First the external supply V

must exceed its undervoltage lockout level. Next the

internally generated supply INTV

must cross its 4.5V

undervoltage threshold. This generates a 60µs to 120µs

power-on-reset pulse. During reset the fault registers are

cleared and the control registers are set or cleared as

described in the register section.

After the power-on-reset pulse, the LTC4260 will go

through the following turn-on sequence. First, the UV and

OV pins must indicate that the input power is within the

acceptable range and the BD_PRST pin must be pulled

low. All of these conditions must be satisfied for duration

of 100ms to ensure that any contact bounce during

insertion has ended.

When these initial conditions are satisfied, the ON pin is

checked. If it is high, the external switch turns on. If it is low,

the external switch turns on when the ON pin is brought high

or if a serial bus turn-on command is received.

The switch is turned on by charging up the GATE with a

18µA current source (Figure 2). The voltage at the GATE

pin rises with a slope equal to 18µA/C1 and the supply

inrush current is set at:

INRUSH L

=µ

118•

When the GATE voltage reaches the FET threshold voltage,

the switch begins to turn on and the SOURCE voltage

follows the GATE voltage as it increases.

2.67k

1.74k

42 1 24 23

49.9k

Z1*

SMBT70A

VDD SENSE

LTC4260GN

100k

FDB3632

0.010Ω

VIN

48V

10Ω

6.8nF

330µF

43.5k

VOUT

48V

3.57k

100k

0.1µF

GATE

INTVCC ADR0 ADR1

ADR2 GND

BD_PRST

TIMER

ADIN

GPIO

4260 F01

SOURCE

SDAI

SDA0

SCL

ALERT

19 15

0.1µF

17 6

68nF

*DIODES, INC

BACKPLANE PLUG-IN

CARD

SDA

SCL

ALERT

GND

CONNECTOR 1

CONNECTOR 2

Figure 1. 5A, 48V Card Resident Application

LTC4260

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As the SOURCE voltage rises, so will the FB pin which is

monitoring it. If the voltage across the current sense

resistor R

gets too high, the inrush current will then be

limited by the internal current limit circuitry. Once the FB

pin crosses its 3.5V threshold, the GPIO pin, in its default

configuration, will cease to pull low and indicate that the

power is now good.

Turn-Off Sequence

The switch can be turned off by a variety of conditions. A

normal turn-off is initiated by the ON pin going low or a

serial bus turn-off command. Additionally, several fault

conditions will turn off the switch. These include an input

overvoltage (OV pin), input undervoltage (UV pin), over-

current circuit breaker (SENSE pin) or BD_PRST going

high. Writing a logic one into the UV, OV or overcurrent

fault bits will also turn off the switch if their autoretry bits

are set to false.

Normally the switch is turned off with a 1mA current

pulling down the GATE pin to ground. With the switch

turned off, the SOURCE voltage drops and when the FB pin

crosses below its threshold, GPIO pulls low to indicate

that the output power is no longer good.

If the V

pin falls below 7.5V for greater than 5µs or

INTV

drops below 3.8V for greater than 1µs, a fast

shutdown of the switch is initiated. The GATE pin is pulled

down with a 600mA current to the SOURCE pin.

Overcurrent Fault

The LTC4260 features an adjustable current limit with

foldback that protects against short circuits or excessive

load current. To protect against excessive power dissipa-

tion in the switch during active current limit, the available

current is reduced as a function of the output voltage

sensed by the FB pin. The device also features a variable

overcurrent response time. A graph in the Typical Perfor-

mance curves shows the delay from a voltage step at the

SENSE pin until the GATE voltage starts falling, as a

function of overdrive.

An overcurrent fault occurs when the current limit circuitry

has been engaged for longer than the time-out delay set by

the TIMER pin. Current limiting begins when the current

sense voltage between the V

and SENSE pins reaches

20mV to 50mV (depending on the foldback). The GATE pin

is then brought down with a 600mA GATE-to-SOURCE

current. The voltage on the GATE is regulated in order to

limit the current sense voltage to less than 50mV. At this

point, a circuit breaker time delay starts by charging the

external timing capacitor from the TIMER pin with a 100µA

pull-up current. If the TIMER pin reaches its 1.2V thresh-

old, the external switch turns off (with a 1mA current from

GATE to ground). The overcurrent present bit, C2, and the

overcurrent fault bit, D2, are set at this time.

The circuit breaker time delay is given by:

= C

• 12 [ms/µF]

After the switch is turned off, the TIMER pin begins

discharging the timing capacitor with a 2µA pull-down

current. When the TIMER pin reaches its 0.2V threshold,

the overcurrent present bit, C2, is cleared, and the switch

will be allowed to turn on again if the overcurrent fault has

been cleared. However, if the overcurrent autoretry bit,

A2, has been set then the switch turns on again automati-

cally (without resetting the overcurrent fault). Use a mini-

mum value of 0.1nF for C

The waveform in Figure 3 shows how the output latches off

following a short circuit. The drop across the sense

resistor is held at 20mV as the timer ramps up.

Figure 2. Supply Turn-On

+ 13V

4260 F02

GATE

OUT

SLOPE = 18µA/C1

LTC4260

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undervoltage autoretry has been disabled by clearing bit

A1. When power is applied to the device, if UV is below its

3.12V threshold after INTV

crosses its 4.5V undervolt-

age lockout threshold, an undervoltage fault will be logged

in the fault register.

Board Present Change of State

Whenever the BD_PRST pin toggles, bit D4 is set to

indicate a change of state. When the BD_PRST pin goes

high, indicating board removal, the switch turns off imme-

diately (with a 1mA current from GATE to ground) and

clears the board present bit, C4. If the BD_PRST pin is

pulled low, indicating a board insertion, all fault bits except

D4 will be cleared and the board present bit, C4, is set. If

the BD_PRST pin remains low for 100ms the state of the

ON pin will be captured in the FET On Control bit A3. This

turns the switch on if the ON pin is tied high. There is an

internal 10µA pull-up current source on the BD_PRST pin.

If the system shuts down due to a fault, it may be desirable

to restart the system simply by removing and reinserting

a load card. In cases where the LTC4260 and the switch

reside on a backplane or midplane and the load resides on

a plug-in card, the BD_PRST pin can be used to detect

when the plug-in card is removed (see Figure 4). Once the

plug-in card is reinserted the fault register is cleared

(except for D4). After 100ms the state of the ON pin is

latched into bit A3 of the control register. At this point the

system will start up again.

If a connection sense on the plug-in card is driving the

BD_PRST pin, the insertion or removal of the card may

cause the pin voltage to bounce. This will result in

clearing the fault register when the card is removed. The

pin can be debounced using a filter capacitor, C

BD_PRST

on the BD_PRST pin as shown in Figure 4. The filter time

is given by:

FILTER

= C

BD_PRST

• 123 [ms/µF]

FET Short Fault

A FET short fault will be reported if the data converter

measures a current sense voltage greater than or equal to

2mV while the FET is turned off. This condition sets the FET

short present bit, C5, and the FET short fault bit D5.

Figure 3. Short-Circuit Waveforms

During a short circuit, if the current limit sense voltage

exceeds 150mV, the active current limit enters a high

current protection mode that immediately turns off the

output transistor by pulling the GATE-to-SOURCE voltage

to zero. Current in the output transistor drops from tens of

amps to zero in a few hundred nanoseconds. The input

voltage will drop during the high current and then spike

upwards due to parasitic inductances when the FET shuts

off (see Supply Transients). Following this event, the part

may turn on again after a delay (typically the 100ms

normal turn-on delay if the input voltage drops below the

UVLO threshold) and enters active current limit before

shutting off.

Overvoltage Fault

An overvoltage fault occurs when the OV pin rises above

its 3.5V threshold. This shuts off the switch immediately

(with a 1mA current from GATE to ground) and sets the

overvoltage present bit, C0, and the overvoltage fault bit

D0. If the OV pin subsequently falls back below the

threshold for 100ms, the switch will be allowed to turn on

again unless the overvoltage autoretry has been disabled

by clearing bit A0.

Undervoltage Fault

An undervoltage fault occurs when the UV pin falls below

its 3.12V threshold. This turns off the switch immediately

(with a 1mA current from GATE to ground) and sets the

undervoltage present bit, C1, and the undervoltage fault bit

D1. If the UV pin subsequently rises above the threshold

for 100ms, the switch will turn on again unless the

VOUT

50V/DIV

IOUT

5A/DIV

∆VGATE

10V/DIV

TIMER

2V/DIV

100µs/DIV

4260 F03

LTC4260

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Power Bad Fault

A power bad fault will be reported if the FB pin drops below

its 3.41V threshold while the FET is on. This pulls the GPIO

pin low immediately, when configured as PWRGD, and

sets the power bad present bit, C3, and the power bad fault

bit D3. A circuit will prevent a power bad fault if the GATE-

to-SOURCE voltage is low, eliminating false power bad

faults during power-up or power-down. If the FB pin

subsequently rises back above the threshold, the GPIO pin

will return to a high impedance state and bit C3 will be

cleared.

Fault Alerts

When any of the fault bits in FAULT register D are set, an

optional I

C bus alert can be generated by setting the

appropriate bit in the ALERT register B. This allows only

selected faults to generate alerts. At power-up the default

state is to not alert on faults. If an alert is enabled, the

corresponding fault will cause the ALERT pin to pull low.

After the bus master controller broadcasts the Alert Re-

sponse Address, the LTC4260 responds with its address

on the SDA line and releases ALERT as shown in Figure 11.

If there is a collision between two LTC4260s responding

with their addresses simultaneously, then the device with

the lower address wins arbitration and responds first. The

ALERT line will also be released if the device is addressed

by the bus master.

Once the ALERT signal has been released for one fault, it

will not be pulled low again until the FAULT register

indicates a different fault has occurred or the original fault

is cleared and it occurs again. Note that this means

repeated or continuing faults will not generate alerts until

the associated FAULT register bit has been cleared.

Resetting Faults

Faults are reset with any of the following conditions. First,

a serial bus command writing zeros to the FAULT register

D will clear the associated faults. Second, the entire FAULT

the ON pin or bit A3 going from high to low, or if the UV pin

is brought below its 1.23V reset threshold, or if INTV

falls below its 3.8V undervoltage lockout threshold. Fi-

nally, when BD_PRST is brought from high to low, only

FAULT bits D0-D3 and D5 are cleared, the bit D4 that

indicates a BD_PRST change of state will be set. Faults that

are still present (as indicated in the STATUS Register C)

cannot be cleared.

The FAULT register will not be cleared when autoretrying.

When autoretry is disabled the existence of a D0, D1 or D2

fault keeps the switch off. As soon as the fault is cleared,

the switch will turn on. If autoretry is enabled, then a high

value in C0, C1 or C2 will hold the switch off and the FAULT

bits are cleared, the switch is allowed to turn on again

Data Converter

The LTC4260 incorporates an 8-bit data converter that

continuously monitors three different voltages. The

SOURCE pin uses a 1/40 resistive divider to monitor a full-

scale voltage of 102.4V with 0.4V resolution (divider

converts 102.4V to 2.56V). The ADIN pin is monitored with

a 2.56V full scale and 10mV resolution, and the voltage

between the V

and SENSE pins is monitored with a

76.8mV full scale and 300µV resolution.

The results from each conversion are stored in registers E,

F and G and are updated 10 times per second. Setting

CONTROL register bit A5 invokes a test mode that halts the

data converter updates so that registers E, F and G can be

written to and read from for software testing.

–

1.235V

GND

MOTHERBOARD CONNECTOR PLUG-IN

CARD

SOURCE

OUT

LTC4260

10µA

BD_PRST 14

BD_PRST

LOAD

4260 F04

Figure 4. Plug-In Card Insertion/Removal

LTC4260

4260fa

Gate Pin Voltage

A curve of gate drive vs VDD is shown in the Typical

Performance curves. At the minimum input supply volt-

age of 8.5V, the minimum gate drive voltage is 4.5V.

When the input supply voltage is higher than 20V, the gate

drive is at least 10V and a regular N-FET can be used. In

applications over a 8.5V to 20V range, a logic level N-FET

must be used to maintain adequate gate enhancement.

The GATE pin is clamped at a typical value of 15V above

the SOURCE pin.

Configuring the GPIO Pin

Table 3 describes the possible states of the GPIO pin using

the control register bits A6 and A7. At power-up, the

default state is for the GPIO pin to go high impedance when

power is good (FB pin greater than 3.5V). Other uses for

the GPIO pin are to pull down when power is good, a

general purpose output and a general purpose input.

Compensating the Active Current Loop

The active current limit circuit is compensated using the

resistor R6 and the slew rate capacitor C1. The value for C1

is calculated to limit the inrush current. The suggested

value for R6 is 100k. This value should work for most pass

FETs (Q1). If the gate capacitance of Q1 is very small then

the best method to compensate the loop is to add a ≈10nF

capacitor between the GATE and SOURCE terminals.The

addition of 10Ω resistor (R5) prevents self-oscillation in

Q1 by isolating trace capacitance from the FETs GATE

Terminal. Locate the gate resistor at, or close to, the body

of the MOSFET.

Supply Transients

The LTC4260 is designed to ride through supply transients

caused by load steps. If there is a shorted load and the

parasitic inductance back to the supply is greater than

0.5µH, there is a chance that the supply could collapse

before the active current limit circuit brings down the

GATE pin. In this case the undervoltage monitors turn off

the pass FET. The undervoltage lockout circuit has a 5µs

filter time after V

drops below 7.5V. The UV pin reacts

in 2µs to shut the GATE off, but it is recommended to add

a filter capacitor C

to prevent unwanted shutdown caused

by short transient. Eventually either the UV pin or the

undervoltage lockout responds to bring the current under

control before the supply completely collapses.

Supply Transient Protection

The LTC4260 is 100% tested and guaranteed to be safe

from damage with supply voltages up to 100V. However,

spikes above 100V may damage the part. During a short-

circuit condition, the large change in currents flowing

through the power supply traces can cause inductive

voltage spikes which could exceed 100V. To minimize the

spikes, the power trace inductance should be minimized

by using wider traces or heavier trace plating. Adding a

snubber circuit will dampen the voltage spikes. It is built

using a 100Ω resistor in series with a 0.1µF capacitor

between V

and GND. A surge suppressor, Z1 in Figure 1,

at the input will clamp the voltage spikes.

Design Example

As a design example, take the following specifications: V

= 48V, I

MAX

= 5A, I

INRUSH

= 1A, C

= 330µF, V

UVON

= 43V,

UVOFF

= 38.5V, V

OVOFF

= 70V, V

PWRGDUP

= 46V, V

PWRGDDN

= 45V and I

ADDRESS

= 1010011. The selection of the

sense resistor, R

, is set by the overcurrent threshold of

50mV:

RmV

SMAX

===Ω

50 50

50 010.

The FET should be sized to handle the power dissipation

during the inrush charging of the output capacitor C

OUT

The method used to determine the power is the principle:

= Energy in C

= Energy in Q1

Thus:

= 1/2 CV

= 1/2(0.33mF)(48V)

= 0.38J

Calculate the time it takes to charge up C

OUT

tCV

Ams

CHARGUP LIN

INRUSH

µ=

••330 48

116

The average power dissipated in the FET:

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LTC4260

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ms W

DISS C

CHARGUP

==≅

038

16 24

The SOA (safe operating area) curves of candidate FETs

must be evaluated to ensure that the heat capacity of the

package can stand 24W for 16ms. The SOA curves of the

Fairchild FDB3632 provide for 1A at 50V (50W) for 10ms,

satisfying the requirement.

The inrush current is set to 1A using C1:

ImF A

AnF

LGATE UP

INRUSH

1033

159==

µ=

() ..

Default values of R5 = 10Ω and R6 = 100k are chosen as

discussed previously.

The power dissipated in the FET during overcurrent must

be limited. The active current limit uses a timer to prevent

excessive energy dissipation in the FET. The worst-case

power occurs when the voltage versus current profile of

the foldback current limit is at the maximum. This occurs

when the current is 5A and the voltage is 1/2 of the 48V or

24V. See the Current Limit Sense Voltage vs FB Voltage in

the Typical Performance curves to view this profile. In

order to survive 120W, the FET SOA curve dictates the

maximum time at this power level. This particular FET

allows 300W at 1ms or less. Therefore, it is acceptable to

set the current limit timeout using C

to be 0.81ms:

Cms

ms F nF

T=µ

[]

081

12 68

Note the minimum value for C

is 0.1nF.

Choose R1, R2, R3, R7 and R8 for the UV, OV and PG

threshold voltages:

OVRISING

= 71.2V, V

OVFALLING

= 69.44V (using V

OV(TH)

3.5V rising and 3.41V falling)

UVRISING

= 43V, V

UVFALLING

= 38.5V, (using V

UV(TH)

3.5V rising and 3.12V falling)

PGRISING

= 46.14V, V

PGFALLING

= 45V, (using V

= 3.5V

rising and 3.411V falling)

In addition a 0.1µF ceramic bypass capacitor is placed on

the INTV

pin. The complete circuit is shown in Figure 1.

Layout Considerations

To achieve accurate current sensing, a Kelvin connection

is recommended. The minimum trace width for 1oz cop-

per foil is 0.02" per amp to make sure the trace stays at a

reasonable temperature. Using 0.03" per amp or wider is

recommended. Note that 1oz copper exhibits a sheet

resistance of about 530µΩ/. Small resistances add up

quickly in high current applications. To improve noise

immunity, put the resistive divider to the UV, OV and FB

pins close to the device and keep traces to V

and GND

short. It is also important to put C3, the bypass capacitor

for the INTV

pin, as close as possible between INTV

and GND. A 0.1µF capacitor from the UV pin (and OV pin

through resistor R2) to GND also helps reject supply

noise. Figure 5 shows a layout that addresses these

issues. Note that a surge suppressor, Z1, is placed be-

tween supply and ground using wide traces.

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SENSE

LTC4260

SENSE RESISTOR R

LOAD

GND I

LOAD

4260 F05

GND INTV

Figure 5. Recommended Layout for

R1, R2, R3, R8, CF, C3, Z1 and RS

LTC4260

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Digital Interface

The LTC4260 communicates with a bus master using a

2-wire interface compatible with the I

C bus and the

SMBus, an I

C extension for low power devices.

The LTC4260 is a read-write slave device and supports

SMBus bus Read Byte, Write Byte, Read Word and Write

Word commands. The second word in a Read Word

command will be identical to the first word. The second

word in a Write Word command is ignored. The data

formats for these commands are shown in Figures 6 to10.

Using Optoisolators with SDA

The LTC4260 separates the SDA line into SDAI and SDAO.

If optoisolators are not used then tie SDAI and SDAO

together to construct a normal SDA line. When using

optoisolators connect the SDAI to the output of the incom-

ing opto and connect the SDAO to the input of the out-

going opto (see Figure 13).

START and STOP Conditions

When the bus is idle, both SCL and SDA must be high

(Figure 6). A bus master signals the beginning of a

transmission with a START condition by transitioning SDA

from high to low while SCL is high. When the master has

finished communicating with the slave, it issues a STOP

condition by transitioning SDA from low to high while SCL

is high. The bus is then free for another transmission.

C Device Addressing

Twenty-seven distinct bus address are configurable using

the three-state ADR0-ADR2 pins. Table 1 shows the

correspondence between pin states and addresses. Note

that address bits B7 and B6 are internally configured to 10.

In addition, the LTC4260 will respond to two special

addresses. Address (1011 111)b is a mass write used to

write to all LTC4260, regardless of their individual address

settings. The mass write can be masked by setting register

bit A4 to zero. Address (0001 100)b is the SMBus Alert

Response Address. If the LTC4260 is pulling low on the

ALERT pin, it will acknowledge this address using the

SMBus Alert Response Protocol.

Acknowledge

The acknowledge signal is used for handshaking between

the transmitter and the receiver to indicate that the last byte

of data was received. The transmitter always releases the

SDA line during the acknowledge clock pulse. When the

slave is the receiver, it must pull down the SDA line so that

it remains LOW during this pulse to acknowledge receipt

of the data. If the slave fails to acknowledge by leaving SDA

HIGH, then the master can abort the transmission by

generating a STOP condition. When the master is receiving

data from the slave, the master must pull down the SDA

line during the clock pulse to indicate receipt of the data.

After the last byte has been received the master will leave

the SDA line HIGH (not acknowledge) and issue a STOP

condition to terminate the transmission.

Write Protocol

The master begins communication with a START condi-

tion followed by the seven bit slave address and the R/W

bit set to zero (Figure 7). The addressed LTC4260 acknowl-

edges this and then the master sends a command byte

which indicates which internal register the master wishes

to write. The LTC4260 acknowledges this and then latches

the lower three bits of the command byte into its internal

data byte and the LTC4260 acknowledges once more and

latches the data into its internal register. The transmission

is ended when the master sends a STOP condition. If the

master continues sending a second data byte, as in a Write

Word command, the second data byte will be acknowl-

edged by the LTC4260 but ignored (Figure 8).

Read Protocol

The master begins a read operation with a START condi-

tion followed by the seven bit slave address and the R/W

bit set to zero (Figure 9). The addressed LTC4260 acknowl-

edges this and then the master sends a command byte that

indicates which internal register the master wishes to read.

The LTC4260 acknowledges this and then latches the

lower three bits of the command byte into its internal

peated START condition followed by the same seven bit

LTC4260

4260fa

address with the R/W bit now set to one. The LTC4260

acknowledges and sends the contents of the requested

sends a STOP condition. If the master acknowledges the

transmitted data byte, as in a Read Word command

(Figure 12), the LTC4260 will repeat the requested register

as the second data byte.

Note that the Register Address pointer is not cleared at the

end of the transaction. Thus the Receive Byte protocol can

be used to repeatedly read a specific register.

Alert Response Protocol

The LTC4260 implements the SMBus Alert Response

Protocol as shown in Figure 11. If enabled to do so through

the ALERT register B, the LTC4260 will respond to faults

by pulling the ALERT pin low. Multiple LTC4260s can

share a common ALERT line and the protocol allows a

master to determine which LTC4260s are pulling the line

low. The master begins by sending a START bit followed

by the special Alert Response Address (0001 100)b with

the R/W bit set to one. Any LTC4260 that is pulling its

ALERT pin low will acknowledge and begin sending back

its individual slave address.

An arbitration scheme ensures that the LTC4260 with the

lowest address will have priority; all others will abort their

response. The successful responder will then release its

ALERT pin while any others will continue to hold their

ALERT pins low. Polling may also be used to search for any

LTC4260 that have detected faults. Any LTC4260 pulling

its ALERT pin low will also release it if it is individually

addressed during a read or write transaction.

The ALERT signal will not be pulled low again until the

FAULT register indicates a different fault has occurred or

the original fault is cleared and it occurs again. Note that

this means repeated or continuing faults will not generate

alerts until the associated FAULT register bit has been

cleared.

SCL

SDA

START

CONDITION

STOP

CONDITION

ADDRESS R/W ACK DATA ACK DATA ACK

1 - 7 8 9

4260 F06

a6 - a0 b7 - b0 b7 - b0

1 - 7 8 9 1 - 7 8 9

Figure 6. Data Transfer Over I2C or SMBus

APPLICATIO S I FOR ATIO

WUUU

LTC4260

4260fa

APPLICATIO S I FOR ATIO

WUUU

S ADDRESS

1 0 a4:a0

4260 F07

FROM MASTER TO SLAVE

FROM SLAVE TO MASTER

A: ACKNOWLEDGE (LOW)

A: NOT ACKNOWLEDGE (HIGH)

R: READ BIT (HIGH)

W: WRITE BIT (LOW)

S: START CONDITION

P: STOP CONDITION

COMMAND DATA

X X X X X b2:b00

000b7:b0

A A AP

S ADDRESS

1 0 a4:a0

COMMAND DATA DATA

X X X X X b2:b00

000 0

4260 F08

X X X X X X X Xb7:b0

AAAAP

S ADDRESS

1 0 a4:a0 1 0 a4:a0 1 0

COMMAND S ADDRESS R A

b7:b0 1

DATA

X X X X X b2:b00

4260 F09

AAAP

S ADDRESS

1 0 a4:a0 1 0 a4:a0 1 0

COMMAND S ADDRESS R A

b7:b0 1

DATA

X X X X X b2:b00

4260 F10

b7:b0

DATA

AAP

ALERT

RESPONSE

ADDRESS

0 0 0 1 1 0 0

DEVICE

ADDRESS

1 0 a4:a00 11

4260 F11

A A P

Figure 7. LTC4260 Serial Bus SDA Write Byte Protocol

Figure 8. LTC4260 Serial Bus SDA Write Word Protocol

Figure 9. LTC4260 Serial Bus SDA Read Byte Protocol

Figure 10. LTC4260 Serial Bus SDA Read Word Protocol

Figure 11. LTC4260 Serial Bus SDA Alert Response Protocol

LTC4260

4260fa

APPLICATIO S I FOR ATIO

WUUU

Table 1. LTC4260 I2C Device Addressing

HEX DEVICE LTC4260

DESCRIPTION ADDRESS BINARY DEVICE ADDRESS ADDRESS PINS

h 6 5 4 3 2 1 0 R/W ADR2 ADR1 ADR0

Mass Write BE 1 0 1 1 1 1 1 0 X X X

Alert Response 19 0 0 0 1 1 0 0 1 X X X

0 80 1 00 0 0 00 X L NC L

1 82 1 00 0 0 01 X L H NC

2 84 1 00 0 0 10 X L NC NC

3 86 1 00 0 0 11 X L NC H

4 88 1 00 0 1 00 X L L L

5 8A 1 00 0 1 01 X L H H

6 8C 1 00 0 1 10 X L L NC

7 8E 1 00 0 1 11 X L L H

8 90 1 00 1 0 00 X NC NC L

9 92 1 00 1 0 01 X NC H NC

10 94 1 0 0 1 0 1 0 X NC NC NC

11 96 1 0 0 1 0 1 1 X NC NC H

12 98 1 0 0 1 1 0 0 X NC L L

13 9A 1001101X NC H H

14 9C 1001110X NC L NC

15 9E 1 0 0 1 1 1 1 X NC L H

16 A0 1010000X H NC L

17 A2 1010001X H H NC

18 A4 1010010X H NC NC

19 A6 1010011X H NC H

20 A8 1010100X H L L

21 AA 1010101X H H H

22 AC 1010110X H L NC

23 AE 1010111X H L H

24 B0 1011000X L H L

25 B2 1011001X NC H L

26 B4 1011010X H H L

LTC4260

4260fa

APPLICATIO S I FOR ATIO

WUUU

Table 2. LTC4260 Register Addresses and Contents

ADDRESS* NAME READ/WRITE DESCRIPTION

00h CONTROL (A) R/W Controls Whether the Part Retries After Faults, Set the Switch State

01h ALERT (B) R/W Controls Whether the ALERT Pin is Pulled Low After a Fault is Logged in the Fault Register

02h STATUS (C) R System Status Information

03h FAULT (D) R/W Fault Log

04h SENSE (E) R/W** ADC Current Sense Voltage Data

05h SOURCE (F) R/W** ADC SOURCE Voltage Data

06h, 07h ADIN (G) R/W** ADC ADIN Voltage Data

*Register address MSBs b7-b3 are ignored.

**Writable if bit A5 set.

Table 3. CONTROL Register A (00h)—Read/Write

BIT NAME OPERATION

A7:6 GPIO Configure Configures Behavior of GPIO Pin

A5 Test Mode Enable Test Mode Halts ADC Operation and Enables Writes to ADC Registers

1 = Enable Test Mode, 0 = Disable Test Mode (Default)

A4 Mass Write Enable Enables Mass Write Using Address (1011 111)b

1 = Enable Mass Write (Default), 0 = Disable Mass Write

A3 FET On Control Turns FET On and Off

1 = Turn FET On, 0 = Turn FET Off. Defaults to ON Pin State at End of Debounce Delay

A2 Overcurrent Autoretry Enables Autoretry After an Overcurrent Fault

1 = Retry Enabled, 0 = Retry Disabled (Default)

A1 Undervoltage Autoretry Enables Autoretry After an Undervoltage Fault

1 = Retry Enabled (Default), 0 = Retry Disabled

A0 Overvoltage Autoretry Enables Autoretry After an Overvoltage Fault

1 = Retry Enabled (Default), 0 = Retry Disabled

FUNCTION A6 A7 GPIO PIN

Power Good (Default) 0 0 GPIO = C3

Power Bad 0 1 GPIO = C3

General Purpose Output 1 0 GPIO = B6

General Purpose Input 1 1

GPIO = Hi-Z

LTC4260

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APPLICATIO S I FOR ATIO

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Table 4. ALERT Register B (01h)—Read/Write

BIT NAME OPERATION

B7 Reserved Not Used

B6 GPIO Output Output Data Bit to GPIO Pin When Configured as Output. Defaults to 0

B5 FET Short Alert Enables Alert for FET Short Condition