Freescale Semiconductor Technical Data Document Number: MC56F8006 Rev. 4, 06/2011 MC56F8006/MC56F8002 48-pin LQFP Case: 932-03 7 x 7 mm2 MC56F8006/MC56F8002 Digital Signal Controller This document applies to parts marked with 2M53M. The 56F8006/56F8002 is a member of the 56800E core-based family of digital signal controllers (DSCs). It combines, on a single chip, the processing power of a DSP and the functionality of a microcontroller with a flexible set of peripherals to create a cost-effective solution. Because of its low cost, configuration flexibility, and compact program code, the 56F8006/56F8002 is well-suited for many applications. It includes many peripherals that are especially useful for cost-sensitive applications, including: * Industrial control * Home appliances * Smart sensors * Fire and security systems * Switched-mode power supply and power management * Power metering * Motor control (ACIM, BLDC, PMSM, SR, and stepper) * Handheld power tools * Arc detection * Medical device/equipment * Instrumentation * Lighting ballast The 56800E core is based on a dual Harvard-style architecture consisting of three execution units operating in parallel, allowing as many as six operations per instruction cycle. The MCU-style programming model and optimized instruction set allow straightforward generation of efficient, compact DSP and control code. The instruction set is also highly efficient for C compilers to enable rapid development of optimized control applications. The 56F8006/56F8002 supports program execution from internal memories. Two data operands can be accessed from the on-chip data RAM per instruction cycle. The 56F8006/56F8002 also offers up to 40 general-purpose input/output (GPIO) lines, depending on peripheral configuration. The 56F8006/56F8002 digital signal controller includes up to 16 KB of program flash and 2 KB of unified data/program 28-pin SOIC Case: 751F-05 7.5 x 18 mm2 32-pin LQFP Case: 873A-03 7 x 7 mm2 32-pin PSDIP Case: 1376-02 9 x 28.5 mm2 RAM. Program flash memory can be independently bulk erased or erased in small pages of 512 bytes (256 words). On-chip features include: * Up to 32 MIPS at 32 MHz core frequency * DSP and MCU functionality in a unified, C-efficient architecture * On-chip memory - 56F8006: 16 KB (8K x 16) flash memory - 56F8002: 12 KB (6K x 16) flash memory - 2 KB (1K x 16) unified data/program RAM * One 6-channel PWM module * Two 28-channel, 12-bit analog-to-digital converters (ADCs) * Two programmable gain amplifiers (PGA) with gain up to 32x * Three analog comparators * One programmable interval timer (PIT) * One high-speed serial communication interface (SCI) with LIN slave functionality * One serial peripheral interface (SPI) * One 16-bit dual timer (2 x 16 bit timers) * One programmable delay block (PDB) * One SMBus compatible inter-integrated circuit (I2C) port * One real time counter (RTC) * Computer operating properly (COP)/watchdog * Two on-chip relaxation oscillators -- 1 kHz and 8 MHz (400 kHz at standby mode) * Crystal oscillator * Integrated power-on reset (POR) and low-voltage interrupt (LVI) module * JTAG/enhanced on-chip emulation (OnCETM) for unobtrusive, real-time debugging * Up to 40 GPIO lines * 28-pin SOIC, 32-pin LQFP, 32-pin PSDIP, and 48-pin LQFP packages Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. (c) Freescale Semiconductor, Inc., 2009-2011. All rights reserved. Table of Contents 1 2 3 4 5 6 7 8 MC56F8006/MC56F8002 Family Configuration . . . . . . . . . . . .3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 3.1 56F8006/56F8002 Features . . . . . . . . . . . . . . . . . . . . . .4 3.2 Award-Winning Development Environment. . . . . . . . . . .8 3.3 Architecture Block Diagram. . . . . . . . . . . . . . . . . . . . . . .9 3.4 Product Documentation . . . . . . . . . . . . . . . . . . . . . . . .11 Signal/Connection Descriptions . . . . . . . . . . . . . . . . . . . . . . .11 4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 4.2 Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 4.3 56F8006/56F8002 Signal Pins . . . . . . . . . . . . . . . . . . .17 Memory Maps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 5.2 Program Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 5.3 Data Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 5.4 Interrupt Vector Table and Reset Vector . . . . . . . . . . . .31 5.5 Peripheral Memory-Mapped Registers . . . . . . . . . . . . .32 5.6 EOnCE Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . .33 General System Control Information . . . . . . . . . . . . . . . . . . .34 6.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 6.2 Power Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 6.3 Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 6.4 On-chip Clock Synthesis . . . . . . . . . . . . . . . . . . . . . . . .34 6.5 Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 6.6 System Integration Module (SIM) . . . . . . . . . . . . . . . . .37 6.7 PWM, PDB, PGA, and ADC Connections. . . . . . . . . . .38 6.8 Joint Test Action Group (JTAG)/Enhanced On-Chip Emulator (EOnCE) . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 Security Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 7.1 Operation with Security Enabled. . . . . . . . . . . . . . . . . .40 7.2 Flash Access Lock and Unlock Mechanisms . . . . . . . .40 7.3 Product Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 8.1 General Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 8.2 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . 8.3 Thermal Characteristics. . . . . . . . . . . . . . . . . . . . . . . . 8.4 Recommended Operating Conditions . . . . . . . . . . . . . 8.5 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . 8.6 Supply Current Characteristics . . . . . . . . . . . . . . . . . . 8.7 Flash Memory Characteristics . . . . . . . . . . . . . . . . . . . 8.8 External Clock Operation Timing. . . . . . . . . . . . . . . . . 8.9 Phase Locked Loop Timing . . . . . . . . . . . . . . . . . . . . . 8.10 Relaxation Oscillator Timing . . . . . . . . . . . . . . . . . . . . 8.11 Reset, Stop, Wait, Mode Select, and Interrupt Timing. 8.12 External Oscillator (XOSC) Characteristics . . . . . . . . . 8.13 AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . 8.14 COP Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.15 PGA Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.16 ADC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.17 HSCMP Specifications . . . . . . . . . . . . . . . . . . . . . . . . 8.18 Optimize Power Consumption . . . . . . . . . . . . . . . . . . . 9 Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.1 Thermal Design Considerations . . . . . . . . . . . . . . . . . 9.2 Electrical Design Considerations. . . . . . . . . . . . . . . . . 9.3 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Package Mechanical Outline Drawings . . . . . . . . . . . . . . . . . 10.1 28-pin SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . 10.2 32-pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.3 48-pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.4 32-Pin PSDIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Appendix A Interrupt Vector Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Appendix B Peripheral Register Memory Map and Reset Value . . . . . . . 41 42 43 45 46 51 53 53 54 54 56 56 57 65 65 66 68 68 70 70 71 72 73 73 76 79 81 83 83 86 MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 2 Freescale Semiconductor MC56F8006/MC56F8002 Family Configuration 1 MC56F8006/MC56F8002 Family Configuration MC56F8006/MC56F8002 device comparison in Table 1. Table 1. MC56F8006 Series Device Comparison MC56F8006 MC56F8002 Feature 28-pin Flash memory size (Kbytes) 32-pin 48-pin 16 12 RAM size (Kbytes) 2 Analog comparators (ACMP) 3 Analog-to-digital converters (ADC) 2 Unshielded ADC inputs Shielded ADC inputs Total number of ADC input pins1 6 7 7 6 9 11 17 9 15 18 24 15 4 3 Programmable gain amplifiers (PGA) 2 Pulse-width modulator (PWM) outputs 6 PWM fault inputs 3 4 Inter-integrated circuit (IIC) 1 Serial peripheral interface (SPI) 1 High speed serial communications interface (SCI) 1 Programmable interrupt timer (PIT) 1 Programmable delay block (PDB) 1 16-bit multi-purpose timers (TMR) 2 Real-time counter (RTC) 1 Computer operating properly (COP) timer Yes Phase-locked loop (PLL) Yes 1 kHz on-chip oscillator Yes 8 MHz (400 kHz at standby mode) on-chip ROSC Yes Crystal oscillator Yes Power management controller (PMC) Yes IEEE 1149.1 Joint Test Action Group (JTAG) interface Yes Enhanced on-chip emulator (EOnCE) IEEE 1149.1 Joint Test Action Group (JTAG) interface Yes 1 28-pin Some ADC inputs share the same pin. See Table 4. MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 Freescale Semiconductor 3 Block Diagram 2 Block Diagram Figure 1 shows a top-level block diagram of the MC56F8006/MC56F8002 digital signal controller. Package options for this family are described later in this document. Italics indicate a 56F8002 device parameter. RESET 4 PWM 6 JTAG/EOnCE Port or GPIOD PWM Outputs Program Controller and Hardware Looping Unit programmable delay block 24 Total VSS 3 Digital Reg ADCA PGA/ADC R/W Control 2 Note: All pins are muxed with other peripheral pins. Flash Memory 16 Kbytes flash 12 Kbytes flash 4 PAB PDB CDBR CDBW Unified Data / Program RAM 2KB CMP2 40 XDB2 XAB1 XAB2 Memory CMP0 CMP or GPIOD CMP1 2 Analog Reg Low-Voltage Supervisor PAB PDB CDBR CDBW ADCB 2 VDDA VSSA PMC 16-Bit 56800E Core Data ALU 16 x 16 + 36 36-Bit MAC Address Bit Three 16-bit Input Registers Generation Unit Manipulation Four 36-bit Accumulators Unit Fault Inputs 3 VDD 3 GPIO are muxed with all other func pins. System Bus Control PIT IPBus Bridge Power Management Controller Dual GP Timer SPI 4 SCI I2C 2 2 COP/ Watchdog Interrupt Controller System Integration Module RTC Clock ROSC Generator* OSC 2 Crystal Oscillator Figure 1. MC56F8006/MC56F8002 Block Diagram 3 Overview 3.1 56F8006/56F8002 Features 3.1.1 * * * * * * Core Efficient 16-bit 56800E family digital signal controller (DSC) engine with dual Harvard architecture As many as 32 million instructions per second (MIPS) at 32 MHz core frequency 155 basic instructions in conjunction with up to 20 address modes Single-cycle 16 16-bit parallel multiplier-accumulator (MAC) Four 36-bit accumulators, including extension bits 32-bit arithmetic and logic multi-bit shifter MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 4 Freescale Semiconductor Overview * * * * * * * * * 3.1.2 * * * 3.1.3 * * * * 3.1.4 * * * * * * 3.1.5 * Parallel instruction set with unique DSP addressing modes Hardware DO and REP loops Three internal address buses Four internal data buses Instruction set supports DSP and controller functions Controller-style addressing modes and instructions for compact code Efficient C compiler and local variable support Software subroutine and interrupt stack with depth limited only by memory JTAG/enhanced on-chip emulation (EOnCE) for unobtrusive, processor speed-independent, real-time debugging Operation Range 1.8 V to 3.6 V operation (power supplies and I/O) From power-on-reset: approximately 1.9 V to 3.6 V Ambient temperature operating range: -- -40 C to 125 C Memory Dual Harvard architecture permits as many as three simultaneous accesses to program and data memory Flash security and protection that prevent unauthorized users from gaining access to the internal flash On-chip memory -- 16 KB of program flash for 56F8006 and 12 KB of program flash for 56F8002 -- 2 KB of unified data/program RAM EEPROM emulation capability using flash Interrupt Controller Five interrupt priority levels -- Three user programmable priority levels for each interrupt source: Level 0, 1, 2 -- Unmaskable level 3 interrupts include: illegal instruction, hardware stack overflow, misaligned data access, SWI3 instruction. Maskable level 3 interrupts include: EOnCE step counter, EOnCE breakpoint unit, EOnCE trace buffer -- Lowest-priority software interrupt: level LP Allow nested interrupt that higher priority level interrupt request can interrupt lower priority interrupt subroutine The masking of interrupt priority level is managed by the 56800E core One programmable fast interrupt that can be assigned to any interrupt source Notification to system integration module (SIM) to restart clock out of wait and stop states Ability to relocate interrupt vector table Peripheral Highlights One multi-function, six-output pulse width modulator (PWM) module -- Up to 96 MHz PWM operating clock -- 15 bits of resolution -- Center-aligned and edge-aligned PWM signal mode -- Phase shifting PWM pulse generation MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 Freescale Semiconductor 5 Overview -- -- -- -- -- -- -- * * * * * Four programmable fault inputs with programmable digital filter Double-buffered PWM registers Separate deadtime insertions for rising and falling edges Separate top and bottom pulse-width correction by means of software Asymmetric PWM output within both Center Aligned and Edge Aligned operation Separate top and bottom polarity control Each complementary PWM signal pair allows selection of a PWM supply source from: - PWM generator - Internal timers - Analog comparator outputs Two independent 12-bit analog-to-digital converters (ADCs) -- 2 x 14 channel external inputs plus seven internal inputs -- Support simultaneous and software triggering conversions -- ADC conversions can be synchronized by PWM and PDB modules -- Sampling rate up to 400 KSPS for 10- or 12-bit conversion result; 470 KSPS for 8-bit conversion result -- Two 16-word result registers Two programmable gain amplifier (PGAs) -- Each PGA is designed to amplify and convert differential signals to a single-ended value fed to one of the ADC inputs -- 1X, 2X, 4X, 8X, 16X, or 32X gain -- Software and hardware triggers are available -- Integrated sample/hold circuit -- Includes additional calibration features: - Offset calibration eliminates any errors in the internal reference used to generate the VDDA/2 output center point - Gain calibration can be used to verify the gain of the overall datapath - Both features require software correction of the ADC result Three analog comparators (CMPs) -- Selectable input source includes external pins, internal DACs -- Programmable output polarity -- Output can drive timer input, PWM fault input, PWM source, external pin output, and trigger ADCs -- Output falling and rising edge detection able to generate interrupts One dual channel 16-bit multi-purpose timer module (TMR) -- Two independent 16-bit counter/timers with cascading capability -- Up to 96 MHz operating clock -- Each timer has capture and compare and quadrature decoder capability -- Up to 12 operating modes -- Four external inputs and two external outputs One serial communication interface (SCI) with LIN slave functionality -- Up to 96 MHz operating clock -- Full-duplex or single-wire operation -- Programmable 8- or 9- bit data format -- Two receiver wakeup methods: - Idle line - Address mark MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 6 Freescale Semiconductor Overview * * * * * * * -- 1/16 bit-time noise detection One serial peripheral interface (SPI) -- Full-duplex operation -- Master and slave modes -- Programmable length transactions (2 to 16 bits) -- Programmable transmit and receive shift order (MSB as first or last bit transmitted) -- Maximum slave module frequency = module clock frequency/2 One inter-integrated Circuit (I2C) port -- Operates up to 400 kbps -- Supports master and slave operation -- Supports 10-bit address mode and broadcasting mode -- Supports SMBus, Version 2 One 16-bit programmable interval timer (PIT) -- 16 bit counter with programmable counter modulo -- Interrupt capability One 16-bit programmable delay block (PDB) -- 16 bit counter with programmable counter modulo and delay time -- Counter is initiated by positive transition of internal or external trigger pulse -- Supports two independently controlled delay pulses used to synchronize PGA and ADC conversions with input trigger event -- Two PDB outputs can be ORed together to schedule two conversions from one input trigger event -- PDB outputs can be can be used to schedule precise edge placement for a pulsed output that generates the control signal for the CMP windowing comparison -- Supports continuous or single shot mode -- Bypass mode supported Computer operating properly (COP)/watchdog timer capable of selecting different clock sources -- Programmable prescaler and timeout period -- Programmable wait, stop, and partial powerdown mode operation -- Causes loss of reference reset 128 cycles after loss of reference clock to the PLL is detected -- Choice of clock sources from four sources in support of EN60730 and IEC61508: - On-chip relaxation oscillator - External crystal oscillator/external clock source - System clock (IPBus up to 32 MHz) - On-chip low power 1 kHz oscillator Real-timer counter (RTC) -- 8-bit up-counter -- Three software selectable clock sources - External crystal oscillator/external clock source - On-chip low-power 1 kHz oscillator - System bus (IPBus up to 32 MHz) -- Can signal the device to exit power down mode Phase lock loop (PLL) provides a high-speed clock to the core and peripherals -- Provides 3x system clock to PWM and dual timer and SCI -- Loss of lock interrupt -- Loss of reference clock interrupt MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 Freescale Semiconductor 7 Overview * * * * 3.1.6 * * * * * 3.2 Clock sources -- On-chip relaxation oscillator with two user selectable frequencies: 400 kHz for low speed mode, 8 MHz for normal operation -- On-chip low-power 1 kHz oscillator can be selected as clock source to the RTC and/or COP -- External clock: crystal oscillator, ceramic resonator, and external clock source Power management controller (PMC) -- On-chip regulator for digital and analog circuitry to lower cost and reduce noise -- Integrated power-on reset (POR) -- Low-voltage interrupt with a user selectable trip voltage of 1.81 V or 2.31 V -- User selectable brown-out reset -- Run, wait, and stop modes -- Low-power run, wait, and stop modes -- Partial power down mode Up to 40 general-purpose I/O (GPIO) pins -- Individual control for each pin to be in peripheral or GPIO mode -- Individual input/output direction control for each pin in GPIO mode -- Hysteresis and configurable pullup device on all input pins -- Configurable slew rate and drive strength and optional input low pass filters on all output pins -- 20 mA sink/source current JTAG/EOnCE debug programming interface for real-time debugging -- IEEE 1149.1 Joint Test Action Group (JTAG) interface -- EOnCE interface for real-time debugging Power Saving Features Three low power modes -- Low-speed run, wait, and stop modes: 200 kHz IP bus clock provided by ROSC -- Low-power run, wait, and stop modes: clock provided by external 32-38.4 kHz crystal -- Partial power down mode Low power external oscillator can be used in any low-power mode to provide accurate clock to active peripherals Low power real time counter for use in run, wait, and stop modes with internal and external clock sources 32 s typical wakeup time from partial power down modes Each peripheral can be individually disabled to save power Award-Winning Development Environment Processor ExpertTM (PE) provides a Rapid Application Design (RAD) tool that combines easy-to-use component-based software application creation with an expert knowledge system. The CodeWarrior Integrated Development Environment is a sophisticated tool for code navigation, compiling, and debugging. A complete set of evaluation modules (EVMs), demonstration board kit, and development system cards support concurrent engineering. Together, PE, CodeWarrior, and EVMs create a complete, scalable tools solution for easy, fast, and efficient development. A full set of programmable peripherals -- PWM, PGAs, ADCs, SCI, SPI, I2C, PIT, timers, and analog comparators -- supports various applications. Each peripheral can be independently shut down to save power. Any pin in these peripherals can also be used as general-purpose input/outputs (GPIOs). MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 8 Freescale Semiconductor Overview 3.3 Architecture Block Diagram The 56F8006/56F8002's architecture is shown in Figure 2 and Figure 3. Figure 2 illustrates how the 56800E system buses communicate with internal memories and the IPBus interface and the internal connections among each unit of the 56800E core. Figure 3 shows the peripherals and control blocks connected to the IPBus bridge. Please see the system integration module (SIM) section in the MC56F8006 Reference Manual for information about which signals are multiplexed with those of other peripherals. DSP56800E Core Program Control Unit PC LA LA2 HWS0 HWS1 FIRA OMR SR LC LC2 FISR Address Generation Unit (AGU) Instruction Decoder Interrupt Unit ALU1 ALU2 R0 R1 R2 R3 R4 R5 N SP M01 N3 Looping Unit Program Memory XAB1 XAB2 PAB PDB Data/ Program RAM CDBW CDBR XDB2 A2 B2 C2 D2 BitManipulation Unit Enhanced OnCETM JTAG TAP Y A1 B1 C1 D1 Y1 Y0 X0 MAC and ALU A0 B0 C0 D0 IPBus Interface Data Arithmetic Logic Unit (ALU) Multi-Bit Shifter Figure 2. 56800E Core Block Diagram MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 Freescale Semiconductor 9 Overview IPBus Bridge Port A Port B OCCS GPIOB7 GPIOB6 GPIOB5 GPIOB4 GPIOB3 GPIOB2 GPIOB1 GPIOB0 Port C Crystal COSC ROSC GPIOC7 GPIOC6 GPIOC5 GPIOC4 GPIOC3 GPIOC2 GPIOC1 GPIOC0 Port D COP Second Clcok source System Clock GPIOA7 GPIOA6 GPIOA5 GPIOA4 GPIOA3 GPIOA2 GPIOA1 GPIOA0 GPIOD3 GPIOD2 GPIOD1 GPIOD0 Port E RTC GPIOE7 GPIOE6 GPIOE5 GPIOE4 GPIOE3 GPIOE2 GPIOE1 GPIOE0 RESTE SIM PMC 1KHz INTC SPI SCI Dual Timer (TMR) PWM PWM Synch PWM Input Mux CMP0 GPIO MUX I2C CMP1 CMP2 PDB Trigger A PreTrigger A ANA15 PGA0 Trigger B ADCB PreTrigger B ANB15 Port F ADCA GPIOF3 GPIOF2 GPIOF1 GPIOF0 PGA1 Figure 3. Peripheral Subsystem MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 10 Freescale Semiconductor Signal/Connection Descriptions 3.4 Product Documentation The documents listed in Table 2 are required for a complete description and proper design with the 56F8006/56F8002. Documentation is available from local Freescale distributors, Freescale Semiconductor sales offices, Freescale Literature Distribution Centers, or online at http://www.freescale.com. Table 2. 56F8006/56F8002 Device Documentation Topic Description Order Number DSP56800E Reference Manual Detailed description of the 56800E family architecture, 16-bit digital signal controller core processor, and the instruction set DSP56800ERM 56F800x Peripheral Reference Manual Detailed description of peripherals of the 56F8006 and 56F8002 devices MC56F8006RM 56F80x Serial Bootloader Detailed description of the Serial Bootloader in the User Guide 56F800x family of devices 56F8006/56F8002 Technical Data Sheet TBD Electrical and timing specifications, pin descriptions, and package descriptions (this document) 56F8006/56F8002 Errata Details any chip issues that might be present 4 Signal/Connection Descriptions 4.1 Introduction MC56F8006 MC56F8006E The input and output signals of the 56F8006/56F8002 are organized into functional groups, as detailed in Table 3. Table 4 summarizes all device pins. In Table 4, each table row describes the signal or signals present on a pin, sorted by pin number. Table 3. Functional Group Pin Allocations Number of Pins Number of Pins Number of Pins Number of Pins in 28 SOIC in 32 LQFP in 32 PSDIP in 48 LQFP Functional Group Power Inputs (VDD, VDDA) 2 2 2 4 Ground (VSS, VSSA) 3 3 3 4 1 1 1 1 Pulse Width Modulator (PWM) Ports 10 12 12 12 Serial Peripheral Interface (SPI) Ports1 5 7 7 7 4 5 5 5 6 7 7 7 Analog-to-Digital Converter (ADC) Inputs 16 18 18 24 High Speed Analog Comparator Inputs1 13 15 15 25 4 4 4 4 8 10 10 10 -- -- -- 1 5 5 5 5 4 4 4 4 1 Reset 1 1 Serial Communications Interface 0 (SCI) Ports 2C) Ports1 Inter-Integrated Circuit Interface (I 1 1 Programmable Gain Amplifiers (PGA) 1 Dual Timer Module (TMR) Ports Programmable Delay Block (PDB) 1 Clock1 1 JTAG/Enhanced On-Chip Emulation (EOnCE ) 1 Pins may be shared with other peripherals. See Table 4. MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 Freescale Semiconductor 11 Signal/Connection Descriptions In Table 4, peripheral pins in bold identify reset state. Table 4. 56F8006/56F8002 Pins Pin Number Peripherals 28 32 32 48 SOIC LQFP PSDIP LQFP Pin Name GPIO I2C SCI RXD SPI ADC PGA COMP ANA131 CMP0_P2 ANA121 CMP2_P3 ANA111 CMP2_M3 26 1 29 1 GPIOB6/RXD/SDA/ANA13 and CMP0_P2/CLKIN B6 SDA 27 2 30 2 GPIOB1/SS/SDA/ANA12 andCMP2_P3 B1 SDA 3 31 3 GPIOB7/TXD/SCL/ANA11 and CMP2_M3 B7 SCL 4 32 4 GPIOB5/T1/FAULT3/SCLK B5 5 GPIOE0 E0 6 GPIOE1/ANB9 and CMP0_P1 E1 ANB91 7 ANB8 and PGA1+ and CMP0_M2/GPIOC4 C4 ANB81 PGA1+ CMP0_M2 8 GPIOE2/ANB7 and CMP0_M1 E2 ANB71 CMP0_M1 9 ANB6 and PGA1- and CMP0_P4/GPIOC5 C5 ANB61 PGA1- CMP0_P4 10 GPIOC7/ANB5 and CMP1_M2 C7 ANB51 CMP1_M2 11 ANB4 and CMP1_P1/GPIOC6/PWM2 C6 ANB41 CMP1_P1 28 1 2 5 6 7 1 2 3 SS TXD SCLK 8 4 12 VDDA 9 5 13 VSSA 14 GPIOE3/ANA10 and CMP2_M1 E3 ANA101 CMP2_M1 15 ANA9 and PGA0- and CMP2_P4/GPIOC2 C2 ANA91 PGA0- CMP2_P4 16 GPIOE5/ANA8 and CMP2_P1 E5 ANA81 CMP2_P1 17 ANA7 and PGA0+ and CMP2_M2/GPIOC1 C1 ANA71 PGA0+ CMP2_M2 18 GPIOE4/ANA6 and CMP2_P2 E4 ANA61 CMP2_P2 ANA5 and CMP1_M1/GPIOC0/FAULT0 C0 ANA51 CMP1_M1 6 11 6 7 Power and JTAG Ground FAULT3 PWM2 VDDA VSSA 7 12 8 19 8 13 9 20 VSS VSS 21 VDD VDD 9 14 10 22 TCK/GPIOD2/ANA4 and CMP1_P2/CMP2_OUT D2 10 15 11 23 RESET/GPIOA7 A7 11 Misc. CMP0_P1 3 10 PWM CLKIN T1 4 5 Dual Timer ANA41 FAULT0 CMP1_P2, CMP2_OUT TCK RESET 1 16 12 24 GPIOB3/MOSI/TIN3/ANA3 and ANB3/PWM5/CMP1_OUT B3 MOSI ANA3 and ANB31 CMP1_OUT TIN3 17 13 25 GPIOB2/MISO/TIN2/ANA2 and ANB2/CMP0_OUT B2 MISO ANA2 and ANB2 CMP0_OUT TIN2 12 18 14 26 GPIOA6/FAULT0/ANA1 and ANB1/SCL/TXD/CLKO_1 A6 SCL TXD 13 19 15 27 GPIOB4/T0/CLKO_0/MISO/ SDA/RXD/ANA0 and ANB0 B4 SDA RXD ANA1 and ANB1 MISO ANA0 and ANB0 PWM5 FAULT0 T0 CLKO_1 CLKO_0 MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 12 Freescale Semiconductor Signal/Connection Descriptions Table 4. 56F8006/56F8002 Pins (continued) Pin Number Peripherals Pin Name 28 32 32 48 SOIC LQFP PSDIP LQFP 14 16 28 GPIOE6 E6 29 GPIOA5/PWM5/FAULT2 or EXT_SYNC/TIN3 A5 I2C SCI SPI ADC PGA COMP Dual Timer TIN3 PWM Power and JTAG Ground VSS VSS 31 VDD VDD 21 17 32 GPIOB0/SCLK/SCL/ANB13/ PWM3/T1 B0 SCL 16 22 18 33 GPIOA4/PWM4/SDA/FAULT1 /TIN2 A4 SDA 34 GPIOE7/CMP1_M3 E7 23 19 35 GPIOA2/PWM2 A2 SCLK ANB13 T1 PWM3 TIN2 PWM4, FAULT1 CMP1_M3 PWM2 17 24 20 36 GPIOA3/PWM3/TXD/EXTAL A3 18 25 21 37 GPIOF0/XTAL F0 19 26 22 38 VDD VDD 20 27 23 39 VSS VSS 28 24 TXD PWM3 GPIOF1/CMP1_P3 F1 CMP1_P3 41 GPIOF2/CMP0_M3 F2 CMP0_M3 42 GPIOF3/CMP0_P3 F3 CMP0_P3 43 GPIOA1/PWM1 A1 29 25 44 GPIOA0/PWM0 A0 23 30 26 45 TDI/GPIOD0/ANB12/SS/ TIN2/CMP0_OUT D0 46 GPIOC3/EXT_TRIGGER C3 EXTAL XTAL 40 22 Misc. PWM5, FAULT2 or EXT_ SYNC 30 15 21 1 20 GPIO PWM1 PWM0 SS ANB12 CMP0_OUT TIN2 TDI EXT_ TRGGER 24 31 27 47 TMS/GPIOD3/ANB11/T1/ CMP1_OUT D3 ANB11 CMP1_OUT T1 TMS 25 32 28 48 TDO/GPIOD1/ANB10/T0/ CMP2_OUT D1 ANB10 CMP2_OUT T0 TDO Shielded ADC input. 4.2 Pin Assignment MC56F8006 and MC56F8002 28-pin small outline IC (28SOIC) assignment is shown in Figure 4; MC56F8006 32-pin low-profile quad flat pack (32LQFP) is shown in Figure 5; MC56F8006 32-pin plastic shrink dual in-line package (PSDIP) is shown in Figure 6; MC56F8006 48-pin low-profile quad flat pack (48LQFP) is shown in Figure 7. MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 Freescale Semiconductor 13 Signal/Connection Descriptions ANB6 & PGA1- & CMP0_P4/GPIOC5 1 28 ANB8 & PGA1+ & CMP0_M2/GPIOC4 ANB4 & CMP1_P1/GPIOC6/PWM2 2 27 GPIOB1/SS/SDA/ANA12 & CMP2_P3 VDDA 3 26 GPIOB6/RXD/SDA/ANA13 & CMP0_P2/CLKIN VSSA 4 25 TDO/GPIOD1/ANB10/T0/CMP2_OUT ANA9 & PGA0- & CMP2_P4/GPIOC2 5 24 TMS/GPIOD3/ANB11/T1/CMP1_OUT ANA7 & PGA0+ & CMP2_M2/GPIOC1 6 23 TDI/GPIOD0/ANB12/SS/TIN2/CMP0_OUT ANA5 and CMP1_M1/GPIOC0/FAULT0 7 22 GPIOA0/PWM0 VSS 8 21 GPIOA1/PWM1 TCK/GPIOD2/ANA4 & CMP1_P2/CMP2_OUT 9 20 VSS RESET/GPIOA7 10 19 VDD GPIOB3/MOSI/TIN3/ANA3 & ANB3/PWM5/CMP1_OUT 11 18 GPIOF0/XTAL GPIOA6/FAULT0/ANA1 & ANB1/SCL/TXD/CLKO_1 12 17 GPIOA3/PWM3/TXD/EXTAL GPIOB4/T0/CLKO_0/MISO/SDA/RXD/ANA0 & ANB0 13 16 GPIOA4/PWM4/SDA/FAULT1/TIN2 GPIOA5/PWM5/FAULT2 or EXT_SYNC/TIN3 14 15 GPIOB0/SCLK/SCL/ANB13/PWM3/T1 Figure 4. Top View, MC56F8006/MC56F8002 28-Pin SOIC Package MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 14 Freescale Semiconductor GPIOA0/PWM0 GPIOA1/PWM1 VSS VDD GPIOF0/XTAL 28 27 26 25 GPIOB5/T1/FAULT3/SCLK 29 3 TDI/GPIOD0/ANB12/SS/TIN2/CMP0_OUT GPIOB7/TXD/SCL/ANA11 & CMP2_M3 30 2 TMS/GPIOD3/ANB11/T1/CMP1_OUT GPIOB1/SS/SDA/ANA12 & CMP2_P3 31 1 TDO/GPIOD1/ANB10/T0/CMP2_OUT GPIOB6/RXD/SDA/ANA13 & CMP0_P2/CLKIN 32 Signal/Connection Descriptions 24 GPIOA3/PWM3/TXD/EXTAL 23 GPIOA2/PWM2 22 GPIOA4/PWM4/SDA/FAULT1/TIN2 4 21 GPIOB0/SCLK/SCL/ANB13/PWM3/T1 ANB8 and PGA1+ & CMP0_M2/GPIOC4 5 20 GPIOA5/PWM5/FAULT2 or EXT_SYNC/TIN3 ANB6 and PGA1- & CMP0_P4/GPIOC5 6 19 GPIOB4/T0/CLKO_0/MISO/SDA/RXD/ANA0 & ANB0 ANB4 & CMP1_P1/GPIOC6/PWM2 7 18 GPIOA6/FAULT0/ANA1 & ANB1/SCL/TXD/CLKO_1 VDDA 8 17 GPIOB2/MISO/TIN2/ANA2 & ANB2/CMP0_OUT 10 11 12 13 14 15 16 ANA9 and PGA0- & CMP2_P4/GPIOC2 ANA7 and PGA0+ & CMP2_M2/GPIOC1 ANA5 and CMP1_M1/GPIOC0/FAULT0 VSS TCK/GPIOD2/ANA4 & CMP1_P2/CMP2_OUT RESET/GPIOA7 GPIOB3/MOSI/TIN3/ANA3 & ANB3/PWM5/CMP1_OUT VSSA 9 ORIENTATION MARK Figure 5. Top View, MC56F8006 32-Pin LQFP Package MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 Freescale Semiconductor 15 Signal/Connection Descriptions !." AND 0'! #-0?-'0)/# '0)/"4&!5,43#,+ !." AND 0'!n #-0?0'0)/# '0)/"48$3#,!.! #-0?- !." #-0?0'0)/#07- '0)/"333$!!.! #-0?0 6$$! '0)/"28$3$!!.! #-0?0#,+). 633! 4$/'0)/$!."4#-0?/54 !.! 0'!n #-0?0'0)/# 4-3'0)/$!."4#-0?/54 !.! 0'! #-0?-'0)/# 4$)'0)/$!."334).#-0?/54 !.! #-0?-'0)/#&!5,4 '0)/!07- 633 '0)/!07- 4#+'0)/$!.! #-0?0#-0?/54 633 2%3%4'0)/! 6$$ '0)/"-/3)4).!.! !."07-#-0?/54 '0)/&84!, '0)/"-)3/4).!.! !."#-0?/54 '0)/!07-48$%84!, '0)/!&!5,4!.! !."3#,48$#,+/? '0)/!07- '0)/"4#,+/?-)3/3$!28$!.! !." '0)/!07-3$!&!5,44). '0)/!07-&!5,4 OR %84?39.#4). '0)/"3#,+3#,!."07-4 Figure 6. Top View, MC56F8006 32-Pin PSDIP Package MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 16 Freescale Semiconductor GPIOF1/CMP1_P3 VSS VDD GPIOF0/XTAL 40 39 38 37 GPIOF3/CMP0_P3 GPIOF2/CMP0_M3 41 43 42 GPIOA0/PWM0 GPIOA1/PWM1 44 GPIOC3/EXT_TRIGGER TDI/GPIOD0/ANB12/SS/TIN2/CMP0_OUT 45 TMS/GPIOD3/ANB11/T1/CMP1_OUT 47 46 TDO/GPIOD1/ANB10/T0/CMP2_OUT 48 Signal/Connection Descriptions GPIOB6/RXD/SDA/ANA13 & CMP0_P2/CLKIN 1 36 GPIOA3/PWM3/TXD/EXTAL GPIOB1/SS/SDA/ANA12 & CMP2_P3 2 35 GPIOA2/PWM2 GPIOB7/TXD/SCL/ANA11 & CMP2_M3 3 34 GPIOE7/CMP1_M3 GPIOB5/T1/FAULT3/SCLK 4 33 GPIOA4/PWM4/SDA/FAULT1/TIN2 Orientation Mark GPIOE0 5 32 GPIOB0/SCLK/SCL/ANB13/PWM3/T1 GPIOE1/ANB9 & CMP0_P1 6 31 VDD ANB8 and PGA1+ & CMP0_M2/GPIOC4 7 30 Vss GPIOE2/ANB7 & CMP0_M1 8 29 GPIOA5/PWM5/FAULT2 or EXT_SYNC/TIN3 ANB6 and PGA1- & CMP0_P4/GPIOC5 18 19 20 21 22 23 ANA5 & CMP1_M1/GPIOC0/FAULT0 VSS VDD TCK/GPIOD2/ANA4 & CMP1_P2/CMP2_OUT RESET/GPIOA7 GPIOB3/MOSI/TIN3/ANA3 & ANB3/PWM5/CMP1_OUT 24 17 GPIOE4/ANA6 & CMP2_P2 GPIOB2/MISO/TIN2/ANA2 & ANB2/CMP0_OUT 16 25 GPIOE5/ANA8 & CMP2_P1 12 ANA7 & PGA0+ & CMP2_M2/GPIOC1 GPIOA6/FAULT0/ANA1 & ANB1/SCL/TXD/CLKO_1 VDDA 15 26 ANA9 and PGA0- & CMP2_P4/GPIOC2 11 14 GPIOB4/T0/CLKO_0/MISO/SDA/RXD/ANA0 & ANB0 ANB4 & CMP1_P1/GPIOC6/PWM2 13 GPIOE6 27 VSSA 28 10 GPIOE3/ANA10 & CMP2_M1 9 GPIOC7/ANB5 & CMP1_M2 Figure 7. Top View, MC56F8006 48-Pin LQFP Package 4.3 56F8006/56F8002 Signal Pins After reset, each pin is configured for its primary function (listed first). Any alternate functionality must be programmed via the GPIO module's peripheral enable registers (GPIO_x_PER) and SIM module's (GPS_xn) GPIO peripheral select registers. If CLKIN or XTAL is selected as device external clock input, the CLK_MOD bit in the OCCS oscillator control register (OSCTL) needs to be set too. EXT_SEL bit in OSCTL selects CLKIN or XTAL. MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 Freescale Semiconductor 17 Signal/Connection Descriptions Table 5. 56F8006/56F8002 Signal and Package Information Signal Name 32 28 32 48 PSDI SOIC LQFP LQFP P VDD 21 VDD 31 Type State During Reset Signal Description Supply Supply I/O Power -- This pin supplies 3.3 V power to the chip I/O interface. Supply Supply I/O Ground -- These pins provide ground for chip I/O interface. VDD 19 26 22 38 VSS 8 13 9 20 VSS 20 27 23 39 VDDA 3 8 4 12 Supply Supply Analog Power -- This pin supplies 3.3 V power to the analog modules. It must be connected to a clean analog power supply. VSSA 4 9 5 13 Supply Supply Analog Ground -- This pin supplies an analog ground to the analog modules. It must be connected to a clean power supply. RESET 10 15 11 23 Input Input, internal pullup enabled Reset -- This input is a direct hardware reset on the processor. When RESET is asserted low, the device is initialized and placed in the reset state. A Schmitt-trigger input is used for noise immunity. The internal reset signal is deasserted synchronous with the internal clocks after a fixed number of internal clocks. VSS 30 (GPIOA7) Input/ Output Port A GPIO -- This GPIO pin can be individually programmed as an input or output pin. RESET functionality is disabled in this mode and the chip can be reset only via POR, COP reset, or software reset. Input/ Output Input, Port A GPIO -- This GPIO pin can be individually programmed as internal an input or output pin. pullup enabled PWM0 -- The PWM channel 0. After reset, the default state is RESET. GPIOA0 22 29 25 44 (PWM0) Output After reset, the default state is GPIOA0. GPIOA1 21 28 24 43 (PWM1) Input/ Output Output Input, Port A GPIO -- This GPIO pin can be individually programmed as internal an input or output pin. pullup enabled PWM1 -- The PWM channel 1. After reset, the default state is GPIOA1. GPIOA2 (PWM2) 23 19 35 Input/ Output Output Input, Port A GPIO -- This GPIO pin can be individually programmed as internal an input or output pin. pullup enabled PWM2 -- The PWM channel 2. After reset, the default state is GPIOA2. MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 18 Freescale Semiconductor Signal/Connection Descriptions Table 5. 56F8006/56F8002 Signal and Package Information (continued) Signal Name GPIOA3 32 28 32 48 PSDI SOIC LQFP LQFP P 17 24 20 36 Type Input/ Output State During Reset Signal Description Input, Port A GPIO -- This GPIO pin can be individually programmed as internal an input or output pin. pullup enabled PWM3 -- The PWM channel 3. (PWM3) Output (TXD) Output TXD -- The SCI transmit data output or transmit/receive in single wire operation. (EXTAL) Analog Input EXTAL -- External Crystal Oscillator Input. This input can be connected to a 32.768 kHz or 1-16 MHz external crystal or ceramic resonator. When used to supply a source to the internal PLL, the crystal/resonator must be in the 4 MHz to 8 MHz range. Tie this pin low or configure as GPIO if XTAL is being driven by an external clock source. If using a 32.768 kHz crystal, place the crystal as close as possible to device pins to speed startup. After reset, the default state is GPIOA3. GPIOA4 16 22 18 33 Input/ Output Input, Port A GPIO -- This GPIO pin can be individually programmed as internal an input or output pin. pullup enabled PWM4 -- The PWM channel 4. (PWM4) Output (SDA) Input/Opendrain Output (FAULT1) Input FAULT1 -- PWM fault input 1used for disabling selected PWM outputs in cases where fault conditions originate off-chip. (TIN2) Input TIN2 -- Dual timer module channel 2 input SDA -- The I2C serial data line. After reset, the default state is GPIOA4. GPIOA5 14 20 16 29 Input/ Output (PWM5) Output (FAULT2/ EXT_SYNC) Input/ Output (TIN3) Input Input, Port A GPIO -- This GPIO pin can be individually programmed as internal an input or output pin. pullup enabled PWM5 -- The PWM channel 5. FAULT2 -- PWM fault input 2 used for disabling selected PWM outputs in cases where fault conditions originate off-chip. EXT_SYNC -- When not being used as a fault input, this pin can be used to receive a pulse to reset the PWM counter or to generate a positive pulse at the start of every PWM cycle. TIN3 -- Dual timer module channel 3 input After reset, the default state is GPIOA5. MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 Freescale Semiconductor 19 Signal/Connection Descriptions Table 5. 56F8006/56F8002 Signal and Package Information (continued) Signal Name GPIOA6 32 28 32 48 PSDI SOIC LQFP LQFP P 12 18 14 26 Type Input/ Output (FAULT0) Input (ANA1 & ANB1) Analog Input (SCL) Input/Opendrain Output (TXD) Output (CLKO_1) Output State During Reset Signal Description Input, Port A GPIO -- This GPIO pin can be individually programmed as internal an input or output pin. pullup enabled FAULT0 -- PWM fault input 0 used for disabling selected PWM outputs in cases where fault conditions originate off-chip. ANA1 and ANB1 -- Analog input to channel 1 of ADCA and ADCB. SCL -- The I2C serial clock TXD -- The SCI transmit data output or transmit/receive in single wire operation. CLKO_1 -- This is a buffered clock output; the clock source is selected by clockout select (CLKOSEL) bits in the clock output select register (CLKOUT) in the SIM. When used as an analog input, the signal goes to the ANA1 and ANB1. After reset, the default state is GPIOA6. GPIOB0 15 21 17 32 Input/ Output Input, Port B GPIO -- This GPIO pin can be individually programmed as internal an input or output pin. pullup enabled SCLK -- The SPI serial clock. In master mode, this pin serves as an output, clocking slaved listeners. In slave mode, this pin serves as the data clock input. (SCLK) Input/ Output (SCL) Input/Opendrain Output (ANB13) Analog Input ANB13 -- Analog input to channel 13 of ADCB (PWM3) Output PWM3 -- The PWM channel 3. (T1) Input/ Output T1 -- Dual timer module channel 1 input/output. SCL -- The I2C serial clock. After reset, the default state is GPIOB0. MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 20 Freescale Semiconductor Signal/Connection Descriptions Table 5. 56F8006/56F8002 Signal and Package Information (continued) Signal Name GPIOB1 32 28 32 48 PSDI SOIC LQFP LQFP P 27 2 30 2 Type Input/ Output (SS) Input/ Output (SDA) Input/Opendrain Output (ANA12 and CMP2_P3) Analog input State During Reset Signal Description Input, Port B GPIO -- This GPIO pin can be individually programmed as internal an input or output pin. pullup enabled SS -- SS is used in slave mode to indicate to the SPI module that the current transfer is to be received. SDA -- The I2C serial data line. ANA12 and CMP2_P3 -- Analog input to channel 12 of ADCA and Positive input 3 of analog comparator 2. When used as an analog input, the signal goes to the ANA12 and CMP2_P3. After reset, the default state is GPIOB1. GPIOB2 17 13 25 Input/ Output Input, Port B GPIO -- This GPIO pin can be individually programmed as internal an input or output pin. pullup enabled MISO -- Master in/slave out. In master mode, this pin serves as the data input. In slave mode, this pin serves as the data output. The MISO line of a slave device is placed in the high-impedance state if the slave device is not selected. (MISO) Input/ Output (TIN2) Input/ Output TIN2 -- Dual timer module channel 2 input. (ANA2 and ANB2) Analog Input ANA2 and ANB2 -- Analog input to channel 2 of ADCA and ADCB. (CMP0_ OUT) Output CMP0_OUT-- Analog comparator 0 output. When used as an analog input, the signal goes to the ANA2 and ANB2. After reset, the default state is GPIOB2. MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 Freescale Semiconductor 21 Signal/Connection Descriptions Table 5. 56F8006/56F8002 Signal and Package Information (continued) Signal Name GPIOB3 32 28 32 48 PSDI SOIC LQFP LQFP P 11 16 12 24 Type Input/ Output (MOSI) Input/ Output (TIN3) Input/ Output (ANA3 and ANB3) Input (PWM5) Output (CMP1_ OUT Output State During Reset Signal Description Input, Port B GPIO -- This GPIO pin can be individually programmed as internal an input or output pin. pullup enabled MOSI -- Master out/slave in. In master mode, this pin serves as the data output. In slave mode, this pin serves as the data input. TIN3 -- Dual timer module channel 3 input. ANA3 and ANB3 -- Analog input to channel 3 of ADCA and ADCB. PWM5 -- The PWM channel 5. CMP1_OUT-- Analog comparator 1 output. When used as an analog input, the signal goes to the ANA3 and ANB3. After reset, the default state is GPIOB3. GPIOB4 13 19 15 27 Input/ Output Input, Port B GPIO -- This GPIO pin can be individually programmed as internal an input or output pin. pullup enabled T0 -- Dual timer module channel 0 input/output. (T0) Input/ Output (CLKO_0) Output CLKO_0 -- This is a buffered clock output; the clock source is selected by clockout select (CLKOSEL) bits in the clock output select register (CLKOUT) of the SIM. (MISO) Input/ Output MISO -- Master in/slave out. In master mode, this pin serves as the data input. In slave mode, this pin serves as the data output. The MISO line of a slave device is placed in the high-impedance state if the slave device is not selected. (SDA) Input/Opendrain Output (RXD) Input (ANA0 and ANB0) Analog Input SDA -- The I2C serial data line. RXD -- The SCI receive data input. ANA0 and ANB0 -- Analog input to channel 0 of ADCA and ADCB. When used as an analog input, the signal goes to the ANA0 and ANB0. After reset, the default state is GPIOB4. MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 22 Freescale Semiconductor Signal/Connection Descriptions Table 5. 56F8006/56F8002 Signal and Package Information (continued) Signal Name 32 28 32 48 PSDI SOIC LQFP LQFP P 4 GPIOB5 32 4 Type Input/ Output State During Reset Signal Description Input, Port B GPIO -- This GPIO pin can be individually programmed as internal an input or output pin. pullup enabled T1 -- Dual timer module channel 1 input/output. (T1) Input/ Output (FAULT3) Input FAULT3 -- PWM fault input 3 used for disabling selected PWM outputs in cases where fault conditions originate off-chip. (SCLK) Input SCLK -- SPI serial clock. In master mode, this pin serves as an output, clocking slaved listeners. In slave mode, this pin serves as the data clock input. After reset, the default state is GPIOB5. GPIOB6 26 1 29 1 (SDA) Input/ Output Input, Port B GPIO -- This GPIO pin can be individually programmed as internal an input or output pin. pullup Input/Open- enabled SDA -- The I2C serial data line. drain Output (ANA13 and CMP0_P2) Analog Input ANA13 and CMP0_P2 -- Analog input to channel 13 of ADCA and positive input 2 of analog comparator 0. (CLKIN) Input External Clock Input -- This pin serves as an external clock input. When used as an analog input, the signal goes to the ANA13 and CMP0_P2. After reset, the default state is GPIOB6. GPIOB7 3 31 3 Input/ Output (TXD) Input/ Output (SCL) Input/Opendrain Output (ANA11 and CMP2_M3) Analog Input Input, Port B GPIO -- This GPIO pin can be individually programmed as internal an input or output pin. pullup enabled TXD -- The SCI transmit data output or transmit/receive in single wire operation. SCL -- The I2C serial clock. ANA11 and CMP2_M3 -- Analog input to channel 11 of ADCA and negative input 3 of analog comparator 2. When used as an analog input, the signal goes to the ANA11 and CMP2_M3. After reset, the default state is GPIOB7. MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 Freescale Semiconductor 23 Signal/Connection Descriptions Table 5. 56F8006/56F8002 Signal and Package Information (continued) Signal Name ANA5 and CMP1_M1 32 28 32 48 PSDI SOIC LQFP LQFP P 7 12 8 19 Type State During Reset Analog Input Analog Input Signal Description ANA5 and CMP1_M1-- Analog input to channel 5 of ADCA and negative input 1 of analog comparator 1. (GPIOC0) Analog Input Port C GPIO -- This GPIO pin can be individually programmed as an input or output pin. (FAULT0) Input FAULT0 -- PWM fault input 0 is used for disabling selected PWM outputs in cases where fault conditions originate off-chip. When used as an analog input, the signal goes to the ANA5 and CMP1_M1. After reset, the default state is ANA5 and CMP1_M1. ANA7 and PGA0+ and CMP2_M2 6 11 7 17 (GPIOC1) Analog Input Analog Input ANA7 and PGA0+ and CMP2_M2 -- Analog input to channel 7 of ADCA and PGA0 positive input and negative input 2 of analog comparator 2. Port C GPIO -- This GPIO pin can be individually programmed as an input or output pin. Input/ Output When used as an analog input, The signal goes to the ANA7 and PGA0+ and CMP2_M2. After reset, the default state is ANA7 and PGA0+ and CMP2_M2. ANA9 and PGA0- and CMP2_P4 5 10 6 15 (GPIOC2) Analog Input Input/ Output Analog Input ANA9 and PGA0- and CMP2_P4 -- Analog input to channel 9 of ADCA and PGA0 negative input and positive input 4 of analog comparator 2. Port C GPIO -- This GPIO pin can be individually programmed as an input or output pin. When used as an analog input, The signal goes to the ANA9 and PGA0- and CMP2_P4. After reset, the default state is ANA9 and PGA0- and CMP2_P4. GPIOC3 (EXT_ TRIGGER) 46 Input/ Output Input Input, Port C GPIO -- This GPIO pin can be individually programmed as internal an input or output pin. pullup enabled EXT_TRIGGER -- PDB external trigger input. After reset, the default state is GPIOC3. MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 24 Freescale Semiconductor Signal/Connection Descriptions Table 5. 56F8006/56F8002 Signal and Package Information (continued) Signal Name ANB8 and PGA1+ and CMP0_M2 32 28 32 48 PSDI SOIC LQFP LQFP P 28 5 1 7 (GPIOC4) Type State During Reset Analog Input Analog Input Input/ Output Signal Description ANB8 and PGA1+ and CMP0_M2 -- Analog input to channel 8 of ADCB and PGA1 positive input and negative input 2 of analog comparator 0. Port C GPIO -- This GPIO pin can be individually programmed as an input or output pin. When used as an analog input, the signal goes to the ANB8 and PGA1+ and CMP0_M2. After reset, the default state is ANB8 and PGA1+ and CMP0_M2. ANB6 and PGA1- and CMP0_P4 1 6 2 9 (GPIOC5) Input/ Output Analog Input Analog Input ANB6 and PGA1- and CMP0_P4 -- Analog input to channel 6 of ADCB and PGA1 negative input and positive input 4 of analog comparator 0. Port C GPIO -- This GPIO pin can be individually programmed as an input or output pin. When used as an analog input, the signal goes to the ANB6 and PGA1- and CMP0_P4. After reset, the default state is ANB6 and PGA1- and CMP0_P4. ANB4 and CMP1_P1 2 7 3 11 Analog Input Analog Input ANB4 and CMP1_P1 -- Analog input to channel 4 of ADCB and positive input 1 of analog comparator 1. (GPIOC6) Input/ Output Port C GPIO -- This GPIO pin can be individually programmed as an input or output pin. (PWM2) Output PWM2 -- The PWM channel 2. When used as an analog input, the signal goes to the ANB4 and CMP1_P1. After reset, the default state is ANB4 and CMP1_P1. GPIOC7 (ANB5 and CMP1_M2) 10 Input/ Output Analog Input Input, Port C GPIO -- This GPIO pin can be individually programmed as internal an input or output pin. pullup enabled ANB5 and CMP1_M2 -- Analog input to channel 5 of ADCB and negative input 2 of analog comparator 1. After reset, the default state is GPIOC7. MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 Freescale Semiconductor 25 Signal/Connection Descriptions Table 5. 56F8006/56F8002 Signal and Package Information (continued) Signal Name TDI 32 28 32 48 PSDI SOIC LQFP LQFP P 23 30 26 45 Type Input State During Reset Signal Description Input, Test Data Input -- This input pin provides a serial input data stream internal to the JTAG/EOnCE port. It is sampled on the rising edge of TCK pullup and has an on-chip pullup resistor. enabled Port D GPIO -- This GPIO pin can be individually programmed as an input or output pin. (GPIOD0) Input/ Output (ANB12) Analog Input (SS) Input SS -- SS is used in slave mode to indicate to the SPI module that the current transfer is to be received. (TIN2) Input TIN2 -- Dual timer module channel 2 input. (CMP0_ OUT) Output CMP1_OUT -- Analog comparator 1 output. ANB12 -- Analog input to channel 12 of ADCB After reset, the default state is TDI. TDO 25 32 28 48 Output Output, tri-stated, internal pullup enabled Test Data Output -- This three-stateable output pin provides a serial output data stream from the JTAG/EOnCE port. It is driven in the shift-IR and shift-DR controller states, and changes on the falling edge of TCK. (GPIOD1) Input/ Output Port D GPIO -- This GPIO pin can be individually programmed as an input or output pin. (ANB10) Analog Input ANB10 -- Analog input to channel 10 of ADCB. (T0) Input/ Output T0 -- Dual timer module channel 0 input/output. (CMP2_ OUT) Output CMP2_OUT -- Analog comparator 2 output. After reset, the default state is TDO. TCK 9 14 10 22 Input Input, internal pullup enabled Test Clock Input -- This input pin provides a gated clock to synchronize the test logic and shift serial data to the JTAG/EOnCE port. The pin is connected internally to a pullup resistor. A Schmitt-trigger input is used for noise immunity. (GPIOD2) Input/ Output Port D GPIO -- This GPIO pin can be individually programmed as an input or output pin. (ANA4 and CMP1_P2) Analog Input ANA4 and CMP1_P2 -- Analog input to channel 4 of ADCA and positive input 2 of analog comparator 1. (CMP2_ OUT) Output CMP2_OUT -- Analog comparator 2 output. After reset, the default state is TCK. MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 26 Freescale Semiconductor Signal/Connection Descriptions Table 5. 56F8006/56F8002 Signal and Package Information (continued) Signal Name TMS 32 28 32 48 PSDI SOIC LQFP LQFP P 24 31 27 47 Type Input State During Reset Signal Description Input, Test Mode Select Input -- This input pin is used to sequence the internal JTAG TAP controller's state machine. It is sampled on the rising pullup edge of TCK and has an on-chip pullup resistor. enabled Port D GPIO -- This GPIO pin can be individually programmed as an input or output pin. (GPIOD3) Input/ Output (ANB11) Analog Input ANB11 -- Analog input to channel 11 of ADCB. (T1) Input/ Output T1 -- Dual timer module channel 1 input/output. (CMP1_ OUT) Output CMP1_OUT -- Analog comparator 2 output. After reset, the default state is TMS. Always tie the TMS pin to VDD through a 2.2 k resistor. GPIOE0 5 Input/ Output Input, Port E GPIO -- This GPIO pin can be individually programmed as internal an input or output pin. pullup enabled After reset, the default state is GPIOE0. GPIOE1 6 Input/ Output Input, Port E GPIO -- This GPIO pin can be individually programmed as internal an input or output pin. pullup enabled ANB9 and CMP0_P1 -- Analog input to channel 9 of ADCB and positive input 1 of analog comparator 0. Analog Input (ANB9 and CMP0_P1) After reset, the default state is GPIOE1. GPIOE2 8 Input/ Output Analog Input (ANB7 and CMP0_M1) Input, Port E GPIO -- This GPIO pin can be individually programmed as internal an input or output pin. pullup enabled ANB7 and CMP0_M1 -- Analog input to channel 7 of ADCB and negative input 1 of analog comparator 0. After reset, the default state is GPIOE2. GPIOE3 14 Input/ Output Analog Input (ANA10 and CMP2_M1) Input, Port E GPIO -- This GPIO pin can be individually programmed as internal an input or output pin. pullup enabled ANA10 and CMP2_M1 -- Analog input to channel 10 of ADCA and negative input 1 of analog comparator 2. After reset, the default state is GPIOE3. GPIOE4 (ANA6 and CMP2_P2) 18 Input/ Output Analog Input Input, Port E GPIO -- This GPIO pin can be individually programmed as internal an input or output pin. pullup enabled ANA6 and CMP2_P2 -- Analog input to channel 6 of ADCA and positive input 2 of analog comparator 2. After reset, the default state is GPIOE4. MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 Freescale Semiconductor 27 Signal/Connection Descriptions Table 5. 56F8006/56F8002 Signal and Package Information (continued) Signal Name 32 28 32 48 PSDI SOIC LQFP LQFP P GPIOE5 16 (ANA8 and CMP2_P1) Type Input/ Output Analog Input State During Reset Signal Description Input, Port E GPIO -- This GPIO pin can be individually programmed as internal an input or output pin. pullup enabled ANA8 and CMP2_P1-- Analog input to channel 8 of ADCA and positive input 1 of analog comparator 2. After reset, the default state is GPIOE5. GPIOE6 28 Input/ Output Input, Port E GPIO -- This GPIO pin can be individually programmed as internal an input or output pin. pullup enable After reset, the default state is GPIOE6. GPIOE7 34 Input/ Output Input, Port E GPIO -- This GPIO pin can be individually programmed as internal an input or output pin pullup enabled CMP1_M3 -- Analog input to both negative input 3 of analog comparator 1. (CMP1_M3) Analog Input After reset, the default state is GPIOE7. GPIOF0 18 25 21 37 (XTAL) Input/ Output Analog Input/ Output Input, Port F GPIO -- This GPIO pin can be individually programmed as internal an input or output pin. pullup enabled XTAL -- External Crystal Oscillator Output. This output connects the internal crystal oscillator output to an external crystal or ceramic resonator. After reset, the default state is GPIOF0. GPIOF1 40 Input/ Output (CMP1_P3) Analog Input Input, Port F GPIO -- This GPIO pin can be individually programmed as internal an input or output pin pullup enabled CMP1_P3 -- Analog input to both positive input 3 of analog comparator 1. After reset, the default state is GPIOF1 GPIOF2 41 Input/ Output Analog Input (CMP0_M3) Input, Port F GPIO -- This GPIO pin can be individually programmed as internal an input or output pin. pullup enabled CMP0_M3 -- Analog input to both negative input 3 of analog comparator 0. After reset, the default state is GPIOF2. GPIOF3 (CMP0_P3) 42 Input/ Output Analog Input Input, Port F GPIO -- This GPIO pin can be individually programmed as internal an input or output pin. pullup enabled CMP0_P3 -- Analog input to both positive input 3 of analog comparator 0. After reset, the default state is GPIOF3. MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 28 Freescale Semiconductor Memory Maps 5 Memory Maps 5.1 Introduction The 56F8006/56F8002 device is based on the 56800E core. It uses a dual Harvard-style architecture with two independent memory spaces for Data and Program. On-chip RAM is shared by both data and program spaces and flash memory is used only in program space. This section provides memory maps for: * Program address space, including the interrupt vector table * Data address space, including the EOnCE memory and peripheral memory maps On-chip memory sizes for the device are summarized in Table 6. Flash memories' restrictions are identified in the "Use Restrictions" column of Table 6. Table 6. Chip Memory Configurations On-Chip Memory 56F8006 56F8002 Use Restrictions Program Flash (PFLASH) 8K x 16 or 16 KB 6K x 16 or 12 KB Erase/program via flash interface unit and word writes to CDBW Unified RAM (RAM) 1K x 16 or 2 KB 1K x 16 or 2 KB Usable by the program and data memory spaces 5.2 Program Map The 56F8006/56F8002 series provide up to 16 KB on-chip flash memory. It primarily accesses through the program memory buses (PAB; PDB). PAB is used to select program memory addresses; instruction fetches are performed over PDB. Data can be read and written to program memory space through primary data memory buses: CDBW for data write and CDBR for data read. Accessing program memory space over the data memory buses takes longer access time compared to accessing data memory space. The special MOVE instructions are provided to support these accesses. The benefit is that non time critical constants or tables can be stored and accessed in program memory. The program memory map is shown in Table 7 and Table 8. Table 7. Program Memory Map1 for 56F8006 at Reset Begin/End Address 1 2 Memory Allocation P: 0x1F FFFF P: 0x00 8800 RESERVED P: 0x00 83FF P: 0x00 8000 On-Chip RAM2: 2 KB P: 0x00 7FFF P: 0x00 2000 RESERVED P: 0x00 1FFF P: 0x00 0000 * * * * Internal program flash: 16 KB Interrupt vector table locates from 0x00 0000 to 0x00 0065 COP reset address = 0x00 0002 Boot location = 0x00 0000 All addresses are 16-bit word addresses. This RAM is shared with data space starting at address X: 0x00 0000; see Figure 8. MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 Freescale Semiconductor 29 Memory Maps Table 8. Program Memory Map1 for 56F8002 at Reset (continued) Begin/End Address 1 2 5.3 Memory Allocation P: 0x1F FFFF P: 0x00 8800 RESERVED P: 0x00 83FF P: 0x00 8000 On-Chip RAM2: 2 KB P: 0x00 7FFF P: 0x00 2000 RESERVED P: 0x00 1FFF P: 0x00 0800 * * * * P: 0x00 07FF P: 0x00 0000 RESERVED Internal program flash: 12 KB Interrupt vector table locates from 0x00 0800 to 0x00 0865 COP reset address = 0x00 0802 Boot location = 0x00 0800 All addresses are 16-bit word addresses. This RAM is shared with data space starting at address X: 0x00 0000; see Figure 9. Data Map The 56F8006/56F8002 series contain a dual access memory. It can be accessed from core primary data buses (XAB1; CDBW; CDBR) and secondary data buses (XAB2; XDB2). Addresses in data memory are selected on the XAB1 and XAB2 buses. Byte, word, and long data transfers occur on the 32-bit CDBR and CDBW buses. A second 16-bit read operation can be performed in parallel on the XDB2 bus. Peripheral registers and on-chip JTAG/EOnCE controller registers are memory-mapped into data memory access. A special direct address mode is supported for accessing a first 64-location in data memory by using a single word instruction. The data memory map is shown in Table 9. Table 9. Data Memory Map1 1 2 Begin/End Address Memory Allocation X:0xFF FFFF X:0xFF FF00 EOnCE 256 locations allocated X:0xFF FEFF X:0x01 0000 RESERVED X:0x00 FFFF X:0x00 F000 On-Chip Peripherals 4096 locations allocated X:0x00 EFFF X:0x00 8800 RESERVED X:0x00 87FF X:0x00 8000 RESERVED X:0x00 7FFF X:0x00 0400 RESERVED X:0x00 03FF X:0x00 0000 On-Chip Data RAM 2 KB2 All addresses are 16-bit word addresses. This RAM is shared with Program space starting at P: 0x00 8000. See Figure 8 and Figure 9. MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 30 Freescale Semiconductor Memory Maps On-chip RAM is also mapped into program space starting at P: 0x00 8000. This makes for easier online reprogramming of on-chip flash. Program Data EOnCE Reserved 0xFF FF00 Reserved 0x00 8400 0x01 0000 RAM 0x00 8000 Peripherals Reserved 0x00 F000 Dual Port RAM Reserved 0x00 2000 0x00 0400 Flash RAM 0x00 0000 0x00 0000 Figure 8. 56F8006 Dual Port RAM Map Program Data EOnCE Reserved Reserved 0x00 8400 0x01 0000 RAM 0x00 8000 Peripherals Reserved 0x00 0000 0x00 F000 Dual Port RAM 0x00 2000 0x00 0800 0xFF FF00 Reserved 0x00 0400 Flash RAM Reserved 0x00 0000 Figure 9. 56F8002 Dual Port RAM Map 5.4 Interrupt Vector Table and Reset Vector The location of the vector table is determined by the vector base address register (VBA). The value in this register is used as the upper 14 bits of the interrupt vector VAB[20:0]. The lower seven bits are determined based on the highest priority interrupt and are then appended onto VBA before presenting the full VAB to the core. Please see the MC56F8006 Peripheral Reference Manual for detail. The reset startup addresses of 56F8002 and 56F8006 are different. * * 56F8006 startup address is located at 0x00 0000. The reset value of VBA is reset to a value of 0x0000 that corresponds to address 0x00 0000 56F8002 startup address is located at 0x00 0800. The reset value of VBA is reset to a value of 0x0010 that corresponds to address 0x00 0800 By default, the chip reset address and COP reset address correspond to vector 0 and 1 of the interrupt vector table. In these instances, the first two locations in the vector table must contain branch or JMP instructions. All other entries must contain JSR instructions. The highest number vector, a user assignable vector USER6 (vector 50), can be defined as a fast interrupt if the instruction located in this vector location is not a JSR or BSR instruction. Please see section 9.3.3.3 of DSP56800E 16-Bit Core Reference Manual for detail. MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 Freescale Semiconductor 31 Memory Maps Table 43 provides the 56F8006/56F8002's reset and interrupt priority structure, including on-chip peripherals. 5.5 Peripheral Memory-Mapped Registers The locations of on-chip peripheral registers are part of the data memory map on the 56800E series. These locations may be accessed with the same addressing modes used for ordinary data memory, except all peripheral registers should be read or written using word accesses only. Table 10 summarizes the base addresses for the set of peripherals on the 56F8006/56F8002 devices. Peripherals are listed in order of the base address. Table 10. Data Memory Peripheral Base Address Map Summary Peripheral Prefix Base Address Dual Channel Timer TMR X:0x00 F000 PWM Module PWM X:0x00 F020 Interrupt Controller INTC X:0x00 F040 ADCA ADCA X:0x00 F060 ADCB ADCB X:0x00 F080 Programmable Gain Amplifier 0 PGA0 X:0x00 F0A0 Programmable Gain Amplifier 1 PGA1 X:0x00 F0C0 SCI SCI X:0x00 F0E0 SPI SPI X:0x00 F100 2C I2C X:0x00 F120 Computer Operating Properly COP X:0x00 F140 On-Chip Clock Synthesis OCCS X:0x00 F160 GPIO Port A GPIOA X:0x00 F180 GPIO Port B GPIOB X:0x00 F1A0 GPIO Port C GPIOC X:0x00 F1C0 GPIO Port D GPIOD X:0x00 F1E0 GPIO Port E GPIOE X:0x00 F200 GPIO Port F GPIOF X:0x00 F220 System Integration Module SIM X:0x00 F240 Power Management Controller PMC X:0x00 F260 Analog Comparator 0 CMP0 X:0x00 F280 Analog Comparator 1 CMP1 X:0x00 F2A0 Analog Comparator 2 CMP2 X:0x00 F2C0 Programmable Interval Timer PIT X:0x00 F2E0 Programmable Delay Block PDB X:0x00 F300 Real Timer Clock RTC X:0x00 F320 Flash Memory Interface FM X:0x00 F400 I MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 32 Freescale Semiconductor Memory Maps 5.6 EOnCE Memory Map Control registers of the EOnCE are located at the top of data memory space. These locations are fixed by the 56F800E core. These registers can also be accessed through JTAG port if flash security is not set. Table 11 lists all EOnCE registers necessary to access or control the EOnCE. Table 11. EOnCE Memory Map Address Register Acronym Register Name X:0xFF FFFF OTX1/ORX1 Transmit Register Upper Word Receive Register Upper Word X:0xFF FFFE OTX/ORX (32 bits) Transmit Register Receive Register X:0xFF FFFD OTXRXSR Transmit and Receive Status and Control Register X:0xFF FFFC OCLSR Core Lock/Unlock Status Register X:0xFF FFFB- X:0xFF FFA1 Reserved X:0xFF FFA0 OCR Control Register X:0xFF FF9F- X:0xFF FF9E OSCNTR (24 bits) Instruction Step Counter X:0xFF FF9D OSR Status Register X:0xFF FF9C OBASE Peripheral Base Address Register X:0xFF FF9B OTBCR Trace Buffer Control Register X:0xFF FF9A OTBPR Trace Buffer Pointer Register X:0xFF FF99- X:0xFF FF98 OTB (21-24 bits/stage) Trace Buffer Register Stages X:0xFF FF97- X:0xFF FF96 OBCR (24 bits) Breakpoint Unit Control Register X:0xFF FF95- X:0xFF FF94 OBAR1 (24 bits) Breakpoint Unit Address Register 1 X:0xFF FF93- X:0xFF FF92 OBAR2 (32 bits) Breakpoint Unit Address Register 2 X:0xFF FF91- X:0xFF FF90 OBMSK (32 bits) Breakpoint Unit Mask Register 2 X:0xFF FF8F X:0xFF FF8E Reserved OBCNTR EOnCE Breakpoint Unit Counter X:0xFF FF8D Reserved X:0xFF FF8C Reserved X:0xFF FF8B Reserved X:0xFF FF8A X:0xFF FF89 - X:0xFF FF00 OESCR External Signal Control Register Reserved MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 Freescale Semiconductor 33 General System Control Information 6 General System Control Information 6.1 Overview This section discusses power pins, reset sources, interrupt sources, clock sources, the system integration module (SIM), ADC synchronization, and JTAG/EOnCE interfaces. 6.2 Power Pins VDD, VSS and VDDA, VSSA are the primary power supply pins for the devices. This voltage source supplies power to all on-chip peripherals, I/O buffer circuitry and to internal voltage regulators. Device has multiple internal voltages provide regulated lower-voltage source for the peripherals, core, memory, and on-chip relaxation oscillators. Typically, there are at least two separate capacitors across the power pins to bypass the glitches and provide bulk charge storage. In this case, there should be a bulk electrolytic or tantalum capacitor, such as a 10 F tantalum capacitor, to provide bulk charge storage for the overall system and a 0.1 F ceramic bypass capacitor located as near to the device power pins as practical to suppress high-frequency noise. Each pin must have a bypass capacitor for best noise suppression. VDDA and VSSAare the analog power supply pins for the device. This voltage source supplies power to the ADC, PGA, and CMP modules. A 0.1 F ceramic bypass capacitor should be located as near to the device VDDA and VSSA pins as practical to suppress high-frequency noise. VDDA and VSSA are also the voltage reference high and voltage reference low inputs, respectively, for the ADC module. 6.3 Reset Resetting the device provides a way to start processing from a known set of initial conditions. During reset, most control and status registers are forced to initial values and the program counter is loaded from the reset vector. On-chip peripheral modules are disabled and I/O pins are initially configured as the reset status shown in Table 5. The 56F8006/56F8002 has the following sources for reset: * * * * * * * Power-on reset (POR) Partial power down reset (PPD) Low-voltage detect (LVD) External pin reset (EXTR) Computer operating properly loss of reference reset (COP_LOR) Computer operating properly time-out reset (COP_CPU) Software Reset (SWR) Each of these sources has an associated bit in the reset status register (RSTAT) in the system integration module (SIM). The external pin reset function is shared with an GPIO port A7 on the RESET/GPIOA7 pin. The reset function is enabled following any reset of the device. Bit 7 of GPIOA_PER register must be cleared to use this pin as an GPIO port pin. When enabled as the RESET pin, an internal pullup device is automatically enabled. 6.4 On-chip Clock Synthesis The on-chip clock synthesis (OCCS) module allows designers using an internal relaxation oscillator, an external crystal, or an external clock to run 56F8000 family devices at user-selectable frequencies up to 32 MHz. The features of OCCS module include: * * * Ability to power down the internal relaxation oscillator or crystal oscillator Ability to put the internal relaxation oscillator into standby mode Ability to power down the PLL MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 34 Freescale Semiconductor General System Control Information * * * Provides a 3X system clock that operates at three times the system clock to PWM, timer, and SCI modules Safety shutdown feature is available if the PLL reference clock is lost Can be driven from an external clock source The clock generation module provides the programming interface for the PLL, internal relaxation oscillator, and crystal oscillator. It also provides a postscaler to divide clock frequency down by 1, 2, 4, 8, 16, 32, 64, 128, 256 before feeding to the SIM. The SIM is responsible for further dividing these frequencies by two, which ensures a 50% duty cycle in the system clock output. For detail, see the OCCS chapter in the MC56F8006 Peripheral Reference Manual. 6.4.1 Internal Clock Source An internal relaxation oscillator can supply the reference frequency when an external frequency source or crystal is not used. It is optimized for accuracy and programmability while providing several power-saving configurations that accommodate different operating conditions. The internal relaxation oscillator has little temperature and voltage variability. To optimize power, the internal relaxation oscillator supports a run state (8 MHz), standby state (400 kHz), and a power-down state. During a boot or reset sequence, the relaxation oscillator is enabled by default (the PRECS bit in the PLLCR word is set to 0). Application code can then also switch to the external clock source and power down the internal oscillator, if desired. If a changeover between internal and external clock sources is required at power-on, ensure that the clock source is not switched until the desired external clock source is enabled and stable. To compensate for variances in the device manufacturing process, the accuracy of the relaxation oscillator can be incrementally adjusted to within + 0.078% of 8 MHz by trimming an internal capacitor. Bits 0-9 of the OSCTL (oscillator control) register allow you to set in an additional offset (trim) to this preset value to increase or decrease capacitance. Each unit added or subtracted changes the output frequency by about 0.078% of 8 MHz, allowing incremental adjustment until the desired frequency accuracy is achieved. The center frequency of the internal oscillator is calibrated at the factory to 8 MHz and the TRIM value is stored in the flash information block and loaded to the FMOPT1 register at reset. When using the relaxation oscillator, the boot code should read the FMOPT1 register and set this value as OSCTL TRIM. For further information, see the MC56F8006 Peripheral Reference Manual. 6.4.2 Crystal Oscillator/Ceramic Resonator The internal crystal oscillator circuit is designed to interface with a parallel-resonant crystal resonator in the frequency range, specified for the external crystal, of 32.768 kHz (Typ) or 1-16 MHz. A ceramic resonator can be substituted for the 1-16 MHz range. When used to supply a source to the internal PLL, the recommended crystal/resonator is in the 4 MHz to 8 MHz (recommend 8 MHz) range to achieve optimized PLL performance. Oscillator circuits are shown in Figure 10, Figure 11, and Figure 12. Follow the crystal supplier's recommendations when selecting a crystal, because crystal parameters determine the component values required to provide maximum stability and reliable start-up. The load capacitance values used in the oscillator circuit design should include all stray layout capacitances. The crystal and associated components should be mounted as near as possible to the EXTAL and XTAL pins to minimize output distortion and start-up stabilization time. When using low-frequency, low-power mode, the only external component is the crystal itself. In the other oscillator modes, load capacitors (Cx, Cy) and feedback resistor (RF) are required. In addition, a series resistor (RS) may be used in high-gain modes. Recommended component values are listed in Table 28. MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 Freescale Semiconductor 35 General System Control Information 56F8002/56F8006 XTAL EXTAL Crystal Frequency = 32-38.4 kHz Figure 10. Typical Crystal Oscillator Circuit: Low-Range, Low-Power Mode 56F8002/56F8006 XTAL EXTAL Crystal Frequency = 1-16 MHz RF C2 C1 Figure 11. Typical Crystal or Ceramic Resonator Circuit: High-Range, Low-Power Mode 56F8002/56F8006 XTAL Low Range: Crystal Frequency = 32-38.4 kHz or High Range: Crystal Frequency = 1-16 MHz EXTAL RS RF C1 C2 Figure 12. Typical Crystal or Ceramic Resonator Circuit: Low Range and High Range, High-Gain Mode 6.4.3 External Clock Input -- Crystal Oscillator Option The recommended method of connecting an external clock is illustrated in Figure 13. The external clock source is connected to XTAL and the EXTAL pin is grounded or configured as GPIO while CLK_MOD bit in OSCTL register is set. The external clock input must be generated using a relatively low impedance driver with maximum frequency less than 8 MHz. MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 36 Freescale Semiconductor General System Control Information 56F8006/56F8002 CLK_MOD = 1 XTAL EXTAL External Clock (<50 MHz) GND or GPIO Figure 13. Connecting an External Clock Signal Using XTAL 6.4.4 Alternate External Clock Input The recommended method of connecting an external clock is illustrated in Figure 14. The external clock source is connected to GPIOB6/RXD/SDA/ANA13 and CMP0_P2/CLKIN while EXT_SEL bit in OSCTL register is set and corresponding bits in GPIOB_PER register GPIO module and GPSB1 register in the system integration module (SIM) are set to the correct values. The external clock input must be generated using a relatively low impedance driver with maximum frequency not greater than 64 MHz. EXT_SEL = 1; GPIO_B_PER[6] = 0; 56F8002/56F8006 GPIOB6/RXD/SDA/ANA13 and CMP0_P2/CLKIN GPS_B6 = 11 External Clock ( 64 MHz) Figure 14. Connecting an External Clock Signal Using GPIO 6.5 Interrupt Controller The 56F8006/56F8002 interrupt controller (INTC) module arbitrates the various interrupt requests (IRQs). The INTC signals to the 56800E core when an interrupt of sufficient priority exists and what address to jump to to service this interrupt. The interrupt controller contains registers that allow up to three interrupt sources to be set to priority level 1 and other up to three interrupt sources to be set to priority level 2. By default, all peripheral interrupt sources are set to priority level 0. Next, all of the interrupt requests of a given level are priority encoded to determine the lowest numeric value of the active interrupt requests for that level. Within a given priority level, the lowest vector number is the highest priority and the highest vector number is the lowest. The highest vector number, a user assignable vector USER6 (vector 50), can be defined as a fast interrupt if the instruction located in this vector location is not a JSR or BSR instruction. Please see section 9.3.3.3 of DSP56800E 16-Bit Core Reference Manual for detail. 6.6 System Integration Module (SIM) The SIM module is a system catchall for the glue logic that ties together the system-on-chip. It controls distribution of resets and clocks and provides a number of control features including the pin muxing control; inter-module connection control (for example connecting comparator output to PWM fault input); individual peripheral enable/disable; PWM, timer, and SCI clock rate control; enabling peripheral operation in stop mode; port configuration overwrite protection. For further information, see the MC56F8006 Peripheral Reference Manual. The SIM is responsible for the following functions: * * * * Chip reset sequencing Core and peripheral clock control and distribution Stop/wait mode control System status control MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 Freescale Semiconductor 37 General System Control Information * * * * * * * * * * * * * 6.7 Registers containing the JTAG ID of the chip Controls for programmable peripheral and GPIO connections Peripheral clocks for TMR and PWM and SCI with a high-speed (3X) option Power-saving clock gating for peripherals Controls the enable/disable functions of large regulator standby mode with write protection capability Permits selected peripherals to run in stop mode to generate stop recovery interrupts Controls for programmable peripheral and GPIO connections Software chip reset I/O short address base location control Peripheral protection control to provide runaway code protection for safety-critical applications Controls output of internal clock sources to CLKO pin Four general-purpose software control registers are reset only at power-on Peripherals stop mode clocking control PWM, PDB, PGA, and ADC Connections The comparators, timers, and PWM_reload_sync output can be connected to the programmable delay block (PDB) trigger input. The PDB pre-trigger A and trigger A outputs are connected to the ADCA and PGA0 hardware trigger inputs. The PDB pre-trigger B and trigger B outputs are connected to the ADCB and PGA1 hardware trigger inputs. When the input trigger of PDB is asserted, PDB trigger and pre-trigger outputs are asserted after a delay of a pre-programmed period. See the MC56F8006 Peripheral Reference Manual for additional information. CMP0 CMP1 CMP2 PWM EXT TMR0 TMR1 SW Trigger0 Trigger1 Trigger2 Trigger3 Trigger4 Trigger5 Trigger6 Trigger7 System Clock Programmable Delay Block (PDB) TriggerA PrePreTriggerA TriggerB TriggerB SSEL[1] ADCA SSEL[0] SSEL[0] ADCA Trigger ADHWT ANA7 ANA9 SSEL[1] ADCB Trigger ANA15 ADCB ADHWT ANB15 ANB8 - PGA1 Controller + - + PGA0 Controller ANB6 Figure 15. Synchronization of ADC, PDB MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 38 Freescale Semiconductor Security Features Each ADC contains a temperature sensor. Outputs of temperature sensors, PGAs, on-chip regulators and VDDA are internally routed to ADC inputs. * * * * * * * * * * * * * 6.8 Internal PGA0 output available on ANA15 Internal PGA0 positive input calibration voltage available on ANA16 Internal PGA0 negative input calibration voltage available on ANA17 Internal PGA1 output available on ANB15 Internal PGA1 positive input calibration voltage available on ANB16 Internal PGA1 negative input calibration voltage available on ANB17 ADCA temperature sensor available on ANA26 ADCB temperature sensor available on ANB26 Output of on-chip digital voltage regulator is routed to ANA24 Output of on-chip analog voltage regulator is routed to ANA25 Output of on-chip small voltage regulator for ROSC is routed to ANB24 Output of on-chip small voltage regulator for PLL is routed to ANB25 VDDA is routed to ANA27 and ANB27 Joint Test Action Group (JTAG)/Enhanced On-Chip Emulator (EOnCE) The DSP56800E Family includes extensive integrated support for application software development and real-time debugging. Two modules, the Enhanced On-Chip Emulation module (EOnCE) and the core test access port (TAP, commonly called the JTAG port), work together to provide these capabilities. Both are accessed through a common 4-pin JTAG/EOnCE interface. These modules allow you to insert the 56F8006/56F8002 into a target system while retaining debug control. This capability is especially important for devices without an external bus, because it eliminates the need for a costly cable to bring out the footprint of the chip, as is required by a traditional emulator system. The DSP56800E EOnCE module is a Freescale-designed module used to develop and debug application software used with the chip. This module allows non-intrusive interaction with the CPU and is accessible through the pins of the JTAG interface or by software program control of the DSP56800E core. Among the many features of the EOnCE module is the support for data communication between the controller and the host software development and debug systems in real-time program execution. Other features allow for hardware breakpoints, the monitoring and tracking of program execution, and the ability to examine and modify the contents of registers, memory, and on-chip peripherals, all in a special debug environment. No user-accessible resources need to be sacrificed to perform debugging operations. The DSP56800E JTAG port is used to provide an interface for the EOnCE module to the DSP JTAG pins. Joint Test Action Group (JTAG) boundary scan is an IEEE 1149.1 standard methodology enabling access to test features using a test access port (TAP). A JTAG boundary scan consists of a TAP controller and boundary scan registers. Please contact your Freescale sales representative or authorized distributor for device-specific BSDL information. NOTE In normal operation, an external pullup on the TMS pin is highly recommend to place the JTAG state machine in reset state if this pin is not configured as GPIO. 7 Security Features The 56F8006/56F8002 offers security features intended to prevent unauthorized users from reading the contents of the flash memory (FM) array. The 56F8006/56F8002's flash security consists of several hardware interlocks that prevent unauthorized users from gaining access to the flash array. After flash security is set, an authorized user can be enabled to access on-chip memory if a user-defined software subroutine, which reads and transfers the contents of internal memory via peripherals, is included in the application software. This MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 Freescale Semiconductor 39 Security Features application software could communicate over a serial port, for example, to validate the authenticity of the requested access, then grant it until the next device reset. The inclusion of such a back door technique is at the discretion of the system designer. 7.1 Operation with Security Enabled After you have programmed flash with the application code, or as part of the programming of the flash with the application code, the 56F8006/56F8002 can be secured by programming the security word, 0x0002, into program memory location 0x00 1FF7. This can also be effected by use of the CodeWarrior IDE menu flash lock command. This nonvolatile word keeps the device secured after reset, caused, for example, by a power-down of the device. Refer to the flash memory chapter in the MC56F8006 Peripheral Reference Manual for detail. When flash security mode is enabled, the 56F8006/56F8002 disables the core EOnCE debug capabilities. Normal program execution is otherwise unaffected. 7.2 Flash Access Lock and Unlock Mechanisms There are several methods that effectively lock or unlock the on-chip flash. 7.2.1 Disabling EOnCE Access On-chip flash can be read by issuing commands across the EOnCE port, which is the debug interface for the 56800E CPU. The TCK, TMS, TDO, and TDI pins comprise a JTAG interface onto which the EOnCE port functionality is mapped. When the device boots, the chip-level JTAG TAP (test access port) is active and provides the chip's boundary scan capability and access to the ID register, but proper implementation of flash security blocks any attempt to access the internal flash memory via the EOnCE port when security is enabled. This protection is effective when the device comes out of reset, even prior to the execution of any code at startup. 7.2.2 Flash Lockout Recovery Using JTAG If the device is secured, one lockout recovery mechanism is the complete erasure of the internal flash contents, including the configuration field, thus disabling security (the protection register is cleared). This does not compromise security, as the entire contents of your secured code stored in flash are erased before security is disabled on the device on the next reset or power-up sequence. To start the lockout recovery sequence via JTAG, the JTAG public instruction (LOCKOUT_RECOVERY) must first be shifted into the chip-level TAP controller's instruction register. After the LOCKOUT_RECOVERY instruction has been shifted into the instruction register, the clock divider value must be shifted into the corresponding 7-bit data register. After the data register has been updated, you must transition the TAP controller into the RUN-TEST/IDLE state for the lockout sequence to commence. The controller must remain in this state until the erase sequence is complete. Refer to the MC56F8006 Peripheral Reference Manual for detail, or contact Freescale. NOTE After the lockout recovery sequence has completed, you must reset the JTAG TAP controller and device to return to normal unsecured operation. Power-on reset resets both too. 7.2.3 Flash Lockout Recovery Using CodeWarrior CodeWarrior can unlock a device by selecting the Debug menu, then selecting DSP56800E, followed by Unlock Flash. Another mechanism is also built into CodeWarrior using the device's memory configuration file. The command "Unlock_Flash_on_Connect 1" in the .cfg file accomplishes the same task as using the Debug menu. This lockout recovery mechanism is the complete erasure of the internal flash contents, including the configuration field, thus disabling security (the protection register is cleared). MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 40 Freescale Semiconductor Specifications 7.2.4 7.2.4.1 Flash Lockout Recovery without Mass Erase Without Presenting Back Door Access Keys to the Flash Unit A user can un-secure a secured device by programming the word 0x0000 into program flash location 0x00 1FF7. After completing the programming, the JTAG TAP controller and the device must be reset to return to normal unsecured operation. You are responsible for directing the device to invoke the flash programming subroutine to reprogram the word 0x0000 into program flash location 0x00 1FF7. This is done by, for example, toggling a specific pin or downloading a user-defined key through serial interfaces. NOTE Flash contents can be programmed only from 1s to 0s. 7.2.4.2 Presenting Back Door Access Key to the Flash Unit It is possible to temporarily bypass the security through a back door access scheme, using a 4-word key, to temporarily unlock of the flash. A back door access requires support from the embedded software. This software would typically permit an external user to enter a four word code through one of the communications interfaces and then use it to attempt the unlock sequence. If your input matches the four word code stored at location 0x00 1FFC-0x00 1FFF in the flash memory, the part immediately becomes unsecured (at runtime) and you can access internal memory via JTAG/EOnCE port. Refer to the MC56F8006 Peripheral Reference Manual for detail. The key must be entered in four consecutive accesses to the flash, so this routine should be designed to run in RAM. 7.3 Product Analysis The recommended method of unsecuring a secured device for product analysis of field failures is via the method described in Section 7.2.4.2, "Presenting Back Door Access Key to the Flash Unit." The customer would need to supply technical support with the details of the protocol to access the subroutines in flash memory. An alternative method for performing analysis on a secured device would be to mass-erase and reprogram the flash with the original code, but modify the security word or not program the security word. 8 Specifications 8.1 General Characteristics The 56F8006/56F8002 is fabricated in high-density low power and low leakage CMOS with a maximum voltage of 3.6 V digital inputs during normal operation without causing damage. Absolute maximum ratings in Table 12 are stress ratings only, and functional operation at the maximum is not guaranteed. Stress beyond these ratings may affect device reliability or cause permanent damage to the device. Unless otherwise stated, all specifications within this chapter apply over the temperature range of -40C to 105C ambient temperature over the following supply ranges: VSS = VSSA = 0V, VDD = VDDA = 3.0-3.6 V, CL < 50 pF, fOP = 32 MHz CAUTION This device contains protective circuitry to guard against damage due to high static voltage or electrical fields. However, normal precautions are advised to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate voltage level. MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 Freescale Semiconductor 41 Specifications 8.2 Absolute Maximum Ratings Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the limits specified Table 12 may affect device reliability or cause permanent damage to the device. For functional operating conditions, refer to the remaining tables in this section. This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, take normal precautions to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for instance, either VSS or VDD) or the programmable pullup resistor associated with the pin is enabled. Table 12. Absolute Maximum Ratings (VSS = 0 V, VSSA = 0 V) Characteristic Symbol Supply Voltage Range Notes Min Max Unit VDD -0.3 3.8 V Analog Supply Voltage Range VDDA -0.3 3.6 V Voltage difference VDD to VDDA VDD -0.3 0.3 V Voltage difference VSS to VSSA VSS -0.3 0.3 V Digital Input Voltage Range VIN Pin Groups 1, 2 -0.3 VDD+0.3 V Oscillator Voltage Range VOSC Pin Group 4 TBD TBD V Analog Input Voltage Range VINA Pin Group 3 -0.3 3.6 V Input clamp current, per pin (VIN < 0)1 2 3 VIC -- -25.0 mA 0)1 2 3 VOC -- -20.0 mA -0.3 VDD V TA -40 105 C TSTG -55 150 C Output clamp current, per pin (VO < Output Voltage Range (Normal Push-Pull mode) Ambient Temperature Industrial Storage Temperature Range (Extended Industrial) VOUT Pin Group 1 1 Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive (VDD) and negative (VSS) clamp voltages, then use the larger of the two resistance values. 2 All functional non-supply pins are internally clamped to V SS and VDD. 3 Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current conditions. If positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could result in external power supply going out of regulation. Ensure external VDD loads shunt current greater than maximum injection current. This is the greatest risk when the MCU is not consuming power. Examples are: if no system clock is present or if the clock rate is low (which would reduce overall power consumption). 8.2.1 ESD Protection and Latch-Up Immunity Although damage from electrostatic discharge (ESD) is much less common on these devices than on early CMOS circuits, use normal handling precautions to avoid exposure to static discharge. Qualification tests are performed to ensure that these devices can withstand exposure to reasonable levels of static without suffering any permanent damage. All ESD testing is in conformity with AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits. During the device qualification ESD stresses were performed for the human body model (HBM), the machine model (MM), and the charge device model (CDM). MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 42 Freescale Semiconductor Specifications A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device specification. Complete DC parametric and functional testing is performed per the applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification. Table 13. ESD and Latch-up Test Conditions Model Description Symbol Value Unit Series Resistance R1 1500 Storage Capacitance C 100 pF Number of Pulses per Pin -- 3 Series Resistance R1 0 Storage Capacitance C 200 pF Number of Pulses per Pin -- 3 Human Body Machine Minimum inpUt Voltage Limit -2.5 V Maximum Input Voltage Limit 7.5 V Latch-up Table 14. 56F8006/56F8002 ESD Protection 1 8.3 Characteristic 1 Min Typ Max Unit ESD for Human Body Model (HBM) 2000 -- -- V ESD for Machine Model (MM) 200 -- -- V ESD for Charge Device Model (CDM) 750 -- -- V Latch-up current at TA= 85oC (ILAT) 100 mA Parameter is achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. Thermal Characteristics This section provides information about operating temperature range, power dissipation, and package thermal resistance. Power dissipation on I/O pins is usually small compared to the power dissipation in on-chip logic and voltage regulator circuits, and it is user-determined rather than being controlled by the MCU design. To take PI/O into account in power calculations, determine the difference between actual pin voltage and VSS or VDD and multiply by the pin current for each I/O pin. Except in cases of unusually high pin current (heavy loads), the difference between pin voltage and VSS or VDD will be very small. Table 15. 28SOIC Package Thermal Characteristics Characteristic Comments Symbol Value (LQFP) Unit Junction to ambient Natural convection Single layer board (1s) RJA 70 C/W Junction to ambient Natural convection Four layer board (2s2p) RJMA 47 C/W Junction to ambient (@200 ft/min) Single layer board (1s) RJMA 55 C/W MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 Freescale Semiconductor 43 Specifications Table 15. 28SOIC Package Thermal Characteristics (continued) Characteristic Comments Symbol Value (LQFP) Unit Junction to ambient (@200 ft/min) Four layer board (2s2p) RJMA 42 C/W Junction to board RJB 23 C/W Junction to case RJC 26 C/W JT 9 C/W Junction to package top Natural Convection Table 16. 32LQFP Package Thermal Characteristics Characteristic Comments Symbol Value (LQFP) Unit Junction to ambient Natural convection Single layer board (1s) RJA 84 C/W Junction to ambient Natural convection Four layer board (2s2p) RJMA 56 C/W Junction to ambient (@200 ft/min) Single layer board (1s) RJMA 70 C/W Junction to ambient (@200 ft/min) Four layer board (2s2p) RJMA 49 C/W Junction to board RJB 33 C/W Junction to case RJC 20 C/W JT 4 C/W Junction to package top Natural convection Table 17. 32PSDIP Package Thermal Characteristics Characteristic Comments Symbol Value (LQFP) Unit Junction to ambient Natural convection Single layer board (1s) RJA 56 C/W Junction to ambient Natural convection Four layer board (2s2p) RJMA 41 C/W Junction to ambient (@200 ft/min) Single layer board (1s) RJMA 45 C/W Junction to ambient (@200 ft/min) Four layer board (2s2p) RJMA 36 C/W Junction to board RJB 18 C/W Junction to case RJC 24 C/W JT 10 C/W Junction to package top Natural convection MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 44 Freescale Semiconductor Specifications Table 18. 48LQFP Package Thermal Characteristics Characteristic Comments Symbol Value (LQFP) Unit Junction to ambient Natural convection Single layer board (1s) RJA 79 C/W Junction to ambient Natural convection Four layer board (2s2p) RJMA 55 C/W Junction to ambient (@200 ft/min) Single layer board (1s) RJMA 66 C/W Junction to ambient (@200 ft/min) Four layer board (2s2p) RJMA 48 C/W Junction to board RJB 34 C/W Junction to case RJC 20 C/W JT 4 C/W Junction to package top Natural Convection NOTE Junction-to-ambient thermal resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test board meets JEDEC specification for this package. Junction-to-board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC specification for the specified package. Junction-to-case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate temperature is used for the case temperature. Reported value includes the thermal resistance of the interface layer. Thermal characterization parameter indicating the temperature difference between the package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. See Section 9.1, "Thermal Design Considerations," for more detail on thermal design considerations. 8.4 Recommended Operating Conditions This section includes information about recommended operating conditions. MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 Freescale Semiconductor 45 Specifications Table 19. Recommended Operating Conditions (VREFL x= 0 V, VSSA = 0 V, VSS = 0 V) 1 Characteristic Symbol Supply voltage Notes Min Typ Max Unit VDD, VDDA 3 3.3 3.6 V Voltage difference VDD to VDDA VDD -0.1 0 0.1 V Voltage difference VSS to VSSA VSS -0.1 0 0.1 V Device Clock Frequency Using relaxation oscillator Using external clock source FSYSCLK 1 0 32 32 MHz Input Voltage High (digital inputs) VIH Pin Groups 1, 2 2.0 VDD V Input Voltage Low (digital inputs) VIL Pin Groups 1, 2 -0.3 0.8 V Oscillator Input Voltage High XTAL driven by an external clock source VIHOSC Pin Group 4 2.0 VDDA + 0.3 V Oscillator Input Voltage Low VILOSC Pin Group 4 -0.3 0.8 V Output Source Current High at VOH min.)1 When programmed for low drive strength When programmed for high drive strength IOH Pin Group 1 Pin Group 1 -- -- -4 -8 mA Output Source Current Low (at VOL max.)1 When programmed for low drive strength When programmed for high drive strength IOL Pin Groups 1, 2 Pin Groups 1, 2 -- -- 4 8 mA Ambient Operating Temperature (Extended Industrial) TA -40 105 C Flash Endurance (Program Erase Cycles) NF TA = -40C to 125C 10,000 -- cycles Flash Data Retention tR TJ 85C avg 15 -- years Flash Data Retention with <100 Program/Erase Cycles tFLRET TJ 85C avg 20 -- years -- Total chip source or sink current cannot exceed 75 mA. Table 20. Default Mode 8.5 Pin Group 1 GPIO, TDI, TDO, TMS, TCK Pin Group 2 SCL, SDA Pin Group 3 ADC and Comparator Analog Inputs and PGA Inputs Pin Group 4 XTAL, EXTAL DC Electrical Characteristics This section includes information about power supply requirements and I/O pin characteristics. MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 46 Freescale Semiconductor Specifications Table 21. DC Characteristics Characteristic Symbol Condition Min Typ 1 1.82 Operating Voltage Output high voltage All I/O pins, low-drive strength VOH All I/O pins, high-drive strength Output high current Output low voltage Max total IOH for all ports IOHT All I/O pins, low-drive strength VOL All I/O pins, high-drive strength Output low current Max total IOL for all ports IOLT Input high voltage all digital inputs VIH Input low voltage all digital inputs Input hysteresis VIL Max Ambient temperature Unit operating range 3.6 V V 1.8 V, ILoad = -2 mA VDD - 0.5 -- -- 2.7 V, ILoad = -10 mA VDD - 0.5 -- -- 2.3 V, ILoad = -6 mA VDD - 0.5 -- -- 1.8 V, ILoad = -3 mA VDD - 0.5 -- -- -- -- 100 mA 1.8 V, ILoad = 2 mA -- -- 0.5 V 2.7 V, ILoad = 10 mA -- -- 0.5 2.3 V, ILoad = 6 mA -- -- 0.5 1.8 V, ILoad = 3 mA -- -- 0.5 -- -- 100 mA VDD 2.7 V 0.70 x VDD -- -- V VDD 1.8 V 0.85 x VDD -- -- VDD 2.7 V -- -- 0.35 x VDD VDD 1.8 V -- -- 0.30 x VDD 0.06 x VDD -- -- mV --40 C ~ +125 C all digital inputs Vhys all input only pins (Per pin) |IIn| VIn = VDD or VSS -- -- 1 A Hi-Z (off-state) leakage current all input/output (per pin) |IOZ| VIn = VDD or VSS -- -- 1 A Pullup resistors all digital inputs, when enabled RPU 17.5 -- 52.5 k -0.2 -- 0.2 mA -5 -- 5 mA CIn -- -- 8 pF RAM retention voltage VRAM -- 0.6 1.0 V POR re-arm voltage6 VPOR 0.9 1.4 1.79 V POR re-arm time tPOR 10 -- -- s Input leakage current DC injection current 3, 4, 5 Single pin limit IIC Total MCU limit, includes sum of all stressed pins Input Capacitance, all pins VIn < VSS, VIn > VDD MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 Freescale Semiconductor 47 Specifications Table 21. DC Characteristics (continued) Characteristic Low-voltage detection threshold -- high range7 Low-voltage warning threshold Max Ambient temperature Unit operating range Symbol Condition Min Typ VLVDH8 VDD falling 2.31 2.34 2.36 2.16 2.3 2.48 --40 C ~ +125 C 2.38 2.44 2.47 -40 C ~ 105 C 2.23 2.39 2.49 --40 C ~ +125 C 1.8 1.84 1.87 N/A N/A N/A --40 C ~ +125 C VDD rising 1.88 1.93 1.96 -40 C ~ 105 C VDD falling 2.58 2.62 2.71 2.5 2.61 2.74 --40 C ~ +125 C 2.59 2.67 2.74 -40 C ~ 105 C 2.51 2.66 2.79 --40 C ~ +125 C VDD rising Low-voltage detection threshold -- low range7 1 VLVDL VLVW9 VDD falling VDD rising V V V -40 C ~ 105 C -40 C ~ 105 C -40 C ~ 105 C Low-voltage inhibit reset/recover hysteresis7 Vhys -- 50 -- mV --40 C ~ +105 C Bandgap Voltage Reference10 VBG 1.15 1.17 1.18 V -40 C ~ 105 C 1.14 1 2 3 4 5 6 7 --40 C ~ +125 C Typical values are measured at 25 C. Characterized, not tested As the supply voltage rises, the LVD circuit holds the MCU in reset until the supply has risen above VLVDL. If the system clock frequency < 16 MHz, VDD can be 1.7 V to 3.6 V. All functional non-supply pins are internally clamped to VSS and VDD. Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then use the larger of the two values. Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current conditions. If positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could result in external power supply going out of regulation. Ensure external VDD load shunts current greater than maximum injection current. This is the greatest risk when the MCU is not consuming power. Examples are: if no system clock is present or if clock rate is low (which would reduce overall power consumption). Maximum is highest voltage that POR is guaranteed. Low voltage detection and warning limits measured at 32 MHz bus frequency. This characteristic is not applicable to devices with a temperature range from -40 C to 125 C. Please see the PMC chapter in the reference manual for details. MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 48 Freescale Semiconductor Specifications 8 Runs at 32 MHz bus frequency. Both Low Voltage Warning (LVW) and Out Of Regulation (OOR) sample the same input source. The OOR flag is a stick bit which is in the PMC_SCR register. 10 Factory trimmed at VDD = 3.3 V, Temp = 25 C. PULLDOWN RESISTANCE (kW) PULLUP RESISTOR (kW) 9 PULLUP RESISTOR TYPICALS 85C 25C -40C 40 35 30 25 20 1.8 2 2.2 2.4 2.6 2.8 3 VDD (V) 3.2 3.4 3.6 PULLDOWN RESISTOR TYPICALS 85C 25C -40C 40 35 30 25 20 1.8 2.3 2.8 VDD (V) 3.3 3.6 Figure 16. Pullup and Pulldown Typical Resistor Values TYPICAL VOL VS IOL AT VDD = 3.0 V 1.2 1 TYPICAL VOL VS VDD 0.2 85C 25C -40C 0.15 VOL (V) VOL (V) 0.8 0.6 0.4 0.1 85C, IOL = 2 mA 25C, IOL = 2 mA -40C, IOL = 2 mA 0.05 0.2 0 0 0 5 10 IOL (mA) 15 1 20 2 VDD (V) 3 4 Figure 17. Typical Low-Side Driver (Sink) Characteristics -- Low Drive (GPIO_x_DRIVEn = 0) 0.4 85C 25C -40C 0.8 85C 25C -40C 0.3 0.6 VOL (V) VOL (V) TYPICAL VOL VS VDD TYPICAL VOL VS IOL AT VDD = 3.0 V 1 0.4 0.2 0.2 0.1 0 0 IOL = 10 mA IOL = 6 mA IOL = 3 mA 0 10 20 30 1 2 IOL (mA) 3 4 VDD (V) Figure 18. Typical Low-Side Driver (Sink) Characteristics -- High Drive (GPIO_x_DRIVEn = 1) MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 Freescale Semiconductor 49 Specifications TYPICAL VDD - VOH VS IOH AT VDD = 3.0 V 85C 25C -40C 1 TYPICAL VDD - VOH VS VDD AT SPEC IOH 0.25 VDD - VOH (V) VDD - VOH (V) 1.2 0.8 85C, IOH = 2 mA 25C, IOH = 2 mA -40C, IOH = 2 mA 0.2 0.15 0.6 0.4 0.1 0.05 0.2 0 0 0 -5 -10 IOH (mA)) -15 -20 1 2 3 VDD (V) 4 Figure 19. Typical High-Side (Source) Characteristics -- Low Drive (GPIO_x_DRIVEn = 0) TYPICAL VDD - VOH VS VDD AT SPEC IOH TYPICAL VDD - VOH VS IOH AT VDD = 3.0 V 85C 25C -40C 0.8 0.6 0.4 0.2 0 0 -5 -10 -15 -20 IOH (mA) -25 -30 VDD - VOH (V) VDD - VOH (V) 0.4 85C 25C -40C 0.3 0.2 IOH = -10 mA IOH = -6 mA IOH = -3 mA 0.1 0 1 2 3 4 VDD (V) Figure 20. Typical High-Side (Source) Characteristics -- High Drive (GPIO_x_DRIVEn = 1) MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 50 Freescale Semiconductor Specifications 8.6 Supply Current Characteristics Table 22. Supply Current Consumption Mode Conditions Typical @ 3.3 V, 25 C Maximum @ 3.6 V, 105 C Maximum @ 3.6 V, 125 C IDD1 IDDA IDD1 IDDA IDD1 IDDA 41.52 mA 1.71 mA 53 mA 2.7 mA 53 mA 2.9 mA LSrun 2 200 kHz device clock; 340.75 A 1.70 mA relaxation oscillator (ROSC) in standby mode; PLL disabled All peripheral modules disabled and clock gated off; simple loop with fetches from program flash; 480 A 2.5 mA 495 A 2.6 mA LPrun 3 32.768 kHz device clock; 166.30 A 1.74 mA Clocked by a 32.768 kHz external crystal relaxation oscillator (ROSC) in power down; PLL disabled All peripheral modules disabled and clock gated off; simple loop with fetches from program flash; 390 A 3.4 mA 399 A 3.8 mA 32 MHz device clock relaxation oscillator (ROSC) in high speed mode PLL engaged; All non-communication peripherals enabled and running; all communication peripherals disabled but clocked; processor core in wait state 1.78 mA 28 mA 2.7 mA 28 mA 2.8 mA 265.42 A 1.70 mA 380 A 2.5 mA 398 A 2.6 mA Run Wait LSwait 2 32 MHz device clock; relaxation oscillator (ROSC) in high speed mode; PLL engaged; All peripheral modules enabled. TMR and PWM using 1X clock; continuous MAC instructions with fetches from program flash; ADC/DAC powered on and clocked; comparator powered on. 200 kHz device clock; relaxation oscillator (ROSC) in standby mode; PLL disabled; All peripheral modules disabled and clock gated off; processor core in wait state 19.3 mA MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 Freescale Semiconductor 51 Specifications Table 22. Supply Current Consumption (continued) Mode Conditions Typical @ 3.3 V, 25 C IDD1 LPwait 3 Stop 32.768 kHz device clock; Clocked by a 32.768 kHz external crystal oscillator in power down; PLL disabled; All peripheral modules disabled and clock gated off; processor core in wait state 32 MHz device clock relaxation oscillator (ROSC) in high speed mode; PLL engaged; all peripheral module and core clocks are off; ADC/DAC/comparator powered off; processor core in stop state LSstop 2 200 kHz device clock; relaxation oscillator (ROSC) in standby mode; PLL disabled; all peripheral modules disabled and clock gated off; processor core in stop state. LPstop 2 32.768 kHz device clock; Clocked by a 32.768 kHz external crystal relaxation oscillator (ROSC) in power down; PLL disabled; all peripheral modules disabled and clock gated off; processor core in stop state. PPD 4 with 32.768 kHz clock fed on XTAL XOSC RTC or COP monitoring XOSC (but no wakeup) processor core in stop state Maximum @ 3.6 V, 125 C IDD1 IDDA IDD1 IDDA 157.55 A 1.57 mA 380 A 3.4 mA 398 A 3.6 mA 65.51 A 9.8 mA 130 A 10.3 mA 132 A 194.69 A 65.51 A 340 A 120 A 357 A 123 A 13.99 nA 45 A 3.0 A 58 A 3.6 A 879.72 nA 11.56 nA 18 A 2.4 A 22 A 3.0 A 13.9 nA 14 A 2.4 A 17 A 2.8 mA 494.04 nA 12.88 nA 14 A 2.4 A 17 A 2.8 A 8.21 mA 2.77 A PPD with LP RTC or COP monitoring LP oscillator (but no 499.15 nA oscillator wakeup); (1 kHz) processor core in stop state. enabled PPD with no RTC and LP oscillator are disabled; clock processor core in stop state. monitoring Maximum @ 3.6 V, 105 C IDDA 1 No output switching; all ports configured as inputs; all inputs low; no DC loads. Low speed mode: LPR (lower voltage regulator control bit) = 0 and voltage regulator is in full regulation. Characterization only. 3 Low power mode: LPR (lower voltage regulator control bit) = 1; the voltage regulator is put into standby. 4 Partial power down mode: PPDE (partial power down enable bit) = 1; power management controller (PMC) enters partial power down mode the next time that the STOP command is executed. 2 MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 52 Freescale Semiconductor Specifications 8.7 Flash Memory Characteristics Table 23. Flash Timing Parameters Characteristic Symbol Min Typ Max Unit Program time1 tprog 20 -- 40 s terase 20 -- -- ms tme 100 -- -- ms Erase time 2 Mass erase time 1 There is additional overhead that is part of the programming sequence. See the MC56F8006 Peripheral Reference Manual for detail. 2 Specifies page erase time. There are 512 bytes per page in the program flash memory. 8.8 External Clock Operation Timing Table 24. External Clock Operation Timing Requirements1 Characteristic Symbol Min Typ Max Unit Frequency of operation (external clock driver)2 fosc -- -- 64 MHz Clock pulse width3 tPW 6.25 -- -- ns 4 trise -- -- 3 ns 5 tfall -- -- 3 ns Input high voltage overdrive by an external clock Vih 0.85VDD -- -- V Input high voltage overdrive by an external clock Vil -- -- 0.3VDD V External clock input rise time External clock input fall time 1 Parameters listed are guaranteed by design. See Figure 21 for detail on using the recommended connection of an external clock driver. 3 The chip may not function if the high or low pulse width is smaller than 6.25 ns. 4 External clock input rise time is measured from 10% to 90%. 5 External clock input fall time is measured from 90% to 10%. 2 External Clock 90% 50% 10% tfall tPW trise VIH 90% 50% 10% VIL tPW Note: The midpoint is VIL + (VIH - VIL)/2. Figure 21. External Clock Timing MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 Freescale Semiconductor 53 Specifications 8.9 Phase Locked Loop Timing Table 25. Phase Locked Loop Timing Characteristic Symbol Min Typ Max Unit PLL input reference frequency1 fref 4 8 -- MHz fop 120 192 -- MHz tplls -- 40 100 s Accumulated jitter using an 8 MHz external crystal as the PLL source5 JA -- -- 0.37 % Cycle-to-cycle jitter tjitterpll -- 350 -- ps PLL output frequency2 34 PLL lock time 1 2 3 4 5 An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work correctly. The PLL is optimized for 8 MHz input. The core system clock operates at 1/6 of the PLL output frequency. This is the time required after the PLL is enabled to ensure reliable operation. From powerdown to powerup state at 32 MHz system clock state. This is measured on the CLKO signal (programmed as system clock) over 264 system clocks at 32 MHz system clock frequency and using an 8 MHz oscillator frequency. 8.10 Relaxation Oscillator Timing Table 26. Relaxation Oscillator Timing Characteristic Symbol Minimum Typical Relaxation oscillator output frequency1 Normal Mode Standby Mode fop Relaxation oscillator stabilization time2 troscs Variation over temperature -40 C to 105 C4 C5 Variation over temperature -40 C to 125 C 4 Unit -- 8.05 400 Cycle-to-cycle jitter. This is measured on the CLKO signal tjitterrosc (programmed prescaler_clock) over 264 clocks3 Variation over temperature 0 C to 105 -- Maximum MHz kHz -- 1 3 ms -- 400 -- ps -- -- -3.0 to +2.0 % -- -- -2.0 to +2.0 % -- -- -3.5 to +3.0 % 1 Output frequency after factory trim. This is the time required from standby to normal mode transition. 3 J is required to meet QSCI requirements. A 4 See Figure 22. The power supply VDD must be greater than or equal to 2.6 V. Below 2.6 V, the maximum variation over the whole temperature and whole voltage range from 1.8 V to 2.6 V will be +/-16%. 5 This data is only applied to devices with temperature range from -40 C to 105 C. 2 MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 54 Freescale Semiconductor MHz Specifications Degrees C (Junction) Figure 22. Relaxation Oscillator Temperature Variation (Typical) After Trim for devices with temperature operating range from -40 C to 105 C Figure 23. Relaxation Oscillator Temperature Variation (Typical) After Trim for devices with temperature operating range from -40 C to 125 C MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 Freescale Semiconductor 55 Specifications 8.11 Reset, Stop, Wait, Mode Select, and Interrupt Timing NOTE All address and data buses described here are internal. Table 27. Reset, Stop, Wait, Mode Select, and Interrupt Timing1,2 Characteristic Symbol Typical Min Typical Max Unit See Figure Minimum RESET Assertion Duration tRA 4T -- ns -- Minimum GPIO pin Assertion for Interrupt tIW 2T -- ns Figure 24 RESET deassertion to First Address Fetch tRDA 96TOSC + 64T 97TOSC + 65T ns -- Delay from Interrupt Assertion to Fetch of first instruction (exiting Stop) tIF -- 6T ns -- 1 In the formulas, T = system clock cycle and Tosc = oscillator clock cycle. For an operating frequency of 32 MHz, T = 31.25 ns. At 4 MHz (used coming out of reset and stop modes), T = 250 ns. 2 Parameters listed are guaranteed by design. GPIO pin (Input) tIW Figure 24. GPIO Interrupt Timing (Negative Edge-Sensitive) 8.12 External Oscillator (XOSC) Characteristics Reference Figure 10, and Figure 11, and Figure 12 for crystal or resonator circuits. MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 56 Freescale Semiconductor Specifications Table 28. Crystal Oscillator Characteristics Characteristic Symbol Min Typ1 Max Unit flo fhi fhi 32 1 1 -- -- -- 38.4 16 8 kHz MHz MHz Oscillator crystal or resonator (PRECS = 1, CLK_MOD = 0) Low range (RANGE = 0) High range (RANGE = 1), high gain (COHL =0) High range (RANGE = 1), low power (COHL =1) Load capacitors Low range (RANGE=0), low power (COHL =1) Other oscillator settings C1,C2 Feedback resistor Low range, low power (RANGE=0, COHL =1)2 Low range, high gain (RANGE=0, COHL =0) High range (RANGE=1, COHL=X) RF Series resistor Low range, low power (RANGE = 0, COHL =1)2 Low range, high gain (RANGE = 0, COHL =0) High range, low power (RANGE = 1, COHL =1) High range, high gain (RANGE = 1,COHL =0) 8 MHz 4 MHz 1 MHz RS Crystal start-up time 4 Low range, low power Low range, high gain High range, low power High range, high gain t t Square wave input clock frequency (PRECS = 1, CLK_MOD = 1) See Note2 See Note3 M CSTL CSTH fxtal -- -- -- -- 10 1 -- -- -- -- -- -- 0 100 0 -- -- -- -- -- -- 0 0 0 0 10 20 -- -- -- -- TBD TBD TBD TBD -- -- -- -- ms -- -- 50.0 MHz k 1 Data in Typical column was characterized at 3.0 V, 25C or is typical recommended value. Load capacitors (C1,C2), feedback resistor (RF) and series resistor (RS) are incorporated internally when RANGE=HGO=0. 3 See crystal or resonator manufacturer's recommendation. 4 Proper PC board layout procedures must be followed to achieve specifications. 2 8.13 AC Electrical Characteristics Tests are conducted using the input levels specified in Table 22. Unless otherwise specified, propagation delays are measured from the 50% to the 50% point, and rise and fall times are measured between the 10% and 90% points, as shown in Figure 25. VIH Input Signal Low High 90% 50% 10% Midpoint1 Fall Time VIL Rise Time The midpoint is VIL + (VIH - VIL)/2. Figure 25. Input Signal Measurement References Figure 26 shows the definitions of the following signal states: * Active state, when a bus or signal is driven, and enters a low impedance state MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 Freescale Semiconductor 57 Specifications * * * Tri-stated, when a bus or signal is placed in a high impedance state Data Valid state, when a signal level has reached VOL or VOH Data Invalid state, when a signal level is in transition between VOL and VOH Data1 Valid Data2 Valid Data1 Data3 Valid Data2 Data3 Data Three-stated Data Invalid State Data Active Data Active Figure 26. Signal States 8.13.1 Serial Peripheral Interface (SPI) Timing Table 29. SPI Timing1 Characteristic Symbol Cycle time Master Slave tC Enable lead time Master Slave tELD Enable lag time Master Slave tELG Clock (SCK) high time Master Slave tCH Clock (SCK) low time Master Slave tCL Data set-up time required for inputs Master Slave tDS Data hold time required for inputs Master Slave tDH Access time (time to data active from high-impedance state) Slave tA Disable time (hold time to high-impedance state) Slave tD Min Max Unit See Figure 125 62.5 -- -- ns ns Figure 27, Figure 28, Figure 29, Figure 30 -- 31 -- -- ns ns -- 125 -- -- ns ns 50 31 -- -- ns ns 50 31 -- -- ns ns 20 0 -- -- ns ns Figure 27, Figure 28, Figure 29, Figure 30 0 2 -- -- ns ns Figure 27, Figure 28, Figure 29, Figure 30 4.8 15 ns 3.7 15.2 ns Figure 30 Figure 30 Figure 27, Figure 28, Figure 29, Figure 30 Figure 30 Figure 30 Figure 30 MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 58 Freescale Semiconductor Specifications Table 29. SPI Timing1 (continued) 1 Characteristic Symbol Data valid for outputs Master Slave (after enable edge) tDV Data invalid Master Slave tDI Rise time Master Slave tR Fall time Master Slave tF Min Max Unit See Figure -- -- 4.5 20.4 ns ns Figure 27, Figure 28, Figure 29, Figure 30 0 0 -- -- ns ns Figure 27, Figure 28, Figure 29, Figure 30 -- -- 11.5 10.0 ns ns Figure 27, Figure 28, Figure 29, Figure 30 -- -- 9.7 9.0 ns ns Figure 27, Figure 28, Figure 29, Figure 30 Parameters listed are guaranteed by design. SS (Input) SS is held high on master tC tR tF tCL SCLK (CPOL = 0) (Output) tCH tF tR tCL SCLK (CPOL = 1) (Output) tDH tCH tDS MISO (Input) MSB in tDI MOSI (Output) Master MSB out Bits 14-1 tDV Bits 14-1 tF LSB in tDI(ref) Master LSB out tR Figure 27. SPI Master Timing (CPHA = 0) MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 Freescale Semiconductor 59 Specifications SS (Input) SS is held High on master tC tF tR tCL SCLK (CPOL = 0) (Output) tCH tF tCL SCLK (CPOL = 1) (Output) tCH tDS tR MISO (Input) MSB in tDH Bits 14-1 tDI tDV(ref) MOSI (Output) LSB in tDV Master MSB out tDI(ref) Bits 14- 1 Master LSB out tF tR Figure 28. SPI Master Timing (CPHA = 1) SS (Input) tC tF tCL SCLK (CPOL = 0) (Input) tR tCH tELD tCL SCLK (CPOL = 1) (Input) tA MISO (Output) tCH Slave MSB out tDV tDH MSB in tF tR Bits 14-1 tDS MOSI (Input) tELG Bits 14-1 tD Slave LSB out tDI tDI LSB in Figure 29. SPI Slave Timing (CPHA = 0) MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 60 Freescale Semiconductor Specifications SS (Input) tF tC tR tCL SCLK (CPOL = 0) (Input) tCH tELG tELD tCL SCLK (CPOL = 1) (Input) tDV tCH tR tA MISO (Output) Slave MSB out Bits 14-1 tDS Slave LSB out tDV tDI tDH MOSI (Input) tD tF MSB in Bits 14-1 LSB in Figure 30. SPI Slave Timing (CPHA = 1) 8.13.2 Serial Communication Interface (SCI) Timing Table 30. SCI Timing1 Characteristic Symbol Min Max Unit See Figure Baud rate2 BR -- (fMAX/16) Mbps -- RXD pulse width RXDPW 0.965/BR 1.04/BR ns Figure 31 TXD pulse width TXDPW 0.965/BR 1.04/BR ns Figure 32 LIN Slave Mode 1 2 Deviation of slave node clock from nominal clock rate before synchronization FTOL_UNSYNCH -14 14 % -- Deviation of slave node clock relative to the master node clock after synchronization FTOL_SYNCH -2 2 % -- Minimum break character length TBREAK 13 -- Master node bit periods -- 11 -- Slave node bit periods -- Parameters listed are guaranteed by design. fMAX is the frequency of operation of the SCI in MHz, which can be selected system clock (max. 32 MHz) or 3x system clock (max. 96 MHz) for the 56F8006/56F8002 device. MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 Freescale Semiconductor 61 Specifications RXD SCI receive data pin (Input) RXDPW Figure 31. RXD Pulse Width TXD SCI receive data pin (Input) TXDPW Figure 32. TXD Pulse Width 8.13.3 Inter-Integrated Circuit Interface (I2C) Timing Table 31. I2C Timing Standard Mode Characteristic Symbol Unit Minimum Maximum SCL Clock Frequency fSCL 0 100 MHz Hold time (repeated) START condition. After this period, the first clock pulse is generated. tHD; STA 4.0 -- s LOW period of the SCL clock tLOW 4.7 -- s HIGH period of the SCL clock tHIGH 4.0 -- s Set-up time for a repeated START condition tSU; STA 4.7 -- s tHD; DAT 01 3.452 s Data set-up time tSU; DAT 250 -- ns Rise time of SDA and SCL signals tr -- 1000 ns Fall time of SDA and SCL signals tf -- 300 ns Set-up time for STOP condition tSU; STO 4.0 -- s Bus free time between STOP and START condition tBUF 4.7 -- s Pulse width of spikes that must be suppressed by the input filter tSP N/A N/A ns 2C Data hold time for I bus devices 1 The master mode I2C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves acknowledge this address byte, a negative hold time can result, depending on the edge rates of the SDA and SCL lines. 2 The maximum tHD; DAT must be met only if the device does not stretch the LOW period (tLOW) of the SCL signal. MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 62 Freescale Semiconductor Specifications SDA tSU; DAT tf tf tr tLOW tHD; STA tr tSP tBUF SCL S tHD; STA tHD; DAT tSU; STA tHIGH tSU; STO SR P S 2 Figure 33. Timing Definition for Standard Mode Devices on the I C Bus 8.13.4 JTAG Timing Table 32. JTAG Timing 1 Characteristic Symbol Min Max Unit See Figure TCK frequency of operation1 fOP DC SYS_CLK/8 MHz Figure 34 TCK clock pulse width tPW 50 -- ns Figure 34 TMS, TDI data set-up time tDS 5 -- ns Figure 35 TMS, TDI data hold time tDH 5 -- ns Figure 35 TCK low to TDO data valid tDV -- 30 ns Figure 35 TCK low to TDO tri-state tTS -- 30 ns Figure 35 TCK frequency of operation must be less than 1/8 the processor rate. 1/fOP tPW tPW VM VM VIH TCK (Input) VM = VIL + (VIH - VIL)/2 VIL Figure 34. Test Clock Input Timing Diagram MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 Freescale Semiconductor 63 Specifications TCK (Input) tDS TDI TMS (Input) tDH Input Data Valid tDV TDO (Output) Output Data Valid tTS TDO (Output) Figure 35. Test Access Port Timing Diagram 8.13.5 Dual Timer Timing Table 33. Timer Timing1, 2 Characteristic Symbol Min Max Unit See Figure Timer input period PIN 2T + 6 -- ns Figure 36 Timer input high/low period PINHL 1T + 3 -- ns Figure 36 Timer output period POUT 125 -- ns Figure 36 Timer output high/low period POUTHL 50 -- ns Figure 36 1 In the formulas listed, T = the clock cycle. For 32 MHz operation, T = 31.25ns. 2. Parameters listed are guaranteed by design. Timer Inputs PIN PINHL PINHL POUT POUTHL POUTHL Timer Outputs Figure 36. Timer Timing MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 64 Freescale Semiconductor Specifications 8.14 COP Specifications Table 34. COP Specifications Parameter Symbol Min Typ Max Unit Oscillator output frequency LPFosc 500 1000 1500 Hz Oscillator current consumption in partial power down mode IDD 8.15 TBD nA PGA Specifications Table 35. PGA Specifications Parameter Digital logic inputs amplitude (_2p5 signal) DC analog input level (@ VDD = avdd3p3) PGA S/H stage enabled (BP=0) PGA S/H stage disabled (BP=1) Max differential input voltage (@ Gain and VDD = avdd3p3) Symbol Min V2p5 VIL Max Unit 2.75 V 0 V VDD VDD - 0.5 VDIFFMAX (VDD - 1) x 0.5/gain V Linearity (@ voltage gain) 1x 2x 4x 8x 16x 32x LV Gain error (@ voltage gain) 1x 2x 4x 8x 16x 32x AV 1% V/V SFmax 8 4 MHz Sampling frequency (pga_clk_2p5) normal mode (pga_lp_2p5 asserted) low power mode (pga_lp_2p5 negated) 1 - 1/2 LSB 2 - 1/2 LSB 4 - 1 LSB 8 - 1 LSB 16 - 4 LSB 32 - 4 LSB 1 + 1/2 LSB 2 + 1/2 LSB 4 + 1 LSB 8 + 1 LSB 16 + 4 LSB 32 + 4 LSB V/V Input signal bandwidth Motor Control mode (BP=0) BWmax General Purpose mode (BP=1) Internal voltage doubler clock frequency(pga_clk_doubler_2p5) Operating temperature PGA sampling rate/2 PGA sampling rate/8 Hz VDclk 100 2000 kHz T -40 125 oC MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 Freescale Semiconductor 65 Specifications 8.16 ADC Specifications Table 36. ADC Operating Conditions Symb Min Typ1 Max Unit Input voltage VADIN VREFL2 -- VREFH3 V Input capacitance CADIN -- 4.5 5.5 pF Input resistance RADIN -- 5 7 k -- -- -- -- 2 5 10-bit mode fADCK > 4 MHz fADCK < 4 MHz -- -- -- -- 5 10 8-bit mode (all valid fADCK) -- -- 10 0.4 -- 8.0 0.4 -- 4.0 Characteristic Analog source resistance Conditions RAS 12-bit mode fADCK > 4 MHz fADCK < 4 MHz ADC conversion High speed (ADLPC=0) clock freq. Low power (ADLPC=1) fADCK k Comment External to MCU MHz 1 Typical values assume VDDAD = 3.0 V, Temp = 25C, fADCK = 1.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 2 VREFL = VSSA 3 V REFH = VDDA Simplified Input Pin Equivalent Circuit Pad leakage due to input protection ZAS RAS VAS + - CAS ZADIN Simplified Channel Select Circuit RADIN ADC SAR Engine + VADIN - RADIN INPUT PIN INPUT PIN RADIN RADIN INPUT PIN CADIN Figure 37. ADC Input Impedance Equivalency Diagram MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 66 Freescale Semiconductor Specifications Table 37. ADC Characteristics (VREFH = VDDA, VREFL = VSSA) Symb Min Typ1 Max Unit Supply current ADLPC=1 ADLSMP=1 ADCO=1 IDDAD -- 120 -- A Supply current ADLPC=1 ADLSMP=0 ADCO=1 IDDAD -- 202 -- A Supply current ADLPC=0 ADLSMP=1 ADCO=1 IDDAD -- 288 -- A Supply current ADLPC=0 ADLSMP=0 ADCO=1 IDDAD -- 0.532 1 mA fADACK 2 3.3 5 MHz 1.25 2 3.3 -- 20 -- -- 40 -- -- 3.5 -- -- 23.5 -- -- 1.75 -- -- 0.5 1.0 -- 0.3 0.5 -- 1.5 -- 10-bit mode -- 0.5 1.0 8-bit mode -- 0.3 0.5 -- -1 to 0 -- 10-bit mode -- -- 0.5 8-bit mode -- -- 0.5 -- 2 -- 10-bit mode -- 0.2 4 8-bit mode -- 0.1 1.2 -- 1.646 -- -- 1.769 -- -- 701.2 -- Characteristic Conditions ADC asynchronous clock source High speed (ADLPC=0) Conversion time (including sample time) Short sample (ADLSMP=0) Sample time Short sample (ADLSMP=0) Low power (ADLPC=1) tADC Long sample (ADLSMP=1) tADS Long sample (ADLSMP=1) Differential Non-linearity 12-bit mode DNL 10-bit mode3 3 8-bit mode Integral non-linearity Quantization error Input leakage error 12-bit mode 12-bit mode 12-bit mode Temp sensor slope -40C-25C Temp sensor voltage 25C INL EQ EIL m 25C-125C VTEMP25 Comment tADACK = 1/fADACK ADCK cycles ADCK cycles LSB2 LSB2 LSB2 LSB2 Pad leakage4 * RAS mV/C mV MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 Freescale Semiconductor 67 Specifications 1 Typical values assume VDDA = 3.0 V, Temp = 25C, fADCK=1.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 2 1 LSB = (VREFH - VREFL)/2N 3 Monotonicity and no-missing-codes guaranteed in 10-bit and 8-bit modes 4 Based on input pad leakage current. Refer to pad electricals. 8.17 HSCMP Specifications Table 38. HSCMP Specifications Parameter Symbol Min Typ Max Unit Supply voltage VPWR 1.8 3.6 V Supply current, high speed mode (EN=1, PMODE=1, VDDA VLVI_trip) IDDAHS 150 A Supply current, low speed mode (EN=1, PMODE=0) IDDALS 10 A Supply current, off mode (EN=0,) IDDAOFF Analog input voltage VAIN Analog input offset voltage VAIO Analog comparator hysteresis VH Propagation Delay, high speed mode (EN=1, PMODE=1), 2.4 V < VDDA < 3.6 V tDHSN1 Propagation Delay, High Speed Mode (EN=1, PMODE=1), 1.8 V < VDDA < 2.4 V 100 nA VDDA + 0.01 V 40 mV 20.0 mV 70 140 ns tDHSB2 70 249 ns Propagation Delay, Low Speed Mode (EN=1, PMODE=0), 2.4 V < VDDA < 3.6 V tAINIT3 400 600 ns Propagation Delay, Low Speed Mode (EN=1, PMODE=0), 1.8 V < VDDA < 2.4 V tAINIT4 400 600 ns VSSA - 0.01 3.0 1 Measured with an input waveform that switches 30 mV above and below the reference, to the CMPO output pin. VDDA > VLVI_WARNING => LVI_WARNING NOT ASSERTED. 2 Measured with an input waveform that switches 30mV above and below the reference, to the CMPO output pin. V DDA < VLVI_WARNING => LVI_WARNING ASSERTED. 3 Measured with an input waveform that switches 30mV above and below the reference, to the CMPO output pin. V DDA > VLVI_WARNING => LVI_WARNING NOT ASSERTED. 4 Measured with an input waveform that switches 30mV above and below the reference, to the CMPO output pin. VDDA < VLVI_WARNING => LVI_WARNING ASSERTED. 8.18 Optimize Power Consumption See Section 8.6, "Supply Current Characteristics," for a list of IDD requirements for the 56F8006/56F8002. This section provides additional detail that can be used to optimize power consumption for a given application. MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 68 Freescale Semiconductor Specifications Power consumption is given by the following equation: Eqn. 1 Total power = A: internal [static component] +B: internal [state-dependent component] +C: internal [dynamic component] +D: external [dynamic component] +E: external [static component] A, the internal [static] component, is comprised of the DC bias currents for the oscillator, leakage currents, PLL, and voltage references. These sources operate independently of processor state or operating frequency. B, the internal [state-dependent] component, reflects the supply current required by certain on-chip resources only when those resources are in use. These include RAM, flash memory, and the ADCs. C, the internal [dynamic] component, is classic C*V2*F CMOS power dissipation corresponding to the 56800E core and standard cell logic. D, the external [dynamic] component, reflects power dissipated on-chip as a result of capacitive loading on the external pins of the chip. This is also commonly described as C*V2*F, although simulations on two of the I/O cell types used on the 56800E reveal that the power-versus-load curve does have a non-zero Y-intercept. Table 39. I/O Loading Coefficients at 10 MHz Intercept Slope 8 mA drive 1.3 0.11 mW/pF 4 mA drive 1.15 mW 0.11 mW/pF Power due to capacitive loading on output pins is (first order) a function of the capacitive load and frequency at which the outputs change. Table 39 provides coefficients for calculating power dissipated in the I/O cells as a function of capacitive load. In these cases: TotalPower = ((Intercept + Slope*Cload)*frequency/10 MHz) Eqn. 2 where: * * * Summation is performed over all output pins with capacitive loads Total power is expressed in mW Cload is expressed in pF Because of the low duty cycle on most device pins, power dissipation due to capacitive loads was found to be fairly low when averaged over a period of time. E, the external [static component], reflects the effects of placing resistive loads on the outputs of the device. Sum the total of all V2/R or IV to arrive at the resistive load contribution to power. Assume V = 0.5 for the purposes of these rough calculations. For instance, if there is a total of eight PWM outputs driving 10 mA into LEDs, then P = 8*0.5*0.01 = 40 mW. In previous discussions, power consumption due to parasitics associated with pure input pins is ignored, as it is assumed to be negligible. MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 Freescale Semiconductor 69 Design Considerations 9 Design Considerations 9.1 Thermal Design Considerations An estimation of the chip junction temperature, TJ, can be obtained from the equation: TJ = TA + (RJ x PD) Eqn. 3 where: TA = Ambient temperature for the package (oC) = Junction-to-ambient thermal resistance (oC/W) RJ = PD Power dissipation in the package (W) The junction-to-ambient thermal resistance is an industry-standard value that provides a quick and easy estimation of thermal performance. Unfortunately, there are two values in common usage: the value determined on a single-layer board and the value obtained on a board with two planes. For packages such as the PBGA, these values can be different by a factor of two. Which value is closer to the application depends on the power dissipated by other components on the board. The value obtained on a single layer board is appropriate for the tightly packed printed circuit board. The value obtained on the board with the internal planes is usually appropriate if the board has low-power dissipation and the components are well separated. When a heat sink is used, the thermal resistance is expressed as the sum of a junction-to-case thermal resistance and a case-to-ambient thermal resistance: RJA = RJC + RCA Eqn. 4 where: RJA = Package junction-to-ambient thermal resistance (C/W) RJC = Package junction-to-case thermal resistance (C/W) RCA = Package case-to-ambient thermal resistance (C/W) RJC is device related and cannot be adjusted. You control the thermal environment to change the case to ambient thermal resistance, RCA. For instance, you can change the size of the heat sink, the air flow around the device, the interface material, the mounting arrangement on printed circuit board, or change the thermal dissipation on the printed circuit board surrounding the device. To determine the junction temperature of the device in the application when heat sinks are not used, the thermal characterization parameter (JT) can be used to determine the junction temperature with a measurement of the temperature at the top center of the package case using the following equation: TJ = TT + (JT x PD) Eqn. 5 where: TT = Thermocouple temperature on top of package (oC) JT = Thermal characterization parameter (oC/W) PD = Power dissipation in package (W) The thermal characterization parameter is measured per JESD51-2 specification using a 40-gauge type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the package. A small amount of epoxy is placed over the thermocouple junction and over about 1 mm of wire extending from the MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 70 Freescale Semiconductor Design Considerations junction. The thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire. When heat sink is used, the junction temperature is determined from a thermocouple inserted at the interface between the case of the package and the interface material. A clearance slot or hole is normally required in the heat sink. Minimizing the size of the clearance is important to minimize the change in thermal performance caused by removing part of the thermal interface to the heat sink. Because of the experimental difficulties with this technique, many engineers measure the heat sink temperature and then back-calculate the case temperature using a separate measurement of the thermal resistance of the interface. From this case temperature, the junction temperature is determined from the junction-to-case thermal resistance. 9.2 Electrical Design Considerations CAUTION This device contains protective circuitry to guard against damage due to high static voltage or electrical fields. However, take normal precautions to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate voltage level. Use the following list of considerations to assure correct operation of the 56F8006/56F8002: * * * * * * * * * * * * * * * * Provide a low-impedance path from the board power supply to each VDD pin on the 56F8006/56F8002 and from the board ground to each VSS (GND) pin. The minimum bypass requirement is to place 0.01-0.1F capacitors positioned as near as possible to the package supply pins. The recommended bypass configuration is to place one bypass capacitor on each of the VDD/VSS pairs, including VDDA/VSSA. Ceramic and tantalum capacitors tend to provide better tolerances. Ensure that capacitor leads and associated printed circuit traces that connect to the chip VDD and VSS (GND) pins are as short as possible. Bypass the VDD and VSS with approximately 100 F, plus the number of 0.1 F ceramic capacitors. PCB trace lengths should be minimal for high-frequency signals. Consider all device loads as well as parasitic capacitance due to PCB traces when calculating capacitance. This is especially critical in systems with higher capacitive loads that could create higher transient currents in the VDD and VSS circuits. Take special care to minimize noise levels on the VREF, VDDA, and VSSA pins. Using separate power planes for VDD and VDDA and separate ground planes for VSS and VSSA are recommended. Connect the separate analog and digital power and ground planes as near as possible to power supply outputs. If an analog circuit and digital circuit are powered by the same power supply, you should connect a small inductor or ferrite bead in serial with VDDA and VSSA traces. Physically separate analog components from noisy digital components by ground planes. Do not place an analog trace in parallel with digital traces. Place an analog ground trace around an analog signal trace to isolate it from digital traces. Because the flash memory is programmed through the JTAG/EOnCE port, SPI, SCI, or I2C, the designer should provide an interface to this port if in-circuit flash programming is desired. If desired, connect an external RC circuit to the RESET pin. The resistor value should be in the range of 4.7 k-10 k; the capacitor value should be in the range of 0.22 F-4.7 F. Configuring the RESET pin to GPIO output in normal operation in a high-noise environment may help to improve the performance of noise transient immunity. Add a 2.2 k external pullup on the TMS pin of the JTAG port to keep EOnCE in a restate during normal operation if JTAG converter is not present. During reset and after reset but before I/O initialization, all I/O pins are at input state with internal pullup enabled. The typical value of internal pullup is around 33 k. These internal pullups can be disabled by software. To eliminate PCB trace impedance effect, each ADC input should have a no less than 33 pF 10 RC filter. External clamp diodes on analog input pins are recommended. MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 Freescale Semiconductor 71 Design Considerations 9.3 Ordering Information Table 40 lists the pertinent information needed to place an order. Consult a Freescale Semiconductor sales office or authorized distributor to determine availability and to order devices. Table 40. 56F8006/56F8002 Ordering Information Ambient Temperature Range Order Number 32 -40 to + 105 C -40 to + 125 C MC56F8002VWL MC56F8002MWL1 28 32 -40 to + 105 C -40 to + 125 C MC56F8006VWL MC56F8006MWL1 Low-Profile Quad Flat Pack (LQFP) 32 32 -40 to + 105 C -40 to + 125 C MC56F8006VLC MC56F8006MLC1 1.8-3.6 V Low-Profile Quad Flat Pack (LQFP) 48 32 -40 to + 105 C -40 to + 125 C MC56F8006VLF MC56F8006MLF1 1.8-3.6 V Plastic Shrink Dual In-line Package (PSDIP) 32 32 -40 to + 105 C MC56F8006VBM Device Supply Voltage Package Type Pin Count Frequency (MHz) MC56F8002 1.8-3.6 V Small Outline IC (SOIC) 28 MC56F8006 1.8-3.6 V Small Outline IC (SOIC) MC56F8006 1.8-3.6 V MC56F8006 MC56F8006 1 This package is RoHS compliant. MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 72 Freescale Semiconductor Package Mechanical Outline Drawings 10 Package Mechanical Outline Drawings 10.1 28-pin SOIC Package MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 Freescale Semiconductor 73 Package Mechanical Outline Drawings MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 74 Freescale Semiconductor Package Mechanical Outline Drawings Figure 38. 56F8006/56F8002 28-Pin SOIC Mechanical Information MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 Freescale Semiconductor 75 Package Mechanical Outline Drawings 10.2 32-pin LQFP MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 76 Freescale Semiconductor Package Mechanical Outline Drawings MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 Freescale Semiconductor 77 Package Mechanical Outline Drawings Figure 39. 56F8006/56F8002 32-Pin LQFP Mechanical Information MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 78 Freescale Semiconductor Package Mechanical Outline Drawings 10.3 48-pin LQFP MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 Freescale Semiconductor 79 Package Mechanical Outline Drawings Figure 40. 56F8006/56F8002 48-Pin LQFP Mechanical Information MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 80 Freescale Semiconductor Package Mechanical Outline Drawings 10.4 32-Pin PSDIP MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 Freescale Semiconductor 81 Package Mechanical Outline Drawings Figure 41. 56F8006/56F8002 32-Pin PSDIP Mechanical Information MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 82 Freescale Semiconductor Revision History 11 Revision History Table 41 lists major changes between versions of the MC56F8006 document. Table 41. Changes Between Revisions 2 and 3 Location Description Introduction on page 1 Added part marking for devices covered by this document Section 6.7, "PWM, PDB, PGA, and ADC Connections," on page 38 Updated routing details for ANB24 and ANB25 Table 12 on page 42 Removed row about open drain mode (GPIO supports only push-pull mode) Table 21 on page 47 Updated specifications for low-voltage detection threshold (high and low range) and low-voltage warning threshold Table 22 on page 51 Updated all Supply Current Consumption specifications Table 26 and Figure 22 on page 55 Updated ROSC variation over temperature specifications (both ranges) Table 31 on page 62 Removed I2C fast mode specifications and footnote about setup time if the TX FIFO is empty (fast mode and FIFO not supported) Appendix B on page 86 Added note explaining ADC and GPIO naming conventions Table 44 on page 86 For I2C_SMB_CSR, clarified that bits 7 and 6 are reserved Table 42. Changes Between Revisions 3 and 4 Location Throughout document. Description Added information for 32-pin PSDIP device and devices with temperature range from -40 C to + 125 C. Appendix A Interrupt Vector Table Table 43 provides the 56F8006/56F8002's reset and interrupt priority structure, including on-chip peripherals. The table is organized with higher-priority vectors at the top and lower-priority interrupts lower in the table. As indicated, the priority of an interrupt can be assigned to different levels, allowing some control over interrupt priorities. All level 3 interrupts are serviced before level 2 and so on. For a selected priority level, the lowest vector number has the highest priority. The location of the vector table is determined by the vector base address (VBA). Please see the MC56F8006 Peripheral Reference Manual for detail. By default, the chip reset address and COP reset address correspond to vector 0 and 1 of the interrupt vector table. In these instances, the first two locations in the vector table must contain branch or JMP instructions. All other entries must contain JSR instructions. MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 Freescale Semiconductor 83 Interrupt Vector Table Table 43. Interrupt Vector Table Contents1 Vector Base Address + Interrupt Function Core P:0x00 Reserved for Reset Overlay2 Core P:0x02 Reserved for COP Reset Overlay Peripheral Vector Number User Encoding Priority Level Core 2 N/A 3 P:0x04 Illegal Instruction Core 3 N/A 3 P:0x06 HW Stack Overflow Core 4 N/A 3 P:0x08 Misaligned Long Word Access Core 5 N/A 3 P:0x0A EOnCE Step Counter Core 6 N/A 3 P:0x0C EOnCE Breakpoint Unit Core 7 N/A 3 P:0x0E EOnCE Trace Buffer Core 9 N/A 3 P:0x10 EOnCE Transmit Register Empty Core 9 N/A 3 P:0x12 EOnCE Receive Register Full PMC 10 0x0A 0 P:0x14 Low-Voltage Detector PLL 11 0x0B 0 P:0x16 Phase-Locked Loop Loss of Locks and Loss of Clock ADCA 12 0x0C 0 P:0x18 ADCA Conversion Complete ADCB 13 0x0D 0 P:0x1A ADCB Conversion Complete PWM 14 0x0E 0 P:0x1C Reload PWM and/or PWM Faults CMP0 15 0x0F 0 P:0x1E Comparator 0 Rising/Falling Flag CMP1 16 0x10 0 P:0x20 Comparator 1 Rising/Falling Flag CMP2 17 0x11 0 P:0x22 Comparator 2 Rising/Falling Flag FM 18 0x12 0 P:0x24 Flash Memory Access Status SPI 19 0x13 0 P:0x26 SPI Receiver Full SPI 20 0x14 0 P:0x28 SPI Transmitter Empty SCI 21 0x15 0 P:0x2A SCI Transmitter Empty/Idle SCI 22 0x16 0 P:0x2C SCI Receiver Full/Overrun/Errors 2C 23 0x17 0 P:0x2E I2C Interrupt PIT 24 0x18 0 P:0x30 Interval Timer Interrupt TMR0 25 0x19 0 P:0x32 Dual Timer, Channel 0 Interrupt TMR1 26 0x1A 0 P:0x34 Dual Timer, Channel 1 Interrupt GPIOA 27 0x1B 0 P:0x36 GPIOA Interrupt GPIOB 28 0x1C 0 P:0x38 GPIOB Interrupt GPIOC 29 0x1D 0 P:0x3A GPIOC Interrupt GPIOD 30 0x1E 0 P:0x3C GPIOD Interrupt GPIOE 29 0x1F 0 P:0x3E GPIOE Interrupt GPIOF 30 0x20 0 P:0x40 GPIOF Interrupt RTC 33 0x21 0 P:0x42 Real Time Clock I MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 84 Freescale Semiconductor Interrupt Vector Table Table 43. Interrupt Vector Table Contents1 (continued) Peripheral Vector Number User Encoding Priority Level Vector Base Address + Reserved 34- 39 0x22-0x27 0 P:0x44 P:0x4E Reserved core 40 N/A 0 P:0x50 SW Interrupt 0 core 41 N/A 1 P:0x52 SW Interrupt 1 core 42 N/A 2 P:0x54 SW Interrupt 2 core 43 N/A 3 P:0x56 SW Interrupt 3 SWILP 44 N/A -1 P:0x58 SW Interrupt Low Priority USER1 45 N/A 1 P:0x5A User Programmable Priority Level 1 Interrupt USER2 46 N/A 1 P:0x5C User Programmable Priority Level 1 Interrupt USER3 47 N/A 1 P:0x5E User Programmable Priority Level 1 Interrupt USER4 48 N/A 2 P:0x60 User Programmable Priority Level 2 Interrupt USER5 49 N/A 2 P:0x62 User Programmable Priority Level 2 Interrupt USER6 3 50 N/A 2 P:0x64 User Programmable Priority Level 2 Interrupt Interrupt Function 1 Two words are allocated for each entry in the vector table. This does not allow the full address range to be referenced from the vector table, providing only 19 bits of address. 2 If the VBA is set to the reset value, the first two locations of the vector table overlay the chip reset addresses because the reset address would match the base of this vector table. 3 USER6 vector can be defined as a fast interrupt if the instruction located in this vector location is not a JSR or BSR instruction. Please see section 9.3.3.3 of DSP56800E 16-Bit Core Reference Manual for detail. MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 Freescale Semiconductor 85 Freescale Semiconductor Appendix B Peripheral Register Memory Map and Reset Value NOTE In Table 44, ADC0 stands for ADCA, ADC1 stands for ADCB, and GPIOn is the same as GPIO_n (for example, GPIOA_PUR is the same as GPIO_A_PUR). Table 44. Detailed Peripheral Memory Map COMPARISON_1 01 0000 TMR0 TMR0_ COMP2 COMPARISON_2 02 0000 TMR0 TMR0_ CAPT CAPTURE 03 0000 TMR0 TMR0_ LOAD LOAD 04 0000 TMR0 TMR0_ HOLD HOLD 05 0000 TMR0 TMR0_ CNTR COUNTER 06 0000 TMR0 TMR0_ CTRL 07 0000 TMR0 TMR0_ SCTRL 08 0000 TMR0 TMR0_ CMPLD1 COMPARATOR_LOAD_1 09 0000 TMR0 TMR0_ CMPLD2 COMPARATOR_LOAD_2 10 9 8 7 TOF IEF IEFIE SCS IPS INPUT PCS TOFIE TCF TCFIE CM 11 6 5 4 3 DIR VAL CAPTURE_ MODE 2 1 Bit 0 OM FORCE TMR0_ COMP1 12 Co_INIT TMR0 13 EEOF 0000 14 LENGTH 00 Bit 15 MSTR Register ONCE Reset Value Periph. (Hex) OPS OEN 86 Peripheral Register Memory Map and Reset Value MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 Offset Addr. (Hex) Register Bit 15 14 13 12 11 10 9 8 7 6 0A 0000 TMR0 TMR0_ CSCTRL DBG_EN ALT_LOAD 0 0 0 0 TCF2EN TCF1EN 0B 0000 TMR0 TMR0_ FILT 0 0 0 0 0C-0E -- TMR0 Reserved 0F 000F TMR0 TMR_ ENBL 10 0000 TMR1 TMR1_ COMP1 COMPARISON_1 11 0000 TMR1 TMR1_ COMP2 COMPARISON_2 12 0000 TMR1 TMR1_ CAPT CAPTURE 13 0000 TMR1 TMR1_ LOAD LOAD 14 0000 TMR1 TMR1_ HOLD HOLD 15 0000 TMR1 TMR1_ CNTR COUNTER 16 0000 TMR1 TMR1_ CTRL 17 0000 TMR1 TMR1_ SCTRL 18 0000 TMR1 TMR1_ CMPLD1 COMPARATOR_LOAD_1 19 0000 TMR1 TMR1_ CMPLD2 COMPARATOR_LOAD_2 0 5 4 3 TCF2 TCF1 FILT_CNT 2 Bit 0 1 CL2 CL1 FILT_PER 0 0 TOF IEF IEFIE SCS IPS 0 0 0 DIR VAL CAPTURE_ MODE ENBL OM FORCE 0 COINIT TCF 0 PCS TOFIE CM 0 EEOF 0 LENGTH 0 MSTR 0 INPUT 0 ONCE RESERVED OPS OEN Peripheral Register Memory Map and Reset Value MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 87 Reset Value Periph. (Hex) FAULT Offset Addr. (Hex) TCFIE Freescale Semiconductor Table 44. Detailed Peripheral Memory Map (continued) Register Bit 15 14 13 12 11 10 9 8 7 6 1A 0000 TMR1 TMR1_ CSCTRL DBG_EN FAULT ALT_LOAD 0 0 0 0 TCF2EN TCF1EN 1B 0000 TMR1 TMR1_ FILT 0 0 0 0 1C-1F -- TMR1 Reserved 20 0000 PWM PWM_ CTRL 21 0000 PWM PWM_ FCTRL 22 0000 PWM 23 0000 24 0 5 4 3 TCF2 TCF1 FILT_CNT 2 Bit 0 1 CL2 CL1 FILT_PER Freescale Semiconductor 0 CR 25 0000 PWM PWM_ CMOD 0 PWMCM 26 0000 PWM PWM_ VAL0 PMVAL 27 0000 PWM PWM_ VAL1 PMVAL 28 0000 PWM PWM_ VAL2 PMVAL LDOK PWMF FTACK0 FMODE0 PWMEN PWM_ CNTR OUT0 PWM 0 FIE0 OUT1 0000 0 FTACK1 FMODE1 PWM_ OUT FIE1 OUT2 PWM ISENS OUT3 PWM_ FLTACK FIE2 FTACK2 FMODE2 FIE3 OUT4 0 PWMRIE IPOL0 FPOL0 OUTCTL0 FFLAG0 0 OUT5 IPOL1 FPOL1 FPIN0 OUTCTL1 PRSC FTACK3 FMODE3 IPOL2 OUTCTL4 FFLAG2 FPOL2 OUTCTL5 OUTCTL2 FFLAG1 FPIN2 0 FPOL3 0 HALF OUTCTL3 0 FFLAG3 LDFQ FPIN1 RESERVED FPIN3 MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 Reset Value Periph. (Hex) PAD_EN Offset Addr. (Hex) Peripheral Register Memory Map and Reset Value 88 Table 44. Detailed Peripheral Memory Map (continued) PWM PWM_ VAL3 PMVAL 2A 0000 PWM PWM_ VAL4 PMVAL 2B 0000 PWM PWM_ VAL5 PMVAL 2C 0FFF PWM PWM_ DTIM0 0 0 0 0 PWMDT0 2D 0FFF PWM PWM_ DTIM1 0 0 0 0 PWMDT1 2E FFFF PWM PWM_ DMAP1 2F 00FF PWM PWM_ DMAP2 0 0 0 0 0 0 0 0 30 0000 PWM PWM_ CNFG 0 EDG 0 TOPNEG23 31 0000 PWM PWM_ CCTRL nBX 32 00-U1 PWM PWM_ PORT 0 0 0 0 0 0 0 33 0000 PWM PWM_ ICCTRL 0 0 0 0 0 0 0 0 0 34 0000 PWM PWM_ SCTRL 0 0 CINV0 0 3 2 1 Bit 0 INDEP01 0000 4 WP DISMAP_15_0 BOTNEG23 BOTNEG01 INDEP45 INDEP23 0 VLMODE 0 SWP45 0 0 SWP01 BOTNEG45 0 ICC1 ICC0 0 SRC0 0 SWP23 TOPNEG01 DISMAP_23_16 PORT 0 PEC2 PEC1 PEC0 ICC2 SRC2 0 SRC1 89 Peripheral Register Memory Map and Reset Value MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 29 MSK1 5 CINV1 6 TOPNEG45 7 MSK2 8 CINV2 9 MSK3 10 CINV3 11 MSK4 12 CINV4 13 WAIT_EN 14 MSK5 Bit 15 CINV5 Register DBG_EN Reset Value Periph. (Hex) ENHA Offset Addr. (Hex) MSK0 Freescale Semiconductor Table 44. Detailed Peripheral Memory Map (continued) Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 1 Bit 0 BKPT 0000 PWM PWM_ SYNC 36 0000 PWM PWM_ FFILT0 37 0000 PWM PWM_ FFILT1 38 0000 PWM PWM_ FFILT2 39 0000 PWM PWM_ FFILT3 3B-3F -- PWM Reserved 40 0000 INTC INTC_ ICSR INT 41 0000 INTC INTC_ VBA 0 0 42 0000 INTC INTC_ IAR0 0 0 USER2 0 0 USER1 43 0000 INTC INTC_ IAR1 0 0 USER4 0 0 USER3 44 0000 INTC INTC_ IAR2 0 0 USER6 0 0 USER5 45-5F -- INTC Reserved 60 001F ADC0 ADC0_ ADCSC1A SYNC_WINDOW 0 0 0 0 FILT0_CNT FILT0_PER 0 0 0 0 FILT1_CNT FILT1_PER 0 0 0 0 FILT2_CNT FILT2_PER 0 0 0 0 FILT3_CNT FILT3_PER ETRE VAB ERRF IPIC INT_DIS RESERVED VECTOR_BASE_ADDRESS RESERVED 0 0 0 0 0 0 0 0 AIEN ADCO Freescale Semiconductor 35 COCO MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 2 STPCNT Register TRBUF Reset Value Periph. (Hex) GSTR3 GSTR2 GSTR1 GSTR0 SYNC_OUT_EN Offset Addr. (Hex) ADCH Peripheral Register Memory Map and Reset Value 90 Table 44. Detailed Peripheral Memory Map (continued) Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 61 0000 ADC0 ADC0_ ADCSC2 0 0 0 0 0 0 0 0 ADACT ADTRG 0 0 0 ECC 62-65 -- ADC0 Reserved 66 0000 ADC0 ADC0_ ADCCFG 67-69 -- ADC0 Reserved 6A 001F ADC0 ADC0_ ADCSC1B 0 6B 0000 ADC0 ADC0_ ADCRA 0 6C 0000 ADC0 ADC0_ ADCRB 0 6D-6F -- ADC0 Reserved 80 001F ADC1 ADC1_ ADCSC1A 0 0 0 0 0 0 0 0 81 0000 ADC1 ADC1_ ADCSC2 0 0 0 0 0 0 0 0 82-85 -- ADC1 Reserved 86 0000 ADC1 ADC1_ ADCCFG 87-89 -- ADC1 Reserved 8A 001F ADC1 ADC1_ ADCSC1B 1 Bit 0 REFSEL 0 0 0 0 0 0 0 ADLSMP 0 ADLPC RESERVED ADIV MODE ADICLK ADR5 ADR4 COCO ADR5 ADR4 ADR0 ADR6 ADR6 0 ADR0 ADR7 ADR7 ADR1 ADR8 ADR8 ADCH ADR1 ADR9 AIEN ADCO 0 ADR2 0 ADR2 0 0 AIEN ADCO 0 ADR3 0 ADR3 0 ADTRG 0 ADR9 RESERVED 0 0 0 0 0 ADACT COCO RESERVED ADCH 0 0 ECC REFSEL 0 0 0 0 0 0 0 ADIV ADLSMP 0 ADLPC RESERVED MODE 0 0 0 0 0 0 0 AIEN ADCO 0 COCO RESERVED ADCH ADICLK 91 Peripheral Register Memory Map and Reset Value MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 Reset Value Periph. (Hex) ADR10 ADR10 Offset Addr. (Hex) ADR11 ADR11 Freescale Semiconductor Table 44. Detailed Peripheral Memory Map (continued) 0 0 0 0 0 0 0 0 TM A1 0002 PGA0 PGA0_ CNTL1 0 0 0 0 0 0 0 0 PPDIS PARMODE 0 A2 000E PGA0 PGA0_ CNTL2 0 0 0 0 0 0 0 0 0 0 SWTRIG NUM_CLK_GS A3 0000 PGA0 PGA0_STS 0 0 0 0 0 0 0 0 0 0 0 0 A4-BF -- PGA0 Reserved C0 0000 PGA1 PGA1_ CNTL0 0 0 0 0 0 0 0 0 TM C1 0002 PGA1 PGA1_ CNTL1 0 0 0 0 0 0 0 0 PPDIS PARMODE 0 C2 000E PGA1 PGA1_ CNTL2 0 0 0 0 0 0 0 0 0 0 SWTRIG ADR0 PGA0_ CNTL0 0 0 ADR0 PGA0 ADR1 0000 0 ADR1 A0 Bit 0 ADR2 Reserved 1 ADR2 ADC1 2 ADR3 -- 3 ADR3 8D-8F 4 ADR4 0 5 ADR4 ADC1_ ADCRB 6 ADR5 ADC1 7 ADR5 0000 8 ADR6 8C 9 ADR6 0 10 ADR7 ADC1_ ADCRA 11 ADR7 ADC1 12 ADR8 0000 13 ADR8 8B 14 ADR9 Bit 15 ADR9 Register ADR10 ADR10 0 0 0 LP EN RESERVED GAINSEL 0 CPD 0 ADIV STCOMP CALMODE RUNNING MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 Freescale Semiconductor Reset Value Periph. (Hex) ADR11 ADR11 Offset Addr. (Hex) LP EN RESERVED GAINSEL CALMODE NUM_CLK_GS CPD ADIV Peripheral Register Memory Map and Reset Value 92 Table 44. Detailed Peripheral Memory Map (continued) 14 13 12 11 10 9 8 7 6 5 4 3 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 E1 0000 SCI SCI_ CTRL1 E2 0000 SCI SCI_ CTRL2 E3 C000 SCI E4 0000 E5-FF SBR FRAC_SBR POL PE PT TEIE TIIE 0 0 0 0 0 0 0 OR NF FE PF 0 0 0 0 0 0 0 M 0 0 0 0 93 SWAI 0 0 SCI_STAT SCI SCI_DATA 0 -- SCI Reserved 00 6141 SPI SPI_ SCTRL 01 000F SPI SPI_ DSCTRL WOM 0 02 0000 SPI SPI_DRCV R15 03 0000 SPI SPI_DXMIT T15 04-1F -- SPI Reserved 20 0000 I2C I2C_ADDR 0 0 0 0 0 0 0 0 21 0000 I2C I2C_ FREQDIV 0 0 0 0 0 0 0 0 RFIE REIE TE RE RWU SBK 0 0 0 0 0 LSE 0 0 RAF RECEIVE_TRANSMIT_DATA ERRIE MODF BD2X SSB_ODM SSB_AUTO SPMSTR CPOL 0 SSB_DATA MODFEN SPTE SSB_DDR R14 R13 R12 R11 R10 R9 R8 R7 R3 R2 R1 R0 T14 T13 T12 T11 T10 T9 T8 T7 T6 T5 T4 T3 T2 T1 T0 AD6 AD5 AD4 AD3 AD2 AD1 0 SPR SPRIE DSO SSB_IN RESERVED SPE SPR3 R6 R5 R4 OVRF SCI_RATE LIN _MODE SCI SPRF 0200 SPTIE E0 RESERVED SSB_OVER Reserved CPHA PGA1 SSB_STRB -- WAKE C4-DF RIDLE PGA1_STS LOOP PGA1 TDRE 0000 Bit 0 DS RESERVED AD7 MULT ICR Peripheral Register Memory Map and Reset Value MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 C3 1 STCOMP Bit 15 RUNNING Register RSRC Reset Value Periph. (Hex) RDRF Offset Addr. (Hex) TIDLE Freescale Semiconductor Table 44. Detailed Peripheral Memory Map (continued) Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 22 0000 I2C I2C_CR1 0 0 0 0 0 0 0 0 IICEN IICIE MST TX 23 0080 I2C I2C_SR 0 0 0 0 0 0 0 0 TCF IAAS BUSY ARBL 24 0000 I2C I2C_DATA 0 0 0 0 0 0 0 0 25 0000 I2C I2C_CR2 0 0 0 0 0 0 0 0 26 0000 I2C I2C_SMB_ CSR 0 0 0 0 0 0 0 0 27 0000 I2C I2C_ ADDR2 0 0 0 0 0 0 0 0 28 0000 I2C I2C_SLT1 0 0 0 0 0 0 0 0 29 0000 I2C I2C_SLT2 0 0 0 0 0 0 0 0 30-3F -- I2C Reserved 40 0302 COP COP_ CTRL 41 FFFF COP COP_ TOUT TIMEOUT 42 FFFF COP COP_ CNTR COUNT_SERVICE 43-5F -- COP Reserved RESERVED 3 2 Bit 0 0 0 0 SRW IICIF RXAK TXAK RSTA 1 0 AD10 AD9 AD8 0 0 0 TCKSEL SLTF SHTF SSLT2 SSLT10 CSEN CWEN SSLT0 SSLT3 SSLT11 CLOREN SSLT9 SSLT4 SSLT12 CLKSEL 0 SSLT1 SSLT5 SSLT13 SSLT6 SSLT14 SAD7 SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SSLT8 0 SIICAEN RESERVED ADEXT DATA RESERVED GCAEN MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 Freescale Semiconductor Reset Value Periph. (Hex) SSLT7 SSLT15 Offset Addr. (Hex) CEN CWP RESERVED 0 0 0 0 0 0 PSS 0 Peripheral Register Memory Map and Reset Value 94 Table 44. Detailed Peripheral Memory Map (continued) 2000 OCCS OCCS_ DIVBY 62 0015 OCCS OCCS_ STAT LOLI1 64 1611 OCCS OCCS_ OCTRL 65 0000 OCCS OCCS_ CLKCHKR 66 0000 OCCS OCCS_ CLKCHKT 0 0 0 0 0 0 0 0 0 67 0000 OCCS OCCS_ PROT 0 0 0 0 0 0 0 0 0 68-7F -- OCCS Reserved 80 00FF GPIOA GPIOA_ PUR 81 0000 GPIOA GPIOA_DR 82 0000 GPIOA 83 0080 84 -- PLLIE0 10 9 8 7 6 5 4 3 2 0 0 0 0 0 0 PRECS 61 PLLIE1 11 0 0 0 0 0 0 0 COSC_RDY OCCS_ CTRL 12 PLLPD OCCS 13 PLLPDN 0011 14 LCKON 60 Bit 15 LOCIE Register ROPD LOCI 0 0 0 COHL CLK_MODE RANGE EXT_SEL COD LOLI0 LORTP ROSB Offset Addr. (Hex) 0 0 0 LCK1 LCK0 1 Bit 0 ZSRC 0 0 ZSRC TRIM REFERENCE_CNT TARGET_CNT 0 FRQEP OSCEP RESERVED 0 0 0 0 0 0 0 0 PU 0 0 0 0 0 0 0 0 D GPIOA_ DDR 0 0 0 0 0 0 0 0 DD GPIOA GPIOA_ PER 0 0 0 0 0 0 0 0 PE GPIOA Reserved RESERVED PLLEP 95 Peripheral Register Memory Map and Reset Value MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 Reset Value Periph. (Hex) CHK_ENA Freescale Semiconductor Table 44. Detailed Peripheral Memory Map (continued) Offset Addr. (Hex) MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 Freescale Semiconductor Reset Value Periph. (Hex) Register Bit 15 14 13 12 11 10 9 8 85 0000 GPIOA GPIOA_ IENR 0 0 0 0 0 0 0 0 IEN 86 0000 GPIOA GPIOA_ IPOLR 0 0 0 0 0 0 0 0 IPOL 87 0000 GPIOA GPIOA_ IPR 0 0 0 0 0 0 0 0 IP 88 0000 GPIOA GPIOA_ IESR 0 0 0 0 0 0 0 0 IES 89 -- GPIOA Reserved 8A 0000 GPIOA GPIOA_ RAWDATA 0 0 0 0 0 0 0 0 RAWDATA 8B 0000 GPIOA GPIOA_ DRIVE 0 0 0 0 0 0 0 0 DRIVE 8C 00FF GPIOA GPIOA_IFE 0 0 0 0 0 0 0 0 IFE 8D 0000 GPIOA GPIOA_ SLEW 0 0 0 0 0 0 0 0 SLEW 8E-9F -- GPIOA Reserved A0 00FF GPIOB GPIOB_ PUR A1 0000 GPIOB GPIOB_DR A2 0000 GPIOB A3 0080 A4 7 6 5 4 3 RESERVED RESERVED 0 0 0 0 0 0 0 0 PUR 0 0 0 0 0 0 0 0 DR GPIOB_ DDR 0 0 0 0 0 0 0 0 DDR GPIOB GPIOB_ PER 0 0 0 0 0 0 0 0 PER -- GPIOB Reserved A5 0000 GPIOB GPIOB_ IENR 0 0 0 0 0 0 0 0 IENR A6 0000 GPIOB GPIOB_ IPOLR 0 0 0 0 0 0 0 0 IPOLR RESERVED 2 1 Bit 0 Peripheral Register Memory Map and Reset Value 96 Table 44. Detailed Peripheral Memory Map (continued) Freescale Semiconductor Table 44. Detailed Peripheral Memory Map (continued) Offset Addr. (Hex) Register Bit 15 14 13 12 11 10 9 8 A7 0000 GPIOB GPIOB_ IPR 0 0 0 0 0 0 0 0 IPR A8 0000 GPIOB GPIOB_ IESR 0 0 0 0 0 0 0 0 IESR A9 -- GPIOB Reserved AA 0000 GPIOB GPIOB_ RAWDATA 0 0 0 0 0 0 0 0 RAWDATA AB 0000 GPIOB GPIOB_ DRIVE 0 0 0 0 0 0 0 0 DRIVE AC 00FF GPIOB GPIOB_IFE 0 0 0 0 0 0 0 0 IFE AD 0000 GPIOB GPIOB_ SLEW 0 0 0 0 0 0 0 0 SLEW AE-BF -- GPIOB Reserved C0 00FF GPIOC GPIOC_ PUR C1 0000 GPIOC GPIOC_DR C2 0000 GPIOC C3 0080 C4 7 6 5 4 3 2 1 Bit 0 RESERVED RESERVED 0 0 0 0 0 0 0 0 PUR 0 0 0 0 0 0 0 0 DR GPIOC_ DDR 0 0 0 0 0 0 0 0 DDR GPIOC GPIOC_ PER 0 0 0 0 0 0 0 0 PER -- GPIOC Reserved C5 0000 GPIOC GPIOC_ IENR 0 0 0 0 0 0 0 0 IENR C6 0000 GPIOC GPIOC_ IPOLR 0 0 0 0 0 0 0 0 IPOLR C7 0000 GPIOC GPIOC_ IPR 0 0 0 0 0 0 0 0 IPR C8 0000 GPIOC GPIOC_ IESR 0 0 0 0 0 0 0 0 IESR RESERVED 97 Peripheral Register Memory Map and Reset Value MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 Reset Value Periph. (Hex) Offset Addr. (Hex) Reset Value Periph. (Hex) Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 C9 -- GPIOC Reserved CA 0000 GPIOC GPIOC_ RAWDATA 0 0 0 0 0 0 0 0 RAWDATA CB 0000 GPIOC GPIOC_ DRIVE 0 0 0 0 0 0 0 0 DRIVE CC 00FF GPIOC GPIOC_ IFE 0 0 0 0 0 0 0 0 IFE CD 0000 GPIOC GPIOC_ SLEW 0 0 0 0 0 0 0 0 SLEW CE-DF -- GPIOC Reserved E0 00FF GPIOD GPIOD_ PUR E1 0000 GPIOD GPIOD_DR E2 0000 GPIOD E3 0080 E4 2 1 RESERVED RESERVED Freescale Semiconductor 0 0 0 0 0 0 0 0 0 0 0 0 PUR 0 0 0 0 0 0 0 0 0 0 0 0 DR GPIOD_ DDR 0 0 0 0 0 0 0 0 0 0 0 0 DDR GPIOD GPIOD_ PER 0 0 0 0 0 0 0 0 0 0 0 0 PER -- GPIOD Reserved E5 0000 GPIOD GPIOD_ IENR 0 0 0 0 0 0 0 0 0 0 0 0 IENR E6 0000 GPIOD GPIOD_ IPOLR 0 0 0 0 0 0 0 0 0 0 0 0 IPOLR E7 0000 GPIOD GPIOD_ IPR 0 0 0 0 0 0 0 0 0 0 0 0 IPR E8 0000 GPIOD GPIOD_ IESR 0 0 0 0 0 0 0 0 0 0 0 0 IESR E9 -- GPIOD Reserved EA 0000 GPIOD GPIOD_ RAWDATA 0 0 0 RAWDATA RESERVED RESERVED 0 0 0 0 0 0 0 0 0 Bit 0 Peripheral Register Memory Map and Reset Value 98 Table 44. Detailed Peripheral Memory Map (continued) Freescale Semiconductor Table 44. Detailed Peripheral Memory Map (continued) Offset Addr. (Hex) Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 EB 0000 GPIOD GPIOD_ DRIVE 0 0 0 0 0 0 0 0 0 0 0 0 DRIVE EC 00FF GPIOD GPIOD_ IFE 0 0 0 0 0 0 0 0 0 0 0 0 IFE ED 0000 GPIOD GPIOD_ SLEW 0 0 0 0 0 0 0 0 0 0 0 0 SLEW EE-9F -- GPIOD Reserved 00 00FF GPIOE GPIOE_ PUR 01 0000 GPIOE GPIOE_DR 02 0000 GPIOE 03 0080 04 3 2 1 Bit 0 RESERVED 0 0 0 0 0 0 0 0 PUR 0 0 0 0 0 0 0 0 DR GPIOE_ DDR 0 0 0 0 0 0 0 0 DDR GPIOE GPIOE_ PER 0 0 0 0 0 0 0 0 PER -- GPIOE Reserved 05 0000 GPIOE GPIOE_ IENR 0 0 0 0 0 0 0 0 IENR 06 0000 GPIOE GPIOE_ IPOLR 0 0 0 0 0 0 0 0 IPOLR 07 0000 GPIOE GPIOE_ IPR 0 0 0 0 0 0 0 0 IPR 08 0000 GPIOE GPIOE_ IESR 0 0 0 0 0 0 0 0 IESR 09 -- GPIOE Reserved 0A 0000 GPIOE GPIOE_ RAWDATA 0 0 0 0 0 0 0 0 RAWDATA 0B 0000 GPIOE GPIOE_ DRIVE 0 0 0 0 0 0 0 0 DRIVE 0C 00FF GPIOE GPIOE_IFE 0 0 0 0 0 0 0 0 IFE RESERVED RESERVED 99 Peripheral Register Memory Map and Reset Value MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 Reset Value Periph. (Hex) Offset Addr. (Hex) MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 Reset Value Periph. (Hex) Register Bit 15 14 13 12 11 10 9 8 0D 0000 GPIOE GPIOE_ SLEW 0 0 0 0 0 0 0 0 0E-1F -- GPIOE Reserved 20 00FF GPIOF GPIOF_ PUR 21 0000 GPIOF GPIOF_DR 22 0000 GPIOF 23 0080 24 7 6 5 4 3 2 1 SLEW RESERVED Freescale Semiconductor 0 0 0 0 0 0 0 0 0 0 0 0 PUR 0 0 0 0 0 0 0 0 0 0 0 0 DR GPIOF_ DDR 0 0 0 0 0 0 0 0 0 0 0 0 DDR GPIOF GPIOF_ PER 0 0 0 0 0 0 0 0 0 0 0 0 PER -- GPIOF Reserved 25 0000 GPIOF GPIOF_ IENR 0 0 0 0 0 0 0 0 0 0 0 0 IENR 26 0000 GPIOF GPIOF_ IPOLR 0 0 0 0 0 0 0 0 0 0 0 0 IPOLR 27 0000 GPIOF GPIOF_ IPR 0 0 0 0 0 0 0 0 0 0 0 0 IPR 28 0000 GPIOF GPIOF_ IESR 0 0 0 0 0 0 0 0 0 0 0 0 IESR 29 -- GPIOF Reserved 2A 0000 GPIOF GPIOF_ RAWDATA 0 0 0 0 0 0 0 0 0 0 0 0 RAWDATA 2B 0000 GPIOF GPIOF_ DRIVE 0 0 0 0 0 0 0 0 0 0 0 0 DRIVE 2C 00FF GPIOF GPIOF_IFE 0 0 0 0 0 0 0 0 0 0 0 0 IFE 2D 0000 GPIOF GPIOF_ SLEW 0 0 0 0 0 0 0 0 0 0 0 0 SLEW 2E-3F -- GPIOF Reserved RESERVED RESERVED RESERVED Bit 0 Peripheral Register Memory Map and Reset Value 100 Table 44. Detailed Peripheral Memory Map (continued) 14 13 12 11 10 9 8 7 6 0 0 0 0 0 0 41 0001 SIM SIM_ RSTAT 0 0 0 0 0 0 0 0 0 SWR 42 01F2 SIM SIM_ MSHID SIM_MSH_ID 43 601D SIM SIM_ LSHID SIM_LSH_ID 45 2020 SIM SIM_ CLKOUT 46 0000 SIM SIM_PCR 47 0000 SIM SIM_PCE 48 0000 SIM SIM_SDR 49 F000 SIM SIM_ISAL 4A 0000 SIM SIM_PROT 0 0 0 0 0 0 0 4B 0000 SIM SIM_GPSA 0 0 0 0 0 0 0 4C 0000 SIM SIM_ GPSB0 GPS_B5 4D 0000 SIM SIM_ GPSB1 0 0 0 CMP1 CMP1 0 0 0 0 0 0 0 0 0 0 0 I2C SCI SPI I2C SCI SPI ADDR_15_6 0 0 0 0 0 0 0 0 GPS_A6 GPS_B3 0 STOP_ DISABLE 0 CLKOSEL1 GPS_B4 3 CLKDIS0 0 PGA0 PGA0 0 PGA1 PGA1 0 ADC0 ADC0 0 SCI_CR SIM_CTRL ADC1 ADC1 SIM CMP0 CMP0 PWM_CR CLKDIS1 0000 4 0 2 Bit 0 WAIT_ DISABLE LVDR PPD POR CLKOSEL0 0 0 0 0 0 PWM COP PDB PIT TA1 TA0 PWM COP PDB PIT TA1 TA0 0 0 0 0 0 0 0 0 GPS_A5 PCEP GIPSP GPS_A4 GPS_A3 GPS_B2 0 GPS_B1 0 0 0 0 1 GPS_B7 GPS_B0 GPS_B6 101 Peripheral Register Memory Map and Reset Value MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 40 5 EXTR Bit 15 SW RST Register COP_LOR Reset Value Periph. (Hex) COP_CPU ONCEEBL Offset Addr. (Hex) CMP2 CMP2 TMR_CR Freescale Semiconductor Table 44. Detailed Peripheral Memory Map (continued) 13 12 11 10 9 8 7 6 5 4 3 2 0 0 0 0 0 0 0000 SIM SIM_GPSC 0 0 0 0 0 0 0 0 4F 0000 SIM SIM_GPSD 0 0 0 0 0 0 0 GPS_D3 50 0000 SIM SIM_IPS0 0 0 0 0 51 0000 SIM SIM_IPS1 0 52-5F -- SIM Reserved 60 0208 PMC PMC_SCR 61 00--2 PMC PMC_CR2 7F -- PMC Reserved 80 0000 CMP0 CMP0_ CR0 0 0 0 0 0 0 0 0 0 81 0000 CMP0 CMP0_ CR1 0 0 0 0 0 0 0 0 SE 82 0000 CMP0 CMP0_ FPR 0 0 0 0 0 0 0 0 83 0000 CMP0 CMP0_ SCR 0 0 0 0 0 0 0 0 84-9F -- CMP0 Reserved A0 0000 CMP1 CMP1_ CR0 IPS_C2_WS IPS_C1_WS GPS_D2 GPS_D1 GPS_D0 IPS_PSRC2 IPS_PSRC1 IPS_PSRC0 IPS_C0_WS IPS_T1 IPS_T0 LVDIE LVDRE 0 0 0 0 0 LPRS BGBE OORIE 0 LPR LPWUI PORF 0 LPO_EN PPDE LVDF PPDF RESERVED OORF LVDE LVLS LPO_TRIM PROT TRIM RESERVED WE 0 PMC INV MMC COS OPE EN CFR CFF COUT FILTER_CNT PMODE MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 Freescale Semiconductor 4E Bit 0 1 GPS_C0 14 GPS_C6 Bit 15 IPS_FAULT1 Register IPS_FAULT2 Reset Value Periph. (Hex) IPS_FAULT3 Offset Addr. (Hex) FILT_PER 0 0 0 IER IEF RESERVED 0 0 0 0 0 0 0 0 0 FILTER_CNT PMC MMC Peripheral Register Memory Map and Reset Value 102 Table 44. Detailed Peripheral Memory Map (continued) Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit 0 SE WE 0 PMODE INV COS OPE EN CFR CFF A1 0000 CMP1 CMP1_ CR1 0 0 0 0 0 0 0 0 A2 0000 CMP1 CMP1_ FPR 0 0 0 0 0 0 0 0 A3 0000 CMP1 CMP1_ SCR 0 0 0 0 0 0 0 0 A4-BF -- CMP1 Reserved C0 0000 CMP2 CMP2_ CR0 0 0 0 0 0 0 0 0 0 C1 0000 CMP2 CMP2_ CR1 0 0 0 0 0 0 0 0 SE C2 0000 CMP2 CMP2_ FPR 0 0 0 0 0 0 0 0 C3 0000 CMP2 CMP2_ SCR 0 0 0 0 0 0 0 0 C4-DF -- CMP2 Reserved E0 0000 PIT PIT_CTRL E1 0000 PIT PIT_MOD MODULO_VALUE E2 0000 PIT PIT_CNTR COUNTER_VALUE E3-FF -- PIT Reserved RESERVED 00 0000 PDB PDB_SCR 01 0000 PDB PDB_ DELAYA 0 0 0 IER IEF COUT FILT_PER RESERVED WE 0 PMC INV MMC COS OPE CFR CFF PRF PRIE CNT_EN FILTER_CNT EN ENA ENB 0 0 0 IER IEF COUT FILT_PER RESERVED 0 0 0 PRESCALER 0 0 0 0 AOS 0 0 0 0 BOS DELAYA PRESCALER TRIGSEL 103 Peripheral Register Memory Map and Reset Value MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 Register PMODE Reset Value Periph. (Hex) SWTRIG Offset Addr. (Hex) CONT Freescale Semiconductor Table 44. Detailed Peripheral Memory Map (continued) Register 02 0000 PDB PDB_ DELAYB DELAYB 03 FFFF PDB PDB_MOD MOD 04 FFFF PDB PDB_ COUNT COUNT 05-1F -- PDB Reserved RESERVED 20 0000 RTC RTC_SC 0 0 0 0 0 0 0 0 21 0000 RTC RTC_CNT 0 0 0 0 0 0 0 0 RTCCNT 22 0000 RTC RTC_MOD 0 0 0 0 0 0 0 0 RTCMOD 23-FF -- RTC Reserved 00 0000 HFM FM_ CLKDIV 0 0 0 0 0 0 0 0 01 0000 HFM FM_CNFG 0 0 0 0 0 LOCK 0 AEIE 03 -0003 HFM FM_SECHI SECSTAT 0 0 0 0 0 0 04 0000 HFM FM_ SECLO 0 0 0 0 0 0 0 0 06-0F -- HFM Reserved RESERVED 10 FFFF6 HFM FM_PROT PROTECT 11 -- HFM Reserved RESERVED 13 00C0 HFM FM_USTAT 0 0 0 0 0 0 0 0 CBEIF 14 0000 HFM FM_CMD 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 RTIF 6 5 RTCLKS 4 3 2 RTIE Bit 0 1 RTCPS 0 0 0 LBTS BTS 0 0 0 0 0 0 0 0 0 0 0 CCIF 0 BLANK 0 0 ACCERR 0 KEYACC PRDIV8 CCIE DIV PVIOL DIVLD RESERVED CBEIE MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 Freescale Semiconductor Reset Value Periph. (Hex) KEYEN Offset Addr. (Hex) CMD SEC 0 0 Peripheral Register Memory Map and Reset Value 104 Table 44. Detailed Peripheral Memory Map (continued) Freescale Semiconductor Table 44. Detailed Peripheral Memory Map (continued) Offset Addr. (Hex) 2 3 4 5 6 Register Bit 15 14 13 12 11 10 9 8 7 17 -- HFM Reserved RESERVED 18 0000 HFM FM_DATA FMDATA 19 -- HFM Reserved RESERVED 1A FFFF4 HFM FM_OPT0 IFR_OPT0 1B FFFF5 HFM FM_OPT1 IFR_OPT1 1D FFFF6 HFM FM_ TSTSIG TST_AREA_SIG 1E-3F -- HFM Reserved RESERVED 6 5 4 3 2 1 Bit 0 The binary reset value of this register is 0000 0000 0UUU UUUU, where U represents an undefined value. Spaces have been added to the value for clarity. The binary reset value of this register is 0000 0000 111NC NC NC NC NC. Spaces have been added to the value for clarity. The binary reset value of this register is FS00 0000 0000 0000, where F indicates that the reset state is loaded from the flash array during reset, and where S indicates that the reset state is determined by the security state of the module. Spaces have been added to the value for clarity. The reset state is loaded from the flash array during reset. The reset state is loaded from the flash array during reset. The reset state is loaded from the flash array during reset. 105 Peripheral Register Memory Map and Reset Value MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 1 Reset Value Periph. (Hex) How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. 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