SN74LS191NG - ON SEMICONDUCTOR

September 1983

Revised February 1999

MM74HC175 Quad D-Type Flip-Flop With Clear

MM74HC175

Quad D-Type Flip-Flop With Clear

General Descript ion

The MM74HC175 high spe ed D-type flip-flop with comple-

mentary outputs utilizes advanced silicon-gate CMOS

technology to achieve the high noise immunity and low

power consumption of standard CMOS integrated circuits,

along with the ability to drive 10 LS-TTL loads.

Information at the D inputs of the MM74HC175 is trans-

ferred to the Q and Q outputs on the positive going edge of

the clock pulse. Both true and complement outputs from

each flip flop ar e externally ava ilable. All four flip- flops are

controlled by a common clock and a common CLEAR.

Clearing is accomplished by a negative pulse at the

CLEAR inpu t. A ll fou r Q o utp uts a re cleared t o a l og ical “ 0”

and all four Q outputs to a logical “1.”

The 74HC logic family is functionally as well as pin-out

compatible with the standard 74LS logic family. All inputs

are protected from damage due to static discharge by inter-

nal diode clamps to VCC and ground.

Features

■Typical propagation delay: 15 ns

■Wide operating supply voltage range: 2–6V

■Low input curre nt: 1 µA maximum

■Low quiescent supply current: 80 µA maximum (74HC)

■High output drive current: 4 mA minimum (74HC)

Ordering Code:

Devices also ava ilable in Tape and Reel. Speci fy by append ing the suffix let t er “X” to the o rdering code.

Connection Diagram

Pin Assignments for DIP, SOIC, SOP and TSSOP

Top View

Truth Table (Each Flip-Flop)

H = HIGH Level (steady state)

L = LOW Level (steady state)

X = Irrelevant

↑ = Transition from LOW-to-HIGH level

Q0 = The lev el of Q before t he indicat ed steady-stat e input c onditions were

established

Order Number Package Number Package Description

MM74HC175M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow

MM74HC175SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

MM74HC175MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

MM74HC175N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Inputs Outputs

Clear Clock D Q Q

LXXLH

H↑HH L

H↑LLH

HLXQ

0Q0

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MM74HC175

Logic Diagram

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MM74HC175

Absolute Maximum Ratings(Note 1)

(Note 2) Recommended Operating

Conditions

Note 1: Absolute M aximum Ra tings are those valu es beyond w hich dam-

age to the device may occur.

Note 2: Unles s ot herwise specified all v olt ages are referenc ed to ground.

Note 3: Power Dis sipation te mperature d erating — pl astic “N” pa ckage: −

12 mW/°C from 65°C to 85°C.

DC Electrical Characteristics (Note 4)

Note 4: F or a pow er sup ply of 5V ±1 0% the worst case output voltages (VOH, and V OL) occu r for HC a t 4.5V. Thus the 4.5V values shou ld be use d when

designing with this supply. Worst case VIH and VIL occur at VCC = 5 .5 V and 4.5V respec t iv ely. (T he VIH value at 5. 5V is 3.8 5V.) The worst c as e leakage cur-

rent (IIN, ICC, and IOZ) occur fo r C M OS at the h igher volta ge and so th e 6. 0V values s hould be used.

Supply Voltage (VCC)−0.5 to +7.0V

DC Input Voltage (VIN)−1.5 to VCC +1.5V

DC Output Voltage (VOUT)−0.5 to VCC +0.5V

Clamp Diode Current (IIK, IOK)±20 mA

DC Output Current, per pin (IOUT)±25 mA

DC VCC or GND Current, per pin (ICC)±50 mA

Stora ge Temper atu re Rang e (TSTG)−65°C to +150°C

Power Di ssipa tion (P D)

(Note 3) 600 mW

S.O. Package only 500 mW

Lead Temper ature (TL)

(Soldering 10 seconds ) 260 °C

Min Max Units

Supply Voltage (VCC)26V

DC Input or Output Voltage

(VIN,VOUT)0V

CC V

Operati ng Temperature Range (TA)−40 +85 °C

Input Rise or Fall Times

(tr, tf)V

CC = 2.0V 1000 ns

VCC = 4.5V 500 ns

VCC = 6.0V 400 ns

Symbol Parameter Conditions VCC TA = 25°CT

A = −40 to 85°CT

A = −55 to 125°CUnits

Typ Guaranteed Limits

VIH Minimum HIGH Level 2.0V 1.5 1.5 1.5 V

Input Voltage 4.5V 3.15 3.15 3.15 V

6.0V 4.2 4.2 4.2 V

VIL Maximum LOW Level 2.0V 0.5 0.5 0.5 V

Input Voltage 4.5V 1.35 1.35 1.35 V

6.0V 1.8 1.8 1.8 V

VOH Minimum HIGH Level VIN = VIH or VIL

Output Voltage |IOUT| ≤ 20 µA 2.0V 2.0 1.9 1.9 1.9 V

4.5V 4.5 4.4 4.4 4.4 V

6.0V 6.0 5.9 5.9 5.9 V

VIN = VIH or VIL

|IOUT| ≤ 4.0 mA 4.5V 4.2 3.98 3.84 3.7 V

|IOUT| ≤ 5.2 mA 6.0V 5.7 5.48 5.34 5.2 V

VOL Maximum LOW Level VIN = VIH or VIL

Output Voltage |IOUT| ≤ 20 µA 2.0V 0 0.1 0.1 0.1 V

4.5V 0 0.1 0.1 0.1 V

6.0V 0 0.1 0.1 0.1 V

VIN = VIH or VIL

|IOUT| ≤ 4.0 mA 4.5V 0.2 0.26 0.33 0.4 V

|IOUT| ≤ 5.2 mA 6.0V 0.2 0.26 0.33 0.4 V

IIN Maxim um Input VIN = VCC or GND 6.0V ±0.1 ±1.0 ±1.0 µA

Current

ICC Maximum Quiescent VIN = VCC or GND 6.0V 8 80 160 µA

Supply Current IOUT = 0 µA

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MM74HC175

AC Electrical Characteristics

VCC = 5V, TA = 25°C, CL = 15 pF, tr = tf = 6 ns

AC Electrical Characteristics

VCC = 2.0V to 6.0V, CL = 50 pF, tr = tf = 6 ns (unless otherwise specified)

Note 5: CPD determines the no load dynamic power consumption, PD=CPD V

CC2f+ICC V

CC, and the no load dynamic current consumption,

IS=CPD VCC f+ICC.

Symbol Parameter Conditions Typ Guaranteed Units

Limit

fMAX Maximum Operating 60 35 MHz

Frequency

tPHL, tPLH Maximum Propagation 15 25 ns

Delay, Clock to Q or Q

tPHL, tPLH Maximum Propagation 13 21 ns

Delay, Reset to Q or Q

tREC Minimu m Remov al 20 ns

Time, Clear to Clock

tSMinimum Setup Time, Data to Clock 20 ns

tHMinimum Hold Time, Data from Clock 0 ns

tWMinimum Pulse Width, Clock or Clear 10 16 ns

Symbol Parameter Conditions VCC TA = 25°CT

A = −40 to 85°CT

A = −55 to 125°CUnits

Typ Guaranteed Limits

fMAX Maximum Operating 2.0V 12 6 5 4 MHz

Frequency 4.5V 60 30 24 20 MHz

6.0V 70 35 28 24 MHz

tPHL, tPLH Maximum Propagation 2.0V 80 150 190 225 ns

Delay, Clock to Q or Q 4.5V 15 30 38 45 ns

6.0V 13 26 32 38 ns

tPHL, tPLH Maximum Propagation 2.0V 64 125 158 186 ns

Delay, Reset to Q or Q 4.5V 14 25 32 37 ns

6.0V 12 21 27 32 ns

tREM Minimum Removal Time 2.0V 100 125 150 ns

Clear to Clock 4.5V 20 25 30 ns

6.0V 17 21 25 ns

tSMinimum Setup Time 2.0V 100 125 150 ns

Data to Clock 4.5V 20 25 30 ns

6.0V 17 21 25 ns

tHMinimum Hold Time 2.0V 0 0 0 ns

Data from Clock 4.5V 0 0 0 ns

6.0V 0 0 0 ns

tWMinimum Pulse Width 2.0V 30 80 100 120 ns

Clear or Clock 4.5V 9 16 20 24 ns

6.0V 8 14 17 20 ns

tr, tfMaximum Input Rise and 2.0V 1000 1000 1000 ns

Fall Time 4.5V 500 500 500 ns

6.0V 400 400 400 ns

tTLH, tTHL Maximum 2.0V 30 75 95 110 ns

Output Rise and 4.5V 9 15 19 22 ns

Fall Time 6.0V 8 13 16 19 ns

CPD Power Dissipation (per package) 150 pF

Capacitance (Note 5)

CIN Maximum Input 5 10 10 10 pF

Capacitance

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MM74HC175

Physical Dimensions inches (millimeters) unless otherwise noted

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow

Package Number M16A

16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

Package Number M16D

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MM74HC175

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Package Number MTC16

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

MM74HC175 Quad D-Type Flip-Flop With Clear

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD

SEMICONDUCTOR CORPORATION. As used herein:

1. Life suppor t de vices o r syst ems are devices or syste ms

which, (a) are intended for surgical implant into the

body, or (b) support or sustain life, and (c) whose failure

to perform when properly used in accordance with

instruct ions fo r use pr ovi de d in the labe l ing, can be re a-

sonably expected to result in a significant injury to the

user.

2. A criti cal com ponen t in any compo nent o f a l ife supp ort

device or system whose failure to perform can be rea-

sonabl y e xpec ted to c ause th e fa i lure of the li fe s upp or t

device or system, or to affect its safety or effectiveness.

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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Package Number N16E