High Performance
HDMI/DVI Transmitter
AD9889B
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
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Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2007–2010 Analog Devices, Inc. All rights reserved.
FEATURES
General
HDMI™/DVI transmitter compatible with HDMI v. 1.3,
DVI v. 1.0, and HDCP v. 1.2
Single 1.8 V power supply
Video/audio inputs accept logic levels from 1.8 V to 3.3 V
80-lead LQFP, Pb-free package
64-lead LFCSP, Pb-free package
76-ball CSP_BGA, Pb-free package
Digital video
165 MHz operation supports all resolutions from 480i to
1080p and UXGA at 60 Hz
Programmable two-way color space converter
Supports RGB, YCbCr, and DDR
Supports ITU656-based embedded syncs
Automatic input video format timing detection (CEA-861B)
Digital audio
Supports standard S/PDIF for stereo LPCM or compressed
audio up to 192 kHz
8-channel, uncompressed, LPCM I2S audio up to 192 kHz
Special features for easy system design
On-chip MPU with I2C® master to perform HDCP
operations and EDID reading operations
5 V tolerant I2C and HPD I/Os, no extra device needed
No audio master clock needed for supporting S/PDIF
and I2S
On-chip MPU reports HDMI events through interrupts and
registers
APPLICATIONS
DVD players and recorders
Digital set-top boxes
A/V receivers
Digital cameras and camcorders
HDMI repeater/splitter
GENERAL DESCRIPTION
The AD9889B is a 165 MHz, high definition multimedia inter-
face (HDMI) v. 1.3 transmitter. It supports HDTV formats up to
1080p, and computer graphic resolutions up to UXGA (1600 ×
1200 @ 60 Hz). With the inclusion of HDCP, the AD9889B allows
the secure transmission of protected content as specified by the
HDCP v. 1.2 protocol.
FUNCTIONAL BLOCK DIAGRAM
SD
A
SCL
DDCSDA
DDCSCL
HPD
IN
T
INTERRUPT
HANDLER
HDCP-EDID
MICRO-
CONTROLLER
HDCP
CORE
I
2
C
MASTER
I
2
C
SLAVE
REGISTER
CONFIGURATION
LOGIC
HDMI
Tx
CORE
XOR
MASK
COLOR
SPACE
CONVER-
SION
4:2:2 TO
4:4:4
CONVER-
SION
VIDEO
DATA
CAPTURE
AUDIO
DATA
CAPTURE
Tx0–/Tx0+
Tx1–/Tx1+
Tx2–/Tx2+
TxC–/TxC+
CLK
VSYNC
HSYNC
DE
D[23:0]
S/PDIF
MCLK
I
2
S[3:0]
LRCLK
SCLK
MDAMCL
AD9889B
06291-001
Figure 1.
The AD9889B supports both S/PDIF and 8-channel I2S audio.
Its high fidelity, 8-channel I2S can transmit either stereo or 7.1
surround audio at 192 kHz. The S/PDIF can carry stereo LPCM
audio or compressed audio, including DTS®, THX®, and Dolby®
Digital.
The AD9889B helps reduce system design complexity and cost
by incorporating such features as an internal MPU for HDCP
operations, an I2C master for EDID reading, a single 1.8 V power
supply, and 5 V tolerance on the I2C and hot plug detect pins.
Fabricated in an advanced CMOS process, the AD9889B is
available in a space-saving, 76-ball CSP_BGA or 64-lead LFCSP
surface-mount package, and an 80-lead LQFP surface-mount
package. All packages are available as Pb-free and are specified
from −25°C to +85°C.
AD9889B
Rev. A | Page 2 of 12
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Absolute Maximum Ratings ............................................................ 5
Explanation of Test Levels ........................................................... 5
ESD Caution .................................................................................. 5
Pin Configurations and Function Descriptions ........................... 6
Applications Information .................................................................9
Design Resources ..........................................................................9
Document Conventions ...............................................................9
PCB Layout Recommendations .................................................... 10
Power Supply Bypassing ............................................................ 10
Digital Inputs .............................................................................. 10
External Swing Resistor ............................................................. 10
Output Signals ............................................................................ 10
Outline Dimensions ....................................................................... 11
Ordering Guide .......................................................................... 12
REVISION HISTORY
3/10—Rev. 0 to Rev. A
Changes to Clock Frequency Parameter, Table 1 ......................... 3
Changes to Digital Inputs Parameter, Table 2 ............................... 5
Changes to Table 3 ............................................................................ 7
Changes to Design Resources Section ........................................... 9
4/07—Revision 0: Initial Version
AD9889B
Rev. A | Page 3 of 12
SPECIFICATIONS
Table 1.
Parameter Conditions Temp
Test
Level1 Min Typ Max Unit
DIGITAL INPUTS
Input Voltage, High (VIH) Full VI 1.4 3.5 V
Input Voltage, Low (VIL) Full VI 0.7 V
Input Capacitance 25°C V 3 pF
DIGITAL OUTPUTS
Output Voltage, High (VOH) Full VI VDD − 0.1 V
Output Voltage, Low (VOL) Full VI 0.4 V
THERMAL CHARACTERISTICS
Thermal Resistance
θJC Junction-to-Case V 15.2 °C/W
θJA Junction-to-Ambient V 59 °C/W
Ambient Temperature Full V −25 +25 +85 °C
DC SPECIFICATIONS
Input Leakage Current, IIL 25°C VI −10 +10 μA
Input Clamp Voltage −16 mA 25°C V −0.8 V
+16 mA 25°C V +0.8 V
Differential High Level Output
Voltage
V AVCC V
Differential Output Short-Circuit
Current
IV 10 μA
POWER SUPPLY
VDD (All) Supply Voltage Full IV 1.71 1.8 1.89 V
VDD Supply Voltage Noise Full V 50 mV p-p
Power-Down Current With active video applied, 165 MHz, typical
random pattern
25°C IV 9 mA
Transmitter Supply Current With active video applied, 165 MHz, typical
random pattern
25°C IV 240 280 mA
Transmitter Total Power Full VI 432 504 mW
AC SPECIFICATIONS
CLK Frequency 25°C IV 13.5 165 MHz
TMDS Output CLK Duty Cycle 25°C IV 48 52 %
Worst Case CLK Input Jitter Full IV 2 ns
Input Data Setup Time Full IV 1 ns
Input Data Hold Time Full IV 1 ns
TMDS Differential Swing VI 800 1000 1200 mV
VSYNC and HSYNC Delay from DE
Falling Edge
VI 1 UI2
VSYNC and HSYNC Delay to DE
Rising Edge
VI 1 UI2
DE High Time 25°C VI 8191 UI2
DE Low Time 25°C VI 138 UI2
Differential Output Swing
Low-to-High Transition Time 25°C VII 75 490 ps
High-to-Low Transition Time 25°C VII 75 490 ps
AD9889B
Rev. A | Page 4 of 12
Parameter Conditions Temp
Test
Level1 Min Typ Max Unit
AUDIO AC TIMING
Sample Rate I2S and S/PDIF Full IV 32 192 kHz
I2S Cycle Time 25°C IV 1 UI2
I2S Setup Time 25°C IV 15 ns
I2S Hold Time 25°C IV 0 ns
Audio Pipeline Delay 25°C IV 75 μs
1 See section. Explanation of Test Levels
2 UI = unit interval.
AD9889B
Rev. A | Page 5 of 12
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
Digital Inputs +5.5 V to −0.3 V
Digital Output Current 20 mA
Operating Temperature Range −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Maximum Junction Temperature 150°C
Maximum Case Temperature 150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
EXPLANATION OF TEST LEVELS
I. 100% production tested.
II. 100% production tested at 25°C and sample tested at
specified temperatures.
III. Sample tested only.
IV. Parameter is guaranteed by design and characterization
testing.
V. Parameter is a typical value only.
VI. 100% production tested at 25°C; guaranteed by design
and characterization testing.
VII. Limits defined by HDMI specification; guaranteed by
design and characterization testing.
ESD CAUTION
AD9889B
Rev. A | Page 6 of 12
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
2
D0
3
DE
4
HSYNC
7
S/PDIF
6
CLK
5
VSYNC
1
DVDD
8
MCLK
9
I
2
S0
10
I
2
S1
12
I
2
S3
13
SCLK
14
LRCLK
15
GND
16
PVDD
17
GND
18
GND
19
PVDD
20
PVDD
11
I
2
S2
59
58
57
54
55
56
60
53
52
GND
D15
D16
D19
D18
D17
GND
D20
D21
51
D22
49
MCL
48
MDA
47
SDA
46
SCL
45
DDCSDA
44
DDCSCL
43
GND
42
GND
41
AVDD
50
D23
21
PVDD
22
GND
23
EXT_SWG
24
AVDD
25
HPD
26
GND
27
TxC–
28
TxC+
29
AVDD
30
Tx0–
31
Tx0+
32
GND
33
PD/A0
34
Tx1–
35
Tx1+
36
AVDD
37
Tx2–
38
Tx2+
39
GND
40
INT
80
GND
79
GND
78
D1
77
D2
76
D3
75
D4
74
D5
73
D6
72
D7
71
D8
70
D9
69
D10
68
D11
67
D12
66
D13
65
D14
64
DVDD
63
DVDD
62
DVDD
61
DVDD
PIN 1
INDICATOR
AD9889B
TOP VIEW
(No t to Scale)
06291-002
Figure 2. 80-Lead LQFP Pin Configuration (Top View)
PIN 1
INDICATOR
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
PVDD
EXT_SWG
AVDD
HPD
TxC–
TxC+
AVDD
Tx0–
Tx0+
PD/A0
Tx1–
Tx1+
AVDD
Tx2–
Tx2+
INT
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
DGND
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
DVDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
DVDD
D0
DE
HSYNC
V
SYN
C
CLK
S/PDIF
MCLK
I
2
S0
I
2
S1
I
2
S2
I
2
S3
SCLK
LRCLK
PVDD
PVDD
DVDD
D15
D16
D17
D18
D19
D20
D21
D22
D23
MCL
MDA
SDA
SCL
DDCSDA
DDCSCL
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
AD9889B
TOP VIEW
(No t t o S cale)
06291-003
NOTES
1. G ND P ADDLE ON BOTTOM O F PACKAGE.
+
Figure 3. 64-Lead LFCSP Pin Configuration (Top View)
AD9889B
Rev. A | Page 7 of 12
J
K
A
B
C
D
E
F
G
H
10 8 7 6 3 2 1954
6291-004
BOTTOM VI EW
(Not to Scale)
0
Figure 4. 76-Ball BGA Configuration (Top View)
Table 3. Pin Function Descriptions
Pin No.
Mnemonic Type1 Description BGA LFCSP LQFP
D10, D9, C10,
C9, A10, B10,
A9, B9, A8, B8,
A7, B7, A6, B6,
A5, B5, A4, B4,
A3, B3, A2, B2,
A1, B1
39 to 47,
50 to 63, 2
50 to 58, 65 to
78, 2
D[23:0] I Video Data Input. Digital input in RGB or YCbCr format.
Supports CMOS logic levels from 1.8 V to 3.3 V.
D1 6 6 CLK I
Video Clock Input. Supports CMOS logic levels from 1.8 V
to 3.3 V.
C2 3 3 DE I
Data Enable Bit for Digital Video. Supports CMOS logic levels
from 1.8 V to 3.3 V.
C1 4 4 HSYNC I
Horizontal Sync Input. Supports CMOS logic levels from
1.8 V to 3.3 V.
D2 5 5 VSYNC I
Vertical Sync Input. Supports CMOS logic levels from 1.8 V
to 3.3 V.
J3 18 23 EXT_SWG I
Sets Internal Reference Currents. Place 887 Ω resistor
(1% tolerance) between this pin and ground.
K3 20 25 HPD I
Hot Plug Detect Signal. This indicates to the interface
whether the receiver is connected. Supports 1.8 V to 5.0 V
CMOS logic levels.
E2 7 7 S/PDIF I
S/PDIF (Sony/Philips Digital Interface) Audio Input. This is
the audio input from a Sony/Philips digital interface.
Supports CMOS logic levels from 1.8 V to 3.3 V.
E1 8 8 MCLK I
Audio Reference Clock. 128 × N × fS with N = 1, 2, 3, or 4.
Set to 128 × sampling frequency (fS), 256 × fS, 384 × fS, or
512 × fS. Supports 1.8 V to 3.3 V CMOS logic levels.
F2, F1, G2, G1 9 to 12 9 to 12 I2S[3:0] I I2S Audio Data Inputs. These represent the eight channels of
audio (two per input) available through I2S. Supports CMOS
logic levels from 1.8 V to 3.3 V.
H2 13 13 SCLK I I2S Audio Clock. Supports CMOS logic levels from 1.8 V to 3.3 V.
H1 14 14 LRCLK I
Left/Right Channel Selection. Supports CMOS logic levels
from 1.8 V to 3.3 V.
J72 262 332 PD/A0 I
Power-Down Control and I2C Address Selection. The I2C
address and the PD polarity are set by the PD/A0 pin state
when the supplies are applied to the AD9889B. Supports
1.8 V to 3.3 V CMOS logic levels.
K1, K2 21, 22 27, 28 TxC−/TxC+ O Differential Clock Output. Differential clock output at pixel
clock rate; supports TMDS logic level.
K10, J10 30, 31 37, 38 Tx2−/Tx2+ O Differential Output Channel 2. Differential output of the red
data at 10× the pixel clock rate; supports TMDS logic level.
AD9889B
Rev. A | Page 8 of 12
Pin No.
Mnemonic Type1 Description BGA LFCSP LQFP
K7, K8 27, 28 34, 35 Tx1−/Tx1+ O Differential Output Channel 1. Differential output of the
green data at 10× the pixel clock rate; supports TMDS logic level.
K4, K5 24, 25 30, 31 Tx0−/Tx0+ O Differential Output Channel 0. Differential output of the blue
data at 10× the pixel clock rate; TMDS logic level.
H10 32 40 INT O
Interrupt. Open drain. A 2 kΩ pull-up resistor to the
microcontroller I/O supply is recommended.
J2, J5, J8, K9 19, 23, 29 24, 29, 36, 41 AVDD P 1.8 V Power Supply for TMDS Outputs.
D5, D6, D7, E7 1, 48, 49 1, 61, 62, 63, 64 DVDD P
1.8 V Power Supply for Digital and I/O Power Supply. These
pins supply power to the digital logic and I/Os. They should
be filtered and as quiet as possible.
G4, G5, J1 15, 16, 17, 16, 19, 20, 21 PVDD P
1.8 V PLL Power Supply. The most sensitive portion of the
AD9889B is the clock generation circuitry. These pins provide
power to the clock PLL. The designer should provide quiet,
noise-free power to these pins.
D4, E4, F4, J4,
G6, J6, K6, F7,
G7, H9, J9
N/A 15, 17, 18, 22,
26, 32, 39, 42,
43, 59, 60, 79, 80
GND P
Ground. The ground return for all circuitry on-chip. For best
practice, assemble the AD9889B on a single, solid ground
plane with careful attention given to ground current paths.
N/A 64, paddle
on bottom
side
N/A DGND P
Digital Ground. The ground return for all circuitry on-chip.
For best practice, assemble the AD9889B on a single, solid
ground plane with careful attention given to ground
current paths.
F9 36 47 SDA C3 Serial Port Data I/O. This pin serves as the serial port data I/O
slave for register access. Supports CMOS logic levels from
1.8 V to 3.3 V.
F10 35 46 SCL C3 Serial Port Data Clock. This pin serves as the serial port data
clock slave for register access. Supports CMOS logic levels
from 1.8 V to 3.3 V.
E10 37 48 MDA C3 Serial Port Data I/O Master to HDCP Key EEPROM. Supports
CMOS logic levels from 1.8 V to 3.3 V.
E9 38 49 MCL C3 Serial Port Data Clock Master to HDCP Key EEPROM. Supports
CMOS logic levels from 1.8 V to 3.3 V.
G9 34 45 DDCSDA C3 Serial Port Data I/O to Receiver. This pin serves as the master
to the DDC bus. Supports a 5 V CMOS logic level.
G10 33 44 DDCSCL C3 Serial Port Data Clock to Receiver. This pin serves as the
master clock for the DDC bus. Supports a 5 V CMOS logic level.
1 I = input, O = output, P = power supply, C = control.
2 Pin J7 (BGA), Pin 26 (LFCSP), and Pin 33 (LQFP) are dual function pins: I2C selection and power-down control. The I2C selection function occurs at power-up; the power-
down control function occurs whenever the state of the pin is changed from its original state at power-up.
3 For a full description of the 2-wire serial interface and its functionality, obtain documentation by contacting NDA from ATV_VideoTx_Apps@analog.com.
AD9889B
Rev. A | Page 9 of 12
APPLICATIONS INFORMATION
DESIGN RESOURCES
Analog Devices, Inc. evaluation kits, reference design
schematics, and other support documentation are available
under the nondisclosure agreement (NDA) from
ATV_VideoTx_Apps@analog.com.
Other resources include:
EIA/CEA-861B, which describes audio and video infoframes as
well as the E-EDID structure for HDMI. It is available from
Consumer Electronics Association (CEA).
The HDMI v. 1.3, a defining document for HDMI Version 1.3,
and the HDMI Compliance Test Specification Version 1.3 are
available from HDMI Licensing, LLC.
The HDCP v. 1.2 is the defining document for HDCP
Version 1.2 available from Digital Content Protection, LLC.
DOCUMENT CONVENTIONS
In this data sheet, data is represented using the conventions
described in Table 4.
Table 4. Document Conventions
Data
Type Format
0xNN Hexadecimal (Base-16) numbers are represented using
the C language notation, preceded by 0x.
0bNN Binary (Base-2) numbers are represented using the C
language notation, preceded by 0b.
NN Decimal (Base-10) numbers are represented using no
additional prefixes or suffixes.
Bit Bits are numbered in little endian format, that is, the
least significant bit of a byte or word is referred to as Bit 0.
AD9889B
Rev. A | Page 10 of 12
PCB LAYOUT RECOMMENDATIONS
The AD9889B is a high precision, high speed analog device. As
such, to obtain the maximum performance from the part, it is
important to have a well laid out board.
POWER SUPPLY BYPASSING
It is recommended to bypass each power supply pin with a
0.1 µF capacitor. The exception is when two or more supply
pins are adjacent to each other. For these groupings of
powers/grounds, it is necessary to have only one bypass
capacitor. The fundamental idea is to have a bypass capacitor
within about 0.5 cm of each power pin. Also, avoid placing the
capacitor on the opposite side of the PC board from the
AD9889B, as that interposes resistive vias in the path.
The bypass capacitors should be physically located between the
power plane and the power pin. Current should flow from the
power plane to the capacitor to the power pin. Do not make a
power connection between the capacitor and the power pin.
Placing a via underneath the capacitor pads, down to the power
plane, is generally the best approach.
It is particularly important to maintain low noise and good
stability of PVDD (the PLL supply). Abrupt changes in PVDD
can result in similarly abrupt changes in sampling clock phase
and frequency. This can be avoided by careful attention to
regulation, filtering, and bypassing. It is best practice to provide
separate regulated supplies for each of the analog circuitry
groups (AVDD and PVDD).
It is also recommended to use a single ground plane for
the entire board. Experience has repeatedly shown that
the noise performance is the same or better with a single
ground plane. Using multiple ground planes can be detri-
mental because each separate ground plane is smaller, and
long ground loops can result.
DIGITAL INPUTS
Video and Audio Data Input Signals
The digital inputs on the AD9889B are designed to work with
signals ranging from 1.8 V to 3.3 V logic levels. Therefore, no
extra components need to be added when using 3.3 V logic.
Any noise that gets onto the clock input (labeled CLK) trace
adds jitter to the system. Therefore, minimize the video clock
input (Pin 6: CLK) trace length and do not run any digital or
other high frequency traces near it. Make sure to match the
length of the input data signals to optimize data capture,
especially for high frequency modes such as 1080p, UXGA, and
double data rate input formats.
Other Input Signals
The HPD must be connected to the HDMI connector. A 10 kΩ
pull-down resistor to ground is also recommended.
The PD/A0 input pin can be connected to GND or supply
(through a resistor or a control signal). The device address and
power-down polarity are set by the state of the PD/A0 pin when
the AD9889B supplies are applied/enabled. For example, if the
PD/A0 pin is low (when the supplies are turned on), then the
device address is 0x72 and the power-down is active high. If the
PD/A0 pin is high (when the supplies are turned on), the device
address is 0x7A and the power-down is active low.
The SCL and SDA pins should be connected to the I2C master.
A pull-up resistor of 2 k to 1.8 V or 3.3 V is recommended.
EXTERNAL SWING RESISTOR
The external swing resistor must be connected directly to the
EXT_SWG pin and ground. The external swing resistor must
have a value of 887 Ω (±1% tolerance). Avoid running any high
speed ac or noisy signals next to, or close to, the EXT_SWG pin.
OUTPUT SIGNALS
TMDS Output Signals
The AD9889B has three TMDS data channels (0, 1, and 2) that
output signals up to 800 MHz as well as the TMDS output data
clock. To minimize the channel-to-channel skew, make the
trace length of these signals the same. Additionally, these traces
need to have a 50 characteristic impedance and need to be
routed as 100 differential pairs. Best practice recommends
routing these lines on the top PCB layer to avoid the use of vias.
Other Output Signals (non TMDS)
DDCSCL and DDCSDA
The DDCSCL and DDCSDA outputs need to have a minimum
amount of capacitance loading to ensure the best signal integrity.
The DDCSCL and DDCSDA capacitance loading must be less
than 50 pF to meet the HDMI compliance specification. The
DDCSCL and DDCSDA must be connected to the HDMI
connector and a pull-up resistor to 5 V is required. The pull-up
resistor must have a value between 1.5 kΩ and 2 kΩ.
INT Pin
The INT pin is an output that should be connected to the micro-
controller of the system. A pull-up resistor to 1.8 V or 3.3 V is
required for proper operation—the recommended value is 2 kΩ.
MCL and MDA
The MCL and MDA outputs should be connected to the
EEPROM containing the HDCP key (if HDCP is implemented).
Pull-up resistors of 2 kΩ are recommended.
AD9889B
Rev. A | Page 11 of 12
OUTLINE DIMENSIONS
COMP LIANT TO JEDEC STANDARDS MS - 026- BE C
1.45
1.40
1.35
0.15
0.05
0.20
0.09
0.10
COPLANARITY
VIEW A
ROTATED 90° CCW
SEATING
PLANE
7°
3.5°
0°
6160
180
20 41
21 40
VIEW A
1.60
MAX
0.75
0.60
0.45
16.20
16.00 SQ
15.80
14.20
14.00 SQ
13.80
0.65
BSC
LEAD PITCH
0.38
0.32
0.22
TOP VI EW
(PINS DOWN)
PIN 1
051706-A
Figure 5. 80-Lead Low Profile Quad Flat Package [LQFP]
(ST-80-2)
Dimensions shown in millimeters
PIN 1
INDICATOR
TOP
VIEW 8.75
BSC SQ
9.00
BSC SQ
1
64
16
17
49
48
32
33
0.50
0.40
0.30
0.50 BS C 0. 20 REF
12° M AX 0.80 M AX
0.65 TYP
1.00
0.85
0.80
7.50
REF
0.05 M A X
0.02 NOM
0.60 M A X
0.60 M A X
*4.85
4.70 SQ
4.55
EXPOSED PAD
(BOTTO M VI EW )
*COM PLI ANT T O JEDEC S TANDARDS MO-220-VMMD-4
EXCEP T F OR EXPOSE D PAD DIMENSION
082908-B
SEATING
PLANE
PIN 1
INDICATOR
0.30
0.25
0.18
FOR PRO PER CONNECTI ON OF
THE EX POSE D PAD, REFER TO
THE PIN CONFI GURATION AND
FUNCT ION DESCRIP TI ONS
SECTION OF THIS DATA SHEET.
Figure 6. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
9 mm × 9 mm Body, Very Thin Quad
(CP-64-1)
Dimensions shown in millimeters
AD9889B
Rev. A | Page 12 of 12
*COMP LIANT TO JEDEC STANDARDS MO-225
WI TH T HE E XCEPT IO N TO PACKAGE HEIGHT.
A
B
C
D
E
F
G
J
H
K
10 8 7 6 321
954
A
1 CORNER
INDEX ARE A
TO P VIEW
BALL A1
PAD CORNE R
DETAIL A BOTTOM VI EW
0.75
REF
6.10
6.00 SQ
5.90
SEATING
PLANE
BALL DI AMET E R
0.15 M IN
0.35
0.30
0.25
COPLANARITY
0.08 MAX
0.65 MIN
0.50
BSC
4.50
BSC SQ
*1.40 M AX
010807-A
DETAIL A
Figure 7. 76-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
6 mm × 6 mm × 1.4 mm
(BC-76-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
AD9889BBCPZ-80 −25°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-64-1
AD9889BBCPZ-165 −25°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-64-1
AD9889BBSTZ-80 −25°C to +85°C 80-Lead Low Profile Quad Flat Package [LQFP] ST-80-2
AD9889BBSTZ-165 −25°C to +85°C 80-Lead Low Profile Quad Flat Package [LQFP] ST-80-2
AD9889BBBCZ-80 −25°C to +85°C 76-Ball Chip Scale Package Ball Grid Array [CSP_BGA] BC-76-1
AD9889BBBCZRL-80 −25°C to +85°C 76-Ball Chip Scale Package Ball Grid Array [CSP_BGA] BC-76-1
AD9889B/PCBZ Evaluation Board
1 Z = RoHS Compliant Part.
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
©2007–2010 Analog Devices, Inc. All rights reserved. Trademarks and
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D06291-0-3/10(A)
