CY7C09569V PRELIMINARY CY7C09579V 3.3V 16K/32K x 36 FLEx36 Synchronous Dual-Port Static RAM Features True Dual-Ported memory cells which allow simulta- neous access of the same memory location 2 Flow-Through/Pipelined devices 16K x 36 organization (CY7CO09569V) 32K x 36 organization (CY7C09579V) * 0.25-micron CMOS for optimum speed/power * 3 Modes Flow-Through Pipelined Burst Bus-Matching Capabilities on Right Port (x36 to x18 or x9) * Byte-Select Capabilities on Left Port 100-MHz Pipelined Operation High-speed clock to data access 5/6/8 ns 3.3V Low operating power Active= 165 mA (typical) Standby= 10 A (typical) Fully synchronous interface for ease of use Burst counters increment addresses internally Shorten cycle times Minimize bus noise Supported in Flow-Through and Pipelined modes Counter Address Read Back via I/O lines Single Chip Enable Automatic power-down Commercial and Industrial Temperature Ranges Compact package 144-Pin TQFP (20 x 20 x 1.4 mm) 144-Ball MiniBGA (.8 mm pitch) (12 x 12 x .51 mm) Logic Block Diagram AAT, r RL TTT y i _____ R/Wp_ so __F OFL Left Right (+ Er Bo-B3 7 ~~Port Port __ CE | Control Control |* CER wrt Logic Logic FT/Pipes 4 i FT/Pipea BE 9 9 V/Opo.-l/Og, p ~ 9 9 VOg-VO471 * 7 > 0 vO N W380 9 Control Control 9 Match R 4 f. XX VO1e.-VOr618 7 , N i 9 9 A 4 LZ > x A | VOon-WOge 7 Sp BM [1] 14/15 Vv 14/15 [1] Ao-Ai314L Ao-A13/14R cLK, } Counter/ Counter/ + CLKp ADS, Address -) True Dual-Ported a Address ADS aL Register RAM Array Register __ PR CNTEN_ Decode Decode CNTENR CNTRSTp it CNTRSTR Note: 1. Ag-Ay3 for 16K; ApAy, for 32K devices. For the most recent information, visit the Cypress web site at www.cypress.com Cypress Semiconductor Corporation + 3901 North First Street * SanJose + CA 95134 + 408-943-2600 February 23, 1999PRELIMINARY CY7CO9569V CY7C09579V (CYPRESS Functional Description The CY7C09569V and CY7C09579V are high-speed 3.3V synchronous CMOS 16K and 32K x 36 dual-port static RAMs. Two ports are provided permitting independent, simultaneous access for reads and writes to any location in memory. Regis- ters on control, address, and data lines allow for minimal set-up and hold times. In pipelined output mode, data is regis- tered for decreased cycle time. Clock to data valid tcps = 5 ns (pipelined). Flow-through mode can also be used to bypass the pipelined output register to eliminate access latency. In flow-through mode data will be available tcp; = 15 ns after the address is clocked into the device. Pipelined output or flow-through mode is selected via the FT/Pipe pin. Each port contains a burst counter on the input address regis- ter. The internal write pulse width is independent of the exter- nal R/W LOW duration. The internal write pulse is self-timed to allow the shortest possible cycle times. A LOW on CE for one clock cycle will power down the internal circuitry to reduce the static power consumption. In the pipe- lined mode, one cycle is required with CE LOW to reactivate the outputs. Counter Enable Inputs are provided to stall the operation of the address input and utilize the internal address generated by the internal counter for fast interleaved memory applications. A ports burst counter is loaded with the port's address strobe (ADS). When the ports Count Enable (CNTEN) is asserted, the address counter will increment on each LOW to HIGH tran- sition of that ports clock signal. This will read/write one word from/into each successive address location until CNTEN is deasserted. The counter can address the entire memory array and will loop back to the start. Counter Reset (CNTRST) is used to reset the burst counter. All parts are available in 144-Pin Thin Quad Plastic Flatpack (TQFP) and 144-Ball Mini-Ball Grid Array (miniBGA).PRELIMINARY CY7CO9569V CY7C09579V Pin Configurations VO32L VO31L GND VO30L V/O29L VO28L VO27L voc VO17L VO16L 144-Pin Thin Quad Flatpack (TQFP) VO15L VO14L GND Top View GND VO14R VO15R VO16R VO17R voc 027R /028R \O29R O30R GND VO31R 032R /O33L /034L (O33. == AOLD 2 ON ooh wnhm Oo wD Al Sig 2223 B aaa ea ase NOoah won oO RWL Oo vec [ GND & GND Co cEL = CLKL == ADSL CNTRSTL CNTENL FrPIrPeEL_C ASLO AL AoLc AL AL =5 ABLo lenp == yo2z6eLE yo2sLE yoxuLo DOHYYwWwH WWONNNMNNNHNNNNN ZS Oak won] C0 WDNO OK WON +~700 8 a aa? NN & O00 == Notes: 2. 3. This pin is A14L for CY7CO9579V. This pin is A14R for CY7CO9579V. 144 143 142 144 VvO21L VO20L 140 139 138 137 136 135 134 133 132 VvO19L VO18L voc VO8L VO7L reanrmnowowOs HOANAAAA rrrr re ee TT 121 120 119 118 417 116 115 CY7CO9569V (16K x 36) CY7C09579V (32K x 36) VO5L GND VO4L VO3L VvOo2L VOL GND VO5R V/O6R VO7R V/O8R voc VO18R 414 VO19R 113 O20R VO21R 112 444 GND O22R V/023R 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 90 89 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 - 1/033R c 1/034R - 1/035R i] ~AOR i] AIR i A2R i ~A3R I A4R CT) ~AS5R i] ~A6R i] A7R - BM - size i] BE J ~2GND [] OER oes iI vec -7 GND [ GND - CER [] CLKR [I1 ADSR 1 CNTRSTR [_ CNTENR [ FT/PIPER i A&R i] ASR )_ Ai0R ] AiR i7 A12R [- Ai3R anvils] - /026R )S1/025R 1/024RCY7C09569V PRELIMINARY CY7C09579V Pin Configurations (continued) 144-Ball Mini-Ball Grid Array (BGA) Top View 1 2 3 4 5 6 7 8 9 10 11 12 13 A VO32L VO30L voc VO15L VO13L VOT1L VO9R VO11R VO13R VO15R vcc VO30R VO32R B AOL VO33L vO2SL VO17L VO14L VvO12L VOSL VO12R VO14R VO17R VO29R VO33R AOR Cc A4L AIL VO31L GND VO27L GND VO10L GND VO27R GND VO31R AIR A4R D A7L ASL VO35L VO34L VvO28L VO16L VO10R VO16R VO28R VO34R VO35R ASR A7R E Be Bo ASL A2L A2R A3R BM WA F OEL B3 BT A6L A6R SIZE BA OER G GND vcc GND RAVE RAWR vcc voc GND H CEL CLKL |CNTRSTL A8L A8R CNTRSTR] CLKR CER I ADSL CNTENL AIL Al2L A12R A11R CNTENR}| ADSR J FY/PIPEL ASL VO26L VO25L VO19L VO7L VO1L VO7R VO19R VO25R VO26R ASR FT/PIPER K A10L A13L vO22L GND VO18L GND VvO1R GND VO18L GND VO22R A13R A10R L GND] VO24L VvO20L VO8L VO5L VO3L VOOL VO3R VO5R V/O8R VO20R VO24R G@NDIl M VO23L VvO21L voc VO6L VO4L VvOe2L VOOR VO2R VO4R VO6R vcc O21R 1/023RCY7CO9569V PRELIMINARY CY7C09579V oe Selection Guide CY7CO09569V CY7CO09569V CY7CO09569V CY7C09579V CY7C09579V CY7C09579V 100 -83 -67 fuaxe (MHz) (Pipelined) 100 83 67 Max. Access Time (ns) (Clock to Data, Pipelined) 5 6 8 Typical Operating Current lec (mA) 165 155 145 Typical Standby Current for lgp, (mA) (Both Ports TTL Level) 30 25 25 Typical Standby Current for Igp3 (uA) (Both Ports CMOS Level) 10 pA 10 pA 10 pA Pin Definitions Left Port Right Port Description Aot-Aiaii4L. | Aorn-Ai3/14p_ | Address Inputs (AgAy3 for 16K, Ag-Ay4 for 32K devices). ADS, ADS Address Strobe Input. Used as an address qualifier. This signal should be asserted LOW to assert the part using the externally supplied address on Address Pins and to load this address into the Burst Address Counter. CE, CER Chip Enable Input. CLK, CLKr Clock Signal. This input can be free running or strobed. Maximum clock input rate is fax. CNTEN, CNTENR Counter Enable Input. Asserting this signal LOW increments the burst address counter of its respective port on each rising edge of CLK. CNTEN is disabled if ADS or CNTRST are asserted LOW. CNTRST,_ CNTRSTR Counter Reset Input. Asserting this signal LOW resets the burst address counter of its respec- tive port to zero. CNTRST is not disabled by asserting ADS or CNTEN. VOo.-VOg5_ | VOoR-VOg5R_ | Data Bus Input/Output. OE, OER Output Enable Input. This signal must be asserted LOW to enable the I/O data pins during read operations. RW R/Wr Read/Write Enable Input. This signal is asserted LOW to write to the dual port memory array. For read operations, assert this pin HIGH. FT/PIPE, FT/PIPER Flow-Through/Pipelined Select Input. For flow-through mode operation, assert this pin LOW. For pipelined mode operation, assert this pin HIGH. By-B3 Byte Select Inputs. Asserting these signals enable read and write operations to the correspond- ing bytes of the memory array. BM, SIZE Select Pins for Bus Matching. See Bus Matching for details. BE Big Endian Pin. See Bus Matching for details. GND Ground Input. Vec Power Input.CY7CO9569V PRELIMINARY CY7C09579V oe Maximum Ratings Output Current into Outputs (LOW)..........: cee 20 mA (Above which the useful life may be impaired. For user guide- Static Discharge Voltage ........eeeceesseeeesneeeeneeeeneeees >2001V lines, not tested.) Latch-Up Current... .eeeseeeesseeseeeeeesneeeeeseeeseneeeeseeees >200mA Storage Temperature .........eeeesseeeesteeeeeees -65C to +150C Ambient Temperature with Operating Range Power Applied ........ecceecesesseeeeesneeeeneeeeneees 55C to +125C Supply Voltage to Ground Potential 0.5V to +4.6V Ambient pply ag Al ec ee cece . +4. Range Temperature Vec DC Voltage Applied to ; 3 + Outputs in High Z State ...eeeeececceeeeeen -0.5V to Vog+0.5V oom oo a - = my DC Input Voltage... eee -0.5V to Veco +0.5Vi4I ndustria - to+ m Shaded areas contain advanced information. Note: 4. Pulse width < 20 ns.CY7CO9569V PRELIMINARY CY7C09579V ESS Electrical Characteristics Over the Operating Range CY7C09569V CY7C09579V 100 83 -67 Symbol Parameter Min | Typ | Max | Min | Typ | Max | Min | Typ | Max | Units Vou Output HIGH Voltage (Vec=Min, Ionq= 4.0MA) | 2.4 2.4 2.4 V VoL Output LOW Voltage (Vec=Min, Io, = +4.0mA) 0.4 0.4 0.4 Vv Vin Input HIGH Voltage 2.2 2.2 2.2 Vv VIL Input LOW Voltage 0.8 0.8 0.8 V loz Output Leakage Current -10 10 | -10 10 | -10 10 HA lec Operating Current (Vec=Max, Com'l. 165 | 300 155 | 275 145 | 255) mA lout=0 mA) Outputs Disabled Indust. 185 | 300 175 | 280 | mA Ispt Standby Current (Both Ports TTL Com'l. 30 | 75 25 | 70 25 | 65 | mA Level) CEL & CER 2 Vin. ffmax Indust. 35 | 85 35 | 80 | mA Ispe Standby Current (One Port TTLLevel) | Coml. 115 | 150 105 | 140 95 | 130} mA CEL | CEr > Vins ffmax Indust. 115 | 165 105 | 155 | mA Isp Standby Current (Both Ports CMOS Com'l. 0.01 | 1 0.01) 1 0.01] 1 mA Level) CE, & CER > Veo0-2V, 20 TF ingust., 0.01] 1 0.01{ 1 | mA Ispa Standby Current (One Port CMOS Com'l. 105 | 135 95 | 125 85 | 115) mA Level) CEL | CEpr 2 Vins f=fax Indust. 105 | 135 95 | 125 | mA Shaded areas contain advanced information. Capacitance Parameter Description Test Conditions Max. Unit Cin Input Capacitance Ta = 25C, f = 1 MHz, 10 pF Cout Output Capacitance Voc = 3.3V 10 pF AC Test Load and Waveforms 3.3V Z)= 502 R=50Q OUTPUT R1 = 5900 Note: cl = VoH = 1.5V (a) Normal Load (Load 1) 3.0V ALLINPUT PULSES GND 5. Test Conditions: C = 10 pF. OUTPUT C=5pF R2 = 4352CY7C09569V PRELIMINARY CY7C09579V Switching Characteristics Over the Operating Range CY7CO9569V CY7C09579V 100 83 -67 Symbol Parameter Min | Max | Min | Max | Min | Max | Units fMAX1 fax Flow-Through 53 45 40 MHz fMaxe fmax Pipelined 100 83 67 MHz teyc1 Clock Cycle Time - Flow-Through 19 22 25 ns teyce2 Clock Cycle Time - Pipelined 10 12 15 ns tout Clock HIGH Time - Flow-Through 6.5 7.5 8.5 ns tou4 Clock LOW Time - Flow-Through 6.5 7.5 8.5 ns toe Clock HIGH Time - Pipelined 4 5 6.5 ns tole Clock LOW Time - Pipelined 4 5 6.5 ns tr Clock Rise Time 3 3 3 ns te Clock Fall Time 3 3 3 ns tsa Address Set-Up Time 3.5 4 4 ns tHa Address Hold Time 0 0 0 ns tsc Chip Enable Set-Up Time 3.5 4 4 ns tuc Chip Enable Hold Time 0 0 0 ns tow R/W Set-Up Time 3.5 4 4 ns tuw R/W Hold Time 0 ) ) ns tsp Input Data Set-Up Time 3.5 4 4 ns tub Input Data Hold Time 0 0 0 ns tsap ADS Set-Up Time 3.5 4 4 ns tuap ADS Hold Time 0 0 0 ns tscn CNTEN Set-Up Time 3.5 4 4 ns ton CNTEN Hold Time 0 ) ) ns tgast CNTRST Set-Up Time 3.5 4 4 ns turst CNTRST Hold Time 0 ) ) ns toe Output Enable to Data Valid 8 9 10 ns to.z 1 | OE to LowZ 2 2 2 ns tonz 7 | OE to High Z 1 7 1 7 1 7 ns tep1 Clock to Data Valid - Flow-Through 15 18 20 ns tep2 Clock to Data Valid - Pipelined 5 6 8 ns toat Clock to Counter Address Valid - Flow-Through 15 18 20 ns tone Clock to Counter Address Valid - Pipelined 6.5 7.5 9 ns toc Data Output Hold After Clock HIGH 2 2 2 ns toxyz! 71 | Clock HIGH to Output High Z 2 9 2 9 2 9 ns toxz 71 | Clock HIGH to Output Low Z 2 2 2 ns Port to Port Delays tewop Write Port Clock HIGH to Read Data Delay 30 35 35 ns tecs Clock to Clock Set-Up Time 9 10 12 ns Notes: 6. This parameter is guaranteed by design, but it is not production tested. 7. Test conditions used are Load 2. CY7C09569V CYPR mec PRELIMINARY CY7C09579V Switching Waveforms Read Cycle for Flow-Through Output (FT/PIPE = V,,)& 9 1 11] teye1 > CLK ___/7 foN YON KY ce KA LL KKK | KKK KKK $+ |ap] tuc At DM | OOO | OOOO XX XOOO | XOXO" tow tga ADDRESS DATAgyt Read Cycle for Pipelined Operation (FT/PIPE = Vy,) % 1 111 teyc2 > <_ tone <_ tele } a, 7H \_ # \_#* \__ tsc the tsc | tic tswl-=|<+! tow tsa tHa 1 Latency DATAgut Qns2 tex.z TP [ iz _ > [ toe Notes: 8. OE/is asynchronously controlled; all other inputs are synchronous to the rising clock edge. 9. ADS =V,, CNTEN= Vj), and CNTRST = Vip. 10. The output is disabled (high-impedance state) by CE=Vjy following the next rising edge of the clock. 11. Addresses do not have to be accessed sequentially since ADS = V; constantly loads the address on the rising edge of the CLK. Numbers are for reference only.CY7C09569V PRELIMINARY CY7C09579V Switching Waveforms (continued) Bus Match Read Cycle for Flow-Through Output (FT/PIPE = V,)!& 9 10 11, 12, 13] teye1 > < tou4 |< toi4 ] CLK __ 7 CON YN ONY ADDRESS DATAgut Bus Match Read Cycle for Pipelined Operation (FT/PIPE = Vj,) 9 10 11, 12, 13) teyca le tone tcLe CLK 4 SON ON ONY \ EO | XXX | RX, | DOCOn | ROOOOXX ts tHe | | we WO OOO | NOOK) NOOK) XOXO tsw ty tsa | tua ~ tcp2 _.- toLkz DATAgut Qn Qnat ________ 1 Latency __________, toc 2nd Cycl 1st Cycl OE LOW 1st Cycle nd Cycle st Cycle Notes: 12. Timing shown is for x18 bus matching; x9 bus matching is similar with 4 cycles between address inputs. 13. See table Right Port Operation for data output on first and subsequent cycles. 10CY7C09569V PRELIMINARY CY7C09579V Switching Waveforms (continued) Bank Select Pipelined Read!'* 15] teyc2 CLK, ADDRESS 1) CE,B1) DATAgut(B1 ADDRESS 9) CE,B2) DATAouT (Be) Left Port Write to Flow-Through Right Port Read!': 16 17, 18, 19] CLK, RW ADDRESS, DATA. CLK, RW ADDRESS, toc toc Notes: 14. In this depth expansion example, B1 represents Bank #1 and B2 is Bank #2; Each Bank consists of one Cypress dual-port device from this data sheet. ADDRESS 91) = ADDRESS gp). 15. BO =B1=B2=B3 = BM = SIZE = ADS = CNTEN = Vy, CNTRST = Vy. 16. The same waveforms apply for a right port write to flow-through left port read. 17. CE=BO=B1 = B2 = B38 = ADS = CNTEN=Vj; CNTRST= Vip. 18. OE = Vj, for the Right Port, which is being read from. OE = Vjy for the Left Port, which is being written to. 19. Ittecg < maximum specified, then data from right port READ is not valid until the maximum specified for towpp: If tecs>maximum specified, then data is not valid until tees + tepy (tewop does not apply in this case). 11Switching Waveforms (continued) Pipelined Read-to-Write-to-Read (OE = V,,)!"1) 2% 1, 22] CLK CE teyc2 o AXX PRELIMINARY CY7CO9569V CY7C09579V tsc at the te ADDRESS DATA DATAgur + NO OPERATION+ WRITE Pipelined Read-to-Write-to-Read (OE Controlled)!"! 0 21, 22] tooo += tole + ck mv IR IR cz XO N teyc2 AXX AX tsc tue aw LO tw KR tsw tow ! ADDRESS tsa tua tsp|_tup | DATA Dosa KKK Ons KOK tebe toKLz tepe DATAout Q, S Qhea toHz la oe 7 QOOOOO. ~- e READ ___+| WRITE READ Notes: 20. Output state (HIGH, LOW, or High-Impedance) is determined by the previous cycle control signals. CE = ADS = CNTEN = Vi; CNTRST = Vin. 21. 22. During No operation, data in memory at the selected address may be corrupted and should be re-written to ensure data integrity.CY7C09569V PRELIMINARY CY7C09579V Switching Waveforms (continued) Bus Match Pipelined Read-to-Write-to-Read (OE = V,_)I"1)12 13, 20, 21, 22, 23] ac A NAVA NANA NANA NANA NEN AXX | AXX | AK AX LAX LAX AXXD | AXXD XXXY tou | toLe OQ AXXD SC tue tuw al m 3 zg =| XXX | AX) | AXX LAXXY | XXXY | NXXY] XXXY | XX) tsa | tha 1st Word 2nd Word texiz| 1stWord 2nd Word VVVVVYV PATAour XXX * ) XX XXX A\ | m toKHZ coe tcoe | 1st Word 2nd Word cpa c DATAin READ READ READ No WRITE WRITE READ READ READ 1st Cycle | 2nd Cycle | Operation | 1st Cycle | 2nd Cycle 1st Cycle | 2nd Cycle Note: 23. BM, SIZE, and BE must be reconfigured 1 cycle before operation is guaranteed. BM, SIZE, and BE should remain static for any particular port configuration. 13 CY7C09569V CPR nee PRELIMINARY CY7C09579V Switching Waveforms (continued) Flow-Through Read-to-Write-to-Read (OE = V,,)! 11, 12, 13,21, 22] teye1 tou tout CLK RAV ADDRESS DATA DATAgut Qnat teKHz NO OPERATIO Flow-Through Read-to-Write-to-Read (OE Controlled)! 11.20.21, 22] tevet tout tout CLK RAW ADDRESS DATA DATAgut Qnia teKLz toc READ- 14_ CY7C09569V FVPRESS PRELIMINARY CY7C09579V Switching Waveforms (continued) Bus Match Flow-Through Read-to-Write-to-Read (OE = V,,)% 11) 12, 13,21, 22, 23] + tovc1 ton , tout ork ANF \ FN ANA NANG \ tsc | tuc OK | AOA LAA | AXA | AX | AXA LAX | AX | AXD tsw] tuw tsw| tow OY) OXY | XXX | AON LAX | AXXY | NXXY | XXXY | XX) tsa | tua moss XA ARS RX RX KEK KEKE KEENER tsp | tub DATA Drat Dav t 1st Word 2nd Word CKHZ tcor | tcor | DATAgut Qn One Qh XX 1st Word 2nd Word toKLz toc READ READ No WRITE WRITE READ READ ist Cycle 2nd Cycle Operation ist Cycle 2nd Cycle 1st Cycle 2nd Cycle 15ee CY7C09569V PRELIMINARY CY7C09579V CYPRESS Switching Waveforms (continued) Pipelined Read with Address Counter Advance!*4] teyc2 teLe tone CLK tHa ADDRESS Qnat Qn Q, Qn READ EXTERNAL ADDRESS toc COUNTER HOLD READ WITH COUNTER READ WITH COUNTER [24] Flow-Through Read with Address Counter Advance tove1 tout tout CLK tHA ADDRESS Qn Qns2 OQn3 DATAgur Q, to Cc READ COUNTER HOLD READ EXTERNAL READ WITH COUNTER WITH - - ADDRESS COUNTER Note: 24. CE= OE= Vit: RAW = CNTRST = Vin. 16 CY7C09569V CPR nee PRELIMINARY CY7C09579V Switching Waveforms (continued) Write with Address Counter Advance (Flow-Through or Pipelined Outputs)*> 26] 7 | CON HNN NN XXL nx An x Ane x Anse x Anas x Ansa tsap tHap FOS KON | LOO | SOOT OO ROD ROOD OO CLK C INTERNAL ADDRESS onten KN | AOA [AK [XOXA LAXOA LAOXOX LOOX tson tHON DATA, Dn Ones KKK On Dre Dns Disa tsp tu WRITE EXTERNAL WRITE WITH_ | WRITE COUNTER - - ADDRESS ~I*~ COUNTER" HOLD ~* WRITE WITH COUNTER Notes: 25. CE= BO = Bi = B2 = B3 = R/W= V; CNTRST = Vip. 26. The Internal Address is equal to the External Address when ADS = CNTEN = V\_and CNTRST=Vjy 17CY7C09569V PRELIMINARY CY7C09579V Switching Waveforms (continued) Counter Reset (Pipelined Outputs)!" 20 27, 28, 29] teyc2 tcHe | tore os #7 ADDRESS A, Am A, ppRess 4x XX 0 xX 1 KX an Ke tow | thw g g S 3 3 daR dx tsrst| turst enmmst TE KXY | XXXY | XXX | XXXY | XXX) XXKY tsp| tuo DATA Do tepe tone | [29] teKLz COUNTER WRITE READ READ READ READ RESET ADDRESS 0 ADDRESS 0 ADDRESS 1 ADDRESS A, ADDRESS A,, Notes: 27. CE=B0=B1=B2=83-V,.. 28. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset. 29. Output state (HIGH, LOW, or High Impedance) is determined by the previous cycle control signals. Ideally, DATAgy7 should be in the High Impedance state during a valid WRITE cycle. 18PRELIMINARY CY7CO9569V CY7C09579V Switching Waveforms (continued) Counter Reset (Flow-Through Outputs) 22 27, 28, 29] CLK A teyc2 Ne, ADDRESS KAKKKKKKX INTERNAL ADDRESS x X tsw tHw tsrast| turst CNTRST OD KxXY KY NZ ten | tup DATA COUNTER WRITE READ RESET ~*[* ADDRESSO*|*_ ADDRESS O [ADDRESS 1} READ READ ADDRESS n_ 7 19CYPRESS PRELIMINARY Switching Waveforms (continued) Pipelined Read of state of Address Counter [30, 31] CY7CO9569V CY7C09579V teyc2 tou ; teLe CLK ae EF \ Ff \ 7 \ tsa] tha tsap | tHap mos ON TKK | AXY | XXXY | KXLY | XXX tscon tucn tsap tuap CNTEN XT AY COUNTER Qh42 Qns3 LOAD READ toc ADDRESS EXTERNAL COUNTER COUNTER ADDRESS ADDRESS READ WITH COUNTER HOLD READ WITH COUNTER Flow-Through Read of State of Address Counter (30, 31] * teyo1 tout fous CLK gry tsa el ADDRESS A tsap me Q TXRX AXY tscn | ton tgon tun tsap] tap onTen OKT AXY | XXX | AKA! AY | XOOK toad t SCN toc LOAD READ EXTERNAL COUNTER COUNTER ADDRESS ADDRESS READ WITH COUNTER HOLD READ WITH COUNTER Notes: 30. CE=0E = V,; RW = CNTRST = Vy. 31. When reading ADDRESSoyz in x9 Bus Match mode, readout of Ay is extended by 1 cycle. 20CY7CO9569V PRELIMINARY CY7C09579V BOS Read/Write and Enable Operation!2: . 41 Inputs Outputs OE CLK CE RAW VOgAVO35 Operation igh- [35] Xx re H X High-Z Deselected X ir L L Din Write [35] L cr L H Dout Read H Xx L X High-Z Outputs Disabled Address Counter Control Operation!* 34 Previous _ __ Address | Address | CLK E R/W ADS CNTEN | CNTRST | Mode Operation X X X X X X L Reset | Counter Reset An xX of Xx Xx L L H Load | Address Load into Counter An An r L H L H H Hold + | External Address Blocked - Read | Counter Address Readout Xx An re Xx Xx H H H Hold | External Address Blocked - Counter Disabled X An re X X H L H Incre- | Counter Increment ment Notes: 32. *X" = Don't Care, "H = Vy, L = Vp. 33. ADS, CNTEN, CNTRST = Don't Care. 34. OE is an asynchronous input signal. 35. When CE changes state In the pipelined mode, deselection and read happen in the following clock cycle. 36. Counter operation is independent of CE. 21CY7CO9569V PRELIMINARY CY7C09579V ahete Right Port Configuration??? 271 BM SIZE Configuration 1/O Pins used 0 0 x36 /OoR-35R 1 0 x18 /Oor_-17R 1 1 x9 /Oor-8R Right Port Operation ! Configuration BE Data on 1st Cycle | Data on 2nd Cycle | Data on 3rd Cycle Data on 4th Cycle x18 0 DQor-17R DQisR-35R - - x18 1 DQigp-35R DQor-17R - - x9 0 DQor-sr DQgp-17R DQ1gR-26R DQo7R-35R x9 1 DQo7R-35R DQisR-26R DQgr-17R DQor-sR Readout of Internal Address Counter! Address on 2nd 1/0 Pins used on 2nd Configuration Address on 1st Cycle | I/O Pins used on 1st Cycle Cycle Cycle Left Port x36 AoL_14L VO3g_-47L - - Right Port x36 AorR-14R VOgr-17R Right Port x18 Aor-14R, WA /Oop-17R - - Right Port x9 Agr_ian, WA, BA /Oor_sR AorR-5R V/OiR-8R Left Port Operation Control Pin Effect Bo /Op_g Byte Control BI 1/Og_47 Byte Control B2 1/018 96 Byte Control B3 1/Oo7_35 Byte Control Notes: 37. In x36 mode, BE input is a Don't Care. 38. DQ represents data output of the chip. 39. x18 and x9 configuration apply to right port only. 22PRELIMINARY CY7CO9569V CY7C09579V (CYPRESS Counter Operation The CY7C09569V/09579V Dual-Port RAM (DPRAM) con- tains on-chip address counters (one for each port) for the syn- chronous members of the product family. Besides the main x36 format, the right port allows bus matching (x18 or x9, us- er-selectable). An internal sub-counter provides the extra ad- dresses required to sequence out the 36-bit word in 18-bit or 9-bit increments. The sub-counter counts up in the Little En- dian mode, and counts down if the user has chosen the Big Endian mode. For a x36 format (the only active format on the left port), each address counter in the CY7C09579V uses addresses (Ag_14). For the right port (allowing for the bus-matching feature), a maximum of two address bits (out of a 2-bit sub-counter) are added. 1. ADS) )p (pin #23/86) is a port's address strobe, allowing the loading of that port's burst counters if the corresponding CNTEN ip pin is active as well. . CNTEN ip (pin #25/84) is a port's count enable, provided to stall the operation of the address input and utilize the internal address generated by the internal counter for fast interleaved memory applications; when asserted, the ad- dress counter will increment on each positive transition of that port's clock signal. 23 3. CNTRST_,R (pin #24/85) is a port's burst counter reset. A new read-back (Hold+Read Mode) feature has been added, which is different between the left and right port due to the bus matching feature provided only for the right port. In read-back mode the internal address of the counter will be read from the data I/Os as shown in Figure 7. Address > emneeee wenneee > cr : = i CY7CO09569V 5 i CY7C09579V a : 0 a: 8: RAM x i ARRAY a a aps 3 nas <q i CNTRST : CNTEN i VOs q_Y_- Figure 1. Counter Operation DiagramSc PRELIMINARY CY7CO9569V CY7C09579V PPP OES Bus Match Operation The right port of the CY7C09569V/09579V 16K/382Kx36 du- al-port SRAM can be configured in a 36-bit long-word, 18-bit word, or 9-bit byte format for data I/O. The data lines are divid- ed into four lanes, each consisting of 9 bits (byte-size data lines). BE CY7C09569V CY7C09579V 16K/32Kx36 Dual Port x36 x9, x18, x36 BUS MODE BM SIZE Figure 2. Bus Match Operation Diagram The Bus Match Select (BM) pin works with Bus Size Select (SIZE) and Big-Endian Select (BE) to select the bus width (long-word, word, or byte) and data sequencing arrangement for the right port of the dual-port device. A logic O applied to both the Bus Match Select (BM) pin and to the Bus Size Select (SIZE) pin will select long-word (36-bit) operation. A logic 1 level applied to the Bus Match Select (BM) pin will enable whether byte or word bus width operation on the right port I/Os depending on the logic level applied to the SIZE pin. The level of Bus Match Select (BM) must be static throughout normal device operation. The Bus Size Select (SIZE) pin selects either a byte or word data arrangement on the right port when the Bus Match Select (BM) pin is HIGH. A logic 1 on the SIZE pin when the BM pin is HIGH selects a byte bus (9-bit) data arrangement). A logic OQ on the SIZE pin when the BM pin is HIGH selects a word bus (18-bit) data arrangement. The level of the Bus Size Select (SIZE) must also be static throughout normal device operation. The Big-Endian Select (BE) pin is a multiple-function pin dur- ing word or byte bus selection (BM = 1). BE is used in Big-En- dian Select mode to determine the order by which bytes (or words) of data are transferred through the right data port. A logic 0 on the BE pin will select Little-Endian data sequencing arrangement and a logic 1 on the BE pin will select a Big-En- dian data sequencing arrangement. Under these circumstanc- es, the level on the BE pin should be static throughout du- al-port operation. Long-Word (36-bit) Operation Bus Match Select (BM) and Bus Size Select (SIZE) set to a logic O will enable standard cycle long-word (36-bit) opera- Note: tion. In this mode, the right ports I/O operates essentially in an identical fashion to the left port of the dual-port SRAM. How- ever no Byte Select control is available. All 36 bits of the long-word are shifted into and out of the right ports I/O buffer stages. All read and write timing parameters may be identical with respect to the two data ports. When the right port is con- figured for a long-word size, Big-Endian Select (BE) pin has no application and their inputs are Don't Care!*4l for the external user. Word (18-bit) Operation Word (18-bit) bus sizing operation is enabled when Bus Match Select (BM) is set to a logic 1 and the Bus Size Select (SIZE) pin is set to a logic O. In this mode, 18 bits of data are ported through /OpR_17R- The level applied to the Big-Endian (BE) pin determines the right port data I/O sequencing order (Big-Endian or Little-Endian). During word (18-bit) bus size operation, a logic LOW applied to the BE pin will select Little-Endian operation. In this case, the least significant data word is read from the right port first or written to the right port first. A logic 1 on the BE pin during word (18-bit) bus size operation will select Big-Endian opera- tion resulting in the most significant data word being trans- ferred through the right port first. Internally, the data will be stored in the appropriate 36-bit LSB or MSB I/O memory loca- tion. Device operation requires a minimum of two clock cycles to read or write during word (18-bit) bus size operation. An internal sub-counter automatically increments the right port multiplexer control when Little- or Big-Endian operation is in effect. Byte (9-bit) Operation Byte (9-bit) bus sizing operation is enabled when Bus Match Select (BM) is set to a logic 1 and the Bus Size Select (SIZE) pin is set to a logic 1. In this mode, 9 bits of data are ported through I/Opor_gr- Big-Endian and Little-Endian data sequencing is available for dual-port operation. The level applied to the Big-Endian pin (BE) under these circumstances will determine the right port data I/O sequencing order (Big- or Little-Endian). A logic LOW applied to the BE pin during byte (9-bit) bus size operation will select Little-Endian operation. In this case, the least signifi- cant data byte is read from the right port first or written to the right port first. A logic 1 on the BE pin during byte (9-bit) bus size operation will select Big-Endian operation resulting in the most significant data word to be transferred through the right port first. Internally, the data will be stored in the appropriate 36-bit LSB or MSB I/O memory location. Device operation re- quires a minimum of four clock cycles to read or write during byte (9-bit) bus size operation. An internal sub-counter auto- matically increments the right port multiplexer control when Little- or Big-Endian operation is in effect. When transferring data in byte (9-bit) bus match format, the unused I/O pins (/Ogag_g5p) are three-stated. 40. Even though a logic level applied to a Don't Care input will not change the logical operation of the dual-port, inputs that are temporarily a Don't Care (along with unused inputs) must not be allowed to float. They must be forced either HIGH or LOW. 24CY7CO9569V PRELIMINARY CY7C09579V ahs Ordering Information 16K x36 3.3V Synchronous Dual-Port SRAM Speed Package Operating (ns) Ordering Code Name Package Type Range 100 CY7C09569V100AC A144 144-Pin Thin Quad Flat Pack Commercial CY7C09569V100BAC BA144 144-Ball Mini-Ball Grid Array (BGA) Commercial 83 CY7C09569V-83AC A144 144-Pin Thin Quad Flat Pack Commercial CY7C09569V-83Al A144 144-Pin Thin Quad Flat Pack Industrial CY7C09569V-83BAC BA144 144-Ball Mini-Ball Grid Array (BGA) Commercial CY7C09569V83BAl BA144 144-Ball Mini-Ball Grid Array (BGA) Industrial 67 CY7C09569V-67AC A144 144-Pin Thin Quad Flat Pack Commercial CY7C09569V-67Al A144 144-Pin Thin Quad Flat Pack Industrial CY7C09569V-67BAC BA144 144-Ball Mini-Ball Grid Array (BGA) Commercial CY7C09569V67BAl BA144 144-Ball Mini-Ball Grid Array (BGA) Industrial 32K x36 3.3V Synchronous Dual-Port SRAM Speed Package Operating (ns) Ordering Code Name Package Type Range 100 CY7C09579V-100AC A144 144-Pin Thin Quad Flat Pack Commercial CY7C09579V100BAC BA144 144-Ball Mini-Ball Grid Array (BGA) Commercial 83 CY7C09579V-83AC A144 144-Pin Thin Quad Flat Pack Commercial CY7C09579V-83Al A144 144-Pin Thin Quad Flat Pack Industrial CY7C09579V-83BAC BA144 144-Ball Mini-Ball Grid Array (BGA) Commercial CY7C09579V-83BAl BA144 144-Ball Mini-Ball Grid Array (BGA) Industrial 67 CY7C09579V-67AC A144 144-Pin Thin Quad Flat Pack Commercial CY7C09579V-67Al A144 144-Pin Thin Quad Flat Pack Industrial CY7C09579V-67BAC BA144 144-Ball Mini-Ball Grid Array (BGA) Commercial CY7C09579V67BAl BA144 144-Ball Mini-Ball Grid Array (BGA) Industrial Document #: 3800743 25CY7C09569V PRELIMINARY CY7C09579V Package Diagrams 144-Pin Plastic Thin Quad Flat Pack (TQFP) A144 22.0020.100 SQ 20.0020050 SG 144 109 DIMENSIONS ARE IN MILLIMETERS. R 0.08 MIN. 0 MIN. 020 MAX. STAND-OFF C......_\ 0.05 MIN. O15 MAX. | CAAT 3 Low PLANE t R 0.08 MIN. 0-7 SEATING PLANE 1p21 0.20 MAX. @Xx> 0.20 MIN. p* MAX. - 0.602015 L i 1.00 REF a P | AiLA 51-85047-A y DETAIL 4 ; 1.4020.05 0.20 MAX. / SEE DETAIL A 26CY7CO09569V PRELIMINARY CY7C09579V Package Diagrams (continued) 144-Ball Mini Ball Grid Array BA144 BUTTOM VIEW pin 1 CORNER TOP VIEW 4 [20.10 (596 } 0c.25 S]c]ale| Fil 1 CORNER DO.S0+ D.05(144%) 125 4 6 8 7 & 2 Wels i211 8 & 7 6 & 4 5 2 1 ql A Poorer peoeroros A B | DOODOopoooooD B c ooAaopooOponpoooD c oO moO m OG Dp om Om mo oO E a oooo0 onog E cl Ae em , F 3 2 oO OD ooo 9 F s + in 4 o a >See H Gj pPoan onoog H Cc J 7 4) tp Oooo J hb Noone opoaonoooy hb L oOoOoooOoOdopeoOoOoOoOY L M | DoOoCoDoOoPOoOAGoOD M N gBooaoon 1 Oogepne N I | L B- 0.80} uw 2 3.60 + a A ts A 12.004 0.20 a { 0.20(48) [ | SS oo : = 5 = [-=) SEATING PLAHE w wo : 51-85104 m et & o =. Hoo cl cl oon * THE BALL DIAMETER, BALL PITCH, STAND-OFF && PAChAGE THIChMESS ARE DIFFERENT FROM JEDEC SPEC MO1S2 (LOW PROFILE BGA FAMILY) Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.