M41T00S - STMicroelectronics

1/23December 2004

M41T00S

Serial Acce ss Re al -Time Cl ock

FEATURES SUMMARY

■2.0 TO 5 .5 V C L O C K O PER AT IN G VOLTAGE

■COUNTERS F OR SECONDS, MINUTES,

HOURS, DAY, DATE, MONTH, YEAR, AND

CENTURY

■SOFT WARE CLOCK CALIBRATION

■AUTOMATIC SWITCH-OVER AND

DESELECT CIRCUITRY (FIXED

REFERENCE)

–V

CC = 2.7 to 5.5V

2.5V ≤ VPFD ≤ 2. 7V

■SERIA L INT ERFACE SUPPORTS I2C BUS

(400kHz PROTOCOL)

■LOW OPERATING CURRENT OF 300µA

■OSCILLATOR STOP DETECTION

■BATTERY OR SUPER- C AP BACK-UP

■OP ERAT ING TEMPER ATURE OF –40 TO

85°C

■ULTRA-L OW BA TTERY SUPP LY CURRENT

OF 1µA

Figure 1. Packages

SO8 (M)

8-pin SOIC

M41T00S

2/23

TABLE OF CONTENTS

FEATUR ES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Figure 1. Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Figure 3. 8-pin SOIC (M) Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

Figure 4. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2-Wire Bus Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 5. Serial Bus Data Transfer Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 6. Acknowledg eme nt Sequenc e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

READ Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 7. Slave Address Location. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 8. READ Mode S equen ce . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Figure 9. Alternative READ Mode Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

WRITE Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Data Retention Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 0

Figure 10.WRITE Mode Seq uence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

CLOCK OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1

Clock Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 2. TIMEKEEPER® Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Calibrating the Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2

Figure 11.Crystal Accuracy Acro ss Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 12.Clock Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Century Bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4

Oscillator Fail Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Output Driver Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Preferred Initial Power-on Default . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 3. Preferred Default Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 4. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

DC AND AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 5. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 13.AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 6. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 6

Table 7. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 8. Crystal Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 14.Power Down/Up Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3/23

M41T00S

Table 9. Power Down/Up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 10. P ower Down/Up Trip Points DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 15.Bus Timing Requiremen ts Sequenc e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 11.AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

PAC KAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 16.SO8 – 8-lead Plastic Small Package Out line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 12. SO8 – 8-lead Plast ic Small Outline (150 mils body width), Package Mech. Data. . . . . . 20

PAR T NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 13. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 14. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

M41T00S

4/23

S UM MARY DE SCRIP TION

The M41T00S Serial Access TIMEKEEPER®

SRAM is a low power Serial RTC with a built-in

32.768kHz oscillator (external crystal controlled).

Eight bytes of the SRAM (see Table 2., page 11)

are used for the clock/calendar function and are

configured in bina ry cod ed dec imal (BCD) form at.

Addresses and data are transferred serially via a

two line, bi-directional I2C interface. The built-in

address register is incremented automatically af-

ter each WRITE or READ da ta byte.

The M41T00S has a built-in power sense circuit

which detects power failures and automatically

switches to the battery supply when a power fail-

ure occurs. The energy needed to sustain the

clock operations can be supplied by a small lithium

button supply when a power failure occurs. The

eight clock address locations contain the cent ury,

year, month, date, day, hour, minu te, and s econd

in 24 hour BCD format. Corrections for 28, 29

(leap year - valid until year 2100), 30 and 31 day

months are made automat ically.

The M41T00S is supplied in an 8-pin SOIC.

Figure 2. Logic Diagram

Note: 1. For SO 8 p ackage only.

Table 1. Signal Names

Note: 1. For SO 8 p ackage only.

Figure 3. 8-pin SOIC (M) Connecti ons

Note: 1. O pen Drai n Output

SCL

VCC

M41T00S

VSS

SDA

FT/OUT

VBAT

(1)

AI09165

XI(1) Oscillator Input

XO(1) Oscillator Output

FT/OUT Frequency Test / Output Driver

(Open Drain)

SDA Serial Data Input/Output

SCL Serial Clock Input

VBAT Battery Supply Voltage

VCC Supply Voltage

VSS Ground

1FT/OUT

(1)

SDA

BAT

SCL

XI V

M41T00S

AI09166

5/23

M41T00S

Figu re 4. Blo ck Diagram

Note: 1. O pen Drai n Output

REAL TIME CLOCK

CALENDAR

RTC &

CALIBRATION

FREQUENCY TEST

OSCILLATOR FAIL

CIRCUIT

OUTPUT DRIVER

FT/OUT

(1)

INTERNAL

POWER

OUT

SDA

SCL

COMPARE

INTERFACE

32KHz

OSCILLATOR

BAT

CRYSTAL

PFD

AI09168

WRITE

PROTECT

M41T00S

6/23

OPERATION

The M41T00S clock operates as a slave device on

the serial bus . Access is obtained by implementing

a start condition f ollowed by the correc t slave ad-

dress (D0h). The 8 bytes contained in the device

can then be accessed sequentially in t he foll owing

order:

1. Seconds Register

2. Min utes Register

3. Century/Hours Register

4. Day Register

5. D ate Register

6. Month Regist er

7. Yea r Register

8. C alibration Register

The M41T00S clock continually monitors VCC for

an out-of-toleranc e condition. S hould VCC f all be-

low VPFD, the device terminates an access in

progress and resets the device address counter.

Inputs to the device will not be recognized at this

time to prev ent erroneous data fr om bei ng wri tten

to the device from a an out-of-tolerance system.

Once VCC falls below the switchover voltage

(VSO), the device automatically switches over to

the battery and powers down i nto an ul tra-low cur-

rent mode of operation to preserve battery life. If

VBAT is less than VPFD, the device power is

switched from VCC to V BAT when V CC drops bel ow

VBAT. If VBAT is greater than VPFD, the device

power is switched from VCC to VBAT when VCC

drops below VPFD. Upon power-up, the device

switches from battery to VCC at VSO. When VCC

rises a bov e VPFD, it will recognize the i n puts.

For more information on Battery Storage Li fe refer

to Application Note AN1012.

2-Wire Bus Characteristics

The bus is intended for communication between

different ICs. It consists of two lines: a bi-direction-

al data signal (SDA) and a clock signal (SCL).

Both the SDA and SCL lines mus t be connected to

a positive supply voltage via a p ull-up resistor.

The following protocol has been defined:

– Data transfer may be initiated only when the

bus is not busy.

– During data transfer, the data line must remain

stable whenever the clock line is High.

– Changes in the data line, while the clock line is

H igh, will be inte rpreted as control signals.

Accordingly, the following bus conditions have

been defined:

Bus not busy. Both data and clock lines remain

High.

Start data transfer . A change in the state of the

data line, from high to Low, while the clock is High,

defines the START condi tion.

Stop data transfer. A change in the state of the

data line, from Low to High, while the clock is High,

defines the STOP condition .

Data Va lid. The state of the data line represents

valid data when after a start condition, the dat a line

is stable for the d uration of the high period of the

clock signal. T he data on the line may be changed

during the Low period of the clock signal. There is

one clock pulse per bit of data.

Each data transfer is initiated with a start condi tion

and terminated with a stop condition. The number

of data bytes transferred between the start and

stop conditions is not limited. The information is

transmitted byte-wide and each rec eiver ack nowl-

edges with a nin th bit.

By definition a dev ice t hat gives o ut a m essag e is

called “transmitter,” the receiving dev ice that gets

the message i s called “receiver.” The device that

controls the message is called “master.” The de-

vices that are controlled by the master are called

“slaves.”

Acknowledge. E ac h byte of eig ht bits is followed

by one Acknowledge B it. Thi s Ac knowledge Bit is

a low level put on t he bus by the receiver whereas

the master generates an extra ack nowled ge relat-

ed clock pulse. A slave receiver which is ad-

dressed is obliged to generate an acknowledge

after the reception of each byte that has been

clocked out of the slave transmitter.

The device that acknowledges has to pull down

the SDA line during the acknowledge clock pulse

in such a way that the SDA line is a stable Low dur-

ing the High period of the acknowledge related

clock pulse. Of course, setup and hold times mus t

be taken int o account. A master recei ver must sig-

nal an end of data to the slave transmitter by not

generating an acknowledge on the last byte that

has been cloc ked out of the slave. In this case the

transmitter must l eave the data l ine High to enable

the mast er to generate the S TOP condition.

7/23

M41T00S

Figure 5. Serial Bus Data Transfer Sequen ce

Figure 6. Acknowledgement Sequence

AI00587

DATA

CLOCK

DATA LINE

STABLE

DATA VALID

START

CONDITION CHANGE OF

DATA ALLOWED STOP

CONDITION

AI00601

DATA OUTPUT

BY RECEIVER

DATA OUTPUT

BY TRANSMITTER

SCL FROM

MASTER

START CLOCK PULSE FOR

ACKNOWLEDGEMENT

12 89

MSB LSB

M41T00S

8/23

READ Mode

In this mode the master reads t he M41T00S sl ave

after setting the slave address (see Figure

8., page 9). Following the WRITE Mode Control

Bit (R/W=0) and the Acknowledge Bit, the word

address 'An' is written to the on-chip address

pointer. Next the START condition and slave ad-

dress are repeated followed by the READ Mode

Control Bit (R/W=1). At this point the master trans-

mitter becomes the master receiver. The data byte

which was addressed will be transmitted and the

master receiver will send an Acknowledge Bit to

the slave transm itter. The address pointer is only

incremented on reception of an Acknowledge

Clock. The M41T00S slave transmitter will now

place the data byte at address An+1 on the bus,

the master receiver reads and acknowledges the

new byte and the ad dress pointer is incremented

to “An+2.”

This cycle of reading consecutive addresses will

continue until the m aster receiver sends a STOP

condition to the slave transmitter.

The system-to-user transfer of clock data will be

halted whenever the address bei ng read is a clock

address (00h to 06h). The update will re su me due

to a Stop Condition or when the pointer increment s

to any non-clock address (07h).

Note: This is true bot h in READ Mode and WRITE

Mode.

An alternate READ Mode may also be implement -

ed whereby the m as ter reads the M41T0 0S s lave

without first w riting t o the (volatile) a ddress poin t-

er. The first address that is read is the last one

stored in the p ointer (see Figure 9., page 9).

Figure 7. Slave Address Lo cation

AI00602

R/W

SLAVE ADDRESS

START A

0100011

MSB

LSB

9/23

M41T00S

Figure 8. READ Mode S equence

Figure 9. Alternative RE AD Mode Sequence

AI00899

BUS ACTIVITY:

ACK

NO ACK STOP

START

SDA LINE

BUS ACTIVITY:

MASTER

R/W

DATA n DATA n+1

DATA n+X

WORD

ADDRESS (An)

SLAVE

ADDRESS

START

R/W

SLAVE

ADDRESS

ACK

AI00895

BUS ACTIVITY:

ACK

NO ACK STOP

START

PSDA LINE

BUS ACTIVITY:

MASTER

R/W

DATA n DATA n+1 DATA n+X

SLAVE

ADDRESS

M41T00S

10/23

WRITE Mod e

In this mode the master transmitter transmits to

the M41T00S slave receiver. Bus protocol is

shown in Figure 10. Following the START condi-

tion and slave address, a logic '0' (R/W=0) is

placed on the bus and indicates to the addressed

dev ic e t h at word addr es s “ An” will follow a nd is t o

be written to the on-chip addres s pointer. The data

word to be written to the memory is strobed in nex t

and the internal address pointer is increme nted to

the next address location on the reception of an

acknowledge clock. The M41T00S slave receiver

will send an acknowledge clock to the master

transmitter after i t has received the slave address

see Figure 7., page 8 and again after it has re-

ceived the word address and each data byte.

Data Reten tion Mode

With valid VCC applied, the M41T00S can be ac-

cessed as des cribed ab ov e with REA D or WRI TE

Cycles. Should the supply voltage decay, t he pow-

er input will be switched from the VCC pin to the

battery when V CC falls below the Battery Back-up

Switchover Voltage (VSO). At this time the clock

registers will be maintained by the attached bat-

tery supply. On power-up , when VCC returns to a

nominal val ue, write protection conti nues for tREC.

For a further, more detailed review of lifetime cal-

culations, please see Appl ication Not e AN1012.

Figure 10. WRI TE Mo de S equenc e

AI00591

BUS ACTIVITY:

ACK

ACK STOP

START

PSDA LINE

BUS ACTIVITY:

MASTER

R/W

DATA n DATA n+1 DATA n+X

WORD

ADDRESS (An)

SLAVE

ADDRESS

11/23

M41T00S

C LOCK OPERA T ION

The 8-byte Register Map (see Tab le 2) is used t o

both set the clock and to read the date and time

from the clock, in a bin ary coded decimal format.

Seconds, Minutes, and Hours are c ont ained within

the first three registers.

Bits D6 and D7 of Clock Register 02h (Century/

Hours Register) contain the CENTURY ENABLE

Bit (CEB) and the CENTURY Bit (CB). Setting

CEB to a '1' will cause CB to toggle, either from '0'

to '1' or fr om '1' to '0' at the turn of the century (de-

pending upon its initial state). If CEB is set to a '0,'

CB will not toggle. B its D0 through D2 of Register

03h contain the Day (day of week). Registers 04h,

05h, and 06h contain the Date (day of month),

Month and Ye ars. The e ighth clock register is the

Calibration Register (this is described in the Clock

Calibration section). Bit D7 of Register 00h con-

ta ins the STOP Bit (ST) . Setting th is bit to a ' 1 ' wil l

cause the oscillator to stop. If the device i s expect -

ed to spend a significant amount of time on the

shelf, the oscillator may be stopped to reduce cur-

rent drain. When reset t o a '0' the oscillator restarts

within one second.

The seven Clock Registers may be read one by te

at a time, or in a sequential block. The Calibration

independently. Provision has been made to as-

sure that a clock upda te do es not occur whi le any

of the seven clock addresses are being read. If a

clock address is being read, an updat e of the clock

registers will be halted. This will prevent a transi-

tion of data du ring the READ.

Clock Registers

The M41T00S offers 8 internal registers which

contain Clock and Calibration data. These regis-

ters are memory locations which contain external

(user accessible) and internal copies of the data

(usually referred to as BiPORT™ TIMEKEEPER

cells). The external copies are independent of in-

ternal functions except that they are updated peri-

odically by the simultaneous transfer of the

incremented internal copy. The i nternal divider (or

clock) chain wil l be reset upon the completion of a

WRITE to any clock address.

The system-to-user transfer of clock data will be

halted whenever the address bei ng read is a clock

address (00h to 06h). The update will resume ei-

ther due to a Stop Condition or when the pointer

increments to any non-clock address (07h).

Clock Registers store data in BCD. The Calibra-

tion Re gister stores data in Binary Format.

Table 2. T IMEKE EPER® Reg ister M ap

K eys: 0 = Mus t be set to '0'

CB = Century Bi t

CE B = C entury Enable Bit

FT = Frequency Test Bit

OF = Oscillator Fail Bit

OUT = Output level

S = Sig n Bit

ST = Sto p Bit

Addr Function/Range BCD

Format

D7 D6 D5 D4 D3 D2 D1 D0

00h ST 10 Seconds Seconds Seconds 00-59

01h OF 10 Minutes Minutes Minutes 00-59

02h CEB CB 10 Hours Hours (24 Hour Format) Century/

Hours 0-1/00-23

03h00000 Day of Week Day01-7

04h 0 0 10 Date Date: Day of Month Date 01-31

05h 0 0 0 10M Month Month 01-12

06h 10 Years Year Year 00-99

07h OUT FT S Calibration Calibration

M41T00S

12/23

Ca libr a tin g t h e C lock

The M41T 00S is driven by a quartz-control led os-

cillator with a nominal frequency of 32,768 Hz. The

devices are t ested not ex ceed ±35 ppm (parts per

million) oscillator frequency error at 25oC, which

equates to about ±1.53 minutes per month (see

Figure 11., page 13 ). When t he Calibration circuit

is properly employed, accuracy improves to better

than ±2 ppm at 25°C.

The oscillation rate of crystals chang es with tem-

perature. The M41T00S design employs periodic

counter correction. The calibration circuit adds or

subtracts counts from the o scillator divider circuit

at the divide by 256 stage, as shown in Figure

12., page 13. The number of times pulses which

are blanked (subtracted, negative calibration) or

split (added, positive calibration) depends upon

the value loaded into the five Calibration B its found

in the Calibration Re giste r. Adding c ounts speeds

the clock up, subtracting counts slows the clock

down.

The Calibration Bits occupy the five lower order

bits (D4-D0) in the Calibration Register 07h. These

bits can be set to represent any value between 0

and 31 in binary form. Bit D5 is a Sign Bit; '1' indi-

cates positive calibration, '0' indicates negative

calibration. Calibration occurs within a 64 minute

cycle. The first 6 2 minutes in t he c ycle m ay , onc e

per minute, h ave one second either shortened by

128 or lengthened by 256 oscillator cycles. If a bi-

nary '1' is loaded into the register, only the first 2

minute s in the 64 minute cycle will be modified; if

a binary 6 is loaded, the first 12 will be affected,

and so on.

Therefore, each calibration step has the effect of

adding 512 or subtracting 256 osc illator cycles for

every 125,829,120 actual oscillator cycles, that is

+4.068 or –2.034 ppm of adjustment per calibra-

tion step in the calibration register (see Figure

12., page 13). Assuming t hat the oscillator is run-

ning at exactly 32,768 Hz, each of the 31 incre-

ments in the Calibration byte would represent

+10.7 or –5.35 seconds per month which corre-

sponds to a total range of +5.5 or –2.75 minutes

per month.

Two methods are available for ascertaining how

much cal ibration a giv en M41T00S may require.

The first involves setting the clock, lett i ng it run for

a month and comparing it to a known accurate r ef-

erence and r ecor ding dev iation over a fi xed period

of time. Calibration values, including the number of

seconds lost or gained in a given period, can be

found in Application Note AN934, “TIMEKEEP-

ER® CALIBRATION.” This allows the designer to

give the end user the ability to calibrate the clock

as the environment r equi res, even i f the final prod-

uct is packaged in a non-user serviceable enclo-

sure. The designer could provide a simple utility

that accesses the Calibration byte.

The second approach is better suited to a m anu-

facturing environment, and involves the use of the

FT/OUT pin. The pin will toggle at 512Hz, when

the Stop Bit (ST, D7 of 00h) is '0,' and the Frequen-

cy Test Bit (FT, D6 of 07h) is '1.'

Any deviation from 512 Hz indicates the degree

and direction of oscillator frequency shift at the tes t

temperature. For example, a reading of

512.010124 Hz would indicate a +20 ppm osci lla-

tor f requency error, requi ring a –10 (XX001010) to

be loaded into the Calibration Byte for co rrection.

Note that setting or changing the Calibration Byte

does not affect the Frequency Test output fre-

quency.

The FT/OUT pin is an open drain output which re-

quires a pull-up resistor to VCC for proper opera-

tion. A 500-10k resistor is recommended in order

to control the rise time. The FT Bit is cleared on

power-down.

13/23

M41T00S

Figure 11. Crys tal Accuracy Acro ss Tem p eratur e

Figu re 12 . Cl ock C al ib r at i on

AI07888

–160

0 10203040506070

Frequency (ppm)

Temperature °C

80–10–20–30–40

–100

–120

–140

–40

–60

–80

–20

= –0.036 ppm/°C2 ± 0.006 ppm/°C2

∆F= K x (T – TO)2

TO = 25°C ± 5°C

AI00594B

NORMAL

POSITIVE

CALIBRATION

NEGATIVE

CALIBRATION

M41T00S

14/23

Century Bit

Bits D7 and D6 of Clock Register 02h contain the

CENTURY ENABLE Bi t (CEB) and the CENTURY

Bit ( CB). Setting CEB to a '1' will cause CB to tog-

gle, either from a '0' to '1' or from '1' to '0' at the turn

of the century (depending upon its initial state). If

CEB is set to a '0,' CB will not toggle.

Osc illator Fail Detect io n

If the Oscillator Fail Bit (OF) is internally set to '1,'

this indicates that the oscillator has either stopped,

or was stopped for some period of time and can be

used to judge the validity of t he clock and date da-

ta.

In the event the OF Bit is found to be set to '1' at

any time other than the initial power-up, the STOP

Bit (ST) should be written to a '1,' then immediately

reset to '0.' Th is w ill re s tart the os c ill a tor .

The following conditions can cause the OF Bit to

be set:

– The first time power is applied ( defaults to a '1'

on powe r-up).

– The volt age present on VCC is i n su fficien t to

suppor t os c illation .

– The ST Bit is set to '1.'

– External interferenc e of the crystal.

The OF Bit will remain set to '1' until written to logic

'0.' The oscillator must start and have run for at

least 4 seconds before attempt ing to reset the OF

Bi t to '0. '

Output Driver Pin

When the FT Bit is not set, the FT/OUT pin be-

comes an output driver that reflects the contents of

D7 of the Calibration Register. In other words,

when D7 (OUT Bit) and D6 (FT Bit) of address lo-

cation 07h are a '0,' then the FT/OUT pin will be

driven low.

Note: The FT /OUT pin is an open drai n whi c h re-

quires an external pull-up resistor.

Preferred Ini tia l Power-on Default

Upon initial application o f power to the device, the

ST and FT bits are set to a '0' state, and the OF

and OUT Bits will be set to a '1.' All other Regis ter

bits will initially power-on in a random state (see

Table 3).

Table 3. Preferred Default Values

Note: 1. State of other control bits undefined.

2. UC = Unchanged

Condition ST Out FT OF

Initial Po wer-up(1) 0101

Subsequent Power-up (with battery back-up)(2) UC UC 0 UC

15/23

M41T00S

MAXI MUM RAT IN G

Stressing the device above t he rating l isted in t he

“Absolute Maximum Ratings” table may cause

permanent damage to the device. These are

stress ratings only and operation of the device at

these or any other conditions above those indicat-

ed in the Oper ating sections of this specification is

not impl ied. Exposure to Absol ute Max imum Ra t-

ing conditions for extended periods may affect de-

vice reliability. Refer also to the

STMicroelectronics S URE P rogram and other rel-

evant quality documents.

Table 4. Absolute Maximum Ratings

Note: 1. For S O8 package, Lead-free (Pb-free) lead finish: Reflow at peak temperature of 260°C (total thermal budget not to exceed 245°C

for greater than 30 seconds).

2. For SO8 package, standard (SnPb) lead finis h: Reflow at peak temperature of 240°C (t otal thermal budget not to exceed 180°C for

between 90 to 15 0 s e c onds) .

3. T he S OX18 pack age ha s Lea d-fr ee (Pb- free ) le ad fin ish , b ut can not b e e xpos ed to pe ak r eflo w te mpe ratur e in exc ess of 24 0° C

(use same reflow prof i l e as s t andard (SnPb) le ad finis h).

CAUTION: Negative undersh oots below –0.3 vol ts are no t all owed on any pin whil e i n the Battery Back-up Mode

Sym Parameter Value Unit

TSTG Storage Temperature (VCC Off , Oscillator Off) SOIC –55 to 125 °C

VCC Supply Voltage –0.3 to 7 V

TSLD Lead Solder Temperature for 10 Seconds Lead-free lead finish(1) 260 °C

Standard (SnPb)

lead finish(2,3) 240 °C

VIO Input or Output Voltages –0.3 to Vcc+0.3 V

IOOutput Current 20 mA

PDPower Dissipation 1 W

M41T00S

16/23

DC AND A C PARAMETERS

This section summarizes the operating and mea-

surement conditions, as well as the DC and AC

characteristics of the device. The parameters in

the follo wing DC and AC Charact eristic tables are

derived from tests pe rform ed under the Meas ure-

ment Condition s listed i n the relevant tables. De-

signers should check that the operating conditions

in their projects match the measurement condi-

tions when using the quoted parameters.

Table 5. Operating and AC Measurem en t Conditions

Note: O ut put Hi-Z is def i ned as the p oi nt wher e data is no l onger dri ven.

Figu re 13. AC Measure m e nt I/ O Wa veform

Table 6. Capacitance

Note: 1. Effective c apacitance me asured with power supply at 5V; s am pl ed on ly, n ot 100% tes ted.

2. At 25°C, f = 1MHz.

3. Outputs deselect ed.

Parameter M41T00S

Supply Voltage (VCC)2.7 to 5.5V

Ambient Operating Temperature (TA)–40 to 85°C

Load Capacitance (CL)100pF

Input Rise and Fall Times ≤ 50ns

Input Pulse Voltages 0.2VCC to 0.8 VCC

Input and Output Timing Ref. Voltages 0.3VCC to 0.7 VCC

AI02568

0.8VCC

0.2VCC

0.7VCC

0.3VCC

Symbol Parameter(1,2) Min Max Unit

CIN Input Capacitance 7 pF

COUT(3) Output Capacitance 10 pF

tLP Low-pass filter input time constant (SD A and SCL) 50 ns

17/23

M41T00S

Table 7. DC Characteristics

Note: 1. Valid fo r A m bi ent Operating T em perature: TA = –40 t o 85°C; VCC = 2.7 t o 5.5V (ex cept wh ere note d).

2. F or F T / OUT pin (Open Dra i n)

3. STM i croelectro ni cs recommend s t he RAYOVAC BR1225 or BR1632 (or equi valent) a s t he battery supply.

4. F or rechargeabl e back-u p, VBAT (max ) m ay be cons i dered to b e VCC.

Table 8. Crystal Ele ctric al Characteristics

Note : 1. Ext ern ally supp lied if usin g th e SO8 pa ckag e. S TMi croe lec tronic s re co mmend s the K DS DT-38 : 1TA/ 1TC 252E 127, Tun ing Fork

Type (thru-hole) or the DMX-26S: 1TJS125FH2A212, (SMD) quartz crystal for industrial temperature operations. KDS can be con-

tacted at kouhou@kdsj.co. j p or h ttp://www.kdsj.co. j p f or furthe r i nformation on this crystal type .

2. Load capacitors are integrated within the M41T00S. Circuit board layout considerations for the 32. 768kHz crys tal of minimum trace

leng ths and isolation f rom RF gen erating signals should be ta ken into accoun t.

3. F or applications requiring back -up supply operat i on below 2.5V, RS (max) should be considered 40kΩ.

Sym Parameter Test Condition(1) Min Typ Max Unit

ILI Input Leakage Current 0V ≤ VIN ≤ VCC ±1 µA

ILO Output Leakage Current 0V ≤ VOUT ≤ VCC ±1 µA

ICC1 Supply Current Switch Freq = 400kHz 300 µA

ICC2 Supply Current (standby)

SCL = 0Hz

All Inputs

≥ VCC – 0.2V

≤ VSS + 0.2V

70 µA

VIL Input Low Voltage –0.3 0.3VCC V

VIH Input High Voltage 0.7VCC VCC + 0.3 V

VOL Output Low Vo ltage IOL = 3.0mA 0.4 V

Output Low Voltage (Open Drain)(2) IOL = 10mA 0.4 V

Pull-up Supply Voltage (Open Drain) FT/OUT 5.5 V

VBAT(3) Back-up Supply Voltage 2.0 3.5(4) V

IBAT Battery Supply Current TA = 25°C, VCC = 0V

Oscillator ON, VBAT = 3V 0.6 1 µA

Sym Parameter(1,2) Min Typ Max Units

fOResonant Frequency 32.768 kHz

RSSeries Resistance 60(3) kΩ

CLLoad Capacitance 12.5 pF

M41T00S

18/23

Figure 14. Power Down /U p Mode AC Waveform s

Table 9. Power Down/U p AC Characteri stics

Note: 1. VCC fall time should no t exceed 5m V/µs.

2. Valid for Ambien t Operat in g T em perat ure: TA = – 40 t o 85°C; VCC = 2. 7 t o 5.5V (except where noted).

Table 10. Power Down/U p Trip Points DC Characteristic s

Note: 1. All voltages referenced to VSS.

2. Valid for Ambien t Operat in g T em perat ure: TA = – 40 t o 85°C; VCC = 2. 7 t o 5.5V (except where noted).

Symbol Parameter(1,2) Min Typ Max Unit

tPD SCL and SDA at VIH before Power Down 0nS

trec SCL and SDA at VIH after Power Up 10 µS

Sym Parameter(1,2) Min Typ Max Unit

VPFD Power-fail Deselect 2.5 2.6 2.7 V

Hysteresis 25 mV

VSO

Battery Back-up Switchover Voltage

(VCC < VBAT; VCC < VPFD)VBAT < VPFD VBAT V

VBAT > VPFD VPFD V

Hysteresis 40 mV

AI00596

VCC

trec

tPD

VSO

SDA

SCL DON'T CARE

19/23

M41T00S

Figure 15. Bus Timing Requirements Sequence

Table 11. AC Characteristics

Note: 1. Valid fo r A m bi ent Operating T em perature: TA = –40 t o 85°C; VCC = 2.7 t o 5.5V (ex cept wh ere note d).

2. T ransmitter mu st in te rnally p rovide a hol d t i m e to b ri dge the un define d region (300ns max) of the fa lli ng edge of SC L.

Sym Parameter(1) Min Typ Max Units

fSCL SCL Clock Frequency 0 400 kHz

tLOW Clock Low Period 1.3 µs

tHIGH Clock High Period 600 ns

tRSDA and SCL Rise Time 300 ns

tFSDA and SCL Fall Time 300 ns

tHD:STA START Condition Hold Time

(after this period the first clock pulse is generated) 600 ns

tSU:STA START Condition Setup Time

(only relevant for a repeated start condition) 600 ns

tSU:DAT(2) Data Setup Time 100 ns

tHD:DAT Data Hold Time 0 µs

tSU:STO STOP Condition Setup Time 600 ns

tBUF Time the bus must be free before a new

transmission can start 1.3 µs

AI00589

SDA

PtSU:STOtSU:STA

tHD:STA

SCL

tSU:DAT

tHD:DAT

tHIGH

tLOW

tHD:STAtBUF

M41T00S

20/23

P ACKAGE MECHANICA L INFORMATION

Figure 16. SO8 – 8-lead Plastic Small Packag e Outli ne

No te : Drawing is not to scal e.

Table 12. SO8 – 8-lead Plastic Small Outline (150 mils body wi dth), Package M ech. D ata

Symb mm inches

Typ Min Max Typ Min Max

A 1.35 1.75 0.053 0.069

A1 0.10 0.25 0.004 0.010

A2 1.10 1.65 0.043 0.065

B 0.33 0.51 0.013 0.020

C 0.19 0.25 0.007 0.010

D 4.80 5.00 0.189 0.197

E 3.80 4.00 0.150 0.157

e1.27– –0.050– –

H 5.80 6.20 0.228 0.244

h 0.25 0.50 0.010 0.020

L 0.40 0.90 0.016 0.035

α0° 8° 0° 8°

N8 8

ddd 0.10 0.004

SO-A

ddd

LA1 α

h x 45˚

21/23

M41T00S

PART NUMBERING

Table 13. Ordering Information Scheme

For other options, or for more information on any aspec t of t his device, pl ease contact the ST Sales Of fice

nearest you.

Example: M41T 00S M 6 E

Device Type

M41T

Supply Voltage and Write Protect Voltage

00S = VCC = 2.7 to 5.5V

Package

M = SO8

Temperature Range

6 = –40°C to 85°C

Shipping Method

For SO8:

E = Lead-free Package (ECO PACK®), Tubes

F = Lead-free Package (ECO PACK®), Tape & Reel

M41T00S

22/23

REVISION HISTORY

Table 14. Document Revi sion History

M41T00S, 41T00S, T00S, Serial, Serial, Serial, Serial, Serial, Serial, Serial , Ser ial, Serial, Serial, Serial, Serial, Seri al, Serial, Serial, Serial , Ser ial, Serial, Serial, Serial,

Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, S eria l, S er ial, Seri al, Se rial, Seria l, Ser ial, Seri al, Se rial, Serial, Serial, Serial, Serial, Serial, Serial, Seri al, Serial,

Serial, Access, Access, Access, Access, Access, Access, Access, Access, A ccess, Access, Access, Access, Access, Access, Access, A ccess, Access, Access, Access,

Access, Access, Access, Access, Access, A ccess, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Ac-

cess, Access, A ccess, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access,

Access, Access, Access, Access, Access, Access, Access, Access, Access, A ccess, Access, Access, Access, Access, Access, Access, Access, Int erface, Interface,

Inter face , Int erface , In ter fa ce, In te rface, Inte rf ace, Inter face , Int er face , In terfa ce, In ter fa ce, In te rface, Inte rf ace, Inter face , Int er face , In terfa ce, In ter fa ce, In te rface, Inte r-

face, In ter fa ce, Inte rface , In ter fa ce, I nte rf ace , In terfa ce, I nte rf ace, Int erface , In te rfa ce, Int erface , In ter fa ce, I nte r face , In terfa ce, I nte rf ace , Int erfa ce, In te rfa ce, Int erface ,

face, Interface, Interface, I nterface, Interface, Interface, Clock, Clock, Clock, Clock, Clo ck, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock,

Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock,

Clock, Clock, Clock, Clock, Clock, Clock, Clo ck, Clock, Clock, Clock, Cl ock, Clock, Clock, Clock, Clock, Cl ock, Clock, Clock, Clock, Clo ck, Cl ock, Clo ck, RTC, RTC, RTC,

RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC,

RT C, RTC, RTC, RT C, RTC, RTC, P rogra mmab le, Pro gram mable , Prog ramma bl e, Prog ramma ble, Pro gramm able , Progr amma ble, Prog ramma ble, Programmable, Pro-

grammable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Progra mm able, Prog ra m-

m abl e , Prog ra mm ab le, Pr og ra mma b le, Pr og ra mma bl e, Pro gr am ma ble , Pro gr am m abl e, Pro gr am mab le , Pro gra mm ab le , Pr ogr a mm ab le, Pr og ra mm able, Programmabl e,

Progra mmable, Prog rammable, Progra mmable, Prog rammable, Progra mmable, Prog rammable, Progra mmable, Prog rammabl e, Programma ble, Pr ogra mmabl e, Pro-

grammable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Progra mm able, Prog ra m-

mable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable Alarm, Programmable Alarm, Programmable Alarm,

Programmable Alarm, Programmable Alarm, Programmable Alarm, Programmable Alarm, Programmable Alarm, Programmable Alarm, Programmable Alarm, Alarm,

Alarm, Alarm, Alarm, Alarm, Ala rm, Alarm, Alarm, Alarm, Alarm, Alarm, Ala rm, Alarm, Alarm, Alarm, Alarm, Alarm, Ala rm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm,

Alarm, Al arm , Al a rm, A larm , A lar m, Alar m, Alar m , In terr upt , In terr up t, In terr up t, In te rrup t, I nte rrup t, I nte rru pt, Inte r rupt, Int er rupt, Int er rupt , In ter rupt , In ter rup t, In terr up t,

Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interr upt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Inter rupt, Interrupt, Interrupt, Interrup t, In-

terrupt, Interrupt, Interrupt, Interrupt, Inter rupt, Interrupt, Inte rrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Inter rupt, Interr upt, Inter-

rupt, Interrupt, Inter rupt, Interrupt, Interrupt, Interru pt, Interrupt, In terrupt, Inter rupt, Interrupt, Interrupt, Interru pt, Interrupt, In te rrup t, In terr upt, Interrupt, Interrupt, Inte rrupt,

Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interr upt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Inter rupt, Interrupt, Interrupt, Interrup t, In-

terrupt, Interrupt, Interrupt, Interrupt, Inter rupt, Interrupt, Inte rrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Inter rupt, Interr upt, Inter-

Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interr upt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Inter rupt, Interrupt, Interrupt, Interrup t, In-

terrupt, Interrupt, Interrupt, Interrupt, Inter rupt, Interrupt, Inte rrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Inter rupt, Interr upt, Inter-

Interr upt, Inter rupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interru pt, Interrupt, W atchdog, Watchdog, Watchdo g, Watchdog, Watch-

dog, Wat chd og, Wa tch do g, Wat chd og, Wa tch dog , Wat chd og, Watc hdog , Wat chd og, Watc hdog , Wat chdo g, Watc hdog , Wat chdo g, Watc hdog , Wa tc hdog, Watc hdog ,

Watchdog, Watchdo g, Watchdog, Watchd og, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watch dog, Watchdog, Watchdog, Watchdog, Watchdog, Watch-

dog, Wat chd og, Wa tch do g, Wat chd og, Wa tch dog , Wat chd og, Watc hdog , Wat chd og, Watc hdog , Wat chdo g, Watc hdog , Wat chdo g, Watc hdog , Wa tc hdog, Watc hdog ,

Watchd og , W atch do g, Bat tery , B att ery , B atte ry , Ba tte ry, Ba tte ry, Bat ter y, B att er y, Batter y, Ba tte ry, Ba tte ry, Bat ter y, B attery, B att er y, Ba tte ry, Batte ry, Bat ter y, Batter y,

Battery, Batter y, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery,

Battery, Battery, Battery, Switchover, Switchover, Switchover, Switchover, Switchover, Switchover, Switchover, Switchover, Switch over, Backup, Ba ckup, Backup, Back-

up, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Writ e Prot ect, Wr it e

Protect, W ri te Pr otect, Wri te Protec t, Wri te Prote c t, W r it e Pr ot ec t, Wri te Protect, W ri te Protec t, W r it e Pr o tec t, Wri te Protect, Write Protect, Write Protect, Write Protect,

Write Protect, Write Protect, Write Protect, Wri te Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Pro-

tect, Ind ustrial, Ind ustrial , Industria l, Industr ial, Industr ial, In dustrial, I ndustri al, Industri al, Indus tria l, Industr ial, Industr ial, vIn dustria l, Industr ia l, Industr ial, SOI C, S OIC,

SOIC, SOIC, SOIC , SOIC , SOIC, SOIC , SOIC, SOIC , SOIC, SOIC , SOIC , SOIC, SOIC

Date Version Revision Details

February 10, 2004 0.1 First Draft

20-Feb-04 0.2 Update characteristics (Table 9, 10, 5, 7, 13)

14-Apr-04 1.0 Product promoted; reformatted; update characteristics, including Lead-free package

information (Figu re 4. 11; Table 4. 11, 13)

05-May-04 1.1 Update DC Characteristics (Table 7)

16-Jun-04 1.2 Added package shipping (Table 13)

13-Se p-04 2.0 Update Maximum ratings (Table 4)

26-Nov-04 3.0 Promote document; update characteristics; remove references to SOX18 package

(Figure 1, 5; Table 14)

23/23

M41T00S

Information fur nished is believed to b e accurate and relia ble. However, STMicroelectronics a ssumes no responsibility for the consequences

of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted

by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject

to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not

authorized for us e as cri t i cal com ponents in lif e support devices or system s without express written a pproval of STMi cr oel ectro nics.

The ST l ogo is a registered tra dem ark of STMi croelectron ics.

All other names are th e property of their respec tive owners

STM i croelectron ics g roup of com panies

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