STA339BWS13TR - STMicroelectronics

November 2011 Doc ID 15276 Rev 5 1/76

STA339BWS

2.1-channel 40-watt high-efficiency digital audio system

Sound Terminal®

Features

■Wide-range supply voltage, 4.5 V to 21.5 V

■Three power output configurations:

– 2 channels of ternary PWM

(2 x 20 W into 8 Ω at 18 V) + PWM output

– 2 channels of ternary PWM

(2 x 20 W into 8 Ω at 18 V) + ternary stereo

line-out

– 2.1 channels of binary PWM (left, right,

LFE) (2 x 9 W into 4 Ω +1 x 20 W into 8 Ω

at 18 V)

■FFX with 100-dB SNR and dynamic range

■Scalable FFX modulation index

■Selectable 32- to 192-kHz input sample rates

■I2C control with selectable device address

■Digital gain/attenuation +48 dB to -80 dB with

0.5-dB/step resolution

■Soft volume update with programmable ratio

■Individual channel and master gain/attenuation

■Two independent DRCs configurable as a

dual-band anticlipper (B2DRC) or as

independent limiters/compressors

■EQ-DRC for DRC based on filtered signals

■Dedicated LFE processing for bass boosting

■Audio presets:

– 15 preset crossover filters

– 5 preset anticlipping modes

– Preset nighttime listening mode

■Individual channel soft/hard mute

■Independent channel volume and DSP bypass

■I2S input data interface

■Input and output channel mapping

■Automatic invalid input-detect mute

■Up to 8 user-programmable biquads/channel

■Three coefficient banks for storing EQ presets

with fast recall via I2C interface

■Bass/treble tones and de-emphasis control

■Selectable high-pass filter for DC blocking

■Advanced AM interference frequency

switching and noise suppression modes

■Selectable high- or low-bandwidth

noise-shaping topologies

■Selectable clock input ratio

■96-kHz internal processing sample rate

■Thermal overload and short-circuit protection

technology

■Video apps: 576 x fS input mode supported

■Pin and SW compatible with STA333BW,

STA339BW, STA559BW and STA559BWS

PowerSSO-36

with exposed pad down (EPD)

Table 1. Device summary

Order code Package Packaging

STA339BWS PowerSSO-36 EPD Tube

STA339BWS13TR PowerSSO-36 EPD Tape and reel

www.st.com

Contents STA339BWS
2/76 Doc ID 15276 Rev 5
Contents
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1 Connection diagram  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  10
2 Pin description  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  10
Electrical specifications  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  12
2 Thermal data   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  12
3 Recommended operating conditions  . . . . . . . . . . . . . . . . . . . . . . . . . . . .  13
4 Electrical specifications for the digital section   . . . . . . . . . . . . . . . . . . . . .  13
5 Electrical specifications for the power section  . . . . . . . . . . . . . . . . . . . . .  14
6 Power on/off sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  16
Processing data paths  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5I
2C bus specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1 Communication protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  19
1.1 Data transition or change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.2 Start condition  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.3 Stop condition   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.4 Data input   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2 Device addressing  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  19
3 Write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  20
3.1 Byte write  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.2 Multi-byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4 Read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  20
4.1 Current address byte read  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.2 Current address multi-byte read   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.3 Random address byte read  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.4 Random address multi-byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Register description  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

STA339BWS Contents
Doc ID 15276 Rev 5 3/76
1 Configuration registers (addr 0x00 to 0x05)  . . . . . . . . . . . . . . . . . . . . . . .  24
1.1 Configuration register A (addr 0x00)  . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
1.2 Configuration register B (addr 0x01)  . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
1.3 Configuration register C (addr 0x02)  . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
1.4 Configuration register D (addr 0x03)  . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
1.5 Configuration register E (addr 0x04)  . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
1.6 Configuration register F (addr 0x05)   . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
2 Volume control registers (addr 0x06 - 0x0A)   . . . . . . . . . . . . . . . . . . . . . .  42
2.1 Mute/line output configuration register (addr 0x06)  . . . . . . . . . . . . . . . . 43
2.2 Master volume register (addr 0x07)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
2.3 Channel 1 volume (addr 0x08) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
2.4 Channel 2 volume (addr 0x09) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
2.5 Channel 3 / line output volume (addr 0x0A) . . . . . . . . . . . . . . . . . . . . . . 44
3 Audio preset registers (addr 0x0B and 0x0C)   . . . . . . . . . . . . . . . . . . . . .  45
3.1 Audio preset register 1 (addr 0x0B)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.2 Audio preset register 2 (addr 0x0C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4 Channel configuration registers (addr 0x0E - 0x10) . . . . . . . . . . . . . . . . .  47
5 Tone control register (addr 0x11)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  49
6 Dynamic control registers (addr 0x12 - 0x15)   . . . . . . . . . . . . . . . . . . . . .  49
6.1 Limiter 1 attack/release rate (addr 0x12)  . . . . . . . . . . . . . . . . . . . . . . . . 49
6.2 Limiter 1 attack/release threshold (addr 0x13) . . . . . . . . . . . . . . . . . . . . 49
6.3 Limiter 2 attack/release rate (addr 0x14)  . . . . . . . . . . . . . . . . . . . . . . . . 50
6.4 Limiter 2 attack/release threshold (addr 0x15) . . . . . . . . . . . . . . . . . . . . 50
6.5 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
6.6 Limiter 1 extended attack threshold (addr 0x32)  . . . . . . . . . . . . . . . . . . 54
6.7 Limiter 1 extended release threshold (addr 0x33)  . . . . . . . . . . . . . . . . . 55
6.8 Limiter 2 extended attack threshold (addr 0x34)  . . . . . . . . . . . . . . . . . . 55
6.9 Limiter 2 extended release threshold (addr 0x35)  . . . . . . . . . . . . . . . . . 55
7 User-defined coefficient control registers (addr 0x16 - 0x26) . . . . . . . . . .  55
7.1 Coefficient address register (addr 0x16)  . . . . . . . . . . . . . . . . . . . . . . . . 55
7.2 Coefficient b1 data register bits (addr 0x17 - 0x19)  . . . . . . . . . . . . . . . . 55
7.3 Coefficient b2 data register bits (addr 0x1A - 0x1C)  . . . . . . . . . . . . . . . 56
7.4 Coefficient a1 data register bits (addr 0x1D - 0x1F)   . . . . . . . . . . . . . . . 56
7.5 Coefficient a2 data register bits (addr 0x20 - 0x22)  . . . . . . . . . . . . . . . . 56
7.6 Coefficient b0 data register bits (addr 0x23 - 0x25)  . . . . . . . . . . . . . . . . 57
7.7 Coefficient read/write control register (addr 0x26) . . . . . . . . . . . . . . . . . 57

Contents STA339BWS
4/76 Doc ID 15276 Rev 5
7.8 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
7.9 Thermal warning and overcurrent adjustment (TWOCL) . . . . . . . . . . . . 61
8 Variable max power correction registers (addr 0x27 - 0x28)  . . . . . . . . . .  62
9 Distortion compensation registers (addr 0x29 - 0x2A) . . . . . . . . . . . . . . .  62
10 Fault detect recovery constant registers (addr 0x2B - 0x2C)  . . . . . . . . . .  62
11 Device status register (addr 0x2D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  63
12 EQ coefficients and DRC configuration register (addr 0x31)  . . . . . . . . . .  64
13 Extended configuration register (addr 0x36)   . . . . . . . . . . . . . . . . . . . . . .  65
13.1 Dual-band DRC (B2DRC)   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
13.2 EQ DRC mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
14 Soft volume configuration registers (addr 0x37 - 0x38)  . . . . . . . . . . . . . .  68
15 DRC RMS filter coefficients (addr 0x39-0x3E) . . . . . . . . . . . . . . . . . . . . .  69
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
1 Applications schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  70
2 PLL filter circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  70
3 Typical output configuration  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  70
Package thermal characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Package mechanical data  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Revision history   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

STA339BWS List of figures
Doc ID 15276 Rev 5 5/76
List of figures
Figure 1. Block diagram   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 2. Pin connection PowerSSO-36 (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 3. Test circuit  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 4. Power-on sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 5. Power-off sequence for pop-free turn-off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 6. Left and right processing, section 1  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 7. Left and right processing, section 2  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 8. Write mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 9. Read mode sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 10. OCFG = 00 (default value) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 11. OCFG = 01   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 12. OCFG = 10   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 13. OCFG = 11   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 14. Output mapping scheme  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 15. 2.0 channels (OCFG = 00) PWM slots   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 16. 2.1 channels (OCFG = 01) PWM slots   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 17. 2.1 channels (OCFG = 10) PWM slots   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 18. Basic limiter and volume flow diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 19. B2DRC scheme  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Figure 20. EQDRC scheme   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 21. Output configuration for stereo BTL mode (RL = 8 Ω)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 22. Applications circuit  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 23. PowerSSO-36 power derating curve  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Figure 24. PowerSSO-36 EPD outline drawing   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

List of tables STA339BWS
6/76 Doc ID 15276 Rev 5
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Pin description  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 4. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 5. Recommended operating condition  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 6. Electrical specifications - digital section (Tamb = 25 °C) . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 7. Electrical specifications - power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 8. Register summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 9. Master clock select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 10. Input sampling rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 11. Internal interpolation ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 12. IR bit settings as a function of input sample rate  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 13. Thermal warning recovery bypass  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 14. Thermal warning adjustment bypass  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 15. Fault detect recovery bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 16. Serial audio input interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 17. Serial data first bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 18. Support serial audio input formats for MSB-first (SAIFB = 0) . . . . . . . . . . . . . . . . . . . . . . . 27
Table 19. Supported serial audio input formats for LSB-first (SAIFB = 1)  . . . . . . . . . . . . . . . . . . . . . 27
Table 20. Delay serial clock enable  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 21. Channel input mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 22. FFX power output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 23. FFX compensating pulse size bits  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 24. Compensating pulse size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 25. Overcurrent warning bypass. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 26. High-pass filter bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 27. De-emphasis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 28. DSP bypass  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 29. Postscale link  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 30. Biquad coefficient link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 31. Dynamic range compression/anticlipping bit  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 32. Zero-detect mute enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 33. Submix mode enable  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 34. Max power correction variable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 35. Max power correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 36. Noise-shaper bandwidth selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 37. AM mode enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 38. PWM speed mode  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 39. Distortion compensation variable enable  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 40. Zero-crossing volume enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 41. Soft volume update enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 42. Output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 43. Output configuration engine selection  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 44. Invalid input detect mute enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 45. Binary output mode clock loss detection  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 46. LRCK double trigger protection  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 47. Auto EAPD on clock loss  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 48. IC power down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

STA339BWS List of tables
Doc ID 15276 Rev 5 7/76
Table 49. External amplifier power down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 50. Line output configuration  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 51. Master volume offset as a function of MVOL[7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 52. Channel volume as a function of CxVOL[7:0]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 53. Audio preset gain compression/limiters selection for AMGC[3:2] = 00. . . . . . . . . . . . . . . . 45
Table 54. AM interference frequency switching bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 55. Audio preset AM switching frequency selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 56. Bass management crossover . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 57. Bass management crossover frequency  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 58. Tone control bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 59. EQ bypass  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 60. Volume bypass register  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 61. Binary output enable registers  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 62. Channel limiter mapping as a function of CxLS bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 63. Channel output mapping as a function of CxOM bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 64. Tone control boost/cut as a function of BTC and TTC bits . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 65. Limiter attack rate vs LxA bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 66. Limiter release rate vs LxR bits  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 67. Limiter attack threshold vs LxAT bits (AC mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 68. Limiter release threshold vs LxRT bits (AC mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 69. Limiter attack threshold vs LxAT bits (DRC mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 70. Limiter release threshold vs LxRT bits (DRC mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 71. RAM block for biquads, mixing, scaling, bass management. . . . . . . . . . . . . . . . . . . . . . . . 59
Table 72. Status register bits  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 73. EQ RAM select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 74. Anticlipping and DRC preset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 75. Anticlipping selection for AMGC[3:2] = 01  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 76. Bit PS48DB description  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 77. Bit XAR1 description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 78. Bit XAR2 description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 79. Bit BQ5 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 80. Bit BQ6 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 81. Bit BQ7 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 82. Bit SVUPE description  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 83. Bit SVDWE description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 84. PowerSSO-36 EPD dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 85. Document revision history  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Description STA339BWS

8/76 Doc ID 15276 Rev 5

1 Description

The STA339BWS is an integrated solution of digital audio processing, digital amplifier

controls and power output stage to create a high-power single-chip FFX digital amplifier with

high quality and high efficiency. Three channels of FFX processing are provided. The FFX

processor implements the ternary, binary and binary differential processing capabilities of

the full FFX processor.

The STA339BWS is part of the Sound Terminal® family that provides full digital audio

streaming to the speakers and offers cost effectiveness, low power dissipation and sound

enrichment.

Also provided in the STA339BWS are a full assortment of digital processing features. This

includes up to 8 programmable biquads (EQ) per channel. Available presets enable a time-

to-market advantage by substantially reducing the amount of software development needed

for functions such as audio preset volume loudness, preset volume curves and preset EQ

settings. There are also new advanced AM radio interference reduction modes. Dual-band

DRC dynamically equalizes the system to provide linear frequency speaker response

regardless of output power level. This feature separates the audio frequency band into two

sub-bands independently processed to provide better sound clarity and to avoid speaker

saturation.

The serial audio data input interface accepts all possible formats, including the popular I2S

format. The high-quality conversion from PCM audio to FFX PWM switching provides over

100 dB of SNR and of dynamic range.

Figure 1. Block diagram

Protection

current/thermal

Logic

Regulators

Bias

Power

control

FFX

PLL

Volume

control

Channel

interface

PowerDigital DSP

STA339BWS Description

Doc ID 15276 Rev 5 9/76

The power section consists of four independent half-bridges. These can be configured via

digital control to operate in different modes.

●2.1 channels can be provided by two half bridges and a single full bridge, supplying up

to 2 x 9 W + 1 x 20 W of output power.

●Two channels can be provided by two full-bridges, supplying up to 2 x 20 W of output

power.

●The IC can also be configured as 2.1 channels with 2 x 20 W supplied by the device

plus a drive for an external FFX power amplifier, such as STA533WF or STA515W.

Pin connections STA339BWS

10/76 Doc ID 15276 Rev 5

2 Pin connections

2.1 Connection diagram

Figure 2. Pin connection PowerSSO-36 (top view)

2.2 Pin description

VDD_DIG

GND_DIG

SCL

SDA

INT_LINE

RESET

SDI

LRCKI

BICKI

XTI

GND_PLL

FILTER_PLL

VDD_PLL

PWRDN

GND_DIG

VDD_DIG

TWARN / OUT4A

EAPD / OUT4B

GND_SUB

TEST_MODE

VSS

VCC_REG

OUT2B

GND2

VCC2

OUT2A

OUT1B

VCC1

GND1

OUT1A

GND_REG

VDD

CONFIG

OUT3B / FFX3B

OUT3A / FFX3A

D05AU1638

EP, exposed pad

(device ground)

Table 2. Pin description

Pin Type Name Description

1 GND GND_SUB Substrate ground

2I SA I

C select address (pull-down)

3 I TEST_MODE This pin must be connected to ground (pull-down)

4 I/O VSS Internal reference at VCC - 3.3 V

5 I/O VCC_REG Internal VCC reference

6 O OUT2B Output half-bridge channel 2B

7 GND GND2 Power negative supply

8 Power VCC2 Power positive supply

9 O OUT2A Output half-bridge channel 2A

10 O OUT1B Output half-bridge channel 1B

STA339BWS Pin connections

Doc ID 15276 Rev 5 11/76

11 Power VCC1 Power positive supply

12 GND GND1 Power negative supply

13 O OUT1A Output half-bridge channel 1A

14 GND GND_REG Internal ground reference

15 Power VDD Internal 3.3 V reference voltage

16 I CONFIG Parallel mode command

17 O OUT3B / FFX3B PWM out channel 3B / external bridge driver

18 O OUT3A / FFX3A PWM out channel 3A / external bridge driver

19 O EAPD / OUT4B Power down for external bridge / PWM out channel 4B

20 I/O TWARN / OUT4A Thermal warning from external bridge (pull-up when input)

/ PWM out channel 4A

21 Power VDD_DIG Digital supply voltage

22 GND GND_DIG Digital ground

23 I PWRDN Power down (pull-up)

24 Power VDD_PLL Positive supply for PLL

25 I FILTER_PLL Connection to PLL filter

26 GND GND_PLL Negative supply for PLL

27 I XTI PLL input clock

28 I BICKI I

S serial clock

29 I LRCKI I

S left/right clock

30 I SDI I

S serial data channels 1 and 2

31 I RESET Reset (pull-up)

32 O INT_LINE Fault interrupt

33 I/O SDA I

C serial data

34 I SCL I

C serial clock

35 GND GND_DIG Digital ground

36 Power VDD_DIG Digital supply voltage

- - EP Exposed pad for PCB heatsink, to be connected to GND

Table 2. Pin description (continued)

Pin Type Name Description

Electrical specifications STA339BWS

12/76 Doc ID 15276 Rev 5

3 Electrical specifications

3.1 Absolute maximum ratings

Warning: Stresses beyond those listed in Table 3 above may cause

permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any

other conditions beyond those indicated under

“Recommended operating conditions” are not implied.

Exposure to absolute-maximum-rated conditions for

extended periods may affect device reliability. In the real

application, power supplies with nominal values rated within

the recommended operating conditions, may experience

some rising beyond the maximum operating conditions for a

short time when no or very low current is sinked (amplifier in

mute state). In this case the reliability of the device is

guaranteed, provided that the absolute maximum ratings are

not exceeded.

3.2 Thermal data

Table 3. Absolute maximum ratings

Symbol Parameter Min Typ Max Unit

VCC Power supply voltage (pins VCCx) -0.3 - 24 V

VDD Digital supply voltage (pins VDD_DIG) -0.3 - 4.0 V

VDD PLL supply voltage (pin VDD_PLL) -0.3 - 4.0 V

Top Operating junction temperature -20 - 150 °C

Tstg Storage temperature -40 - 150 °C

Table 4. Thermal data

Parameter Min Typ Max Unit

Rth j-case Thermal resistance junction-case (thermal pad) - - 1.5 °C/W

Tth_sdj Thermal shut-down junction temperature - 150 - °C

Tth_warn Thermal warning temperature - 130 - °C

Tth_sdh Thermal shut-down hysteresis - 20 - °C

Rth j-amb Thermal resistance junction-ambient (1)

1. See Chapter 8: Package thermal characteristics on page 72 for details.

-24-°C/W

STA339BWS Electrical specifications

Doc ID 15276 Rev 5 13/76

3.3 Recommended operating conditions

3.4 Electrical specifications for the digital section

Table 5. Recommended operating condition

Symbol Parameter Min Typ Max Unit

VCC Power supply voltage (VCCxA, VCCxB) 4.5 - 21.5 V

VDD_DIG Digital supply voltage 2.7 3.3 3.6 V

VDD_PLL PLL supply voltage 2.7 3.3 3.6 V

Tamb Ambient temperature -20 - 70 °C

Table 6. Electrical specifications - digital section (Tamb = 25 °C)

Symbol Parameter Conditions Min Typ Max Unit

Iil

Low level input current without

pull-up/down device Vi = 0 V - - 1 µA

Iih

High level input current without

pull-up/down device

Vi = VDD_DIG

= 3.6 V --1µA

Vil Low level input voltage - - - 0.2 *

VDD_DIG V

Vih High level input voltage - 0.8 *

VDD_DIG --V

Vol Low level output voltage Iol = 2 mA - 0.4 *

VDD_DIG V

Voh High level output voltage Ioh = 2 mA 0.8 *

VDD_DIG --V

Rpu

Equivalent pull-up/down

resistance --50-kΩ

Electrical specifications STA339BWS

14/76 Doc ID 15276 Rev 5

3.5 Electrical specifications for the power section

The specifications given in this section are valid for the operating conditions: VCC =18V,

f=1kHz, f

sw = 384 kHz, Tamb = 25 °C and RL = 8 Ω, unless otherwise specified.

Table 7. Electrical specifications - power section

Symbol Parameter Conditions Min Typ Max Unit

Output power BTL THD = 1% - 16 - W

THD = 10% - 20 -

Output power SE THD = 1%,RL= 4 Ω-7-W

THD = 10%,RL= 4 Ω-9-

RdsON Power P-channel or N-channel MOSFET ld = 0.75 A - - 250 mΩ

gP Power P-channel RdsON matching ld = 0.75 A - 100 - %

gN Power N-channel RdsON matching ld = 0.75 A - 100 - %

Idss Power P-channel/N-channel leakage VCC = 20 V - - 1 μA

trRise time Resistive load,

see Figure 3 below

- - 10 ns

tfFall time - - 10 ns

IVCC

Supply current from VCC in power down PWRDN = 0 - 0.3 - μA

Supply current from VCC in operation PWRDN = 1 - 15 - mA

IVDD Supply current FFX processing Internal clock =

49.152 MHz -55-mA

ILIM Overcurrent limit (1) 2.2 3.0 - A

ISCP Short -circuit protection RL = 0 Ω2.7 3.6 - A

VUVP Undervoltage protection - - - 4.3 V

tmin Output minimum pulse width No load 20 40 60 ns

DR Dynamic range - - 100 - dB

SNR Signal to noise ratio, ternary mode A-Weighted - 100 - dB

Signal to noise ratio binary mode - - 90 - dB

THD+N Total harmonic distortion + noise

FFX stereo mode,

Po = 1 W

f=1kHz

-0.2-%

XTA L K Crosstalk

FFX stereo mode,

<5 kHz

One channel driven

at 1 W, other channel

measured

-80-dB

Peak efficiency, FFX mode Po = 2 x 20 W

into 8 Ω-90-

Peak efficiency, binary modes Po = 2 x 9 W into 4 Ω

+ 1 x 20 W into 8 Ω-87-

1. Limit the current if overcurrent warning detect adjustment bypass is enabled (register bit CONFC.OCRB on

page 30). When disabled refer to the ISCP.

STA339BWS Electrical specifications

Doc ID 15276 Rev 5 15/76

Figure 3. Test circuit

tr tf

OUTxY

VCC

(0.9)*VCC

½VCC

(0.1)*VCC

+Vcc

Duty cycle = 50%

INxY OUTxY

gnd

vdc = Vcc/2

Rload = 8 Ω

Electrical specifications STA339BWS

16/76 Doc ID 15276 Rev 5

3.6 Power on/off sequence

Figure 4. Power-on sequence

Note: The definition of a stable clock is when fmax - fmin < 1 MHz.

Section Serial audio input interface format on page 26 gives information on setting up the

I2S interface.

Figure 5. Power-off sequence for pop-free turn-off

Don’t care

Don’t care CMD0 CMD1 CMD2

VCC

VDD_Dig

XTI

Reset

I2C

PWDN

TR TC

Don’t care

Don’t care CMD0 CMD1 CMD2

VCC

VDD_Dig

XTI

Reset

I2C

PWDN

TR TC

Don’t care

Don’t care CMD0 CMD1 CMD2

VCC

VDD_Dig

XTI

Reset

I2C

PWDN

TR TC

Don’t care

Don’t care CMD0 CMD1 CMD2

VCC

VDD_Dig

XTI

Reset

I2C

PWDN

TR TC

Don’t care

Don’t care CMD0 CMD1 CMD2

VCC

VDD_Dig

XTI

Reset

I2C

PWDN

TR TC

Don’t care

Note: no specific VCC and

VDD_DIG turn

−

on sequence

is required

TR = minimum time between XTI master clock stable and Reset removal: 1 ms

TC = minimum time between Reset removal and I2C program, sequence start: 1ms

Don’t care

VCC

VDD_Dig

XTI Don’t care

Soft Mute

Reg. 0x07

Data 0xFE

Soft EAPD

Reg. 0x05

Bit 7 = 0

Don’t care

Don’t care Don’t care

Don’t care

VCC

VDD_Dig

XTI Don’t care

Soft Mute

Reg. 0x07

Data 0xFE

Soft EAPD

Reg. 0x05

Bit 7 = 0

Don’t care

Don’t care Don’t care

Note: no specific VCC and

VDD_DIG turn

−

off sequence

is required

STA339BWS Processing data paths

Doc ID 15276 Rev 5 17/76

4 Processing data paths

Figure 6 and Figure 7 below show the data processing paths inside STA339BWS. The

whole processing chain is composed of two consecutive sections. In the first one,

dual-channel processing is implemented and in the second section each channel is fed into

the post-mixing block either to generate a third channel (typically used in 2.1 output

configuration and with crossover filters enabled) or to have the channels processed by the

dual-band DRC block (2.0 output configuration with crossover filters used to define the

cut-off frequency of the two bands).

The first section, Figure 6, begins with a 2x oversampling FIR filter providing 2 * fS audio

processing. Then a selectable high-pass filter removes the DC level (enabled if HPB = 0).

The left and right channel processing paths can include up to 8 filters, depending on the

selected configuration (bits BQL, BQ5, BQ6, BQ7 and XO[3:0]). By default, four user

programmable, independent filters per channel are enabled, plus the preconfigured

de-emphasis, bass and treble controls (BQL = 0, BQ5 = 0, BQ6 = 0, BQ7 = 0).

If the coefficient sets for the two channels are linked (BQL = 1) it is possible to use the

de-emphasis, bass and treble filters in a user defined configuration (provided the relevant

BQx bits are set). In this case both channels use the same processing coefficients and can

have up to seven filters each. If BQL = 0 the BQx bits are ignored and the fifth, sixth and

seventh filters are configured as de-emphasis, bass and treble controls, respectively.

Figure 6. Left and right processing, section 1

Moreover, the common 8th filter can be available on both channels provided the predefined

crossover frequencies are not used, XO[3:0] = 0, and the dual-band DRC is not used.

In the second section, Figure 7, mixing and crossover filters are available. If B2DRC is not

enabled they are fully user-programmable and allow the generation of a third channel

(2.1 outputs). Alternatively, in mode B2DRC, these blocks are used to split the sub-band and

define the cut-off frequencies of the two bands. A prescaler and a final postscaler allow full

control over the signal dynamics before and after the filtering stages. A mixer function is also

available.

From

I2S input

interface

PreScale Biquad

Biquad

If HPB=0 User Defined Filters

If DSPB=0 and C1EQBP=0

FIR

over

Sampling

frequency=Fs

Sampling

frequency=2xFs

From

I2S input

interface

PreScale Hi-Pass

Filter

Hi-Pass

Filter

Biquad

#4 De-Emph.

If DEMP=0

FIR

over

sampling

Sampling

frequency=Fs

Sampling

frequency=2xFs

Bass Treble

If C1TCB=0

BTC: Bass Boost/Cut

TTC: Treble Boost/Cut

PreScale Hi-Pass

Filter

Biquad

If HPB=0 User Defined Filters

If DSPB=0 and C2EQBP=0

FIR

over

PreScale Hi-Pass

Filter

Biquad

#4 De-Emph.

If DEMP=0

FIR

over

sampling

Bass Treble

If C2TCB=0

BTC: Bass Boost/Cut

TTC: Treble Boost/Cut

If BQ5=1

and BQL=1

Biquad

If BQ6=1

and BQL=1

Biquad

IF BQ7=1

and BQL=1

Biquad

If BQ5=1

and BQL=1

Biquad

If BQ6=1

and BQL=1

Biquad

IF BQ7=1

and BQL=1

Biquad

From

I2S input

interface

PreScale Biquad

Biquad

If HPB=0 User Defined Filters

If DSPB=0 and C1EQBP=0

FIR

over

Sampling

frequency=Fs

Sampling

frequency=2xFs

From

I2S input

interface

PreScale Hi-Pass

Filter

Hi-Pass

Filter

Hi-Pass

Filter

Hi-Pass

Filter

Biquad

#4 De-Emph.

If DEMP=0

FIR

over

sampling

Sampling

frequency=Fs

Sampling

frequency=2xFs

Bass Treble

If C1TCB=0

BTC: Bass Boost/Cut

TTC: Treble Boost/Cut

PreScale Hi-Pass

Filter

Biquad

If HPB=0 User Defined Filters

If DSPB=0 and C2EQBP=0

FIR

over

PreScale Hi-Pass

Filter

Biquad

#4 De-Emph.

If DEMP=0

FIR

over

sampling

Bass Treble

If C2TCB=0

BTC: Bass Boost/Cut

TTC: Treble Boost/Cut

If BQ5=1

and BQL=1

Biquad

If BQ6=1

and BQL=1

Biquad

IF BQ7=1

and BQL=1

Biquad

If BQ5=1

and BQL=1

Biquad

If BQ6=1

and BQL=1

Biquad

IF BQ7=1

and BQL=1

Biquad

Processing data paths STA339BWS

18/76 Doc ID 15276 Rev 5

Figure 7. Left and right processing, section 2

Dual-band DRC enabled

Dual-band DRC disabled

Crossover frequency determined by XO setting

User-defined if XO = 0000

C1Mx2

C2Mx1

C2Mx2

C3Mx1

C3Mx2

C1Mx1

Hi-Pass XO

Filter

Hi-Pass XO

Filter

User-defined mix coefficients

Post scale

C1Mx2 =

0x00000

C2Mx1=

0x000000

C2Mx2 =

0x7FFFFF

C3Mx1 =

0x40000

C3Mx2 =

0x400000

C1Mx1 =

0x7FFFFF

B2DRC

Hi-pass

filter

Post-scale

Vol

And

Limiter

DRC1

DRC2

Ch1

Volume

Ch2

Volume

Ch3

Volume

B2DRC

Hi-pass

filter

B2DRC Enabled

DRC2

Ch3

Volume

Crossover frequency determined by XO setting

User-defined if XO = 0000

C1Mx2

C2Mx1

C2Mx2

C3Mx1

C3Mx2

C1Mx1

Hi-Pass XO

Filter

Hi-Pass XO

Filter

User-defined mix coefficients

Post scale

C1Mx2 =

0x00000

C2Mx1=

0x000000

C2Mx2 =

0x7FFFFF

C3Mx1 =

0x40000

C3Mx2 =

0x400000

C1Mx1 =

0x7FFFFF

B2DRC

Hi-pass

filter

Post-scale

Vol

And

Limiter

DRC1

DRC2

Ch1

Volume

Ch2

Volume

Ch3

Volume

B2DRC

Hi-pass

filter

B2DRC Enabled

DRC2

Ch3

Volume

Crossover frequency determined by XO setting

User defined if XO = 0000

C1Mx2

C2Mx1

C2Mx2

C3Mx1

C3Mx2

C1Mx1

Hi-Pass XO

Filter

Hi-Pass XO

Filter

Lo-Pass XO

Filter

User-defined mix coefficients

Vol

And

Limiter

Vol

And

Limiter

Vol

And

Limiter

Post scale

C1Mx2

C2Mx1

C2Mx2

C3Mx1

C3Mx2

C1Mx1

Channel 1/2

Biquad #5

--------------

Hi-pass XO

filter

Volume

and

Limiter

Volume

and

Limiter

Volume

and

Limiter

Post-scale

Channel 1/2

Biquad #5

--------------

Hi-pass XO

filter

Channel 3

Biquad

--------------

Low-pass XO

filter

B2DRC Disabled

Crossover frequency determined by XO setting

User defined if XO = 0000

C1Mx2

C2Mx1

C2Mx2

C3Mx1

C3Mx2

C1Mx1

Hi-Pass XO

Filter

Hi-Pass XO

Filter

Lo-Pass XO

Filter

User-defined mix coefficients

Vol

And

Limiter

Vol

And

Limiter

Vol

And

Limiter

Post scale

C1Mx2

C2Mx1

C2Mx2

C3Mx1

C3Mx2

C1Mx1

Channel 1/2

Biquad #5

--------------

Hi-pass XO

filter

Volume

and

Limiter

Volume

and

Limiter

Volume

and

Limiter

Post-scale

Channel 1/2

Biquad #5

--------------

Hi-pass XO

filter

Channel 3

Biquad

--------------

Low-pass XO

filter

B2DRC Disabled

STA339BWS I2C bus specification

Doc ID 15276 Rev 5 19/76

5 I2C bus specification

The STA339BWS supports the I2C protocol via the input ports SCL and SDA_IN (master to

slave) and the output port SDA_OUT (slave to master). This protocol defines any device that

sends data on to the bus as a transmitter and any device that reads the data as a receiver.

The device that controls the data transfer is known as the master and the other as the slave.

The master always starts the transfer and provides the serial clock for synchronization. The

STA339BWS is always a slave device in all of its communications. It supports up to 400 kb/s

(fast-mode bit rate).

For correct operation of the I2C interface ensure that the master clock generated by the PLL

has a frequency at least 10 times higher than the frequency of the applied SCL clock.

5.1 Communication protocol

5.1.1 Data transition or change

Data changes on the SDA line must only occur when the clock SCL is low. A SDA transition

while the clock is high is used to identify a START or STOP condition.

5.1.2 Start condition

START is identified by a high to low transition of the data bus, SDA, while the clock, SCL, is

stable in the high state. A START condition must precede any command for data transfer.

5.1.3 Stop condition

STOP is identified by low to high transition of SDA while SCL is stable in the high state. A

STOP condition terminates communication between STA339BWS and the bus master.

5.1.4 Data input

During the data input the STA339BWS samples the SDA signal on the rising edge of SCL.

For correct device operation the SDA signal must be stable during the rising edge of the

clock and the data can change only when the SCL line is low.

5.2 Device addressing

To start communication between the master and the STA339BWS, the master must initiate

with a start condition. Following this, the master sends onto the SDA line 8-bits (MSB first)

corresponding to the device select address and read or write mode bit.

The seven most significant bits are the device address identifiers, corresponding to the I2C

bus definition. In the STA339BWS the I2C interface has two device addresses depending on

the SA pin configuration, 0x38 when SA = 0, and 0x3A when SA = 1.

The eighth bit (LSB) identifies a read or write operation (R/W); this is set to 1 for read and to

0 for write. After a START condition the STA339BWS identifies the device address on the

SDA bus and if a match is found, acknowledges the identification during the 9th bit time

frame. The byte following the device identification is the address of a device register.

I2C bus specification STA339BWS

20/76 Doc ID 15276 Rev 5

5.3 Write operation

Following the START condition the master sends a device select code with the RW bit set

to 0. The STA339BWS acknowledges this and then waits for the byte of internal address.

After receiving the internal byte address the STA339BWS again responds with an

acknowledgement.

5.3.1 Byte write

In the byte write mode the master sends one data byte, this is acknowledged by the

STA339BWS. The master then terminates the transfer by generating a STOP condition.

5.3.2 Multi-byte write

The multi-byte write modes can start from any internal address. The master generating a

STOP condition terminates the transfer.

Figure 8. Write mode sequence

5.4 Read operation

5.4.1 Current address byte read

Following the START condition the master sends a device select code with the RW bit set

to 1. The STA339BWS acknowledges this and then responds by sending one byte of data.

The master then terminates the transfer by generating a STOP condition.

5.4.2 Current address multi-byte read

The multi-byte read modes can start from any internal address. Sequential data bytes are

read from sequential addresses within the STA339BWS. The master acknowledges each

data byte read and then generates a STOP condition terminating the transfer.

5.4.3 Random address byte read

Following the START condition the master sends a device select code with the RW bit set

to 0. The STA339BWS acknowledges this and then the master writes the internal address

byte. After receiving, the internal byte address the STA339BWS again responds with an

acknowledgement. The master then initiates another START condition and sends the device

select code with the RW bit set to 1. The STA339BWS acknowledges this and then

responds by sending one byte of data. The master then terminates the transfer by

generating a STOP condition.

DEV-ADDR

ACK

START RW

SUB-ADDR

ACK

DATA IN

ACK

STOP

BYTE

WRITE

DEV-ADDR

ACK

START RW

SUB-ADDR

ACK

DATA IN

ACK

STOP

MULTIBYTE

WRITE

DATA IN

ACK

STA339BWS I2C bus specification

Doc ID 15276 Rev 5 21/76

5.4.4 Random address multi-byte read

The multi-byte read modes could start from any internal address. Sequential data bytes are

read from sequential addresses within the STA339BWS. The master acknowledges each

data byte read and then generates a STOP condition terminating the transfer.

Figure 9. Read mode sequence

DEV-ADDR

ACK

START RW

DATA

NO ACK

STOP

CURRENT

ADDRESS

READ

DEV-ADDR

ACK

START RW

SUB-ADDR

ACK

DEV-ADDR

ACK

STOP

RANDOM

ADDRESS

READ

DATA

NO ACK

START RW

DEV-ADDR

ACK

START

DATA

ACK

DATA

ACK

STOP

SEQUENTIAL

CURRENT

READ

DATA

NO ACK

DEV-ADDR

ACK

START RW

SUB-ADDR

ACK

DEV-ADDR

ACK

SEQUENTIAL

RANDOM

READ

DATA

ACK

START RW

DATA

ACK NO ACK

STOP

DATA

RW=

HIGH

22/76 Doc ID 15276 Rev 5

6 Register description

Note: Addresses exceeding the maximum address number must not be written.

Table 8. Register summary

Addr Name D7 D6 D5 D4 D3 D2 D1 D0

0x00 CONFA FDRB TWAB TWRB IR1 IR0 MCS2 MCS1 MCS0

0x01 CONFB C2IM C1IM DSCKE SAIFB SAI3 SAI2 SAI1 SAI0

0x02 CONFC OCRB Reserved CSZ3 CSZ2 CSZ1 CSZ0 OM1 OM0

0x03 CONFD SME ZDE DRC BQL PSL DSPB DEMP HPB

0x04 CONFE SVE ZCE DCCV PWMS AME NSBW MPC MPCV

0x05 CONFF EAPD PWDN ECLE LDTE BCLE IDE OCFG1 OCFG0

0x06 MUTELOC LOC1 LOC0 Reserved Reserved C3M C2M C1M Reserved

0x07 MVOL MVOL[7:0]

0x08 C1VOL C1VOL[7:0]

0x09 C2VOL C2VOL[7:0]

0x0A C3VOL C3VOL[7:0]

0x0B AUTO1 Reserved Reserved AMGC[1:0] Reserved Reserved Reserved Reserved

0x0C AUTO2 XO3 XO2 XO1 XO0 AMAM2 AMAM1 AMAM0 AMAME

0x0D AUTO3 Reserved

0x0E C1CFG C1OM1 C1OM0 C1LS1 C1LS0 C1BO C1VBP C1EQBP C1TCB

0x0F C2CFG C2OM1 C2OM0 C2LS1 C2LS0 C2BO C2VBP C2EQBP C2TCB

0x10 C3CFG C3OM1 C3OM0 C3LS1 C3LS0 C3BO C3VBP Reserved Reserved

0x11 TONE TTC3 TTC2 TTC1 TTC0 BTC3 BTC2 BTC1 BTC0

0x12 L1AR L1A3 L1A2 L1A1 L1A0 L1R3 L1R2 L1R1 L1R0

0x13 L1ATRT L1AT3 L1AT2 L1AT1 L1AT0 L1RT3 L1RT2 L1RT1 L1RT0

0x14 L2AR L2A3 L2A2 L2A1 L2A0 L2R3 L2R2 L2R1 L2R0

0x15 L2ATRT L2AT3 L2AT2 L2AT1 L2AT0 L2RT3 L2RT2 L2RT1 L2RT0

0x16 CFADDR Reserved Reserved CFA[5:0]

0x17 B1CF1 C1B[23:16]

0x18 B1CF2 C1B[15:8]

0x19 B1CF3 C1B[7:0]

0x1A B2CF1 C2B[23:16]

0x1B B2CF2 C2B[15:8]

0x1C B2CF3 C2B[7:0]

0x1D A1CF1 C3B[23:16]

0x1E A1CF2 C3B[15:8]

STA339BWS Register description

Doc ID 15276 Rev 5 23/76

0x1F A1CF3 C3B[7:0]

0x20 A2CF1 C4B[23:16]

0x21 A2CF2 C4B[15:8]

0x22 A2CF3 C4B[7:0]

0x23 B0CF1 C5B[23:16]

0x24 B0CF2 C5B[15:8]

0x25 B0CF3 C5B[7:0]

0x26 CFUD Reserved RA R1 WA W1

0x27 MPCC1 MPCC[15:8]

0x28 MPCC2 MPCC[7:0]

0x29 DCC1 DCC[15:8]

0x2A DCC2 DCC[7:0]

0x2B FDRC1 FDRC[15:8]

0x2C FDRC2 FDRC[7:0]

0x2D STATUS PLLUL FAULT UVFAULT Reserved OCFAULT OCWARN TFAULT TWARN

0x2E Reserved Reserved

0x2F Reserved Reserved

0x30 Reserved Reserved

0x31 EQCFG XOB Reserved Reserved AMGC[3:2] Reserved SEL[1:0]

0x32 EATH1 EATHEN1 EATH1[6:0]

0x33 ERTH1 ERTHEN1 ERTH1[6:0]

0x34 EATH2 EATHEN2 EATH2[6:0]

0x35 ERTH2 ERTHEN2 ERTH2[6:0]

0x36 CONFX MDRC[1:0] PS48DB XAR1 XAR2 BQ5 BQ6 BQ7

0x37 SVCA Reserved Reserved SVUPE SVUP[4:0]

0x38 SVCB Reserved Reserved SVDWE SVDW[4:0]

0x39 RMS0A R_C0[23:16]

0x3A RMS0B R_C0[15:8]

0x3B RMS0C R_C0[7:0]

0x3C RMS1A R_C1[23:16]

0x3D RMS1B R_C1[15:8]

0x3E RMS1C R_C1[7:0]

Table 8. Register summary (continued)

Addr Name D7 D6 D5 D4 D3 D2 D1 D0

24/76 Doc ID 15276 Rev 5

6.1 Configuration registers (addr 0x00 to 0x05)

6.1.1 Configuration register A (addr 0x00)

Master clock select

The STA339BWS supports sample rates of 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz,

176.4 kHz, and 192 kHz. Therefore the internal clock is:

●32.768 MHz for 32 kHz

●45.1584 MHz for 44.1 kHz, 88.2 kHz, and 176.4 kHz

●49.152 MHz for 48 kHz, 96 kHz, and 192 kHz

The external clock frequency provided to the XTI pin must be a multiple of the input sample

frequency (fs).

The relationship between the input clock and the input sample rate is determined by both

the MCSx and the IR (input rate) register bits. The MCSx bits determine the PLL factor

generating the internal clock and the IR bit determines the oversampling ratio used

internally.

Interpolation ratio select

D7 D6 D5 D4 D3 D2 D1 D0

FDRB TWAB TWRB IR1 IR0 MCS2 MCS1 MCS0

01100011

Table 9. Master clock select

Bit R/W RST Name Description

0R/W1 MCS0

Selects the ratio between the input I2S sample

frequency and the input clock.

1R/W1 MCS1

2R/W0 MCS2

Table 10. Input sampling rates

Input sample rate

fs (kHz) IR MCS[2:0]

101 100 011 010 001 000

32, 44.1, 48 00 576 * fs 128 * fs 256 * fs 384 * fs 512 * fs 768 * fs

88.2, 96 01 NA 64 * fs 128 * fs 192 * fs 256 * fs 384 * fs

176.4, 192 1X NA 32 * fs 64 * fs 96 * fs 128 * fs 192 * fs

Table 11. Internal interpolation ratio

Bit R/W RST Name Description

4:3 R/W 00 IR [1:0] Selects internal interpolation ratio based on input I2S

sample frequency

STA339BWS Register description

Doc ID 15276 Rev 5 25/76

The STA339BWS has variable interpolation (oversampling) settings such that internal

processing and FFX output rates remain consistent. The first processing block interpolates

by either 2-times or 1-time (pass-through) or provides a 2-times downsample. The

oversampling ratio of this interpolation is determined by the IR bits.

Thermal warning recovery bypass

This bit sets the behavior of the IC after a thermal warning disappears. If TWRB is enabled

the device automatically restores the normal gain and output limiting is no longer active. If it

is disabled the device keeps the output limit active until a reset is asserted or until TWRB set

to 0. This bit works in conjunction with TWAB

Thermal warning adjustment bypass

Bit TWAB enables automatic output limiting when a power stage thermal warning condition

persists for longer than 400ms. When the feature is active (TWAB = 0) the desired output

limiting, set through bit TWOCL (-3 dB by default) at address 0x37 in the RAM coefficients

bank, is applied. The way the limiting acts after the warning condition disappears is

controlled by bit TWRB.

Table 12. IR bit settings as a function of input sample rate

Input sample rate fs (kHz) IR 1st stage interpolation ratio

32 00 2-times oversampling

44.1 00 2-times oversampling

48 00 2-times oversampling

88.2 01 Pass-through

96 01 Pass-through

176.4 10 2-times downsampling

192 10 2-times downsampling

Table 13. Thermal warning recovery bypass

Bit R/W RST Name Description

5R/W1 TWRB 0: thermal warning recovery enabled

1: thermal warning recovery disabled

Table 14. Thermal warning adjustment bypass

Bit R/W RST Name Description

6R/W1 TWAB 0: thermal warning adjustment enabled

1: thermal warning adjustment disabled

26/76 Doc ID 15276 Rev 5

Fault detect recovery bypass

The on-chip power block provides feedback to the digital controller which is used to indicate

a fault condition (either overcurrent or thermal). When fault is asserted, the power control

block attempts a recovery from the fault by asserting the 3-state output, holding it for period

of time in the range of 0.1 ms to 1 second, as defined by the fault-detect recovery constant

sequence is repeated as log as the fault indication exists. This feature is enabled by default

but can be bypassed by setting the FDRB control bit to 1. The fault condition is also

asserted by a low-state pulse of the normally high INT_LINE output pin.

6.1.2 Configuration register B (addr 0x01)

Serial audio input interface format

Serial data interface

The STA339BWS audio serial input interfaces with standard digital audio components and

accepts a number of serial data formats. STA339BWS always acts as slave when receiving

audio input from standard digital audio components. Serial data for two channels is provided

using three inputs: left/right clock LRCKI, serial clock BICKI, and serial data SDI.

Bits SAI and bit SAIFB are used to specify the serial data format. The default serial data

format is I2S, MSB first. Available formats are shown in the tables and figure that follow.

Serial data first bit

Table 15. Fault detect recovery bypass

Bit R/W RST Name Description

7 R/W 0 FDRB 0: fault detect recovery enabled

1: fault detect recovery disabled

D7 D6 D5 D4 D3 D2 D1 D0

C2IM C1IM DSCKE SAIFB SAI3 SAI2 SAI1 SAI0

10000000

Table 16. Serial audio input interface

Bit R/W RST Name Description

0R/W0 SAI0

Determines the interface format of the input serial

digital audio interface.

1R/W0 SAI1

2R/W0 SAI2

3R/W0 SAI3

Table 17. Serial data first bit

SAIFB Format

0 MSB-first

1 LSB-first

STA339BWS Register description

Doc ID 15276 Rev 5 27/76

Table 18. Support serial audio input formats for MSB-first (SAIFB = 0)

BICKI SAI [3:0] SAIFB Interface format

32 * fs 0000 0 I2S 15-bit data

0001 0 Left/right-justified 16-bit data

48 * fs

0000 0 I2S 16 to 23-bit data

0001 0 Left-justified 16 to 24-bit data

0010 0 Right-justified 24-bit data

0110 0 Right-justified 20-bit data

1010 0 Right-justified 18-bit data

1110 0 Right-justified 16-bit data

64 * fs

0000 0 I2S 16 to 24-bit data

0001 0 Left-justified 16 to 24-bit data

0010 0 Right-justified 24-bit data

0110 0 Right-justified 20-bit data

1010 0 Right-justified 18-bit data

1110 0 Right-justified 16-bit data

Table 19. Supported serial audio input formats for LSB-first (SAIFB = 1)

BICKI SAI [3:0] SAIFB Interface Format

32 * fs 1100 1 I2S 15-bit data

1110 1 Left/right-justified 16-bit data

48 * fs

0100 1 I2S 23-bit data

0100 1 I2S 20-bit data

1000 1 I2S 18-bit data

1100 1 LSB first I2S 16-bit data

0001 1 Left-justified 24-bit data

0101 1 Left-justified 20-bit data

1001 1 Left-justified 18-bit data

1101 1 Left-justified 16-bit data

0010 1 Right-justified 24-bit data

0110 1 Right-justified 20-bit data

1010 1 Right-justified 18-bit data

1110 1 Right-justified 16-bit data

28/76 Doc ID 15276 Rev 5

To make the STA339BWS work properly, the serial audio interface LRCKI clock must be

synchronous to the PLL output clock. It means that:

■N-4< = (frequency of PLL clock) / (frequency of LRCKI) = < N+4 cycles,

where N depends on the settings in Table 12 on page 25

■the PLL must be locked.

If these two conditions are not met, and IDE bit (register 0x05, bit 2) is set to 1, the

STA339BWS immediately mutes the I2S PCM data out (provided to the processing block)

and it freezes any active processing task.

Clock desyncronization can happen during STA339BWS operation because of source

switching or TV channel change. To avoid audio side effects, like click or pop noise, it is

strongly recommended to complete the following actions:

1. soft volume change

2. I2C read /write instructions

while the serial audio interface and the internal PLL are still synchronous.

Delay serial clock enable

64 * fs

0000 1 I2S 24-bit data

0100 1 I2S 20-bit data

1000 1 I2S 18-bit data

1100 1 LSB first I2S 16-bit data

0001 1 Left-justified 24-bit data

0101 1 Left-justified 20-bit data

1001 1 Left-justified 18-bit data

1101 1 Left-justified 16-bit data

0010 1 Right-justified 24-bit data

0110 1 Right-justified 20-bit data

1010 1 Right-justified 18-bit data

1110 1 Right-justified 16-bit data

Table 20. Delay serial clock enable

Bit R/W RST Name Description

5 R/W 0 DSCKE

0: no serial clock delay

1: serial clock delay by 1 core clock cycle to tolerate

anomalies in some I2S master devices

Table 19. Supported serial audio input formats for LSB-first (SAIFB = 1) (continued)

BICKI SAI [3:0] SAIFB Interface Format

STA339BWS Register description

Doc ID 15276 Rev 5 29/76

Channel input mapping

Each channel received via I2S can be mapped to any internal processing channel via the

Channel Input Mapping registers. This allows for flexibility in processing. The default

settings of these registers maps each I2S input channel to its corresponding processing

channel.

6.1.3 Configuration register C (addr 0x02)

FFX power output mode

The FFX power output mode selects how the FFX output timing is configured.

Different power devices use different output modes.

FFX compensating pulse size register

Table 21. Channel input mapping

Bit R/W RST Name Description

6R/W0 C1IM 0: processing channel 1 receives left I2S Input

1: processing channel 1 receives right I2S Input

7R/W1 C2IM 0: processing channel 2 receives left I2S Input

1: processing channel 2 receives right I2S Input

D7 D6 D5 D4 D3 D2 D1 D0

OCRB Reserved CSZ3 CSZ2 CSZ1 CSZ0 OM1 OM0

10010111

Table 22. FFX power output mode

Bit R/W RST Name Description

0 R/W 1 OM0 Selects configuration of FFX output:

00: drop compensation

01: discrete output stage: tapered compensation

10: full-power mode

11: variable drop compensation (CSZx bits)

1R/W1 OM1

Table 23. FFX compensating pulse size bits

Bit R/W RST Name Description

2R/W1 CSZ0

When OM[1,0] = 11, this register determines the

size of the FFX compensating pulse from 0 clock

ticks to 15 clock periods.

3R/W1 CSZ1

4R/W1 CSZ2

5R/W0 CSZ3

30/76 Doc ID 15276 Rev 5

Overcurrent warning adjustment bypass

The OCRB is used to indicate how STA339BWS behaves when an overcurrent warning

condition occurs. If OCRB = 0 and the overcurrent condition happens, the power control

block forces an adjustment to the modulation limit (default is -3 dB) in an attempt to

eliminate the overcurrent warning condition. Once the overcurrent warning clipping

adjustment is applied, it remains in this state until reset is applied or OCRB is set to 1. The

level of adjustment can be changed via the TWOCL (thermal warning/overcurrent limit)

setting at address 0x37 of the user defined coefficient RAM (Section 6.7.7 on page 57). The

OCRB can be enabled when the output bridge is already on.

6.1.4 Configuration register D (addr 0x03)

High-pass filter bypass

The STA339BWS features an internal digital high-pass filter for the purpose of AC coupling.

The purpose of this filter is to prevent DC signals from passing through a FFX amplifier. DC

signals can cause speaker damage. When HPB = 0, this filter is enabled.

Table 24. Compensating pulse size

CSZ[3:0] Compensating pulse size

0000 0 ns (0 tick) compensating pulse size

0001 20 ns (1 tick) clock period compensating pulse size

……

1111 300 ns (15 tick) clock period compensating pulse size

Table 25. Overcurrent warning bypass

Bit R/W RST Name Description

7 R/W 1 OCRB 0: overcurrent warning adjustment enabled

1: overcurrent warning adjustment disabled

D7 D6 D5 D4 D3 D2 D1 D0

SME ZDE DRC BQL PSL DSPB DEMP HPB

01000000

Table 26. High-pass filter bypass

Bit R/W RST Name Description

0 R/W 0 HPB 1: bypass internal AC coupling digital high-pass filter

STA339BWS Register description

Doc ID 15276 Rev 5 31/76

De-emphasis

DSP bypass

Setting the DSPB bit bypasses the EQ function of the STA339BWS.

Postscale link

Postscale functionality can be used for power-supply error correction. For multi-channel

applications running off the same power-supply, the postscale values can be linked to the

value of channel 1 for ease of use and update the values faster.

Biquad coefficient link

For ease of use, all channels can use the biquad coefficients loaded into the Channel-1

coefficient RAM space by setting the BQL bit to 1. Therefore, any EQ updates only have to

be performed once.

Dynamic range compression/anticlipping bit

Table 27. De-emphasis

Bit R/W RST Name Description

1R/W0 DEMP 0: no de-emphasis

1: enable de-emphasis on all channels

Table 28. DSP bypass

Bit R/W RST Name Description

2 R/W 0 DSPB 0: normal operation

1: bypass of biquad and bass/treble functions

Table 29. Postscale link

Bit R/W RST Name Description

3R/W0 PSL 0: each channel uses individual postscale value

1: each channel uses channel 1 postscale value

Table 30. Biquad coefficient link

Bit R/W RST Name Description

4R/W0 BQL 0: each channel uses coefficient values

1: each channel uses channel 1 coefficient values

Table 31. Dynamic range compression/anticlipping bit

Bit R/W RST Name Description

5 R/W 0 DRC 0: limiters act in anticlipping mode

1: limiters act in dynamic range compression mode

32/76 Doc ID 15276 Rev 5

Both limiters can be used in one of two ways, anticlipping or dynamic range compression.

When used in anticlipping mode the limiter threshold values are constant and dependent on

the limiter settings. In dynamic range compression mode the limiter threshold values vary

with the volume settings allowing a nighttime listening mode that provides a reduction in the

dynamic range regardless of the volume level.

Zero-detect mute enable

Setting the ZDE bit enables the zero-detect automatic mute. The zero-detect circuit looks at

the data for each processing channel at the output of the crossover (bass management)

filter. If any channel receives 2048 consecutive zero value samples (regardless of fs) then

that individual channel is muted if this function is enabled.

Submix mode enable

6.1.5 Configuration register E (addr 0x04)

Max power correction variable

Max power correction

Table 32. Zero-detect mute enable

Bit R/W RST Name Description

6R/W1 ZDE 0: automatic zero-detect mute disabled

1: automatic zero-detect mute enabled

Table 33. Submix mode enable

Bit R/W RST Name Description

7R/W0 SME 0: submix into left/right disabled

1: submix into left/right enabled

D7 D6 D5 D4 D3 D2 D1 D0

SVE ZCE DCCV PWMS AME NSBW MPC MPCV

11000010

Table 34. Max power correction variable

Bit R/W RST Name Description

0R/W0 MPCV 0: use standard MPC coefficient

1: use MPCC bits for MPC coefficient

Table 35. Max power correction

Bit R/W RST Name Description

1R/W1 MPC

0: function disabled

1: enables power bridge correction for THD

reduction near maximum power output.

STA339BWS Register description

Doc ID 15276 Rev 5 33/76

Setting the MPC bit turns on special processing that corrects the STA339BWS power device

at high power. This mode should lower the THD+N of a full FFX system at maximum power

output and slightly below. If enabled, MPC is operational in all output modes except tapered

(OM[1,0] = 01) and binary. When OCFG = 00, MPC has no effect on channels 3 and 4, the

line-out channels.

Noise-shaper bandwidth selection

AM mode enable

STA339BWS features a FFX processing mode that minimizes the amount of noise

generated in frequency range of AM radio. This mode is intended for use when FFX is

operating in a device with an AM tuner active. The SNR of the FFX processing is reduced to

approximately 83 dB in this mode, which is still greater than the SNR of AM radio.

PWM speed mode

Distortion compensation variable enable

Table 36. Noise-shaper bandwidth selection

Bit R/W RST Name Description

2 R/W 0 NSBW 1: third-order NS

0: fourth-order NS

Table 37. AM mode enable

Bit R/W RST Name Description

3R/W0 AME 0: normal FFX operation.

1: AM reduction mode FFX operation

Table 38. PWM speed mode

Bit R/W RST Name Description

4R/W0 PWMS 0: normal speed (384 kHz) all channels

1: odd speed (341.3 kHz) all channels

Table 39. Distortion compensation variable enable

Bit R/W RST Name Description

5 R/W 0 DCCV 0: use preset DC coefficient

1: use DCC coefficient

34/76 Doc ID 15276 Rev 5

Zero-crossing volume enable

The ZCE bit enables zero-crossing volume adjustments. When volume is adjusted on digital

zero-crossings no clicks are audible.

Soft volume update enable

6.1.6 Configuration register F (addr 0x05)

Output configuration

Table 40. Zero-crossing volume enable

Bit R/W RST Name Description

6R/W1 ZCE

1: volume adjustments only occur at digital zero-

crossings

0: volume adjustments occur immediately

Table 41. Soft volume update enable

Bit R/W RST Name Description

7 R/W 1 SVE

1: volume adjustments ramp according to SVUP/SVDW

settings

0: volume adjustments occur immediately

D7 D6 D5 D4 D3 D2 D1 D0

EAPD PWDN ECLE LDTE BCLE IDE OCFG1 OCFG0

01011100

Table 42. Output configuration

Bit R/W RST Name Description

0 R/W 0 OCFG0 Selects the output configuration

1 R/W 0 OCFG1

STA339BWS Register description

Doc ID 15276 Rev 5 35/76

Note: To the left of the arrow is the processing channel. When using channel output mapping, any

of the three processing channel outputs can be used for any of the three inputs.

Figure 10. OCFG = 00 (default value)

Table 43. Output configuration engine selection

OCFG[1:0] Output configuration Config pin

2 channel (full-bridge) power, 2 channel data-out:

1A/1B → 1A/1B

2A/2B → 2A/2B

LineOut1 → 3A/3B

LineOut2 → 4A/4B

Line Out Configuration determined by LOC register

2 (half-bridge), 1(full-bridge) on-board power:

1A → 1A Binary 0 °

2A → 1B Binary 90°

3A/3B → 2A/2B Binary 45°

1A/B → 3A/B Binary 0°

2A/B → 4A/B Binary 90°

2 channel (full-bridge) power, 1 channel FFX:

1A/1B → 1A/1B

2A/2B → 2A/2B

3A/3B → 3A/3B

EAPDEXT and TWARNEXT Active

1 channel mono-parallel:

3A → 1A/1B w/ C3BO 45°

3B → 2A/2B w/ C3BO 45°

1A/1B → 3A/3B

2A/2B → 4A/4B

Half

Bridge

Half

Bridge

Half

Bridge

Half

Bridge

OUT1A

OUT1B

OUT2A

OUT2B

Channel 2

Channel 1

LPF

LineOut1

OUT3B

LPF

LineOut2

OUT4B

OUT4A

OUT3A

Half

Bridge

Half

Bridge

Half

Bridge

Half

Bridge

OUT1A

OUT1B

OUT2A

OUT2B

Channel 2

Channel 1

LPF

LineOut1

OUT3B

LPF

LineOut2

OUT4B

OUT4A

OUT3A

36/76 Doc ID 15276 Rev 5

Figure 11. OCFG = 01

Figure 12. OCFG = 10

Figure 13. OCFG = 11

The STA339BWS can be configured to support different output configurations. For each

PWM output channel a PWM slot is defined. A PWM slot is always 1 / (8 * fs) seconds

length. The PWM slot define the maximum extension for PWM rise and fall edge, that is,

rising edge as far as the falling edge cannot range outside PWM slot boundaries.

Half

Bridge

Half

Bridge

Half

Bridge

Half

Bridge

OUT1A

OUT1B

OUT2A

OUT2B

Channel 3

Channel 1

Channel 2

Half

Bridge

Half

Bridge

Half

Bridge

Half

Bridge

OUT1A

OUT1B

OUT2A

OUT2B

Channel 3

Channel 1

Channel 2

Half

Bridge

Half

Bridge

Half

Bridge

Half

Bridge

OUT1A

OUT1B

OUT2A

OUT2B

Channel 2

Channel 1

Power

Device

OUT3B

OUT3A

EAPD

Channel 3

Half

Bridge

Half

Bridge

Half

Bridge

Half

Bridge

OUT1A

OUT1B

OUT2A

OUT2B

Channel 2

Channel 1

Power

Device

OUT3B

OUT3A

EAPD

Channel 3

Half

Bridge

Half

Bridge

Half

Bridge

Half

Bridge

OUT1A

OUT1B

OUT2A

OUT2B

Channel 3

OUT3B

OUT4B

OUT4A

OUT3A Channel 1

Channel 2

Half

Bridge

Half

Bridge

Half

Bridge

Half

Bridge

OUT1A

OUT1B

OUT2A

OUT2B

Channel 3

OUT3B

OUT4B

OUT4A

OUT3A Channel 1

Channel 2

STA339BWS Register description

Doc ID 15276 Rev 5 37/76

Figure 14. Output mapping scheme

For each configuration the PWM signals from the digital driver are mapped in different ways

to the power stage:

FFX ™

modulator

REMAP

FFX1A

FFX1 B

FFX2 A

FFX 2B

OUT1A

OUT1B

OUT2A

OUT2B

Power

Bridge

OUT1A

OUT1B

OUT2A

OUT2B

FFX3 A

FFX3B

FFX4 A

FFX 4B

OUT3A

OUT3B

OUT4A

OUT4B

FFX ™

modulator

REMAP

FFX1A

FFX1 B

FFX2 A

FFX 2B

OUT1A

OUT1B

OUT2A

OUT2B

Power

Bridge

OUT1A

OUT1B

OUT2A

OUT2B

FFX3 A

FFX3B

FFX4 A

FFX 4B

OUT3A

OUT3B

OUT4A

OUT4B

FFX ™

modulator

REMAP

FFX1A

FFX1 B

FFX2 A

FFX 2B

OUT1A

OUT1B

OUT2A

OUT2B

Power

Bridge

OUT1A

OUT1B

OUT2A

OUT2B

FFX3 A

FFX3B

FFX4 A

FFX 4B

OUT3A

OUT3B

OUT4A

OUT4B

FFX ™

modulator

REMAP

FFX1A

FFX1 B

FFX2 A

FFX 2B

OUT1A

OUT1B

OUT2A

OUT2B

Power

Bridge

OUT1A

OUT1B

OUT2A

OUT2B

FFX3 A

FFX3B

FFX4 A

FFX ™

modulator

REMAP

FFX1A

FFX1 B

FFX2 A

FFX 2B

OUT1A

OUT1B

OUT2A

OUT2B

Power

Bridge

OUT1A

OUT1B

OUT2A

OUT2B

FFX3 A

FFX3B

FFX4 A

FFX 4B

OUT3A

OUT3B

OUT4A

OUT4B

FFX ™

modulator

REMAP

FFX1A

FFX1 B

FFX2 A

FFX 2B

OUT1A

OUT1B

OUT2A

OUT2B

Power

Bridge

OUT1A

OUT1B

OUT2A

OUT2B

FFX3 A

FFX3B

FFX4 A

FFX 4B

OUT3A

OUT3B

OUT4A

OUT4B

38/76 Doc ID 15276 Rev 5

2.0 channels, two full-bridges (OCFG = 00)

Mapping:

●FFX1A -> OUT1A

●FFX1B -> OUT1B

●FFX2A -> OUT2A

●FFX2B -> OUT2B

●FFX3A -> OUT3A

●FFX3B -> OUT3B

●FFX4A -> OUT4A

●FFX4B -> OUT4B

Default modulation:

●FFX1A/1B configured as ternary

●FFX2A/2B configured as ternary

●FFX3A/3B configured as lineout ternary

●FFX4A/4B configured as lineout ternary

On channel 3 line out (LOC bits = 00) the same data as channel 1 processing is sent. On

channel 4 line out (LOC bits = 00) the same data as channel 2 processing is sent. In this

configuration, volume control or EQ have no effect on channels 3 and 4.

In this configuration the PWM slot phase is the following as shown in Figure 15.

Figure 15. 2.0 channels (OCFG = 00) PWM slots

OUT1A

OUT1B

OUT2A

OUT2B

OUT3A

OUT3B

OUT4A

OUT4B

OUT1A

OUT1B

OUT2A

OUT2B

OUT3A

OUT3B

OUT4A

OUT4B

STA339BWS Register description

Doc ID 15276 Rev 5 39/76

2.1 channels, two half-bridges + one full-bridge (OCFG = 01)

Mapping:

●FFX1A -> OUT1A

●FFX2A -> OUT1B

●FFX3A -> OUT2A

●FFX3B -> OUT2B

●FFX1A -> OUT3A

●FFX1B -> OUT3B

●FFX2A -> OUT4A

●FFX2B -> OUT4B

Modulation:

●FFX1A/1B configured as binary

●FFX2A/2B configured as binary

●FFX3A/3B configured as binary

●FFX4A/4B configured as binary

In this configuration, channel 3 has full control (volume, EQ, etc…). On OUT3/OUT4

channels the channel 1 and channel 2 PWM are replicated.

In this configuration the PWM slot phase is the following as shown in Figure 16.

Figure 16. 2.1 channels (OCFG = 01) PWM slots

OUT1A

OUT2A

OUT2B

OUT3A

OUT3B

OUT1B

OUT4A

OUT4B

OUT1A

OUT2A

OUT2B

OUT3A

OUT3B

OUT1B

OUT4A

OUT4B

OUT1A

OUT2A

OUT2B

OUT3A

OUT3B

OUT1B

OUT4A

OUT4B

OUT1A

OUT2A

OUT2B

OUT3A

OUT3B

OUT1B

OUT1A

OUT2A

OUT2B

OUT3A

OUT3B

OUT1B

OUT4A

OUT4B

OUT1A

OUT2A

OUT2B

OUT3A

OUT3B

OUT1B

OUT4A

OUT4B

40/76 Doc ID 15276 Rev 5

2.1 channels, two full-bridges + one external full-bridge (OCFG = 10)

Mapping:

●FFX1A -> OUT1A

●FFX1B -> OUT1B

●FFX2A -> OUT2A

●FFX2B -> OUT2B

●FFX3A -> OUT3A

●FFX3B -> OUT3B

●EAPD -> OUT4A

●TWARN -> OUT4B

Default modulation:

●FFX1A/1B configured as ternary

●FFX2A/2B configured as ternary

●FFX3A/3B configured as ternary

●FFX4A/4B is not used

In this configuration, channel 3 has full control (volume, EQ, etc…). On OUT4 channel the

external bridge control signals are multiplexed.

In this configuration the PWM slot phase is the following as shown in Figure 17.

Figure 17. 2.1 channels (OCFG = 10) PWM slots

OUT1A

OUT1B

OUT2A

OUT2B

OUT3A

OUT3B

OUT1A

OUT1B

OUT2A

OUT2B

OUT3A

OUT3B

OUT1A

OUT1B

OUT2A

OUT2B

OUT3A

OUT3B

OUT1A

OUT1B

OUT2A

OUT2B

OUT3A

OUT3B

STA339BWS Register description

Doc ID 15276 Rev 5 41/76

Invalid input detect mute enable

Setting the IDE bit enables this function, which looks at the input I2S data and automatically

mutes if the signals are perceived as invalid.

Binary output mode clock loss detection

Detects loss of input MCLK in binary mode and will output 50% duty cycle.

LRCK double trigger protection

LDTE, when enabled, prevents double trigger of LRCLK on instable I2S input.

Auto EAPD on clock loss

When active, issues a power device power down signal (EAPD) on clock loss detection.

IC power down

Table 44. Invalid input detect mute enable

Bit R/W RST Name Description

2R/W1 IDE 0: disables the automatic invalid input detect mute

1: enables the automatic invalid input detect mute

Table 45. Binary output mode clock loss detection

Bit R/W RST Name Description

3R/W1 BCLE 0: binary output mode clock loss detection disabled

1: binary output mode clock loss detection enable

Table 46. LRCK double trigger protection

Bit R/W RST Name Description

4R/W1 LDTE 0: LRCLK double trigger protection disabled

1: LRCLK double trigger protection enabled

Table 47. Auto EAPD on clock loss

Bit R/W RST Name Description

5R/W0 ECLE 0: auto EAPD on clock loss not enabled

1: auto EAPD on clock loss

Table 48. IC power down

Bit R/W RST Name Description

6R/W1 PWDN 0: IC power down low-power condition

1: IC normal operation

42/76 Doc ID 15276 Rev 5

The PWDN register is used to place the IC in a low-power state. When PWDN is written

as 0, the output begins a soft-mute. After the mute condition is reached, EAPD is asserted

to power down the power-stage, then the master clock to all internal hardware expect the

I2C block is gated. This places the IC in a very low power consumption state.

External amplifier power down

The EAPD register directly disables/enables the internal power circuitry.

When EAPD = 0, the internal power section is placed in a low-power state (disabled). This

6.2 Volume control registers (addr 0x06 - 0x0A)

The volume structure of the STA339BWS consists of individual volume registers for each

channel and a master volume register that provides an offset to each channels volume

setting. The individual channel volumes are adjustable in 0.5 dB steps from +48 dB

to -80 dB.

As an example if C3VOL = 0x00 or +48 dB and MVOL = 0x18 or -12 dB, then the total gain

for channel 3 = +36 dB.

The channel mutes provide a “soft mute” with the volume ramping down to mute in

4096 samples from the maximum volume setting at the internal processing rate

(approximately 96 kHz).

All changes in volume take place at zero-crossings when ZCE = 1 (Configuration register E

(addr 0x04)) on a per channel basis as this creates the smoothest possible volume

transitions. When ZCE = 0, volume updates occur immediately.

Table 49. External amplifier power down

Bit R/W RST Name Description

7R/W0 EAPD 0: external power stage power down active

1: normal operation

STA339BWS Register description

Doc ID 15276 Rev 5 43/76

6.2.1 Mute/line output configuration register (addr 0x06)

Line output is only active when OCFG = 00. In this case LOC determines the line output

configuration. The source of the line output is always the channel 1 and 2 inputs.

6.2.2 Master volume register (addr 0x07)

6.2.3 Channel 1 volume (addr 0x08)

6.2.4 Channel 2 volume (addr 0x09)

D7 D6 D5 D4 D3 D2 D1 D0

LOC1 LOC0 Reserved Reserved C3M C2M C1M Reserved

00010000

Table 50. Line output configuration

LOC[1:0] Line output configuration

00 Line output fixed - no volume, no EQ

01 Line output variable - channel 3 volume effects line output, no EQ

10 Line output variable with EQ - channel 3 volume effects line output

D7 D6 D5 D4 D3 D2 D1 D0

MVOL7 MVOL6 MVOL5 MVOL4 MVOL3 MVOL2 MVOL1 MVOL0

11111111

Table 51. Master volume offset as a function of MVOL[7:0]

MVOL[7:0] Volume offset from channel value

00000000 (0x00) 0 dB

00000001 (0x01) -0.5 dB

00000010 (0x02) -1 dB

……

01001100 (0x4C) -38 dB

……

11111110 (0xFE) -127.5 dB

11111111 (0xFF) Default mute, not to be used during operation

D7 D6 D5 D4 D3 D2 D1 D0

C1VOL7 C1VOL6 C1VOL5 C1VOL4 C1VOL3 C1VOL2 C1VOL1 C1VOL0

01100000

D7 D6 D5 D4 D3 D2 D1 D0

C2VOL7 C2VOL6 C2VOL5 C2VOL4 C2VOL3 C2VOL2 C2VOL1 C2VOL0

01100000

44/76 Doc ID 15276 Rev 5

6.2.5 Channel 3 / line output volume (addr 0x0A)

D7 D6 D5 D4 D3 D2 D1 D0

C3VOL7 C3VOL6 C3VOL5 C3VOL4 C3VOL3 C3VOL2 C3VOL1 C3VOL0

01100000

Table 52. Channel volume as a function of CxVOL[7:0]

CxVOL[7:0] Volume

00000000 (0x00) +48 dB

00000001 (0x01) +47.5 dB

00000010 (0x02) +47 dB

……

01011111 (0x5F) +0.5 dB

01100000 (0x60) 0 dB

01100001 (0x61) -0.5 dB

……

11010111 (0xD7) -59.5 dB

11011000 (0xD8) -60 dB

11011001 (0xD9) -61 dB

11011010 (0xDA) -62 dB

……

11101100 (0xEC) -80 dB

11101101 (0xED) Hard channel mute

……

11111111 (0xFF) Hard channel mute

STA339BWS Register description

Doc ID 15276 Rev 5 45/76

6.3 Audio preset registers (addr 0x0B and 0x0C)

6.3.1 Audio preset register 1 (addr 0x0B)

Using AMGC[3:0] bits, attack and release thresholds and rates are automatically configured

to properly fit application specific configurations. AMGC[3:2] is defined in register EQ

coefficients and DRC configuration register (addr 0x31) on page 64.

The AMGC[1:0] bits behave in two different ways depending on the value of AMGC[3:2].

When this value is 00 then bits AMGC[1:0] are defined below in Ta b l e 5 3 .

6.3.2 Audio preset register 2 (addr 0x0C)

AM interference frequency switching

D7 D6 D5 D4 D3 D2 D1 D0

Reserved Reserved AMGC[1] AMGC[0] Reserved Reserved Reserved Reserved

10000000

Table 53. Audio preset gain compression/limiters selection for AMGC[3:2] = 00

AMGC[1:0] Mode

00 User programmable GC

01 AC no clipping 2.1

10 AC limited clipping (10%) 2.1

11 DRC night-time listening mode 2.1

D7 D6 D5 D4 D3 D2 D1 D0

XO3 XO2 XO1 XO0 AMAM2 AMAM1 AMAM0 AMAME

00000000

Table 54. AM interference frequency switching bits

Bit R/W RST Name Description

0 R/W 0 AMAME

Audio preset AM enable

0: switching frequency determined by PWMS setting

1: switching frequency determined by AMAM settings

Table 55. Audio preset AM switching frequency selection

AMAM[2:0] 48 kHz/96 kHz input fs 44.1 kHz/88.2 kHz input fs

000 0.535 MHz - 0.720 MHz 0.535 MHz - 0.670 MHz

001 0.721 MHz - 0.900 MHz 0.671 MHz - 0.800 MHz

010 0.901 MHz - 1.100 MHz 0.801 MHz - 1.000 MHz

011 1.101 MHz - 1.300 MHz 1.001 MHz - 1.180 MHz

100 1.301 MHz - 1.480 MHz 1.181 MHz - 1.340 MHz

46/76 Doc ID 15276 Rev 5

Bass management crossover

101 1.481 MHz - 1.600 MHz 1.341 MHz - 1.500 MHz

110 1.601 MHz - 1.700 MHz 1.501 MHz - 1.700 MHz

Table 56. Bass management crossover

Bit R/W RST Name Description

4R/W0 XO0

Selects the bass-management crossover frequency.

A 1st-order hign-pass filter (channels 1 and 2) or a

2nd-order low-pass filter (channel 3) at the selected

frequency is performed.

5R/W0 XO1

6R/W0 XO2

7R/W0 XO3

Table 57. Bass management crossover frequency

XO[3:0] Crossover frequency

0000 User-defined (Section 6.7.8 on page 57)

0001 80 Hz

0010 100 Hz

0011 120 Hz

0100 140 Hz

0101 160 Hz

0110 180 Hz

0111 200 Hz

1000 220 Hz

1001 240 Hz

1010 260 Hz

1011 280 Hz

1100 300 Hz

1101 320 Hz

1110 340 Hz

1111 360 Hz

Table 55. Audio preset AM switching frequency selection (continued)

AMAM[2:0] 48 kHz/96 kHz input fs 44.1 kHz/88.2 kHz input fs

STA339BWS Register description

Doc ID 15276 Rev 5 47/76

6.4 Channel configuration registers (addr 0x0E - 0x10)

Tone control bypass

Tone control (bass/treble) can be bypassed on a per channel basis for channels 1 and 2.

EQ bypass

EQ control can be bypassed on a per channel basis for channels 1 and 2. If EQ control is

bypassed on a given channel the prescale and all filters (high-pass, biquads, de-emphasis,

bass, treble in any combination) are bypassed for that channel.

Volume bypass

Each channel contains an individual channel volume bypass. If a particular channel has

volume bypassed via the CxVBP = 1 register then only the channel volume setting for that

particular channel affects the volume setting, the master volume setting has no effect on that

channel.

D7 D6 D5 D4 D3 D2 D1 D0

C1OM1 C1OM0 C1LS1 C1LS0 C1BO C1VPB C1EQBP C1TCB

00000000

D7 D6 D5 D4 D3 D2 D1 D0

C2OM1 C2OM0 C2LS1 C2LS0 C2BO C2VPB C2EQBP C2TCB

01000000

D7 D6 D5 D4 D3 D2 D1 D0

C3OM1 C3OM0 C3LS1 C3LS0 C3BO C3VPB Reserved Reserved

10000000

Table 58. Tone control bypass

CxTCB Mode

0 Perform tone control on channel x - normal operation

1 Bypass tone control on channel x

Table 59. EQ bypass

CxEQBP Mode

0 Perform EQ on channel x - normal operation

1 Bypass EQ on channel x

Table 60. Volume bypass register

CxVBP Mode

0 Normal volume operations

1 Volume is by-passed

48/76 Doc ID 15276 Rev 5

Binary output enable registers

Each individual channel output can be set to output a binary PWM stream. In this mode

output A of a channel is considered the positive output and output B is negative inverse.

Limiter select

Limiter selection can be made on a per-channel basis according to the channel limiter select

bits. CxLS bits are not considered when dual band DRC (Section 6.13.1 on page 65) or

EQ DRC (Section 6.13.2) is used.

Output mapping

Output mapping can be performed on a per channel basis according to the CxOM channel

output mapping bits. Each input into the output configuration engine can receive data from

any of the three processing channel outputs.

Table 61. Binary output enable registers

CxBO Mode

0 FFX output operation

1 Binary output

Table 62. Channel limiter mapping as a function of CxLS bits

CxLS[1:0] Channel limiter mapping

00 Channel has limiting disabled

01 Channel is mapped to limiter #1

10 Channel is mapped to limiter #2

Table 63. Channel output mapping as a function of CxOM bits

CxOM[1:0] Channel x output source from

00 Channel1

01 Channel 2

10 Channel 3

STA339BWS Register description

Doc ID 15276 Rev 5 49/76

6.5 Tone control register (addr 0x11)

Tone control

6.6 Dynamic control registers (addr 0x12 - 0x15)

6.6.1 Limiter 1 attack/release rate (addr 0x12)

6.6.2 Limiter 1 attack/release threshold (addr 0x13)

D7 D6 D5 D4 D3 D2 D1 D0

TTC3 TTC2 TTC1 TTC0 BTC3 BTC2 BTC1 BTC0

01110111

Table 64. Tone control boost/cut as a function of BTC and TTC bits

BTC[3:0]/TTC[3:0] Boost/Cut

0000 -12 dB

0001 -12 dB

0010 -10 dB

……

0101 -4 dB

0110 -2 dB

0111 0 dB

1000 +2 dB

1001 +4 dB

……

1100 +10 dB

1101 +12 dB

1110 +12 dB

1111 +12 dB

D7 D6 D5 D4 D3 D2 D1 D0

L1A3 L1A2 L1A1 L1A0 L1R3 L1R2 L1R1 L1R0

01101010

D7 D6 D5 D4 D3 D2 D1 D0

L1AT3 L1AT2 L1AT1 L1AT0 L1RT3 L1RT2 L1RT1 L1RT0

01101001

50/76 Doc ID 15276 Rev 5

6.6.3 Limiter 2 attack/release rate (addr 0x14)

6.6.4 Limiter 2 attack/release threshold (addr 0x15)

6.6.5 Description

The STA339BWS includes two independent limiter blocks. The purpose of the limiters is to

automatically reduce the dynamic range of a recording to prevent the outputs from clipping

in anticlipping mode or to actively reduce the dynamic range for a better listening

environment such as a night-time listening mode which is often needed for DVDs. The two

modes are selected via the DRC bit in Configuration register E (addr 0x04) on page 32.

Each channel can be mapped to either limiter or not mapped, meaning that channel will clip

when 0 dBFS is exceeded. Each limiter looks at the present value of each channel that is

mapped to it, selects the maximum absolute value of all these channels, performs the

limiting algorithm on that value, and then if needed adjusts the gain of the mapped channels

in unison.

Figure 18. Basic limiter and volume flow diagram

The limiter attack thresholds are determined by the LxAT registers if EATHx[7] bits are set

to 0 else the thresholds are determined by EATHx[6:0]. It is recommended in anticlipping

mode to set this to 0 dBFS, which corresponds to the maximum unclipped output power of a

FFX amplifier. Since gain can be added digitally within the STA339BWS it is possible to

exceed 0 dBFS or any other LxAT setting, when this occurs, the limiter, when active,

automatically starts reducing the gain. The rate at which the gain is reduced when the attack

threshold is exceeded is dependent upon the attack rate register setting for that limiter. Gain

reduction occurs on a peak-detect algorithm. Setting EATHx[7] bits to 1 selects the

anticlipping mode.

The limiter release thresholds are determined by the LxRT registers if ERTHx[7] bits are set

to 0 else the thresholds are determined by ERTHx[6:0]. Settings to 1 ERTHx[7] bits the

anticlipping mode is selected automatically. The release of limiter, when the gain is again

increased, is dependent on a RMS-detect algorithm. The output of the volume/limiter block

is passed through a RMS filter. The output of this filter is compared to the release threshold,

determined by the Release Threshold register. When the RMS filter output falls below the

D7 D6 D5 D4 D3 D2 D1 D0

L2A3 L2A2 L2A1 L2A0 L2R3 L2R2 L2R1 L2R0

01101010

D7 D6 D5 D4 D3 D2 D1 D0

L2AT3 L2AT2 L2AT1 L2AT0 L2RT3 L2RT2 L2RT1 L2RT0

01101001

ATTENUATION SATURATION

RMS

LIMITER

GAIN

GAIN / VOLUME

INPUT OUTPUT

ATTENUATION SATURATION

RMS

LIMITER

GAIN

GAIN / VOLUME

INPUT OUTPUT

STA339BWS Register description

Doc ID 15276 Rev 5 51/76

release threshold, the gain is again increased at a rate dependent upon the Release Rate

occurs if the limiter has already reduced the gain. The release threshold value can be used

to set what is effectively a minimum dynamic range, this is helpful as over limiting can

reduce the dynamic range to virtually zero and cause program material to sound “lifeless”.

In AC mode, the attack and release thresholds are set relative to full-scale. In DRC mode,

the attack threshold is set relative to the maximum volume setting of the channels mapped

to that limiter and the release threshold is set relative to the maximum volume setting plus

the attack threshold.

Table 65. Limiter attack rate vs LxA bits

LxA[3:0] Attack Rate dB/ms

0000 3.1584

Fast

Slow

0001 2.7072

0010 2.2560

0011 1.8048

0100 1.3536

0101 0.9024

0110 0.4512

0111 0.2256

1000 0.1504

1001 0.1123

1010 0.0902

1011 0.0752

1100 0.0645

1101 0.0564

1110 0.0501

1111 0.0451

52/76 Doc ID 15276 Rev 5

Anticlipping mode

Table 66. Limiter release rate vs LxR bits

LxR[3:0] Release Rate dB/ms

0000 0.5116

Fast

Slow

0001 0.1370

0010 0.0744

0011 0.0499

0100 0.0360

0101 0.0299

0110 0.0264

0111 0.0208

1000 0.0198

1001 0.0172

1010 0.0147

1011 0.0137

1100 0.0134

1101 0.0117

1110 0.0110

1111 0.0104

Table 67. Limiter attack threshold vs LxAT bits (AC mode)

LxAT[3:0] AC (dB relative to fs)

0000 -12

0001 -10

0010 -8

0011 -6

0100 -4

0101 -2

0110 0

0111 +2

1000 +3

1001 +4

1010 +5

1011 +6

1100 +7

1101 +8

STA339BWS Register description

Doc ID 15276 Rev 5 53/76

Dynamic range compression mode

1110 +9

1111 +10

Table 68. Limiter release threshold vs LxRT bits (AC mode)

LxRT[3:0] AC (dB relative to fs)

0000 -∞

0001 -29

0010 -20

0011 -16

0100 -14

0101 -12

0110 -10

0111 -8

1000 -7

1001 -6

1010 -5

1011 -4

1100 -3

1101 -2

1110 -1

1111 -0

Table 69. Limiter attack threshold vs LxAT bits (DRC mode)

LxAT[3:0] DRC (dB relative to Volume)

0000 -31

0001 -29

0010 -27

0011 -25

0100 -23

0101 -21

0110 -19

0111 -17

1000 -16

Table 67. Limiter attack threshold vs LxAT bits (AC mode) (continued)

LxAT[3:0] AC (dB relative to fs)

54/76 Doc ID 15276 Rev 5

6.6.6 Limiter 1 extended attack threshold (addr 0x32)

The extended attack threshold value is determined as follows:

attack threshold = -12 + EATH1 / 4

1001 -15

1010 -14

1011 -13

1100 -12

1101 -10

1110 -7

1111 -4

Table 70. Limiter release threshold vs LxRT bits (DRC mode)

LxRT[3:0] DRC (db relative to Volume + LxAT)

0000 -∞

0001 -38

0010 -36

0011 -33

0100 -31

0101 -30

0110 -28

0111 -26

1000 -24

1001 -22

1010 -20

1011 -18

1100 -15

1101 -12

1110 -9

1111 -6

Table 69. Limiter attack threshold vs LxAT bits (DRC mode) (continued)

LxAT[3:0] DRC (dB relative to Volume)

D7 D6 D5 D4 D3 D2 D1 D0

EATHEN1 EATH1[6] EATH1[5] EATH1[4] EATH1[3] EATH1[2] EATH1[1] EATH1[0]

00110000

STA339BWS Register description

Doc ID 15276 Rev 5 55/76

6.6.7 Limiter 1 extended release threshold (addr 0x33)

The extended release threshold value is determined as follows:

release threshold = -12 + ERTH1 / 4

6.6.8 Limiter 2 extended attack threshold (addr 0x34)

The extended attack threshold value is determined as follows:

attack threshold = -12 + EATH2 / 4

6.6.9 Limiter 2 extended release threshold (addr 0x35)

The extended release threshold value is determined as follows:

release threshold = -12 + ERTH2 / 4

Note: Attack/release threshold step is 0.125 dB in the range -12 dB and 0 dB.

6.7 User-defined coefficient control registers (addr 0x16 - 0x26)

6.7.1 Coefficient address register (addr 0x16)

6.7.2 Coefficient b1 data register bits (addr 0x17 - 0x19)

D7 D6 D5 D4 D3 D2 D1 D0

ERTHEN1 ERTH1[6] ERTH1[5] ERTH1[4] ERTH1[3] ERTH1[2] ERTH1[1] ERTH1[0]

00110000

D7 D6 D5 D4 D3 D2 D1 D0

EATHEN2 EATH2[6] EATH2[5] EATH2[4] EATH2[3] EATH2[2] EATH2[1] EATH2[0]

00110000

D7 D6 D5 D4 D3 D2 D1 D0

ERTHEN2 ERTH2[6] ERTH2[5] ERTH2[4] ERTH2[3] ERTH2[2] ERTH2[1] ERTH2[0]

00110000

D7 D6 D5 D4 D3 D2 D1 D0

Reserved Reserved CFA5 CFA4 CFA3 CFA2 CFA1 CFA0

00000000

D7 D6 D5 D4 D3 D2 D1 D0

C1B23 C1B22 C1B21 C1B20 C1B19 C1B18 C1B17 C1B16

00000000

D7 D6 D5 D4 D3 D2 D1 D0

C1B15 C1B14 C1B13 C1B12 C1B11 C1B10 C1B9 C1B8

00000000

56/76 Doc ID 15276 Rev 5

6.7.3 Coefficient b2 data register bits (addr 0x1A - 0x1C)

6.7.4 Coefficient a1 data register bits (addr 0x1D - 0x1F)

6.7.5 Coefficient a2 data register bits (addr 0x20 - 0x22)

D7 D6 D5 D4 D3 D2 D1 D0

C1B7 C1B6 C1B5 C1B4 C1B3 C1B2 C1B1 C1B0

00000000

D7 D6 D5 D4 D3 D2 D1 D0

C2B23 C2B22 C2B21 C2B20 C2B19 C2B18 C2B17 C2B16

00000000

D7 D6 D5 D4 D3 D2 D1 D0

C2B15 C2B14 C2B13 C2B12 C2B11 C2B10 C2B9 C2B8

00000000

D7 D6 D5 D4 D3 D2 D1 D0

C2B7 C2B6 C2B5 C2B4 C2B3 C2B2 C2B1 C2B0

00000000

D7 D6 D5 D4 D3 D2 D1 D0

C3B23 C3B22 C3B21 C3B20 C3B19 C3B18 C3B17 C3B16

00000000

D7 D6 D5 D4 D3 D2 D1 D0

C3B15 C3B14 C3B13 C3B12 C3B11 C3B10 C3B9 C3B8

00000000

D7 D6 D5 D4 D3 D2 D1 D0

C3B7 C3B6 C3B5 C3B4 C3B3 C3B2 C3B1 C3B0

00000000

D7 D6 D5 D4 D3 D2 D1 D0

C4B23 C4B22 C4B21 C4B20 C4B19 C4B18 C4B17 C4B16

00000000

D7 D6 D5 D4 D3 D2 D1 D0

C4B15 C4B14 C4B13 C4B12 C4B11 C4B10 C4B9 C4B8

00000000

D7 D6 D5 D4 D3 D2 D1 D0

C4B7 C4B6 C4B5 C4B4 C4B3 C4B2 C4B1 C4B0

00000000

STA339BWS Register description

Doc ID 15276 Rev 5 57/76

6.7.6 Coefficient b0 data register bits (addr 0x23 - 0x25)

6.7.7 Coefficient read/write control register (addr 0x26)

6.7.8 Description

Coefficients for user-defined EQ, mixing, scaling, and bass management are handled

internally in the STA339BWS via RAM. Access to this RAM is available to the user via an

I2C register interface. A collection of I2C registers are dedicated to this function. One

contains a coefficient base address, five sets of three store the values of the 24-bit

coefficients to be written or that were read, and one contains bits used to control the

write/read of the coefficient(s) to/from RAM.

Three different RAM banks are embedded in STA339BWS. The three banks are managed in

paging mode using EQCFG register bits. They can be used to store different EQ settings.

For speaker frequency compensation, a sampling frequency independent EQ must be

implemented. Computing three different coefficients set for 32 kHz, 44.1kHz, 48 kHz and

downloading them into the three RAM banks, it is possible to select the suitable RAM block

depending from the incoming frequency with a simple I2C write operation on register 0x31.

For example, in case of different input sources (different sampling rates), the three different

sets of coefficients can be downloaded once at the start up, and during the normal play it is

possible to switch among the three RAM blocks allowing a faster operation, without any

additional download from the microcontroller.

To write the coefficients in a particular RAM bank, this bank must be selected first writing

bit 0 and bit 1 in register 0x31. Then the write procedure below can be used.

Note that as soon as a RAM bank is selected, the EQ settings are automatically switched to

the coefficients stored in the active RAM block.

Note: The read and write operation on RAM coefficients works only if LRCKI (pin 29) is switching.

D7 D6 D5 D4 D3 D2 D1 D0

C5B23 C5B22 C5B21 C5B20 C5B19 C5B18 C5B17 C5B16

00000000

D7 D6 D5 D4 D3 D2 D1 D0

C5B15 C5B14 C5B13 C5B12 C5B11 C5B10 C5B9 C5B8

00000000

D7 D6 D5 D4 D3 D2 D1 D0

C5B7 C5B6 C5B5 C5B4 C5B3 C5B2 C5B1 C5B0

00000000

D7 D6 D5 D4 D3 D2 D1 D0

Reserved RA R1 WA W1

0 0000

58/76 Doc ID 15276 Rev 5

Reading a coefficient from RAM

1. Select the RAM block with register 0x31 bit1, bit0.

2. Write 6-bits of address to I2C register 0x16.

3. Write 1 to R1 bit in I2C address 0x26.

4. Read top 8-bits of coefficient in I2C address 0x17.

5. Read middle 8-bits of coefficient in I2C address 0x18.

6. Read bottom 8-bits of coefficient in I2C address 0x19.

Reading a set of coefficients from RAM

1. Select the RAM block with register 0x31 bit1, bit0.

2. Write 6-bits of address to I2C register 0x16.

3. Write 1 to RA bit in I2C address 0x26.

4. Read top 8-bits of coefficient in I2C address 0x17.

5. Read middle 8-bits of coefficient in I2C address 0x18.

6. Read bottom 8-bits of coefficient in I2C address 0x19.

7. Read top 8-bits of coefficient b2 in I2C address 0x1A.

8. Read middle 8-bits of coefficient b2 in I2C address 0x1B.

9. Read bottom 8-bits of coefficient b2 in I2C address 0x1C.

10. Read top 8-bits of coefficient a1 in I2C address 0x1D.

11. Read middle 8-bits of coefficient a1 in I2C address 0x1E.

12. Read bottom 8-bits of coefficient a1 in I2C address 0x1F.

13. Read top 8-bits of coefficient a2 in I2C address 0x20.

14. Read middle 8-bits of coefficient a2 in I2C address 0x21.

15. Read bottom 8-bits of coefficient a2 in I2C address 0x22.

16. Read top 8-bits of coefficient b0 in I2C address 0x23.

17. Read middle 8-bits of coefficient b0 in I2C address 0x24.

18. Read bottom 8-bits of coefficient b0 in I2C address 0x25.

Writing a single coefficient to RAM

1. Select the RAM block with register 0x31 bit1, bit0.

2. Write 6-bits of address to I2C register 0x16.

3. Write top 8-bits of coefficient in I2C address 0x17.

4. Write middle 8-bits of coefficient in I2C address 0x18.

5. Write bottom 8-bits of coefficient in I2C address 0x19.

6. Write 1 to W1 bit in I2C address 0x26.

STA339BWS Register description

Doc ID 15276 Rev 5 59/76

Writing a set of coefficients to RAM

1. Select the RAM block with register 0x31 bit1, bit0.

2. Write 6-bits of starting address to I2C register 0x16.

3. Write top 8-bits of coefficient b1 in I2C address 0x17.

4. Write middle 8-bits of coefficient b1 in I2C address 0x18.

5. Write bottom 8-bits of coefficient b1 in I2C address 0x19.

6. Write top 8-bits of coefficient b2 in I2C address 0x1A.

7. Write middle 8-bits of coefficient b2 in I2C address 0x1B.

8. Write bottom 8-bits of coefficient b2 in I2C address 0x1C.

9. Write top 8-bits of coefficient a1 in I2C address 0x1D.

10. Write middle 8-bits of coefficient a1 in I2C address 0x1E.

11. Write bottom 8-bits of coefficient a1 in I2C address 0x1F.

12. Write top 8-bits of coefficient a2 in I2C address 0x20.

13. Write middle 8-bits of coefficient a2 in I2C address 0x21.

14. Write bottom 8-bits of coefficient a2 in I2C address 0x22.

15. Write top 8-bits of coefficient b0 in I2C address 0x23.

16. Write middle 8-bits of coefficient b0 in I2C address 0x24.

17. Write bottom 8-bits of coefficient b0 in I2C address 0x25.

18. Write 1 to WA bit in I2C address 0x26.

The mechanism for writing a set of coefficients to RAM provides a method of updating the

five coefficients corresponding to a given biquad (filter) simultaneously to avoid possible

unpleasant acoustic side-effects. When using this technique, the 6-bit address specifies the

address of the biquad b1 coefficient (for example, 0, 5, 10, 20, 35 decimal), and the

STA339BWS generates the RAM addresses as offsets from this base value to write the

complete set of coefficient data.

Table 71. RAM block for biquads, mixing, scaling, bass management

Index

(Decimal) Index (Hex) Description Coefficient Default

0 0x00

Channel 1 - Biquad 1

C1H10(b1/2) 0x000000

1 0x01 C1H11(b2) 0x000000

2 0x02 C1H12(a1/2) 0x000000

3 0x03 C1H13(a2) 0x000000

4 0x04 C1H14(b0/2) 0x400000

5 0x05 Channel 1 - Biquad 2 C1H20 0x000000

…… … … …

19 0x13 Channel 1 - Biquad 4 C1H44 0x400000

20 0x14 Channel 2 - Biquad 1 C2H10 0x000000

21 0x15 C2H11 0x000000

…… … … …

39 0x27 Channel 2 - Biquad 4 C2H44 0x400000

60/76 Doc ID 15276 Rev 5

User-defined EQ

The STA339BWS can be programmed for four EQ filters (biquads) per each of the two input

channels. The biquads use the following equation:

Y[n] = 2 * (b0 / 2) * X[n] + 2 * (b1 / 2) * X[n-1] + b2 * X[n-2] - 2 * (a1 / 2) * Y[n-1] - a2 * Y[n-2]

= b0 * X[n] + b1 * X[n-1] + b2 * X[n-2] - a1 * Y[n-1] - a2 * Y[n-2]

where Y[n] represents the output and X[n] represents the input. Multipliers are 24-bit signed

fractional multipliers, with coefficient values in the range of 0x800000 (-1) to 0x7FFFFF

(0.9999998808).

40 0x28

Channel 1/2 - Biquad 8

for XO = 000

High-pass 2nd order filter

for XO ≠ 000

C12H0(b1/2) 0x000000

41 0x29 C12H1(b2) 0x000000

42 0x2A C12H2(a1/2) 0x000000

43 0x2B C12H3(a2) 0x000000

44 0x2C C12H4(b0/2) 0x400000

45 0x2D

Channel 3 - Biquad

for XO = 000

Low-pass 2nd order filter

for XO ≠ 000

C3H0(b1/2) 0x000000

46 0x2E C3H1(b2) 0x000000

47 0x2F C3H2(a1/2) 0x000000

48 0x30 C3H3(a2) 0x000000

49 0x31 C3H4(b0/2) 0x400000

50 0x32 Channel 1 - Prescale C1PreS 0x7FFFFF

51 0x33 Channel 2 - Prescale C2PreS 0x7FFFFF

52 0x34 Channel 1 - Postscale C1PstS 0x7FFFFF

53 0x35 Channel 2 - Postscale C2PstS 0x7FFFFF

54 0x36 Channel 3 - Postscale C3PstS 0x7FFFFF

55 0x37 TWARN/OC - Limit TWOCL 0x5A9DF7

56 0x38 Channel 1 - Mix 1 C1MX1 0x7FFFFF

57 0x39 Channel 1 - Mix 2 C1MX2 0x000000

58 0x3A Channel 2 - Mix 1 C2MX1 0x000000

59 0x3B Channel 2 - Mix 2 C2MX2 0x7FFFFF

60 0x3C Channel 3 - Mix 1 C3MX1 0x400000

61 0x3D Channel 3 - Mix 2 C3MX2 0x400000

62 0x3E Unused

63 0x3F Unused

Table 71. RAM block for biquads, mixing, scaling, bass management (continued)

Index

(Decimal) Index (Hex) Description Coefficient Default

STA339BWS Register description

Doc ID 15276 Rev 5 61/76

Coefficients stored in the user defined coefficient RAM are referenced in the following

manner:

CxHy0 = b1 / 2

CxHy1 = b2

CxHy2 = -a1 / 2

CxHy3 = -a2

CxHy4 = b0 / 2

where x represents the channel and the y the biquad number. For example, C2H41 is the b2

coefficient in the fourth biquad for channel 2.

Crossover and biquad #8

Additionally, the STA339BWS can be programmed for a high-pass filter (processing

channels 1 and 2) and a low-pass filter (processing channel 3) to be used for bass-

management crossover when the XO setting is 000 (user-defined). Both of these filters

when defined by the user (rather than using the preset crossover filters) are second order

filters that use the biquad equation given above. They are loaded into the C12H0-4 and

C3Hy0-4 areas of RAM noted in Ta b l e 7 1 , addresses 0x28 to 0x31.

By default, all user-defined filters are pass-through where all coefficients are set to 0, except

the b0/2 coefficient which is set to 0x400000 (representing 0.5)

Prescale

The STA339BWS provides a multiplication for each input channel for the purpose of scaling

the input prior to EQ. This pre-EQ scaling is accomplished by using a 24-bit signed

fractional multiplier, with 0x800000 = -1 and 0x7FFFFF = 0.9999998808. The scale factor

for this multiply is loaded into RAM. All channels can use the channel-1 prescale factor by

setting the Biquad link bit. By default, all prescale factors (RAM addresses 0x32 to 0x33) are

set to 0x7FFFFF.

Postscale

The STA339BWS provides one additional multiplication after the last interpolation stage and

the distortion compensation on each channel. This postscaling is accomplished by using a

24-bit signed fractional multiplier, with 0x800000 = -1 and 0x7FFFFF = 0.9999998808. The

scale factor for this multiply is loaded into RAM. This postscale factor can be used in

conjunction with an ADC equipped micro-controller to perform power-supply error

correction. All channels can use the channel-1 postscale factor by setting the postscale link

bit. By default, all postscale factors (RAM addresses 0x34 to 0x36) are set to 0x7FFFFF.

When line output is being used, channel-3 postscale affects both channels 3 and 4.

6.7.9 Thermal warning and overcurrent adjustment (TWOCL)

The STA339BWS provides a simple mechanism for reacting to overcurrent or thermal

warning detection in the power block. When the warning occurs, the TWOCL value is used

to provide output attenuation clipping on all channels.

The amount of attenuation to be applied in this situation can be adjusted by modifying the

overcurrent and thermal warning limiting value (RAM addr 0x37). By default, the overcurrent

postscale adjustment factor is set to 0x5A9DF7 (that is, -3 dB). Once the limiting is applied,

it remains until the device is reset or according to the TWRB and OCRB settings.

62/76 Doc ID 15276 Rev 5

6.8 Variable max power correction registers (addr 0x27 - 0x28)

MPCC bits determine the 16 MSBs of the MPC compensation coefficient. This coefficient is

used in place of the default coefficient when MPCV = 1.

6.9 Distortion compensation registers (addr 0x29 - 0x2A)

DCC bits determine the 16 MSBs of the distortion compensation coefficient. This coefficient

is used in place of the default coefficient when DCCV = 1.

6.10 Fault detect recovery constant registers (addr 0x2B - 0x2C)

FDRC bits specify the 16-bit fault detect recovery time delay. When FAULT is asserted, the

TRISTATE output is immediately asserted low and held low for the time period specified by

this constant. A constant value of 0x0001 in this register is approximately 0.083 ms. The

default value of 0x000C gives approximately 0.1 ms.

Note: 0x0000 is a reserved value for these registers.

D7 D6 D5 D4 D3 D2 D1 D0

MPCC15 MPCC14 MPCC13 MPCC12 MPCC11 MPCC10 MPCC9 MPCC8

00011010

D7 D6 D5 D4 D3 D2 D1 D0

MPCC7 MPCC6 MPCC5 MPCC4 MPCC3 MPCC2 MPCC1 MPCC0

11000000

D7 D6 D5 D4 D3 D2 D1 D0

DCC15 DCC14 DCC13 DCC12 DCC11 DCC10 DCC9 DCC8

11110011

D7 D6 D5 D4 D3 D2 D1 D0

DCC7 DCC6 DCC5 DCC4 DCC3 DCC2 DCC1 DCC0

00110011

D7 D6 D5 D4 D3 D2 D1 D0

FDRC15 FDRC14 FDRC13 FDRC12 FDRC11 FDRC10 FDRC9 FDRC8

00000000

D7 D6 D5 D4 D3 D2 D1 D0

FDRC7 FDRC6 FDRC5 FDRC4 FDRC3 FDRC2 FDRC1 FDRC0

00001100

STA339BWS Register description

Doc ID 15276 Rev 5 63/76

6.11 Device status register (addr 0x2D)

This read-only register provides fault and thermal-warning status information from the power

control block. Logic value 1 for faults or warning means normal state. Logic 0 means a fault

or warning detected on power bridge. The PLLUL = 1 means that the PLL is not locked.

D7 D6 D5 D4 D3 D2 D1 D0

PLLUL FAULT UVFAULT Reserved OCFAULT OCWARN TFAULT TWARN

Table 72. Status register bits

Bit R/W RST Name Description

7 R - PLLUL 0: PLL locked

1: PLL not locked

6R - FAULT 0: fault detected on power bridge

1: normal operation

5R - UVFAULT 0: VCCxX internally detected

< undervoltage threshold

4 R - Reserved -

3 R - OCFAULT 0: overcurrent fault detected

2 R - OCWARN 0: overcurrent warning

1 R - TFAULT 0: thermal fault, junction temperature over limit

0R - TWARN 0: thermal warning, junction temperature is close to

the fault condition

64/76 Doc ID 15276 Rev 5

6.12 EQ coefficients and DRC configuration register (addr 0x31)

EQ RAM

DRC / Anticlipping

Bits AMGC[3:2] change the behavior of the bits AMGC[1:0] as given in Ta b l e 7 4 below.

Anticlipping when AMGC[3:2] = 01

AC0, AC1, AC2 settings are designed for the loudspeaker protection function, limiting at the

minimum any audio artefacts introduced by typical anticlipping / DRC algorithms. More

detailed information is available in the applications notes “Configurable output power rate

using STA335BW” and “STA335BWS vs STA335BW”.

XOB

This bit can be used to bypass the crossover filters. Logic 1 means that the function is not

active. In this case, high pass crossover filter works as a pass-through on the data path

(b0 = 1, all the other coefficients at logic 0) while the low-pass filter is configured to have

zero signal on channel-3 data processing (all the coefficients are at logic 0).

D7 D6 D5 D4 D3 D2 D1 D0

XOB Reserved Reserved AMGC[3] AMGC[2] Reserved SEL[1] SEL[0]

00000000

Table 73. EQ RAM select

SEL[1:0] EQ RAM bank selected

00 / 11 Bank 0 activated

01 Bank 1 activated

10 Bank 2 activated

Table 74. Anticlipping and DRC preset

AMGC[3:2] Anticlipping and DRC preset selected

00 DRC / Anticlipping behavior is described in Table 53 on page 45 (default)

01 DRC / Anticlipping behavior is described Table 75 on page 64

10 / 11 Reserved

Table 75. Anticlipping selection for AMGC[3:2] = 01

AMGC[1:0] Mode

00 AC0, stereo anticlipping 0 dB limiter

01 AC1, stereo anticlipping +1.25 dB limiter

10 AC2, stereo anticlipping +2 dB limiter

11 Reserved do not use

STA339BWS Register description

Doc ID 15276 Rev 5 65/76

6.13 Extended configuration register (addr 0x36)

Extended configuration register provides access to B2DRC and biquad 5, 6 and 7.

6.13.1 Dual-band DRC (B2DRC)

STA339BWS device provide a dual-band DRC (B2DRC) on the left and right channels data

path, as depicted in Figure 19. Dual-band DRC is activated by setting MDRC[1:0] = 1x.

Figure 19. B2DRC scheme

The low frequency information (LFE) is extracted from left and right channels, removing the

high frequencies using a programmable biquad filter, and then computing the difference with

the original signal. Limiter 1 (DRC1) is then used to control left/right high frequency

components amplitude while limiter 2 (DRC2) is used to control the low frequency

components (see Chapter 6.6).

The cut-off frequency of the high pass filters can be user defined, XO[3:0] = 0, or selected

from the predefined values.

DRC1 and DRC2 are then used to independently limit L/R high frequencies and LFE

channels amplitude (see Chapter 6.6) as well as their volume control. To be noted that, in

this configuration, the dedicated channel 3 volume control can be actually acted as a bass

boost enhancer as well (0.5 dB/step resolution).

The processed LFE channel is then recombined with the L and R channels in order to

reconstruct the 2.0 output signal.

Sub-band decomposition

The sub-band decomposition for B2DRC can be configured specifying the cutoff frequency.

The cut off frequency can be programmed in two ways, using XO bits in register 0x0C, or

using “user programmable” mode (coefficients stored in RAM addresses 0x28 to 0x31).

D7 D6 D5 D4 D3 D2 D1 D0

MDRC[1] MDRC[0] PS48DB XAR1 XAR2 BQ5 BQ6 BQ7

00000000

Pass XO

Filter

Pass XO

Filter

B2DRC

Hi-pass

filter

B2DRC

Hi-pass

filter -

CH1

Volume

VolAndLimiter

DRC1

CH2

Volume DRC1

CH3

Volume

VolAndLimiter

DRC2

CH3

Volume

VolAndLimiter

DRC2

Pass XO

Filter

Pass XO

Filter

B2DRC

Hi-pass

filter

B2DRC

Hi-pass

filter -

CH1

Volume

VolAndLimiter

DRC1

CH2

Volume DRC1

CH3

Volume

VolAndLimiter

DRC2

CH3

Volume

VolAndLimiter

DRC2

66/76 Doc ID 15276 Rev 5

For the user programmable mode, use the formulae below to compute the high pass filters:

where alpha = (1-sin(ω0)) / cos(ω0), and ω0 is the cut-off frequency.

A first-order filter is suggested to guarantee that for every ω0 the corresponding low-pass

filter obtained as difference (as shown in Figure 19) has a symmetric (relative to HP filter)

frequency response, and the corresponding recombination after the DRC has low ripple.

Second-order filters can be used as well, but in this case the filter shape must be carefully

chosen to provide good low pass response and minimum ripple recombination. For second-

order is not possible to give a closed formula to get the best coefficients, but empirical

adjustment should be done.

DRC settings

The DRC blocks used by B2DRC are the same as those described in Chapter 6.6. B2DRC

configure automatically the DRC blocks in anticlipping mode. Attack and release thresholds

can be selected using registers 0x32, 0x33, 0x34, 0x35, while attack and release rates are

configured by registers 0x12 and 0x14.

Band downmixing

The low-frequency band is down-mixed to the left and right channels at the B2DRC output.

Channel volume can be used to weight the bands recombination to fine tune the overall

frequency response.

6.13.2 EQ DRC mode

Setting MDRC = 01, it is possible to add a programmable biquad (the XO biquad at RAM

addresses 0x28 to 0x2C is used for this purpose) to the Limiter/compressor measure path

(side chain). Using EQDRC the peak detector input can be shaped in frequency using the

programmable biquad. For example, if a bass boost of 2 dB is applied (using a low-shelf

filter, for example), the effect is that the EQDRC out will limit bass frequencies to 2 dB below

the selected attack threshold.

Generally speaking, if the biquad boosts frequency f with an amount of X dB, the level of a

compressed sine wave at the output is TH - X, where TH is the selected attack threshold.

Note: EQDRC works only if the biquad frequency response magnitude is >= 0 dB for every

frequency.

b0 = (1 + alpha) / 2 a0 = 1

b1 = -(1 + alpha) / 2 a1 = -alpha

b2 = 0 a2 = 0

STA339BWS Register description

Doc ID 15276 Rev 5 67/76

Figure 20. EQDRC scheme

Extended postscale range

Postscale is an attenuation by default. When PS48DB is set to 1, an offset of 48 dB is

applied to the configured word, so postscale can act as a gain too.

Extended attack rate

The attack rate shown in Ta b l e 6 5 can be extended to provide up to 8 dB/ms attack rate on

both limiters.

Extended biquad selector

De-emphasis filter as well as bass and treble controls can be configured as user defined

filters when equalization coefficients link is activated (BQL = 1) and the corresponding BQx

bit is set to 1.

Table 76. Bit PS48DB description

PS48DB Mode

0 Postscale value is applied as defined in coefficient RAM

1Postscale value is applied with offset of +48 dB with respect to the coefficient

RAM value

Table 77. Bit XAR1 description

XAR1 Mode

0 Limiter1 attack rate is configured using Ta b l e 6 5

1 Limiter1 attack rate is 8 dB/ms

Table 78. Bit XAR2 description

XAR2 Mode

0 Limiter2 attack rate is configured using Ta b l e 6 5

1 Limiter2 attack rate is 8 dB/ms

Channel In

Channel In BIQUAD

EQDRC

Standard DRC

Channel In

Channel In BIQUADBIQUAD PEAK

DETECTOR

PEAK

DETECTOR

ATTENUATION

CLACULATOR

ATTENUATION

CLACULATOR

ATTENUAT ION

ATTENUATION

Channel In

Channel In BIQUAD

EQDRC

Standard DRC

Channel In

Channel In BIQUADBIQUAD PEAK

DETECTOR

PEAK

DETECTOR

ATTENUATION

CLACULATOR

ATTENUATION

CLACULATOR

ATTENUAT ION

ATTENUATION

68/76 Doc ID 15276 Rev 5

When filters from 5th to 7th are configured as user-programmable, the corresponding

coefficients are stored respectively in addresses 0x14-0x18 (BQ5), 0x19-0x1D (BQ6) and

0x1E-0x22 (BQ7) as in Table 71 on page 59.

Note: BQx bits are ignored if BQL = 0 or if DEMP = 1 (relevant for BQ5) or CxTCB = 1 (relevant for

BQ6 and BQ7).

6.14 Soft volume configuration registers (addr 0x37 - 0x38)

Soft volume update has a fixed rate by default. Using register 0x37 and 0x38 it is possible to

override the default behavior allowing different volume change rates.

It is also possible to independently define the fade-in (volume is increased) and fade-out

(volume is decreased) rates according to the desired behavior.

Table 79. Bit BQ5 description

BQ5 Mode

0 Preset de-emphasis filter selected

1 User defined biquad 5 coefficients are selected

Table 80. Bit BQ6 description

BQ6 Mode

0 Preset bass filter selected as per Ta b l e 6 4

1 User defined biquad 6 coefficients are selected

Table 81. Bit BQ7 description

BQ7 Mode

0 Preset treble filter selected as per Tab l e 6 4

1 User defined biquad 7 coefficients are selected

D7 D6 D5 D4 D3 D2 D1 D0

Reserved Reserved SVUPE SVUP[4] SVUP[3] SVUP[2] SVUP[1] SVUP[0]

00000000

D7 D6 D5 D4 D3 D2 D1 D0

Reserved Reserved SVDWE SVDW4] SVDW[3] SVDW[2] SVDW[1] SVDW[0]

00000000

Table 82. Bit SVUPE description

SVUPE Mode

0 When volume is increased, use the default rate

1 When volume is increased, use the rates defined by SVUP[4:0]

STA339BWS Register description

Doc ID 15276 Rev 5 69/76

When SVUPE = 1 the fade-in rate is defined by the SVUP[4:0] bits according to the following

formula:

Fade-in rate = 48 / (N + 1) dB/ms

where N is the SVUP[4:0] value.

When SVDWE = 1 the fade-out rate is defined by the SVDW[4:0] bits according to the

following formula:

Fade-in rate = 48 / (N + 1) dB/ms

where N is the SVDW[4:0] value.

Note: For fade-out rates greater than 6 dB/ms it is suggested to disable bit ZCE (Section 6.1.5 on

page 32) in order to avoid any audible pop noise.

6.15 DRC RMS filter coefficients (addr 0x39-0x3E)

Signal level detection in DRC algorithm is computed using the following formula:

y(t) = c0 * abs(x(t)) + c1 * y(t-1)

where x(t) represents the audio signal applied to the limiter, and y(t) the measured level.

Table 83. Bit SVDWE description

SVDWE Mode

0 When volume is decreased, use the default rate

1 When volume is decreased, use the rates defined by SVDW[4:0]

D7 D6 D5 D4 D3 D2 D1 D0

R_C0[23] R_C0[22] R_C0[21] R_C0[20] R_C0[19] R_C0[18] R_C0[17] R_C0[16]

00000001

D7 D6 D5 D4 D3 D2 D1 D0

R_C0[15] R_C0[14] R_C0[13] R_C0[12] R_C0[11] R_C0[10] R_C0[9] R_C0[8]

11101110

D7 D6 D5 D4 D3 D2 D1 D0

R_C0[7] R_C0[6] R_C0[5] R_C0[4] R_C0[3] R_C0[2] R_C0[1] R_C0[0]

11111111

D7 D6 D5 D4 D3 D2 D1 D0

R_C1[23] R_C1[22] R_C1[21] R_C1[20] R_C1[19] R_C1[18] R_C1[17] R_C1[16]

01111110

D7 D6 D5 D4 D3 D2 D1 D0

R_C1[15] R_C1[14] R_C1[13] R_C1[12] R_C1[11] R_C1[10] R_C1[9] R_C1[8]

11000000

D7 D6 D5 D4 D3 D2 D1 D0

R_C1[7] R_C1[6] R_C1[5] R_C1[4] R_C1[3] R_C1[2] R_C1[1] R_C1[0]

00100110

Applications STA339BWS

70/76 Doc ID 15276 Rev 5

7 Applications

7.1 Applications schematic

Figure 22 below shows the typical applications schematic for STA339BWS. Special

attention has to be paid to the layout of the PCB. All the decoupling capacitors have to be

placed as close as possible to the device to limit spikes on the supplies.

7.2 PLL filter circuit

It is recommended to use the applications circuit and values for the PLL loop filter to achieve

the best performance from the device in general applications. Note that the ground of this

filter circuit has to be connected to the ground of the PLL without any resistive path.

Concerning the component values, it must be taken into account that the greater the filter

bandwidth, the less is the lock time but the higher is the PLL output jitter.

7.3 Typical output configuration

Figure 21 shows the typical output configuration used for BTL stereo mode. Please contact

STMicroelectronics for other recommended output configurations.

Figure 21. Output configuration for stereo BTL mode (RL = 8 Ω)

OUT1A

100 nF

6R2

330 pF

22R

OUT1B

22 µH

Left

470 nF

OUT2A

100 nF

6R2

330 pF

22R

OUT2B

22 µH

Right

470 nF

STA339BWS Applications

Doc ID 15276 Rev 5 71/76

Figure 22. Applications circuit

C33

100nF

C14

100µF 25V

C22

1nF

SCL

SDA

3V3

Vcc

RESET

C18

100nF

R36 0

C30

100nF

C21 1µF 25V

C23 100nF

C29 100nF

C31 1µF 25V

INTL

C32

100nF

C13

100nF

3V3

C36

4.7nF

R14

2K2 C35

680pF

LRCKI

PWDN

3V3

OUT2B

XTI

R35 2R2

BICKI

OUT2A

STA339BWS

GND_SUB

TEST_MODE

VSS

VCC_REG

OUT2B

GND2

VCC2

OUT2A

OUT1B

Vcc1

GND1

OUT1A

GND_REG

VDD

CONFIG

OUT3B / FFX3B

OUT3A / FFX3A

18 EAPD / OUT4B 19

TWARN / OUT4A 20

VDD_DIG 21

GND_DIG 22

PWRDN 23

VDD_PLL 24

FILTER_PLL 25

GND_PLL 26

XTI 27

BICKI 28

LRCKI 29

SDI 30

RESET 31

INT_LINE 32

SDA 33

SCL 34

GND_DIG 35

VDD_DIG 36

OUT1B

DATA

OUT1A

R11

10K

Package thermal characteristics STA339BWS

72/76 Doc ID 15276 Rev 5

8 Package thermal characteristics

Using a double-layer PCB the thermal resistance, junction to ambient, with 2 copper ground

areas of 3 x 3 cm2 and with 16 via holes is 24 °C/W in natural air convection.

The dissipated power within the device depends primarily on the supply voltage, load

impedance and output modulation level.

Thus, the maximum estimated dissipated power for the STA339BWS is:

Figure 23 shows the power derating curve for the PowerSSO-36 package on PCBs with

copper areas of 2 x 2 cm2 and 3 x 3 cm2.

Figure 23. PowerSSO-36 power derating curve

2 x 20 W @ 8 Ω, 18 V Pd max is approximately 4 W

2 x 9 W + 1 x 20 W @ 4 Ω, 8 Ω, 18 V Pd max is approximately 5 W

0 20406080100120140160

Pd (W)

Tamb ( °C)

Copper Area 2x2 cm

and via holes

STA339BW

PSSO36

Copper Area 3x3 cm

and via holes

0 20406080100120140160

Pd (W)

Tamb ( °C)

Copper Area 2x2 cm

and via holes

STA339BW

PSSO36

Copper Area 3x3 cm

and via holes

STA339BWS

PowerSSO-36

STA339BWS Package mechanical data

Doc ID 15276 Rev 5 73/76

9 Package mechanical data

Figure 24 shows the package outline and Ta bl e 8 4 gives the dimensions.

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®

specifications, grade definitions and product status are available at: www.st.com.

ECOPACK® is an ST trademark.

Table 84. PowerSSO-36 EPD dimensions

Symbol

Dimensions in mm Dimensions in inches

Min Typ Max Min Typ Max

A 2.15 - 2.47 0.085 - 0.097

A2 2.15 - 2.40 0.085 - 0.094

a1 0.00 - 0.10 0.00 - 0.004

b 0.18 - 0.36 0.007 - 0.014

c 0.23 - 0.32 0.009 - 0.013

D 10.10 - 10.50 0.398 - 0.413

E 7.40 - 7.60 0.291 - 0.299

e - 0.5 - - 0.020 -

e3 - 8.5 - - 0.335 -

F - 2.3 - - 0.091 -

G- - 0.10 - - 0.004

H 10.10 - 10.50 0.398 - 0.413

h- - 0.40 - - 0.016

k 0 - 8 degrees 0 - 8 degrees

L 0.60 - 1.00 0.024 - 0.039

M - 4.30 - - 0.169 -

N - - 10 degrees - - 10 degrees

O - 1.20 - - 0.047 -

Q - 0.80 - - 0.031 -

S - 2.90 - - 0.114 -

T - 3.65 - - 0.144 -

U - 1.00 - - 0.039 -

X 4.10 - 4.70 0.161 - 0.185

Y 6.50 - 7.10 0.256 - 0.280

Package mechanical data STA339BWS

74/76 Doc ID 15276 Rev 5

Figure 24. PowerSSO-36 EPD outline drawing

h x 45°

STA339BWS Revision history
Doc ID 15276 Rev 5 75/76
10 Revision history
         
Table 85. Document revision history
Date Revision Changes
10-Dec-2008 1 Initial release.
16-Feb-2009 2
Updated names/descriptions for pins 17-20 in Chapter 2 on page 10
Added cross reference to I2S interface setup in Section 3.6: Power 
on/off sequence on page 18
Added Figure 4: Power-off sequence for pop-free turn-off on page 18
Updated text and Figure 22: Application diagram on page 71
Updated Section 7.2: PLL filter on page 71
01-Mar-2010 3
Updated presentation
Removed master mute from Section 6.2.5 on page 44
Added Rth j-amb typical value to Table 4 on page 12
Updated Biquad # in Figure 7 on page 18
Updated section Fault detect recovery bypass on page 26
Updated SV naming in Table 41 on page 34
Updated CxBO description in Table 61 on page 48
Updated Biquad # for C12Hx in Table 71 on page 59
Updated text in sections Crossover and biquad #8, Prescale and 
Postscale on page 61. 
17-Dec-2010 4
“Sound Terminal” now has registered trademark status
Updated test circuit in Figure 3 on page 15
Removed text concerning hard mute in Section 6.2 on page 42
Updated coefficient register addresses towards end of 
Section 6.13.2 on page 66
Updated applications circuit in Figure 22 on page 71
22-Nov-2011 5 Updated bit D4 to “1” in Section 6.2.1: Mute/line output configuration 
register (addr 0x06) on page 43

STA339BWS

76/76 Doc ID 15276 Rev 5

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