Rev. 1.4 6/18 Copyright © 2018 by Silicon Laboratories Si510/511
Si510/511
CRYSTAL OSCILLATOR (XO) 100 kHZ TO 250 MHZ
Features
Applications
Description
The Si510/511 XO utilizes Silicon Laboratories' advanced DSPLL technology
to provide any frequency from 100 kHz to 250 MHz. Unlike a traditional XO
where a different crystal is required for each output frequency, the Si510/511
uses one fixed crystal and Silicon Labs’ proprietary DSPLL synthesizer to
generate any frequency across this range. This IC-based approach allows
the crystal resonator to provide enhanced reliability, improved mechanical
robustness, and excellent stability. In addition, this solution provides superior
supply noise rejection, simplifying low jitter clock generation in noisy
environments. Crystal ESR and DLD are individually production-tested to
guarantee performance and enhance reliability. The Si510/511 is factory-
configurable for a wide variety of user specifications, including frequency,
supply voltage, output format, output enable polarity, and stability. Specific
configurations are factory-programmed at time of shipment, eliminating long
lead times and non-recurring engineering charges associated with custom
frequency oscillators.
Functional Block Diagram
Supports any frequency from
100 kHz to 250 MHz
Low jitter operation
2 to 4 week lead times
Total stability includes 10-year
aging
Comprehensive production test
coverage includes crystal ESR and
DLD
On-chip LDO regulator for power
supply noise filtering
3.3, 2.5, or 1.8 V operation
Differential (LVPECL, LVDS,
HCSL) or CMOS output options
Optional integrated 1:2 CMOS
fanout buffer
Runt suppression on OE and
power on
Industry standard 5 x 7, 3.2 x 5,
and 2.5 x 3.2 mm packages
Pb-free, RoHS compliant
–40 to 85 oC operation
SONET/SDH/OTN
Gigabit Ethernet
Fibre Channel/SAS/SATA
PCI Express
3G-SDI/HD-SDI/SDI
Telec o m
Switches/routers
FPGA/ASIC clock generation
VDD
Any-Frequency
0.1 to 250 MHz
DSPLL® Synthesis
Fixed
Frequency
Oscillator
CLK+
CLK–
OE
GND
Low Noise Regulator
Ordering Information:
See page 14.
Pin Assignments:
See page 12.
Si5602
2.5x3.2mm
5x7mm and 3.2x5mm
1
2
3
6
5
4GND
OE
VDD
CLK+
CLK–
NC
1
2
3
6
5
4GND
NC
VDD
CLK+
CLK–
OE
Si510(LVDS/LVPECL/HCSL/
Dual CMOS)
Si510 (CMOS)
Si511(LVDS/LVPECL/HCSL/
Dual CMOS)
1
2
4
3GND
VDD
CLK
OE
1
2
3
6
5
4GND
NC
VDD
CLK+
CLK–
OE
Si510/511
2 Rev. 1.4
TABLE OF CONTENTS
Section Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
2. Solder Reflow and Rework Requirements for 2.5x3.2 mm Packages . . . . . . . . . . . . . .11
3. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
3.1 Dual CMOS Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
4. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
5. Si510/511 Mark Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
6. Package Outline Diagram: 5 x 7 mm, 4-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7. PCB Land Pattern: 5 x 7 mm, 4-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
8. Package Outline Diagram: 5 x 7 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
9. PCB Land Pattern: 5 x 7 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
10. Package Outline Diagram: 3.2 x 5 mm, 4-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
11. PCB Land Pattern: 3.2x5mm, 4-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
12. Package Outline Diagram: 3.2 x 5 mm, 6-Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
13. PCB Land Pattern: 3.2 x 5.0 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
14. Package Outline Diagram: 2.5 x 3.2 mm, 4-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
15. PCB Land Pattern: 2.5 x 3.2 mm, 4-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
16. Package Outline Diagram: 2.5 x 3.2 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
17. PCB Land Pattern: 2.5 x 3.2 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Si510/511
Rev. 1.4 3
1. Electrical Specifications
Table 1. Operating Specifications
VDD = 1.8 V ±5%, 2.5 or 3.3 V ±10%, TA = –40 to +85 oC
Parameter Symbol Test Condition Min Typ Max Unit
Supply Voltage VDD 3.3 V option 2.97 3.3 3.63 V
2.5 V option 2.25 2.5 2.75 V
1.8 V option 1.71 1.8 1.89 V
Supply Current IDD CMOS, 100 MHz,
single-ended
—21 26mA
LVDS
(output enabled)
—19 23mA
LVPECL
(output enabled)
—39 43mA
HCSL
(output enabled)
—41 44mA
Tristate
(output disabled)
—— 18mA
OE "1" Setting VIH See Note 0.80 x VDD ——V
OE "0" Setting VIL See Note — — 0.20 x VDD V
OE Internal Pull-Up/Pull-
Down Resistor*RI—45 —k
Operating Temperature TA–40 — 85 oC
*Note: Active high and active low polarity OE options available. Active high option includes an internal pull-up.
Active low option includes an internal pull-down. See ordering information on page 14.
Si510/511
4 Rev. 1.4
Table 2. Output Clock Frequency Characteristics
VDD = 1.8 V ±5%, 2.5 or 3.3 V ±10%, TA = –40 to +85 oC
Parameter Symbol Test Condition Min Typ Max Unit
Nominal Frequency FOCMOS, Dual CMOS 0.1 — 212.5 MHz
FOLVDS/LVPECL/HCSL 0.1 — 250 MHz
Total Stability* Frequency Stability Grade C –30 — +30 ppm
Frequency Stability Grade B –50 — +50 ppm
Frequency Stability Grade A –100 — +100 ppm
Temperature Stability Frequency Stability Grade C –20 — +20 ppm
Frequency Stability Grade B –25 — +25 ppm
Frequency Stability Grade A –50 — +50 ppm
Startup Time TSU Minimum VDD until output
frequency (FO) within specification
——10ms
Disable Time TDFO10 MHz — — 5 µs
FO<10MHz — — 40 µs
Enable Time TEFO10 MHz — — 20 µs
FO<10MHz — — 60 µs
*Note: Total stability includes initial accuracy, operating temperature, supply voltage change, load change, shock and vibration
(not under operation), and 10 years aging at 40 oC.
Si510/511
Rev. 1.4 5
Table 3. Output Clock Levels and Symmetry
VDD = 1.8 V ±5%, 2.5 or 3.3 V ±10%, TA = –40 to +85 oC
Parameter Symbol Test Condition Min Typ Max Unit
CMOS Output Logic
High
VOH 0.85 x VDD ——V
CMOS Output Logic
Low
VOL — — 0.15 x VDD V
CMOS Output Logic
High Drive
IOH 3.3 V –8 — — mA
2.5 V –6 — — mA
1.8 V –4 — — mA
CMOS Output Logic
Low Drive
IOL 3.3 V 8 — — mA
2.5 V 6 — — mA
1.8 V 4 — — mA
CMOS Output Rise/Fall
Time
(20 to 80% VDD)
TR/TF0.1 to 212.5 MHz,
CL = 15 pF
0.45 0.8 1.2 ns
0.1 to 212.5 MHz,
CL = no load
0.3 0.6 0.9 ns
LVPECL Output
Rise/Fall Time
(20 to 80% VDD)
TR/TF100 — 565 ps
HCSL Output Rise/Fall
Time (20 to 80% VDD)
TR/TF100 — 470 ps
LVDS Output Rise/Fall
Time (20 to 80% VDD)
TR/TF350 — 800 ps
LVPECL Output
Common Mode
VOC 50 to VDD – 2 V,
single-ended
—V
DD –
1.4 V
—V
LVPECL Output Swing VO50 to VDD – 2 V,
single-ended
0.55 0.8 0.90 VPPSE
LVDS Output Common
Mode
VOC 100 line-line
VDD = 3.3/2.5 V
1.13 1.23 1.33 V
100 line-line, VDD = 1.8 V 0.83 0.92 1.00 V
LVDS Output Swing VOSingle-ended, 100 differential
termination
0.25 0.35 0.45 VPPSE
HCSL Output Common
Mode
VOC 50 to ground 0.35 0.38 0.42 V
HCSL Output Swing VOSingle-ended 0.58 0.73 0.85 VPPSE
Duty Cycle DC All formats 485052%
Si510/511
6 Rev. 1.4
Table 4. Output Clock Jitter and Phase Noise (LVPECL)
VDD = 2.5 or 3.3 V ±10%, TA = –40 to +85 oC; Output Format = LVPECL
Parameter Symbol Test Condition Min Typ Max Unit
Period Jitter
(RMS)
JPRMS 10k samples1 ——1.3ps
Period Jitter
(Pk-Pk)
JPPKPK 10k samples1 ——11ps
Phase Jitter
(RMS)
φJ 1.875 MHz to 20 MHz integration
bandwidth2 (brickwall)
—0.310.5 ps
12 kHz to 20 MHz integration band-
width2 (brickwall)
—0.81.0ps
Phase Noise,
156.25 MHz
φN 100 Hz — –86 — dBc/Hz
1 kHz — –109 — dBc/Hz
10 kHz — –116 — dBc/Hz
100 kHz — –123 — dBc/Hz
1 MHz — –136 — dBc/Hz
Additive RMS
Jitter Due to
External Power
Supply Noise3
JPSR 10 kHz sinusoidal noise — 3.0 — ps
100 kHz sinusoidal noise — 3.5 — ps
500 kHz sinusoidal noise — 3.5 — ps
1 MHz sinusoidal noise — 3.5 — ps
Spurious SPR LVPECL output, 156.25 MHz,
offset>10 kHz
—–75—dBc
Notes:
1. Applies to output frequencies: 74.17582, 74.25, 75, 77.76, 100, 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25,
212.5, 250 MHz.
2. Applies to output frequencies: 100, 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25, 212.5 and 250 MHz.
3. 156.25 MHz. Increase in jitter on output clock due to sinewave noise added to VDD (2.5/3.3 V = 100 mVPP).
Si510/511
Rev. 1.4 7
Table 5. Output Clock Jitter and Phase Noise (LVDS)
VDD = 1.8 V ±5%, 2.5 or 3.3 V ±10%, TA = –40 to +85 oC; Output Format = LVDS
Parameter Symbol Test Condition Min Typ Max Unit
Period Jitter
(RMS)
JPRMS 10k samples1 ——2.1ps
Period Jitter
(Pk-Pk)
JPPKPK 10k samples1 ——18ps
Phase Jitter
(RMS)
φJ 1.875 MHz to 20 MHz integration
bandwidth2 (brickwall)
—0.250.55ps
12 kHz to 20 MHz integration band-
width2 (brickwall)
—0.81.0ps
Phase Noise,
156.25 MHz
φN 100 Hz — –86 — dBc/Hz
1 kHz — –109 — dBc/Hz
10 kHz — –116 — dBc/Hz
100 kHz — –123 — dBc/Hz
1 MHz — –136 — dBc/Hz
Spurious SPR LVPECL output, 156.25 MHz,
offset>10 kHz
—–75—dBc
Notes:
1. Applies to output frequencies: 74.17582, 74.25, 75, 77.76, 100, 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25,
212.5, 250 MHz.
2. Applies to output frequencies: 100, 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25, 212.5 and 250 MHz.
Si510/511
8 Rev. 1.4
Table 6. Output Clock Jitter and Phase Noise (HCSL)
VDD = 1.8 V ±5%, 2.5 or 3.3 V ±10%, TA = –40 to +85 oC; Output Format = HCSL
Parameter Symbol Test Condition Min Typ Max Unit
Period Jitter
(RMS)
JPRMS 10k samples*——1.2ps
Period Jitter
(Pk-Pk)
JPPKPK 10k samples*——11ps
Phase Jitter
(RMS)
φJ 1.875 MHz to 20 MHz integration
bandwidth*(brickwall)
—0.250.30ps
12 kHz to 20 MHz integration band-
width* (brickwall)
—0.81.0ps
Phase Noise,
156.25 MHz
φN 100 Hz — –90 — dBc/Hz
1kHz — –112 — dBc/Hz
10 kHz — –120 — dBc/Hz
100 kHz — –127 — dBc/Hz
1 MHz — –140 — dBc/Hz
Spurious SPR LVPECL output, 156.25 MHz,
offset>10 kHz
—–75—dBc
*Note: Applies to an output frequency of 100 MHz.
Si510/511
Rev. 1.4 9
Table 7. Output Clock Jitter and Phase Noise (CMOS, Dual CMOS (Complementary))
VDD = 1.8 V ±5%, 2.5 or 3.3 V ±10%, TA = –40 to +85 oC; Output Format = CMOS, Dual CMOS (Complementary)
Parameter Symbol Test Condition Min Typ Max Unit
Phase Jitter
(RMS)
φJ 1.875 MHz to 20 MHz integration
bandwidth2 (brickwall)
—0.250.35ps
12 kHz to 20 MHz integration band-
width2 (brickwall)
—0.81.0ps
Phase Noise,
156.25 MHz
φN 100 Hz — –86 — dBc/Hz
1 kHz — –108 — dBc/Hz
10 kHz — –115 — dBc/Hz
100 kHz — –123 — dBc/Hz
1 MHz — –136 — dBc/Hz
Spurious SPR LVPECL output, 156.25 MHz,
offset>10 kHz
—–75—dBc
Notes:
1. Applies to output frequencies: 74.17582, 74.25, 75, 77.76, 100, 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25,
212.5 MHz.
2. Applies to output frequencies: 100, 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25, 212.5 MHz.
Table 8. Environmental Compliance and Package Information
Parameter Conditions/Test Method
Mechanical Shock MIL-STD-883, Method 2002
Mechanical Vibration MIL-STD-883, Method 2007
Solderability MIL-STD-883, Method 2003
Gross and Fine Leak MIL-STD-883, Method 1014
Resistance to Solder Heat MIL-STD-883, Method 2036
Contact Pads Gold over Nickel
Si510/511
10 Rev. 1.4
Table 9. Thermal Characteristics
Parameter Symbol Test Condition Value Unit
CLCC, Thermal Resistance Junction to Ambient JA Still air 110 °C/W
2.5x3.2mm, Thermal Resistance Junction to Ambient JA Still air 164 °C/W
Table 10. Absolute Maximum Ratings1
Parameter Symbol Rating Unit
Maximum Operating Temperature TAMAX 85 oC
Storage Temperature TS–55 to +125 oC
Supply Voltage VDD –0.5 to +3.8 V
Input Voltage (any input pin) VI–0.5 to VDD + 0.3 V
ESD Sensitivity (HBM, per JESD22-A114) HBM 2 kV
Soldering Temperature (Pb-free profile)2TPEAK 260 oC
Soldering Temperature Time at TPEAK (Pb-free profile)2TP 20–40 sec
Notes:
1. Stresses beyond those listed in this table may cause permanent damage to the device. Functional operation or
specification compliance is not implied at these conditions. Exposure to maximum rating conditions for extended
periods may affect device reliability.
2. The device is compliant with JEDEC J-STD-020E.
Si510/511
Rev. 1.4 11
2. Solder Reflow and Rework Requirements for 2.5x3.2 mm Packages
Reflow of Silicon Labs' components should be done in a manner consistent with the IPC/JEDEC J-STD-20E
standard. The temperature of the package is not to exceed the classification Temperature provided in the standard.
The part should not be within -5°C of the classification or peak reflow temperature (TPEAK) for longer than 30
seconds. Key to maintaining the integrity of the component is providing uniform heating and cooling of the part
during reflow and rework. Uniform heating is achieved through having a preheat soak and controlling the
temperature ramps in the process. J-STD-20E provides minimum and maximum temperatures and times for the
preheat/Soak step that need to be followed, even for rework. The entire assembly area should be heated during
rework. Hot air should be flowed from both the bottom of the board and the top of the component. Heating from the
top only will cause un-even heating of component and can lead to part integrity issues. Temperature Ramp-up rate
are not to exceed 3°C/second. Temperature ramp-down rates from peak to final temperature are not to exceed
6°C/second. Time from 25°C to peak temperature is not to exceed 8 min for Pb-free solders.
Si510/511
12 Rev. 1.4
3. Pin Descriptions
*Supports integrated 1:2 CMOS buffer. See ordering information and section 2.1“Dual CMOS Buffer”.
Table 11. Si510 Pin Descriptions (CMOS)
Pin Name CMOS Function
1OE Output Enable. Includes internal pull-up for OE active high. Includes
internal pull-down for OE active low. See ordering information.
2GND Electrical and Case Ground.
3CLK Clock Output.
4 VDD Power Supply Voltage.
Table 12. Si510 Pin Descriptions (LVPECL/LVDS/HCSL, Dual CMOS, OE Pin 2)
Pin Name LVPECL/LVDS/HCSL Function
1NC No connect. Make no external connection to this pin.
2OE Output Enable. Includes internal pull-up for OE active high. Includes
internal pull-down for OE active low. See ordering information.
3GND Electrical and Case Ground.
4CLK+ Clock Output.
5CLK– Complementary Clock Output.
6 VDD Power Supply Voltage.
Table 13. Si511 Pin Descriptions (LVPECL/LVDS/HCSL, Dual CMOS, OE Pin 1)
Pin Name LVPECL/LVDS/HCSL Function
1OE Output Enable. Includes internal pull-up for OE active high. Includes
internal pull-down for OE active low. See ordering information.
2NC No connect. Make no external connection to this pin.
3GND Electrical and Case Ground.
4CLK+ Clock Output.
5CLK– Complementary Clock Output.
6 VDD Power Supply Voltage.
1
2
3
6
5
4GND
OE
VDD
CLK+
CLK–*
NC
1
2
3
6
5
4GND
NC
VDD
CLK+
CLK–*
OE
Si510 (CMOS) Si510 (LVDS/LVPECL/HCSL/Dual CMOS*) Si511 (LVDS/LVPECL/HCSL/DualCMOS)*)
1
2
4
3GND
VDD
CLK
OE
Si510/511
Rev. 1.4 13
3.1. Dual CMOS Buffer
Dual CMOS output format ordering options support either complementary or in-phase output signals. This feature
enables replacement of multiple XOs with a single Si510/11 device.
Figure 1. Integrated 1:2 CMOS Buffer Supports Complementary or In-Phase Outputs
~
~
Complementary
Outputs
In-Phase
Outputs
Si510/511
14 Rev. 1.4
4. Ordering Information
The Si510/511 supports a wide variety of options including frequency, stability, output format, and VDD. Specific
device configurations are programmed into the Si510/511 at time of shipment. Configurations can be specified
using the Part Number Configuration chart below. Silicon Labs provides a web browser-based part number
configuration utility to simplify this process. To access this tool refer to www.silabs.com/oscillators and click
“Customize” in the product table. The Si510/511 XO series is supplied in industry-standard, RoHS compliant, lead-
free, 2.5 x 3.2 mm, 3.2 x 5.0 mm, and 5 x 7 mm packages. Tape and reel packaging is an ordering option.
Figure 2. Part Number Syntax
Example orderable part number: 510ECB156M250AAG supports 2.5 V LVPECL, ±30 ppm total stability, OE active
low in 5 x 7 mm package across –40oC to 85oC temperature range. The output frequency is 156.25 MHz.
Note: CMOS and Dual CMOS maximum frequency is 212.5 MHz.
X
X
AGR
51X
X
XXXMXXX
X
VDD
Output Format
X
X
AGR
51X
X
XXXMXXX
X
VDD
Output
Format
D
33V
HCSL
A
OE Active High
A
5x7mm
D
3
3V
HCSL
H
25V
HCSL
A
OE
Active
High
Frequency Stability
A
5
x
7
mm
H
2
5V
HCSL
M
33V
DlCMOS(I
h)
F
Diti
Frequency
Stability
50pp
5pp
M
3
3V
D
l
CMOS
(I
h
)
F
D
i
ti
50pp
5pp
V
Si510/511
Rev. 1.4 15
5. Si510/511 Mark Specification
Figure 3 illustrates the mark specification for the Si510/511. Use the part number configuration utility located at:
www.silabs.com/VCXOpartnumber to cross-reference the mark code to a specific device configuration.
Figure 3. Top Mark
0CCCCC
TTTTTT YY
0 = Si510, 1 = Si511
CCCCC = mark code
TTTTTT = assembly manufacturing code
YY = year
WW = work week
WW
Si510/511
16 Rev. 1.4
6. Package Outline Diagram: 5 x 7 mm, 4-pin
Figure 4 illustrates the package details for the 5 x 7 mm Si510/511. Table 14 lists the values for the dimensions
shown in the illustration.
Figure 4. Si510/511 Outline Diagram
Table 14. Package Diagram Dimensions (mm)
Dimension Min Nom Max
A 1.50 1.65 1.80
b 1.30 1.40 1.50
c 0.50 0.60 0.70
D 5.00 BSC
D1 4.30 4.40 4.50
e 5.08 BSC
f0.50 TYP
E 7.00 BSC
E1 6.10 6.20 6.30
H 0.55 0.65 0.75
L 1.17 1.27 1.37
L1 0.05 0.10 0.15
p 2.50 2.60 2.70
aaa 0.15
bbb 0.15
ccc 0.10
ddd 0.10
eee 0.05
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
Si510/511
Rev. 1.4 17
7. PCB Land Pattern: 5 x 7 mm, 4-pin
Figure 5 illustrates the 5 x 7 mm PCB land pattern for the 5 x 7 mm Si510/511. Table 15 lists the values for the
dimensions shown in the illustration.
Figure 5. Si510/511 PCB Land Pattern
Table 15. PCB Land Pattern Dimensions (mm)
Dimension (mm)
C1 4.20
E5.08
X1 1.55
Y1 1.95
Notes:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.
3. This Land Pattern Design is based on the IPC-7351 guidelines.
4. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition
(LMC) is calculated based on a Fabrication Allowance of 0.05 mm.
Solder Mask Design
5. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder
mask and the metal pad is to be 60 µm minimum, all the way around the pad.
Stencil Design
6. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used
to assure good solder paste release.
7. The stencil thickness should be 0.125 mm (5 mils).
8. The ratio of stencil aperture to land pad size should be 1:1.
Card Assembly
9. A No-Clean, Type-3 solder paste is recommended.
10. The recommended card reflow profile is per the JEDEC/IPC J-STD-020D specification for
Small Body Components.
Si510/511
18 Rev. 1.4
8. Package Outline Diagram: 5 x 7 mm, 6-pin
Figure 6 illustrates the package details for the Si510/511. Table 16 lists the values for the dimensions shown in the
illustration.
Figure 6. Si510/511 Outline Diagram
Table 16. Package Diagram Dimensions (mm)
Dimension Min Nom Max
A 1.50 1.65 1.80
b 1.30 1.40 1.50
c 0.50 0.60 0.70
D 5.00 BSC
D1 4.30 4.40 4.50
e 2.54 BSC
E 7.00 BSC
E1 6.10 6.20 6.30
H 0.55 0.65 0.75
L 1.17 1.27 1.37
L1 0.05 0.10 0.15
p 1.80 — 2.60
R0.70 REF
aaa 0.15
bbb 0.15
ccc 0.10
ddd 0.10
eee 0.05
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
Si510/511
Rev. 1.4 19
9. PCB Land Pattern: 5 x 7 mm, 6-pin
Figure 7 illustrates the 5 x 7 mm PCB land pattern for the Si510/511. Table 17 lists the values for the dimensions
shown in the illustration.
Figure 7. Si510/511 PCB Land Pattern
Table 17. PCB Land Pattern Dimensions (mm)
Dimension (mm)
C1 4.20
E2.54
X1 1.55
Y1 1.95
Notes:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.
3. This Land Pattern Design is based on the IPC-7351 guidelines.
4. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition
(LMC) is calculated based on a Fabrication Allowance of 0.05 mm.
Solder Mask Design
5. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder
mask and the metal pad is to be 60 µm minimum, all the way around the pad.
Stencil Design
6. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to
assure good solder paste release.
7. The stencil thickness should be 0.125 mm (5 mils).
8. The ratio of stencil aperture to land pad size should be 1:1.
Card Assembly
9. A No-Clean, Type-3 solder paste is recommended.
10. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small
Body Components.
Si510/511
20 Rev. 1.4
10. Package Outline Diagram: 3.2 x 5 mm, 4-pin
Figure 8 illustrates the package details for the 3.2 x 5 mm Si510/511. Table 18 lists the values for the dimensions
shown in the illustration.
Figure 8. Si510/511 Outline Diagram
Table 18. Package Diagram Dimensions (mm)
Dimension Min Nom Max
A 1.06 1.17 1.28
b 1.10 1.20 1.30
c 0.70 0.80 0.90
D3.20 BSC
D1 2.55 2.60 2.65
e2.54 BSC
f0.40 TYP
E5.00 BSC
E1 4.35 4.40 4.45
H 0.40 0.50 0.60
L 0.90 1.00 1.10
L1 0.05 0.10 0.15
p 1.17 1.27 1.37
aaa 0.15
bbb 0.15
ccc 0.10
ddd 0.10
eee 0.05
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
Si510/511
Rev. 1.4 21
11. PCB Land Pattern: 3.2 x 5 mm, 4-pin
Figure 9 illustrates the 3.2 x 5 mm PCB land pattern for the Si510/511. Table 19 lists the values for the dimensions
shown in the illustration.
Figure 9. Si510/511 PCB Land Pattern
Table 19. PCB Land Pattern Dimensions (mm)
Dimension (mm)
C1 2.60
E2.54
X1 1.35
Y1 1.70
Notes:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.
3. This Land Pattern Design is based on the IPC-7351 guidelines.
4. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition
(LMC) is calculated based on a Fabrication Allowance of 0.05 mm.
Solder Mask Design
5. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder
mask and the metal pad is to be 60 µm minimum, all the way around the pad.
Stencil Design
6. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be
used to assure good solder paste release.
7. The stencil thickness should be 0.125 mm (5 mils).
8. The ratio of stencil aperture to land pad size should be 1:1.
Card Assembly
9. A No-Clean, Type-3 solder paste is recommended.
10. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for
Small Body Components.
Si510/511
22 Rev. 1.4
12. Package Outline Diagram: 3.2 x 5 mm, 6-Pin
Figure 10 illustrates the package details for the 3.2 x 5 mm Si510/511. Table 20 lists the values for the dimensions
shown in the illustration.
Figure 10. Si510/511 Outline Diagram
Table 20. Package Diagram Dimensions (mm)
Dimension Min Nom Max
A1.061.171.33
b0.540.640.74
c0.350.450.55
D 3.20 BSC
D1 2.55 2.60 2.65
e 1.27 BSC
E 5.00 BSC
E1 4.35 4.40 4.45
H0.450.550.65
L0.800.901.00
L1 0.05 0.10 0.15
p1.171.271.37
R0.32 REF
aaa 0.15
bbb 0.15
ccc 0.10
ddd 0.10
eee 0.05
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
Si510/511
Rev. 1.4 23
13. PCB Land Pattern: 3.2 x 5.0 mm, 6-pin
Figure 11 illustrates the 3.2 x 5.0 mm PCB land pattern for the Si510/511. Table 21 lists the values for the
dimensions shown in the illustration.
Figure 11. Si510/511 Recommended PCB Land Pattern
Table 21. PCB Land Pattern Dimensions (mm)
Dimension (mm)
C1 2.60
E1.27
X1 0.80
Y1 1.70
Notes:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.
3. This Land Pattern Design is based on the IPC-7351 guidelines.
4. All dimensions shown are at Maximum Material Condition (MMC). Least Material
Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm.
Solder Mask Design
5. All metal pads are to be non-solder mask defined (NSMD). Clearance between the
solder mask and the metal pad is to be 60 µm minimum, all the way around the pad.
Stencil Design
6. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be
used to assure good solder paste release.
7. The stencil thickness should be 0.125 mm (5 mils).
8. The ratio of stencil aperture to land pad size should be 1:1.
Card Assembly
9. A No-Clean, Type-3 solder paste is recommended.
10. The recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification
for Small Body Components.
Si510/511
24 Rev. 1.4
14. Package Outline Diagram: 2.5 x 3.2 mm, 4-pin
Figure12 illustrates the package details for the 2.5x3.2mm Si510/511. Table 22 lists the values for the
dimensions shown in the illustration.
Figure 12. Si510/511 Outline Diagram
Si510/511
Rev. 1.4 25
Table 22. Package Diagram Dimensions (mm)
Dimension Min Nom Max
A— — 1.1
A1 0.26 REF
A2 0.7 REF
W0.65 0.7 0.75
D 3.20 BSC
e 2.10 BSC
E 2.50 BSC
L 0.85 0.9 0.95
E1 1.65 BSC
SE 0.825 BSC
aaa 0.1
bbb 0.2
ddd 0.08
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
Si510/511
26 Rev. 1.4
15. PCB Land Pattern: 2.5 x 3.2 mm, 4-pin
Figure illustrates the 2.5 x 3.2 mm PCB land pattern for the Si510/511. Table 23 lists the values for the dimensions
shown in the illustration.
Figure 13. Si510/511 Recommended PCB Land Pattern
Table 23. PCB Land Pattern Dimensions (mm)
Dimension (mm)
C1 2.0
E2.10
X1 0.95
Y1 1.15
Notes:
General
1. All dimensions shown are at Maximum Material Condition (MMC). Least Material
Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm.
2. This Land Pattern Design is based on the IPC-7351 guidelines.
Solder Mask Design
3. All metal pads are to be non-solder mask defined (NSMD). Clearance between the
solder mask and the metal pad is to be 60 µm minimum, all the way around the pad.
Stencil Design
4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be
used to assure good solder paste release.
5. The stencil thickness should be 0.125 mm (5 mils).
6. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pins.
Card Assembly
7. A No-Clean, Type-3 solder paste is recommended.
8. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for
Small Body Components.
Si510/511
Rev. 1.4 27
16. Package Outline Diagram: 2.5 x 3.2 mm, 6-pin
Figure14 illustrates the package details for the 2.5x3.2mm Si510/511. Table 24 lists the values for the
dimensions shown in the illustration.
Figure 14. Si510/511 Outline Diagram
Si510/511
28 Rev. 1.4
Table 24. Package Diagram Dimensions (mm)
Dimension Min Nom Max
A— — 1.1
A1 0.26 REF
A2 0.7 REF
W0.65 0.7 0.75
D 3.20 BSC
e 1.25 BSC
E 2.50 BSC
M 0.30 BSC
L 0.45 0.5 0.55
D1 2.5 BSC
E1 1.65 BSC
SE 0.825 BSC
aaa 0.1
bbb 0.2
ddd 0.08
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
Si510/511
Rev. 1.4 29
17. PCB Land Pattern: 2.5 x 3.2 mm, 6-pin
Figure 15 illustrates the 2.5 x 3.2 mm PCB land pattern for the Si510/511. Table 25 lists the values for the
dimensions shown in the illustration.
Figure 15. Si510/511 Recommended PCB Land Pattern
Table 25. PCB Land Pattern Dimensions (mm)
Dimension (mm)
C1 1.9
E2.50
X1 0.70
Y1 1.05
Notes:
General
3. All dimensions shown are at Maximum Material Condition (MMC). Least Material
Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm.
4. This Land Pattern Design is based on the IPC-7351 guidelines.
Solder Mask Design
5. All metal pads are to be non-solder mask defined (NSMD). Clearance between the
solder mask and the metal pad is to be 60 µm minimum, all the way around the pad.
Stencil Design
6. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be
used to assure good solder paste release.
7. The stencil thickness should be 0.125 mm (5 mils).
8. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pins.
Card Assembly
9. A No-Clean, Type-3 solder paste is recommended.
10. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification
for Small Body Components.
Si510/511
30 Rev. 1.4
REVISION HISTORY
Revision 1.4
June, 2018
Changed “Trays” to “Coil Tape” in the Ordering Guide.
Revision 1.3
December, 2017
Added new 2.5 x 3.2 mm package options.
Revision 1.2
Updated Table 3.
Separated LVPECL and HCSL output Rise/Fall time specs.
Min Rise/Fall times added.
Revision 1.1
Updated Table 3.
CMOS Output Rise/Fall Time Test Condition updated.
Revision 1.0
Updated Table 1 on page 3.
Updates to supply current typical and maximum values for CMOS, LVDS, LVPECL and HCSL.
CMOS frequency test condition corrected to 100 MHz.
Updates to OE VIH minimum and VIL maximum values.
Updated Table 2 on page 4.
Dual CMOS nominal frequency maximum added.
Total stability footnotes clarified for 10 year aging at 40 °C.
Disable time maximum values updated.
Enable time parameter added.
Updated Table 3 on page 5.
CMOS output rise / fall time typical and maximum values updated.
LVPECL/HCSL output rise / fall time maximum value updated.
LVPECL output swing maximum value updated.
LVDS output common mode typical and maximum values updated.
HCSL output swing maximum value updated.
Duty cycle minimum and maximum values tightened to 48/52%.
Updated Table 4 on page 6.
Phase jitter test condition and maximum value updated.
Phase noise typical values updated.
Additive RMS jitter due to external power supply noise typical values updated.
Footnote 3 updated limiting the VDD to 2.5/3.3V
Added Tables 5, 6, 7 for LVDS, HCSL, CMOS, and Dual CMOS operations.
Moved Absolute Maximum Ratings table.
Added note to Figure 2 clarifying CMOS and Dual CMOS maximum frequency.
Updated Figure 10 outline diagram to correct pinout.
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intending to use the Silicon Labs products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and "Typical"
parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Labs reserves the right to make changes
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