A3935KLQTR-T - ALLEGRO MICROSYSTEMS

26301.102J

Description

The A3935 is designed specifically for automotive applications

that require high-power motors. Each provides six high-current

gate drive outputs capable of driving a wide range of N-channel

power MOSFETs.

A requirement of automotive systems is steady operation over

a varying battery input range. The A3935 integrates a pulse-

frequency modulated boost converter to create a constant

supply voltage for driving the external MOSFETs. Bootstrap

capacitors are utilized to provide the above battery supply

voltage required for N-channel FETs.

Direct control of each gate output is possible via six TTL-

compatible inputs. A differential amplifier is integrated to

allow accurate measurement of the current in the three-phase

bridge.

Diagnostic outputs can be continuously monitored to protect

the driver from short-to-battery, short-to-supply, bridge-open,

and battery under/overvoltage conditions. Additional protection

features include dead-time, VDD undervoltage, and thermal

shutdown.

The A3935 is supplied in a 36-lead 0.8 mm pitch QSOP (package

LQ, similar to SOICW). The lead (Pb) free variants (suffix –T )

have 100% matte tin leadframe plating.

Features and Benefits

▪ Drives wide range of N-channel MOSFETs in 3-phase bridges

▪ PFM boost converter for use with low-voltage battery supplies

▪ Internal LDO regulator for gate-driver supply

▪ Bootstrap circuits for high-side gate drivers

▪ Current monitor output

▪ Adjustable battery overvoltage detection

▪ Diagnostic outputs

▪ Motor lead short-to-battery, short-to-ground, and bridge-

open protection

▪ Undervoltage protection

▪ –40°C to 150°C TJ operation

▪ Thermal shutdown

3-Phase Power MOSFET Controller for Automotive Applications

Package 36-pin QSOP (LQ):

Typical Application

Approximate scale 1:1

A3935

3-Phase Power MOSFET Controller for Automotive Applications

A3935

Allegro MicroSystems, Inc.

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000

www.allegromicro.com

Selection Guide

Absolute Maximum Ratings

Part Number Pb-free Packing Terminals Package

A3935KLQTR1– 1500 pieces/reel 36 QSOP (similar to

SOICW) surface mount

A3935KLQTR-T2Yes

1Variant has been determined to be obsolete and is no longer in production. Status change: October 31, 2011.

2Variant is in production but has been determined to be NOT FOR NEW DESIGN. This classification indicates that

sale of the variant is currently restricted to existing customer applications. The variant should not be purchased for

new design applications because obsolescence in the near future is probable. Samples are no longer available.

Status change: October 31, 2011.

Parameter Symbol Conditions Rating Units

Load Supply Voltage

VBAT VBAT pin

–0.6 to 40 V

VDRAIN VDRAIN pin

VBOOST VBOOST pin

VBOOSTD VBOOSTD pin

Output Voltage Range

VGHxGHA, GHB, and GHC pins –4 to 55 V

VSxSA, SB, and SC pins –4 to 40 V

VGLxGLA, GLB, and GLC pins –4 to 16 V

VCxCA, CB, and CC pins –0.6 to 55 V

Sense Circuit Voltage VCSxCSN and CSP pins –4 to 6.5 V

VLSS LSS pin

Logic Supply Voltage VDD VDD pin

–0.3 to 6.5 V

Logic Input/Output

VOVSET OVSET pin

VBOOSTS BOOSTS pin

VCSOUT CSOUT pin

VDSTH VDSTH pin

remaining logic pins

ESD Rating – Human Body Model AEC-Q100-002; all pins 2.5 kV

ESD Rating – Charged Device Model AEC-Q100-011; all pins 1050 V

Operating Temperature TARange K –40 to 135 °C

Junction Temperature* TJ(max)

Fault conditions that produce excessive junction temperature

will activate device thermal shutdown circuitry. These condi-

tions can be tolerated, but should be avoided.

150 °C

Storage Temperature Range Tstg –55 to 150 °C

3-Phase Power MOSFET Controller for Automotive Applications

A3935

Allegro MicroSystems, Inc.

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000

www.allegromicro.com

VREG

High-Side

Driver

Low-Side

Driver

Turn ON

Delay

Phase A

GHA

GLA

LSS

CSN

To P hase B

BOOT

To P hase C

Turn ON

Delay

VBOOST

VBAT

Control

Logic

CSP

BOOSTS

BOOSTD

AHI

ALO

BHI

BLO

CHI

CLO

ENABLE

GND

Drain-Source

Fault Monitor

VBAT Overvoltage

VBAT Undervoltage

VREG Undervoltage

Short to Ground

Short to Battery

Bridge Open

VDD Undervoltage

Thermal Shutdown

VDSTH

CSOUTVDRAIN

Low Drop

Out

Linear

Regulator

VREG

REFi

REFv

LSS

VDRAIN

(KELVIN)

FAULT

Motor

Supply

Voltage

UVFLT

OVFLT

OVSET

VDD

VBAT VIGN

VBAT

VREG

VDD

External +5V

(blank)

(off)

Dwg. FP-053

Functional Block Diagram

3-Phase Power MOSFET Controller for Automotive Applications

A3935

Allegro MicroSystems, Inc.

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000

www.allegromicro.com

ELECTRICAL CHARACTERISTICS at TJ = –40°C to 150°C, VBAT = 7 to 16 V, VDD = 4.75 to 5.25 V, ENABLE = 22.5 kHz,

50% duty cycle, two phases active;unless otherwise noted

Characteristics Symbol Conditions Min. Typ1. Max. Units

Power Supply

VDD Supply Current IDD All logic inputs = 0 V – – 7.0 mA

VBAT Supply Current IBAT All logic inputs = 0 V – – 3.0 mA

Battery Voltage Operating Range VBAT 7.0 – 40 V

Bootstrap Diode Forward Voltage VDBOOT

IDBOOT = –ICx = 10 mA, VDBOOT = VREG – VCx0.8 – 2.0 V

IDBOOT = –ICx = 100 mA 1.5 – 2.3 V

Bootstrap Diode Resistance rDBOOT

rDBOOT(100 mA) = (VDBOOT(150 mA)

– VDBOOT(50 mA)) / 100 mA 2.5 – 7.5 Ω

Bootstrap Diode Current Limit2IDM 3 V < VREG – VCx < 12 V –150 – –1150 mA

Bootstrap Quiescent Current ICx VCx = 40 V, GHx = ON 10 – 30 μA

Bootstrap Refresh Time trefresh

VSx = low, to guarantee ΔV = +0.5 V refresh of 0.47 μF

Bootstrap Capacitor, CBOOT, to VCx – VSx = +10 V – – 2.0 μs

VREG Output Voltage3VREG VBAT = 7 to 40 V, VBOOST from Boost Regulator 12.7 – 14 V

VREG Dropout Voltage4VREGDO VREGDO = VBOOST – VREG, IREG = 40 mA – 0.9 – V

Gate Drive Average Supply Current IREG No external dc load at VREG, CREG = 10 μF––40mA

VREG Input Bias Current IREGbias Current into VBOOST, ENABLE = 0 – – 4.0 mA

Boost Supply

VBOOST Output Voltage Limit VBOOSTM VBAT = 7 V 14.9 – 16.3 V

VBOOST Output Voltage Limit Hysteresis ∆VBOOSTM 35 – 180 mV

Boost Switch On Resistance rDS(on) IBOOSTD < 300 mA – 1.4 3.3 Ω

Boost Switch Maximum Current IBOOSTSW – – 300 mA

Boost Current Limit Threshold Voltage VBI(th) Increasing VBOOSTS 0.45 – 0.55 V

Off Time toff 3.0 – 8.0 μs

Blanking Time tblank 100 – 220 ns

Control Logic

Logic Input Voltage VI(1) Minimum high level input for logic 1 2.0 – – V

VI(0) Maximum low level input for logic 0 – – 0.8 V

Logic Input Current II(1) VI = VDD – – 500 μA

II(0) VI = 0.8 V 50 – – μA

Logic Input Hysteresis VIhys 100 – 300 mV

Logic Output High Voltage VO(H) IO(H) = –800 μAVDD –

0.8 –– V

Logic Output Low Voltage VO(L) IO(L) = 1.6 mA – – 0.4 V

Gate Drives, GHx (internal source, or upper, switch stages)5

Output High Voltage VDSL(H)

GHx: IxU = –10 mA, VSx = 0 VREG –

2.26 –V

REG V

GLx: IxU = –10 mA, VLSS = 0 VREG –

0.26 –V

REG V

Source Current (pulsed) IxU

VSDU = 10 V, TJ = 25°C – 800 – mA

VSDU = 10 V, TJ = 135°C 400 – – mA

Source On Resistance rSDU(on)

IxU = –150 mA, TJ = 25°C 4.0 – 10 Ω

IxU = –150 mA, TJ = 135°C 7.0 – 15 Ω

Continued on the next page…

3-Phase Power MOSFET Controller for Automotive Applications

A3935

Allegro MicroSystems, Inc.

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000

www.allegromicro.com

ELECTRICAL CHARACTERISTICS (continued) at TJ = –40°C to 150°C, VBAT = 7 to 16 V, VDD = 4.75 to 5.25 V,

ENABLE = 22.5 kHz, 50% duty cycle, two phases active;unless otherwise noted

Characteristics Symbol Conditions Min. Typ1. Max. Units

Gate Drives, GLx (internal sink or lower switch stages)6

Sink Current (pulsed) IxL

VDSL = 10 V, TJ = 25°C – 850 – mA

VDSL = 10 V, TJ = 135°C 550 – – mA

Sink On Resistance rDSL(on)

IxL = 150 mA, TJ = 25°C 1.8 – 6.0 Ω

IxL = 150 mA, TJ = 135°C 3.0 – 7.5 Ω

Gate Drives, GHx, GLx (General)5,6

Propagation Delay, Logic only tpd Logic input to unloaded GHx, GLx– – 150 ns

Output Skew Time tsk(o) Grouped by edge, phase–to–phase – – 50 ns

Dead Time (shoot–through prevention) tdead Between GHx, GLx transitions of same phase 75 – 180 ns

Sense Amplifier

Input Bias Current2Ibias CSP = CSN = 0 V –180 – –360 μA

Input Offset Current2IIO CSP = CSN = 0 V – – ±35 μA

Input Resistance ri

CSP with respect to GND – 80 – kΩ

CSN with respect to GND – 4.0 – kΩ

Diff. Input Operating Voltage VID VID = CSP – CSN, –1.3V < CSP,N < 4V – – ±200 mV

Output Offset Voltage VOO CSP = CSN = 0 V 77 250 450 mV

Output Offset Voltage Drift ΔVOO CSP = CSN = 0 V – 100 – μV/°C

Input Common Mode Operating Range VIC CSP = CSN –1.5 – 4.0 V

Voltage Gain AVVID = 40 to 200 mV 18.6 19.2 19.8 V/V

Low Output Voltage Error EVVID = 0 to 40 mV, VO = (19.2 × VID) + VO + Ev– – ±25 mV

DC Common Mode Attenuation A

VCCSP = CSN = 200 mV 28 – – dB

Output Resistance rOVCSOUT = 2.0 V – 8.0 – Ω

Output Dynamic Range VCSOUT ICSOUT = –100 μA at top rail, 100 μA at bottom rail 0.075 – VDD –

0.25 V

Output Current, Sink Isink VCSOUT = 2.5 V 20 – – mA

Output Current, Source2Isource VCSOUT = 2.5 V –1.0 – – mA

VDD Supply Ripple Rejection PSRRVDD CSP = CSN = GND, frequency = 0 to 1 MHz 20 – – dB

VREG Supply Ripple Rejection PSRRVREG CSP = CSN = GND, frequency = 0 to 300 kHz 45 – – dB

Small Signal 3 dB Bandwidth BWf3db 10 mV input – 1.6 – MHz

AC Common Mode Attenuation A

VC(ac) Vcm = 250 mV(pp), frequency = 0 to 800 kHz 26 – – dB

Output Slew Rate (positive or negative) SR 200 mV step input, measured at 10/90% points 10 – – V/μs

Fault Logic

VDD Undervoltage VDD(uv) Decreasing VDD 3.8 – 4.3 V

VDD Undervoltage Hysteresis ∆VDD(uv) VDD(recovery) – VDD(uv) 100 – 300 mV

OVSET Operating Voltage Range VSET(ov) 0–V

DD V

OVSET Calibrated Voltage Range VSET(ov)cal 0 – 2.5 V

OVSET Input Current Range2ISET(ov) –1.0 – 1.0 μA

VBAT Overvoltage Range VBAT(ov)

0 V < VSET(ov) < 2.5 V 19.4 – 40 V

Increasing VBAT, VSET(ov) = 0 V 19.4 22.4 25.4 V

VBAT Overvoltage Hysteresis ∆VBAT(ov) Percent of VBAT(ov) value set by VSET(ov) 9.0 – 15 %

Continued on the next page…

3-Phase Power MOSFET Controller for Automotive Applications

A3935

Allegro MicroSystems, Inc.

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000

www.allegromicro.com

ELECTRICAL CHARACTERISTICS (continued) at TJ = –40°C to 150°C, VBAT = 7 to 16 V, VDD = 4.75 to 5.25 V,

ENABLE = 22.5 kHz, 50% duty cycle, two phases active;unless otherwise noted

Characteristics Symbol Conditions Min. Typ1. Max. Units

VBAT Overvoltage Gain Constant KBAT(ov)

VBAT(ov) = (KBAT(ov) x VSET(ov)) + VBAT(ov)(0);

VBAT(ov)(0) at VSET(ov) = 0 – 12 – V/V

VBAT Undervoltage VBAT(uv) Decreasing VBAT 5.0 5.25 5.5 V

VBAT Undervoltage Hysteresis VBAT(uv) Percent of VBAT(uv) 8.0 – 12 %

VREG Undervoltage VREG(uv) Decreasing VREG 9.9 – 11.1 V

VDSTH Input Range VDSTH 0.5 – 3.0 V

VDSTH Input Current IDSTH VDSTH > 0.8 V 40 – 100 μA

Short–to–Ground Threshold VSTG(th)

With a high–side driver on, as VSX decreases,

VDRAIN – VSx > VSTG causes a fault

VDSTH –

0.3 –VDSTH +

0.2 V

Short–to–Battery Threshold VSTB(th)

With a low–side driver on, as VSX increases,

VSx – VLSS > VSTB causes a fault

VDSTH –

0.3 –VDSTH +

0.2 V

VDRAIN-Open Bridge Operating Range VDRAIN 7 V < VBAT < 40 V –0.3 – VBAT +

2.0 V

VDRAIN-Open Bridge Current IVDRAIN 7 V < VBAT < 40 V 0 – 1.0 mA

VDRAIN /Open Bridge Threshold Voltage VBDGO(th) If VDRAIN < VBDGOTH then a bridge fault occurs 1.0 – 3.0 V

Thermal Shut Down Temperature TJ160 170 180 °C

Thermal Shutdown Hysteresis ∆TJ7.0 10 13 °C

1Typical data are for initial design estimations only, and assume optimum manufacturing and application conditions. Performance may vary for individual

units, within the specified maximum and minimum limits.

2Negative current is defined as coming out of (sourcing) the specified device terminal.

3For VBOOSTM < VBOOST < 40 V power dissipation in the VREG LDO increases. Observe TJ < 150°C limit.

4With VBOOST decreasing, dropout voltage measured at VREG = VREG(ref) – 200 mV where VREG(ref) = VREG at VBOOST = 16 V.

5For GHx: VSDU = VCx – VGHx, VDSL = VGHx – VSx, VDSL(H) = VCx – VSDU – VSx.

6For GLx: VSDU = VREG – VGLx, VDSL = VGLx – VLSS, VDSL(H) = VREG – VSDU – VLSS.

3-Phase Power MOSFET Controller for Automotive Applications

A3935

Allegro MicroSystems, Inc.

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000

www.allegromicro.com

Characteristic Symbol Test Conditions* Value Units

Package Thermal Resistance RθJA On 4-layer PCB, based on JEDEC standard 44 ºC/W

*Additional thermal information available on Allegro Web site.

Thermal Characteristics

50 75 100 125 15025

ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS

AMBIENT TEMPERATURE IN °C

5.0

1.0

2.0

3.0

4.0

θJA

= 44°C/W*

Power Dissipation versus Ambient Temperature

3-Phase Power MOSFET Controller for Automotive Applications

A3935

Allegro MicroSystems, Inc.

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000

www.allegromicro.com

Terminal Descriptions

AHI, BHI, and CHI. Direct control of high-side gate outputs

GHA, GHB, and GHC. Logic 1 drives the gate on. Logic 0 pulls

the gate down, turning off the external power MOSFET. Inter-

nally pulled down when the terminal is open.

ALO, BLO, and CLO. Direct control of low-side gate outputs

GHA, GHB, and GHC. Logic 1 drives the gate on. Logic 0 pulls

the gate down, turning off the external power MOSFET. Inter-

nally pulled down when the terminal is open.

BOOSTD. Boost converter switch drain connection.

BOOSTS. Boost converter switch source connection.

CA, CB, and CC. High-side connection for the bootstrap

capacitors, CBOOTx, positive supply for high-side gate drive.

The bootstrap capacitor is charged to VREG when the output Sx

terminal is low. When the output swings high, the voltage on this

terminal rises with the output to provide the boosted gate voltage

needed for N-channel power MOSFETs.

CSN. Input for current-sense differential amplifier, on the

inverting, negative side. Kelvin connection for the ground side of

the current-sense resistor, RSENSE.

CSOUT. Amplifier output voltage proportional to the current

sensed across an external low-value resistor placed in the ground

side of the power MOSFET bridge.

CSP. Input for current-sense differential amplifier, on the non-

inverting, positive side. Connected to the positive side of the

sense resistor, RSENSE.

ENABLE. Logic 0 disables the gate control signals and switches

off all the gate drivers (low) causing a coast condition. Can be

used in conjunction with the gate inputs to PWM (pulse wave

modulate) the load current. Internally pulled down when the

terminal is open.

¯F¯ ¯A¯ ¯U¯ ¯L¯ ¯T¯ . Diagnostic logic output signal. When low, indicates

that one or more fault conditions have occurred.

GHA, GHB, and GHC. High-side gate drive outputs for

N-channel MOSFET drivers. External series gate resistors can

control the slew rate seen at the power driver gate, thereby

controlling the di/dt and dv/dt of Sx outputs.

GLA, GLB, and GLC. Low-side gate drive outputs for external,

N-channel MOSFET drivers. External series gate resistors can

control slew rate.

GND. Ground, or negative, side of VDD and VBAT supplies.

LSS. Low-side gate driver return. Connects to the common

sources on the low sides of the power MOSFET bridge.

OVFLT. Logic 1 indicates that the VBAT level exceeded the

VBAT overvoltage trip point set by the OVSET level. It will

recover after exceeding a hysteresis below that maximum value.

Normally, it has a high-impedance state. If OVFLT and UVFLT

are both in high-impedance state; then, at least, a thermal

shutdown or VDD undervoltage has occurred.

OVSET. A positive dc level that controls the VBAT overvoltage

trip point. Usually, set by a precision resistor divider network

between VDD and GND, but can be held grounded for a preset

value. When this terminal is open, it sets an unspecified but high

overvoltage trip point.

SA, SB, and SC. Directly connected to the motor terminals,

these terminals sense the voltages switched across the load and

are connected to the negative side of the bootstrap capacitors,

CBOOTx. Also, are the negative supply connection for the

floating high-side drivers.

UVFLT. Logic 1 indicates that the VBAT level is below its

minimum value. It will recover after exceeding a hysteresis above

that minimum value. Has a high-impedance state. If UVFLT and

OVFLT are both in high-impedance state; then, at least, a thermal

shutdown or VDD undervoltage has occurred.

VBAT. Battery voltage. Positive input. usually connected to the

motor voltage supply.

VBOOST. Boost converter output, 16 V nominal, is also the

input to the regulator for VREG. Has internal boost-current

and boost-voltage control loops. In high-voltage systems is

approximately one diode drop below VBAT.

VDD. Logic supply, +5 V nominal.

VDRAIN. Kelvin connection for drain-to-source voltage monitor.

Connected to the high-side drains of the MOSFET bridge. High

impedance when this terminal is open, and registers as a short-to-

ground fault on all motor phases.

VDSTH. A positive dc level that sets the drain-to-source monitor

threshold voltage. Internally pulled down when this terminal is

open.

VREG. High-side gate driver supply, 13.5 V nominal. Has low-

voltage dropout (LDO) feature.

3-Phase Power MOSFET Controller for Automotive Applications

A3935

Allegro MicroSystems, Inc.

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000

www.allegromicro.com

Motor Lead Protection. A fault detection circuit monitors

the voltage across the drain-to-source of the external MOSFETs.

A fault is asserted low on the output terminal, ¯F¯ ¯A¯ ¯U¯ ¯L¯ ¯T¯ , if the

drain-to-source voltage of any MOSFET that is instructed to

turn on is greater than the voltage applied to the VDSTH input

terminal. When a high-side switch is turned on, the voltage from

VDRAIN to the appropriate motor phase output, VSX, is examined.

If the motor lead is shorted to ground before the high-side is

turned on, the measured voltage will exceed the threshold and

the ¯F¯ ¯A¯ ¯U¯ ¯L¯ ¯T¯ terminal will go low. Similarly, when a low-side

MOSFET is turned on, the differential voltage between the motor

phase (drain) and the LSS terminal (source) is monitored. VDSTH

is set by a resistor divider to VDD.

The VDRAIN is intended to be a Kelvin connection for the

high-side, drain-to-source monitor circuit. Voltage drops across

the power bus are eliminated by connecting an isolated PCB trace

from the VDRAIN terminal to the drain of the MOSFET bridge.

This allows improved accuracy in setting the VDSTH threshold

voltage. The low-side, drain-to-source monitor uses the LSS

terminal, rather than VDRAIN, for comparison with VDSTH.

The A3935 just reports these motor faults.

Fault Outputs. Transient faults on any of the fault outputs

are to be expected during switching, and will not disable the

gate drive outputs. External circuitry or controller logic must

determine if the faults represent a hazardous condition.

¯F¯ ¯A¯ ¯U¯ ¯L¯ ¯T¯ . This terminal will go active low when any of the follow-

ing conditions occur:

• VBAT overvoltage

• VBAT undervoltage

• VREG undervoltage

• Motor lead short-to-ground

• Motor lead short-to-supply

or short-to-battery

• Bridge (or VDRAIN) open

• VDD undervoltage

• Thermal shut down

OVFLT. Asserts high when a VBAT overvoltage fault occurs and

resets low after a recovery hysteresis. It has a high-impedance

state when a thermal shutdown or VDD undervoltage occurs. The

voltage at the OVSET terminal, VOVSET, controls the VBAT over-

voltage set point VBAT(ov), as follows:

VBAT(ov) = (ABAT(ov) × VSET(ov)) + VBAT(ov)(0),

where ABAT(ov) is the gain (12) and VBAT(ov)(0) is the value of

VBAT(ov) when VSET(ov) = 0 (VBAT(ov) ≈ 22.4). For the above

formula to be valid, all variables must be in range and below the

maximum operating specification.

UVFLT. Asserts high when a VBAT undervoltage fault occurs and

resets low after exceeding a recovery hysteresis. It has a high-

impedance state when a thermal shut down or VDD undervoltage

occurs. OVFLT and UVFLT are mutually exclusive by definition.

Current Sensing. A current-sense amplifier is provided to

allow system monitoring of the load current. The differential

amplifier inputs are intended to be Kelvin-connected across a

low-value sense resistor or current shunt. The output voltage is

represented by:

VCSOUT = ( ILOAD ×AV × RSENSE) + VOS

where VOS is the output voltage calibrated at zero load current

and A V is the differential amplifier gain of about 19.2. If either

the CSP or CSN pin is open, the CSOUT pin will go to its

maximum positive level.

Shut Down. If a fault occurs because of excessive junction

temperature or undervoltage on VDD or VBAT, all gate driver

outputs are driven low until the fault condition is removed. In

addition, the boost supply switch and VREG are turned off until

those undervoltages and junction temperatures recover.

Boost Supply. VBOOST is controlled by an inner current-

control loop, and by an outer voltage-feedback loop. The

current-control loop turns off the boost switch for 5 μs whenever

the voltage across the boost current-sense resistor exceeds

500 mV. A diode reverse-recovery current flows through the

sense resistor whenever the boost switch turns on, which could

result in turning off the switch again if not for the blanking-time

circuit. Adjustment of this external sense resistor determines the

maximum current in the inductor. Whenever VBOOST exceeds the

predefined threshold, 16 V nominal the boost switch is inhibited.

Functional Description

3-Phase Power MOSFET Controller for Automotive Applications

A3935

Allegro MicroSystems, Inc.

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000

www.allegromicro.com

Input Logic Table

Input Output Mode of Operation

ENABLE xLO xHI GLxGHx

0 Don’t Care Don’t Care 0 0 All gate drive outputs low

10000Both gate drive outputs low

10101High-side on

11010Low-side on

11100XOR circuitry prevents shoot-through

Fault Response Table

Operating Conditions Fault Output Regulator State Driver Output

Fault Mode ENABLE ¯F¯ ¯A¯ ¯U¯ ¯L¯ ¯T¯ OVFLT UVFLT Boost VREG GHxGLx

No Fault Don’t Care 1 0 0 ON ON aa

Short-to-Battery 1b000ONON

Short-to-Ground 1c000ONON

Bridge (VDRAIN) Fault 1d000ONON

VREG Undervoltage Don’t Care 0 0 0 ON ON aa

VBAT Overvoltage Don’t Care 0 1 0 OFFeON aa

VBAT UndervoltagefDon’t Care 0 0 1 OFF OFF 0 0

VDD UndervoltagefDon’t Care 0 High Z High Z OFF OFF 0 0

Thermal Shut DownfDon’t Care 0 High Z High Z OFF OFF 0 0

aDetermined by input states: xLO, xHI, and ENABLE. See Input Logic table.

bShort-to-battery can only be detected when the corresponding GLx = 1. This fault is not detected when ENABLE = 0.

cShort-to-ground can only be detected when the corresponding GHx = 1. This fault is not detected when ENABLE = 0.

dBridge fault appears as a short-to-ground fault on all motor phases. This fault is not detected when ENABLE = 0.

eOff only because VBOOST ≈ VBAT , which is above the voltage threshold of the Boost regulator voltage control loop.

fThese faults are not only reported, but also action is taken by the internal logic to protect the A3935 and the system.

3-Phase Power MOSFET Controller for Automotive Applications

A3935

Allegro MicroSystems, Inc.

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000

www.allegromicro.com

Number Name Function

1 CSP Current-sense input, positive-side

2 VDSTH DC input, drain-to-source monitor threshold voltage

3 LSS Gate-drive source return, low-side

4 GLC Gate-drive C output, low-side

5 SC Load phase C input

6 GHC Gate-drive C output, high-side

7 CC Bootstrap capacitor C

8 GLB Gate-drive B output, low-side

9 SB Load phase B input

10 GHB Gate-drive B output, high-side

11 CB Bootstrap capacitor B

12 GLA Gate-drive A output, low-side

13 SA Load phase A input

14 GHA Gate-drive A output, high-side

15 CA Bootstrap capacitor A

16 VREG Gate drive supply, positive

17 VDRAIN Kelvin connection to MOSFET high-side drains

18 VBOOST Boost supply output

Number Name Function

19 BOOSTS Boost switch, source

20 BOOSTD Boost switch, drain

21 GND Ground, dc supply returns, negative

22 VBAT Battery supply, positive

23 UVFLT VBAT undervoltage fault output

24 OVFLT VBAT overvoltage fault output

25 ¯F¯ ¯A¯ ¯U¯ ¯L¯ ¯T¯ Active-low fault output, primary

26 ALO Gate control input A, low-side

27 AHI Gate control input A, high-side

28 BHI Gate control input B, high-side

29 BLO Gate control input B, low-side

30 CLO Gate control input C, low-side

31 CHI Gate control input C, high-side

32 ENABLE Gate output enable

33 OVSET DC input, overvoltage threshold setting for VBAT

34 CSOUT Current-sense amplifier output

35 VDD Logic supply, nominally +5 V

36 CSN Current-sense input, negative-side

Pin-out Diagram

GLA

GHA

VREG

VDRAIN

VBOOST

ALO

FAULT

OVFLT

UVFLT

VBAT

GND

BOOSTD

BOOSTS

LSS

GLC

GHC

GLB

GHB

CSOUT1

OVSET

ENABLE

CHI

CLO

BLO

BHI

CSP

VDSTH

CSN

VDD

AHI

Terminal List

3-Phase Power MOSFET Controller for Automotive Applications

A3935

Allegro MicroSystems, Inc.

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000

www.allegromicro.com

Package LQ, 36-pin QSOP

SEATING

PLANE

15.30 ±0.10

10.31 ±0.307.50 ±0.10

0.20 ±0.10

2.64 MAX

A0.10

36X

(0.36)

0.60 0.80

9.50

2.15

(0.80)

4° ±4

0.28 +0.05

–0.04

0.84 +0.44

–0.43

0.40 +0.12

–0.11

GAGE PLANE

SEATING PLANE A

Terminal #1 mark area

For Reference Only

(QSOP, nonJEDEC standard)

Dimensions in millimeters

Dimensions exclusive of mold flash, gate burrs, and dambar protrusions

Exact case and lead configuration at supplier discretion within limits shown

Reference land pattern layout (reference IPC7351

SOP80P1033X264-36M); adjust as necessary to meet

application process requirements and PCB layout

tolerances. All pads a minimum of 0.20 mm from all

adjacent pads; adjust as necessary to meet application

process requirements and PCB layout tolerances

3-Phase Power MOSFET Controller for Automotive Applications

A3935

Allegro MicroSystems, Inc.

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000

www.allegromicro.com

Allegro MicroSystems, Inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to per-

mit improvements in the per for mance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the

information being relied upon is current.

Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the

failure of that life support device or system, or to affect the safety or effectiveness of that device or system.

The in for ma tion in clud ed herein is believed to be ac cu rate and reliable. How ev er, Allegro MicroSystems, Inc. assumes no re spon si bil i ty for its use;

nor for any in fringe ment of patents or other rights of third parties which may result from its use.

For the latest version of this document, visit our website:

www.allegromicro.com

Revision History

Revision Revision Date Description of Revision

Rev. J October 31, 2011 Update product availability