SN74ALVCH16601 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES027E - JULY 1995 - REVISED MAY 2000 D D D D D D D DGG OR DL PACKAGE (TOP VIEW) Member of the Texas Instruments Widebus Family UBT (Universal Bus Transceiver) Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, Clocked, or Clock-Enabled Mode EPIC (Enhanced-Performance Implanted CMOS) Submicron Process ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 250 mA Per JESD 17 Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors Package Options Include Plastic 300-mil Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages OEAB LEAB A1 GND A2 A3 VCC A4 A5 A6 GND A7 A8 A9 A10 A11 A12 GND A13 A14 A15 VCC A16 A17 GND A18 OEBA LEBA description This 18-bit universal bus transceiver is designed for 1.65-V to 3.6-V VCC operation. The SN74ALVCH16601 combines D-type latches and D-type flip-flops to allow data flow in transparent, latched, and clocked modes. 1 56 2 55 3 54 4 53 5 52 6 51 7 50 8 49 9 48 10 47 11 46 12 45 13 44 14 43 15 42 16 41 17 40 18 39 19 38 20 37 21 36 22 35 23 34 24 33 25 32 26 31 CLKENAB CLKAB B1 GND B2 B3 VCC B4 B5 B6 GND B7 B8 B9 B10 B11 B12 GND B13 B14 B15 VCC B16 B17 GND B18 CLKBA CLKENBA Data flow in each direction is controlled by 27 30 output-enable (OEAB and OEBA), latch-enable 28 29 (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. The clock can be controlled by the clock-enable (CLKENAB and CLKENBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is low, the A data is stored in the latch/flip-flop on the low-to-high transition of CLKAB. Output enable OEAB is active low. When OEAB is low, the outputs are active. When OEAB is high, the outputs are in the high-impedance state. Data flow for B to A is similar to that of A to B, but uses OEBA, LEBA, CLKBA, and CLKENBA. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. The SN74ALVCH16601 is characterized for operation from -40C to 85C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC, UBT, and Widebus are trademarks of Texas Instruments. Copyright 2000, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 SN74ALVCH16601 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES027E - JULY 1995 - REVISED MAY 2000 FUNCTION TABLE INPUTS LEAB CLKAB A OUTPUT B H X X X Z L H X L L CLKENAB OEAB X X X L H X H H H L L X X H L L X X B0 B0 L L L L L L L L H L L L H H B0 X B0 A-to-B data flow is shown; B-to-A flow is similar but uses OEBA, LEBA, and CLKBA. Output level before the indicated steady-state input conditions were established, provided that CLKAB was high before LEAB went low Output level before the indicated steady-state input conditions were established L 2 L L POST OFFICE BOX 655303 L X * DALLAS, TEXAS 75265 SN74ALVCH16601 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES027E - JULY 1995 - REVISED MAY 2000 logic diagram (positive logic) OEAB CLKENAB CLKAB LEAB LEBA CLKBA CLKENBA OEBA A1 1 56 55 2 28 30 29 27 CE 3 1D C1 CLK 54 B1 CE 1D C1 CLK To 17 Other Channels POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 3 SN74ALVCH16601 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES027E - JULY 1995 - REVISED MAY 2000 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 4.6 V Input voltage range, VI: Except I/O ports (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 4.6 V I/O ports (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Continuous current through each VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA Package thermal impedance, JA (see Note 3): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64C/W DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. This value is limited to 4.6 V maximum. 3. The package thermal impedance is calculated in accordance with JESD 51. recommended operating conditions (see Note 4) VCC Supply voltage VIH High-level input voltage VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VCC = 1.65 V to 1.95 V VIL VI VO IOH IOL t/v Low-level input voltage MIN MAX 1.65 3.6 2 0.35 x VCC 0.7 0 0 VCC = 1.65 V VCC = 2.3 V Low level output current Low-level VCC = 2.7 V VCC = 3 V Input transition rise or fall rate V 0.8 Output voltage VCC = 2.7 V VCC = 3 V V 1.7 Input voltage High level output current High-level V 0.65 x VCC VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VCC = 1.65 V VCC = 2.3 V UNIT VCC VCC V V -4 -12 -12 mA -24 4 12 12 mA 24 10 ns/V TA Operating free-air temperature -40 85 C NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 4 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN74ALVCH16601 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES027E - JULY 1995 - REVISED MAY 2000 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC 1.65 V to 3.6 V IOH = -100 A IOH = -4 mA 1.65 V IOH = -6 mA VOH IOH = -12 mA IOH = -24 mA IOL = 100 A IOZ ICC ICC Ci 2 2.3 V 1.7 2.7 V 2.2 3V 2.4 3V 2 UNIT V 0.2 2.3 V 0.4 2.3 V 0.7 2.7 V 0.4 3V 0.55 3.6 V 5 VI = 0.58 V VI = 1.07 V 1.65 V 25 1.65 V -25 VI = 0.7 V VI = 1.7 V 2.3 V 45 2.3 V -45 VI = 0.8 V VI = 2 V 3V 75 3V -75 V A A VI = 0 to 3.6 V 3.6 V 500 VO = VCC or GND VI = VCC or GND, 3.6 V 10 A 3.6 V 40 A 750 A One input at VCC - 0.6 V, Control inputs 2.3 V 0.45 IOL = 24 mA VI = VCC or GND II(hold) ( ) MAX VCC-0.2 1.2 1.65 V IOL = 12 mA II TYP 1.65 V to 3.6 V IOL = 4 mA IOL = 6 mA VOL MIN IO = 0 Other inputs at VCC or GND 3 V to 3.6 V VI = VCC or GND VO = VCC or GND 3.3 V 4 pF Cio A or B ports 3.3 V 8 pF All typical values are at VCC = 3.3 V, TA = 25C. This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another. For I/O ports, the parameter IOZ includes the input leakage current. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 5 SN74ALVCH16601 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES027E - JULY 1995 - REVISED MAY 2000 timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 through 3) VCC = 1.8 V MIN fclock Clock frequency Pulse duration tw tsu Setup time th Hold time MAX VCC = 2.5 V 0.2 V MIN MAX VCC = 2.7 V MIN 150 MAX VCC = 3.3 V 0.3 V MIN 150 150 LE high 3.3 3.3 3.3 CLK high or low 3.3 3.3 3.3 Data before CLK 2.3 2.4 2.1 CLK high 2 1.6 1.6 CLK low 1.3 1.2 1.1 CLKEN before CLK 2 2 1.7 Data after CLK 0.7 0.7 0.8 CLK high 1.3 1.6 1.4 CLK low 1.7 2 1.7 0.3 0.5 0.6 Data before LE Data after LE CLKEN after CLK UNIT MAX MHz ns ns ns This information was not available at the time of publication. switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 through 3) PARAMETER FROM (INPUT) TO (OUTPUT) A or B B or A VCC = 1.8 V MIN fmax tpd LEAB or LEBA CLKAB or CLKBA ten tdis OEAB or OEBA A or B A or B OEAB or OEBA A or B This information was not available at the time of publication. TYP VCC = 2.5 V 0.2 V MIN MAX 150 VCC = 2.7 V MIN MAX 150 VCC = 3.3 V 0.3 V MIN UNIT MAX 150 MHz 1 4 4.6 4.1 1 4.6 5.3 4.7 1.2 5.2 5.8 5 1.1 5.3 6.1 5.2 ns 1.4 4.9 4.8 4.4 ns ns operating characteristics, TA = 25C PARAMETER Cpd d Power dissipation capacitance TEST CONDITIONS Outputs enabled Outputs disabled CL = 50 pF, pF VCC = 1.8 V TYP f = 10 MHz This information was not available at the time of publication. 6 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 VCC = 2.5 V TYP VCC = 3.3 V TYP 41 52 6 6 UNIT pF SN74ALVCH16601 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES027E - JULY 1995 - REVISED MAY 2000 PARAMETER MEASUREMENT INFORMATION VCC = 1.8 V 2 x VCC S1 1 k From Output Under Test Open GND CL = 30 pF (see Note A) 1 k TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 2 x VCC GND LOAD CIRCUIT tw VCC Timing Input VCC/2 VCC/2 VCC/2 VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC/2 VCC/2 0V tPLH Output Control (low-level enabling) tPLZ VCC VCC/2 VCC/2 VOL Output Waveform 2 S1 at GND (see Note B) VOL + 0.15 V VOL tPHZ tPZH VOH VCC/2 0V Output Waveform 1 S1 at 2 x VCC (see Note B) tPHL VCC/2 VCC VCC/2 tPZL VCC Input VOLTAGE WAVEFORMS PULSE DURATION th VCC Data Input VCC/2 0V 0V tsu Output VCC Input VCC/2 VOH VOH - 0.15 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2 ns, tf 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 7 SN74ALVCH16601 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES027E - JULY 1995 - REVISED MAY 2000 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V 0.2 V 2 x VCC S1 500 From Output Under Test Open GND CL = 30 pF (see Note A) 500 TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 2 x VCC GND LOAD CIRCUIT tw VCC Timing Input VCC/2 VCC/2 VCC/2 VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC/2 VCC/2 0V tPLH Output Control (low-level enabling) tPLZ VCC VCC/2 VCC/2 VOL Output Waveform 2 S1 at GND (see Note B) VOL + 0.15 V VOL tPHZ tPZH VOH VCC/2 0V Output Waveform 1 S1 at 2 x VCC (see Note B) tPHL VCC/2 VCC VCC/2 tPZL VCC Input VOLTAGE WAVEFORMS PULSE DURATION th VCC Data Input VCC/2 0V 0V tsu Output VCC Input VCC/2 VOH VOH - 0.15 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2 ns, tf 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 2. Load Circuit and Voltage Waveforms 8 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN74ALVCH16601 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES027E - JULY 1995 - REVISED MAY 2000 PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V 0.3 V 6V S1 500 From Output Under Test Open GND CL = 50 pF (see Note A) 500 TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND tw LOAD CIRCUIT 2.7 V 2.7 V Timing Input Input 1.5 V 1.5 V 0V 1.5 V 0V tsu VOLTAGE WAVEFORMS PULSE DURATION th 2.7 V Data Input 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Output Control (low-level enabling) 2.7 V 1.5 V 1.5 V 0V tPLZ tPZL 2.7 V Input 1.5 V 1.5 V 0V tPLH tPHL 1.5 V 3V 1.5 V VOL + 0.3 V VOL tPHZ tPZH VOH Output Output Waveform 1 S1 at 6 V (see Note B) 1.5 V VOL Output Waveform 2 S1 at GND (see Note B) 1.5 V VOH VOH - 0.3 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2.5 ns, tf 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 3. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 9 MECHANICAL DATA MSSO001C - JANUARY 1995 - REVISED DECEMBER 2001 DL (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0.025 (0,635) 0.0135 (0,343) 0.008 (0,203) 48 0.005 (0,13) M 25 0.010 (0,25) 0.005 (0,13) 0.299 (7,59) 0.291 (7,39) 0.420 (10,67) 0.395 (10,03) Gage Plane 0.010 (0,25) 1 0-8 24 0.040 (1,02) A 0.020 (0,51) Seating Plane 0.110 (2,79) MAX 0.004 (0,10) 0.008 (0,20) MIN PINS ** 28 48 56 A MAX 0.380 (9,65) 0.630 (16,00) 0.730 (18,54) A MIN 0.370 (9,40) 0.620 (15,75) 0.720 (18,29) DIM 4040048 / E 12/01 NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). Falls within JEDEC MO-118 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 MECHANICAL DATA MTSS003D - JANUARY 1995 - REVISED JANUARY 1998 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0,27 0,17 0,50 48 0,08 M 25 6,20 6,00 8,30 7,90 0,15 NOM Gage Plane 1 0,25 24 0- 8 A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 48 56 64 A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 DIM 4040078 / F 12/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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