MC100ES6254FAR2 - Motorola / Freescale Semiconductor

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA Order Number: MC100ES6254/D

Rev 1, 05/2002

 Motorola, Inc. 2002

2.5/3.3V Differential LVPECL

2x2 Clock Switch and

Fanout Buffer

The Motorola MC100ES6254 is a bipolar monolithic differential 2x2

clock switch and fanout buffer. Designed for most demanding clock

distribution systems, the MC100ES6254 supports various applications

that require to drive precisely aligned clock signals. The device is capable

of driving and switching differential LVPECL signals. Using SiGe

technology and a fully differential architecture, the device offers superior

digitial signal characteristics and very low clock skew error. Target

applications for this clock driver are high performance clock/data

switching, clock distribution or data loopback in computing, networking

and telecommunication systems.

Features:

•Fully differential architecture from input to all outputs

•SiGe technology supports near-zero output skew

•Supports DC to 3GHz operation1 of clock or data signals

•LVPECL compatible dif ferential clock inputs and outputs

•LVCMOS compatible control inputs

•Single 3.3V or 2.5V supply

•50 ps maximum device skew1

•Synchronous output enable eliminating output runt pulse generation

and metastability

•Standard 32 lead LQFP package

•Industrial temperature range

Functional Description

MC100ES6254 is designed for very skew critical differential clock distribution systems and supports clock frequencies from

DC up to 3.0 GHz. Typical applications for the MC100ES6254 are primary clock distribution, switching and loopback systems of

high-performance computer, networking and telecommunication systems, as well as on-board clocking of OC-3, OC-12 and

OC-48 speed communication systems. Primary purpose of the MC100ES6254 is high–speed clock switching applications. In

addition, the MC100ES6254 can be configured as single 1:6 or dual 1:3 LVPECL fanout buffer for clock signals, or as loopback

device in high–speed data applications.

The MC100ES6254 can be operated from a 3.3V or 2.5V positive supply without the requirement of a negative supply line.

1. The device is functional up to 3 GHz and characterized up to 2.7 GHz.

FA SUFFIX

32–LEAD LQFP PACKAGE

CASE 873A

MC100ES6254

2.5V/3.3V DIFFERENTIAL

LVPECL 2x2

CLOCK SWITCH

AND FANOUT BUFFER

MC100ES6254

MOTOROLA TIMING SOLUTIONS2

Figure 1. MC100ES6254 Logic Diagram

QA2

VCC

QA1

QA0

QB2

VCC

QB1

VCC

GND

OEA

CLK0

SEL0

GND

VCC

GND

SEL1

CLK1

OEB

GND

VCC

12345678

24 23 22 21 20 19 18 17 16

MC100ES6254

Figure 2. 32–Lead Package Pinout (Top View)

VCC

QB0

QA0

QA1

OEB

QA2

QB0

QB1

QB2

CLK0

SEL1

SEL0

VCC Bank A

Bank B

QA0

QA1

QA2

QB0

QB1

QB2

QB0

QB1

QB2

QA0

QA1

QA2

Sync

CLK1

VCC

OEA

MC100ES6254

TIMING SOLUTIONS 3 MOTOROLA

TABLE 1: PIN CONFIGURATION

Pin I/O Type Function

CLK0, CLK0 Input LVPECL Differential reference clock signal input 0

CLK1, CLK1 Input LVPECL Differential reference clock signal input 1

OEA, OEB Input LVCMOS Output enable

SEL0, SEL1 Input LVCMOS Clock switch select

QA[0-2], QA[0-2]

QB[0-2], QB[0-2] Output LVPECL Differential clock outputs (banks A and B)

GND Supply GND Negative power supply

VCC Supply VCC Positive power supply. All VCC pins must be connected to the positive power supply for

correct DC and AC operation

TABLE 2: FUNCTION TABLE

Control Default 0 1

OEA 0 QA[0-2], Qx[0-2] are active. Deassertion of OE can

be asynchronous to the reference clock without

generation of output runt pulses

QA[0-2] = L, QA[0-2] =H (outputs disabled).

Assertion of OE can be asynchronous to the

reference clock without generation of output runt

pulses

OEB 0QA[0-2], Qx[0-2] are active. Deassertion of OE can

be asynchronous to the reference clock without

generation of output runt pulses

QA[0-2] = L, QA[0-2] =H (outputs disabled).

Assertion of OE can be asynchronous to the

reference clock without generation of output runt

pulses

SEL0, SEL1 00 See Table 3

TABLE 3: CLOCK SELECT CONTROL

SEL0 SEL1 CLK0 routed to CLK1 routed to Application Mode

0 0 QA[0:2] and QB[0:2] ––– 1:6 fanout of CLK0

0 1 ––– QA[0:2] and QB[0:2] 1:6 fanout of CLK1

1 0 QA[0:2] QB[0:2] Dual 1:3 buffer

1 1 QB[0:2] QA[0:2] Dual 1:3 buffer (crossed)

TABLE 4: ABSOLUTE MAXIMUM RATINGSa

Symbol Characteristics Min Max Unit Condition

VCC Supply Voltage -0.3 3.6 V

VIN DC Input Voltage -0.3 VCC+0.3 V

VOUT DC Output Voltage -0.3 VCC+0.3 V

IIN DC Input Current ±20 mA

IOUT DC Output Current ±50 mA

TSStorage temperature -65 125 °C

a. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur . Exposure to these conditions

or conditions beyond those indicated may adversely affect device reliability . Functional operation at absolute-maximum-rated conditions is not

implied.

MC100ES6254

MOTOROLA TIMING SOLUTIONS4

TABLE 5: GENERAL SPECIFICATIONS

Symbol Characteristics Min Typ Max Unit Condition

VTT Output termination voltage VCC - 2aV

MM ESD Protection (Machine model) 200 V

HBM ESD Protection (Human body model) 2000 V

CDM ESD Protection (Charged device model) 1500 V

LU Latch-up immunity 200 mA

CIN 4.0 pF Inputs

θJA Thermal resistance junction to ambient

JESD 51-3, single layer test board

JESD 51-6, 2S2P multilayer test board

83.1

73.3

68.9

63.8

57.4

59.0

54.4

52.5

50.4

47.8

86.0

75.4

70.9

65.3

59.6

60.6

55.7

53.8

51.5

48.8

°C/W

Natural convection

100 ft/min

200 ft/min

400 ft/min

800 ft/min

Natural convection

100 ft/min

200 ft/min

400 ft/min

800 ft/min

θJC Thermal resistance junction to case 23.0 26.3 °C/W MIL-SPEC 883E

Method 1012.1

Operating junction temperatureb

(continuous operation) MTBF = 9.1 years 110 °C

TFunc Functional temperature range TA=–40 TJ=+110 °C

a. Output termination voltage VTT = 0V for VCC=2.5V operation is supported but the power consumption of the device will increase.

b. Operating junction temperature impacts device life time. Maximum continuous operating junction temperature should be selected according

to the application life time requirements (See application note AN1545 and the application section in this datasheet for more information).

The device AC and DC parameters are specified up to 110°C junction temperature allowing the MC100ES6254 to be used in applications

requiring industrial temperature range. It is recommended that users of the MC100ES6254 employ thermal modeling analysis to assist in

applying the junction temperature specifications to their particular application.

TABLE 6: DC CHARACTERISTICS (VCC = 3.3V ± 5% or 2.5V ± 5%, TJ = 0° to +110°C)

Symbol Characteristics Min Typ Max Unit Condition

LVCMOS control inputs (OEA, OEB, SEL0, SEL1)

VIL Input voltage low 0.8 V

VIH Input voltage high 2.0 V

IIN Input Currenta±100 µA VIN = VCC or VIN = GND

LVPECL clock inputs (CLK0, CLK0, CLK1, CLK1)

VPP AC differential input voltageb0.1 1.3 V Differential operation

VCMR Differential cross point voltagec1.0 VCC-0.3 V Differential operation

LVPECL clock outputs (QA0-2, QA0-2, QB0-2, QB0-2)

VOH Output High Voltage VCC-1.2 VCC-1.005 VCC-0.7 V IOH = –30 mAd

VOL Output Low Voltage VCC=3.3V±5%

VCC=2.5V±5% VCC-1.9

VCC-1.9 VCC-1.705

VCC-1.705 VCC-1.5

VCC-1.3 V IOL = –5 mAe

IGND Maximum Quiescent Supply Current

without output termination current 52 85 mA GND pin

a. Input have internal pullup/pulldown resistors which affect the input current.

b. VPP is the minimum differential input voltage swing required to maintain AC characteristic.

c. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the V CMR (DC)

range and the input swing lies within the VPP (DC) specification.

d. Equivalent to a termination 50

to VTT.

e. ICC calculation: ICC = (number of differential output pairs used) * (IOH + IOL) + IGND

ICC = (number of differential output pairs used) * (VOH–VTT)

Rload +(VOL–VTT)

Rload) + IGND

MC100ES6254

TIMING SOLUTIONS 5 MOTOROLA

TABLE 7: AC CHARACTERISTICS (VCC = 3.3V ± 5% or 2.5V ± 5%, TJ = 0° to +110°C)a

Symbol Characteristics Min Typ Max Unit Condition

VPP Differential input voltage b (peak-to-peak) 0.3 1.3 V

VCMR Differential input crosspoint voltagec1.2 VCC-0.3 V

VO(P-P) Differential output voltage (peak-to-peak)

fO < 1.1 GHz

fO < 2.5 GHz

fO < 3.0 GHz

0.45

0.35

0.20

0.7

0.55

0.35

fCLK Input Frequency 0 3000dMHz

tPD Propagation delay CLK, 1 to QA[] or QB[] 485 360 610 ps Differential

tsk(O) Output-to-output skew 50 ps Differential

tsk(PP) Output-to-output skew (part-to-part) 250 ps Dif ferential

tSK(P)

DCO

Output pulse skewe

Output duty cycle tREF<100 MHz

tREF<800 MHz 49.4

45.2

50.6

54.8

%DCfref= 50%

DCfref= 50%

tJIT(CC) Output cycle-to-cycle jitter (SEL0 ≠ SEL1) TBD

tr, tfOutput Rise/Fall Time 0.05 300 ps 20% to 80%

tPDLf Output disable time 2.5⋅T + tPD 3.5⋅T + tPD ns T=CLK period

tPLDg Output enable time 3⋅T + tPD 4⋅T + tPD ns T=CLK period

a. AC characteristics apply for parallel output termination of 50Ω to VTT.

b. VPP is the minimum differential input voltage swing required to maintain AC characteristics including tpd and device-to-device ske w.

c. VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR (AC)

range and the input swing lies within the VPP (AC) specification. Violation of VCMR (AC) or VPP (AC) impacts the device propagation delay ,

device and part-to-part skew.

d. The MC100ES6254 is fully operational up to 3.0 GHz and is characterized up to 2.7 GHz.

e. Output pulse skew is the absolute difference of the propagation delay times: | tPLH - tPHL |.

f. Propagation delay OE deassertion to differential output disabled (differential low: true output low, complementary output high).

g. Propagation delay OE assertion to output enabled (active).

tPDL (OEX to Qx[])

Figure 3. MC100ES6254 output disable/enable timing

50%

tPLD (OEX to Qx[])

Outputs disabled

CLKX

OEX

Qx[]

Figure 4. MC100ES6254 AC test reference

Differential

Pulse Generator

Z = 50

RT = 50Ω

ZO = 50Ω

DUT

MC100ES6254

VTT

RT = 50Ω

ZO = 50Ω

VTT

MC100ES6254

MOTOROLA TIMING SOLUTIONS6

APPLICATIONS INFORMATION

Example Configurations

SEL0 SEL1 Switch configuration

0 0 CLK0 clocks system A and system B

0 1 CLK1 clocks system A and system B

1 0 CLK0 clocks system A and CLK1 clocks system B

1 1 CLK1 clocks system B and CLK1 clocks system A

CLK0

CLK1

SEL0

SEL1

System A

System B

MC100ES6254

2x2 clock switch

CLK0

CLK1

SEL0

SEL1

MC100ES6254

1:6 Clock Fanout Buffer

SEL0 SEL1 Switch configuration

0 0 System loopback

0 1 Line loopback

1 0 T ransmit / Receive operation

1 1 System and line loopback

CLK0

CLK1

SEL0

SEL1

Transmitter

Receiver

MC100ES6254

Loopback device

QA[]

System–Tx

System–Rx

QB[]

Understanding the junction temperature range of the

MC100ES6254

To make the optimum use of high clock frequency and low

skew capabilities of the MC100ES6254, the MC100ES6254

is specified, characterized and tested for the junction

temperature range of TJ=0°C to +110°C. Because the exact

thermal performance depends on the PCB type, design,

thermal management and natural or forced air convection,

the junction temperature provides an exact way to correlate

the application specific conditions to the published

performance data of this datasheet. The correlation of the

junction temperature range to the application ambient

temperature range and vice versa can be done by

calculation:

TJ = TA + Rthja ⋅ Ptot

Assuming a thermal resistance (junction to ambient) of

54.4 °C/W (2s2p board, 200 ft/min airflow , see table 4) and a

typical power consumption of 467 mW (all outputs terminated

50 ohms to VTT, VCC=3.3V, frequency independent), the

junction temperature of the MC100ES6254 is approximately

TA + 24.5 °C, and the minimum ambient temperature in this

example case calculates to -24.5 °C (the maximum ambient

temperature is 85.5 °C. See Table 8). Exceeding the

minimum junction temperature specification of the

MC100ES6254 does not have a significant impact on the

device functionality. However, the continuous use the

MC100ES6254 at high ambient temperatures requires

thermal management to not exceed the specified maximum

junction temperature. Please see the application note

AN1545 for a power consumption calculation guideline.

Table 8: Ambient temperature ranges (Ptot = 467 mW)

Rthja (2s2p board) TA, mina TA, max

Natural convection 59.0 °C/W -28 °C 82 °C

100 ft/min 54.4 °C/W -25 °C 85 °C

200 ft/min 52.5 °C/W -24.5 °C85.5 °C

400 ft/min 50.4 °C/W -23.5 °C 86.5 °C

800 ft/min 47.8 °C/W -22 °C88 °C

a. The MC100ES6254 device function is guaranteed from T A=-40 °C

to TJ=110 °C

Maintaining Lowest Device Skew

The MC100ES6254 guarantees low output-to-output bank

skew of 50 ps and a part-to-part skew of max. 250 ps. To

ensure low skew clock signals in the application, both outputs

of any differential output pair need to be terminated

identically, even if only one output is used. When fewer than

all nine output pairs are used, identical termination of all

output pairs within the output bank is recommended. If an

entire output bank is not used, it is recommended to leave all

of these outputs open and unterminated. This will reduce the

device power consumption while maintaining minimum

output skew.

MC100ES6254

TIMING SOLUTIONS 7 MOTOROLA

Power Supply Bypassing

The MC100ES6254 is a mixed analog/digital product. The

differential architecture of the MC100ES6254 supports low

noise signal operation at high frequencies. In order to

maintain its superior signal quality, all VCC pins should be

bypassed by high-frequency ceramic capacitors connected

to GND. If the spectral frequencies of the internally generated

switching noise on the supply pins cross the series resonant

point of an individual bypass capacitor , its overall impedance

begins to look inductive and thus increases with increasing

frequency. The parallel capacitor combination shown

ensures that a low impedance path to ground exists for

frequencies well above the noise bandwidth.

Figure 5. VCC Power Supply Bypass

VCC

MC100ES6254

VCC

33...100 nF 0.1 nF

MC100ES6254

MOTOROLA TIMING SOLUTIONS8

OUTLINE DIMENSIONS

FA SUFFIX

LQFP PACKAGE

CASE 873A-02

ISSUE A

ÉÉ

DETAIL Y

BASE

METAL

SECTION AE–AE

SEATING

PLANE

0.250 (0.010)

GAUGE PLANE

DETAIL AD

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DATUM PLANE –AB– IS LOCATED AT BOTTOM

OF LEAD AND IS COINCIDENT WITH THE LEAD

WHERE THE LEAD EXITS THE PLASTIC BODY AT

THE BOTTOM OF THE PARTING LINE.

4. DATUMS –T–, –U–, AND –Z– TO BE DETERMINED

AT DATUM PLANE –AB–.

5. DIMENSIONS S AND V TO BE DETERMINED AT

SEATING PLANE –AC–.

6. DIMENSIONS A AND B DO NOT INCLUDE MOLD

PROTRUSION. ALLOWABLE PROTRUSION IS

0.250 (0.010) PER SIDE. DIMENSIONS A AND B

DO INCLUDE MOLD MISMATCH AND ARE

DETERMINED AT DATUM PLANE –AB–.

7. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. DAMBAR PROTRUSION SHALL

NOT CAUSE THE D DIMENSION TO EXCEED

0.520 (0.020).

8. MINIMUM SOLDER PLATE THICKNESS SHALL BE

0.0076 (0.0003).

9. EXACT SHAPE OF EACH CORNER MAY VARY

FROM DEPICTION.

DIM

AMIN MAX MIN MAX

INCHES

7.000 BSC 0.276 BSC

MILLIMETERS

B7.000 BSC 0.276 BSC

C1.400 1.600 0.055 0.063

D0.300 0.450 0.012 0.018

E1.350 1.450 0.053 0.057

F0.300 0.400 0.012 0.016

G0.800 BSC 0.031 BSC

H0.050 0.150 0.002 0.006

J0.090 0.200 0.004 0.008

K0.500 0.700 0.020 0.028

M12 REF 12 REF

N0.090 0.160 0.004 0.006

P0.400 BSC 0.016 BSC

Q1 5 1 5

R0.150 0.250 0.006 0.010

V9.000 BSC 0.354 BSC

V1 4.500 BSC 0.177 BSC

____

DETAIL AD

B1 V1

B1 3.500 BSC 0.138 BSC

A1 3.500 BSC 0.138 BSC

S9.000 BSC 0.354 BSC

S1 4.500 BSC 0.177 BSC

W0.200 REF 0.008 REF

X1.000 REF 0.039 REF

–T–

–Z–

–U–

T–U0.20 (0.008) Z

T–U0.20 (0.008) ZAB

0.10 (0.004) AC

–AC–

–AB–

–T–, –U–, –Z–

T–U

0.20 (0.008) ZAC

MC100ES6254

TIMING SOLUTIONS 9 MOTOROLA

NOTES

MC100ES6254

MOTOROLA TIMING SOLUTIONS10

NOTES

MC100ES6254

TIMING SOLUTIONS 11 MOTOROLA

NOTES

MC100ES6254

MOTOROLA TIMING SOLUTIONS12

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Motorola, Inc. 2002.

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MC100ES6254/D

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