NOTE: For detailed information on purchasing options, contact your
local Allegro field applications engineer or sales representative.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, revisions to the anticipated product life cycle plan
for a product to accommodate changes in production capabilities, alternative product availabilities, or market demand. The
information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no respon-
sibility for its use; nor for any infringements of patents or other rights of third parties which may result from its use.
Recommended Substitutions:
Low Voltage Full Bridge Brushless DC Motor Driver with Hall Commutation and
Soft Switching, and Reverse Battery, Short Circuit, and Thermal Shutdown Protection
A1442
For existing customer transition, and for new customers or new appli-
cations, contact Allegro Sales.
This device is in production, however, it has been deemed Pre-End
of Life. The product is approaching end of life. Within a minimum of
6 months, the device will enter its final, Last Time Buy, order phase.
Date of status change: January 30, 2012
Description
The A1442 is a full-bridge motor driver designed to drive low-
voltage, brushless DC motors. Commutation of the motor is
achieved by use of a single Hall element to detect the rotational
position of an alternating-pole ring magnet. A high-density
CMOS semiconductor process allows the integration of all
the necessary electronics. This includes the Hall element, the
motor control circuitry, and the full output bridge. Low-voltage
design techniques have been employed to achieve full device
functionality down to low VDD values. This fully integrated
single chip solution provides enhanced reliability (including
reverse battery protection and output short circuit protection)
and eliminates the need for any external support components.
The A1442 employs a soft-switching algorithm to reduce audible
switching noise and EMI interference. A micropower sleep
mode can be enabled by an external signal, to reduce current
consumption for battery management in portable electronic
devices. This feature allows the removal of a FET transistor
for switching the device on and off.
The A1442 is optimized for vibration motor applications in
cellular phones, pagers, electronic toothbrushes, hand-held
video game controllers, and low power fan motors.
The small package outline and low profile make this device
ideally suited for use in applications where printed circuit board
area and component headroom are at a premium. It is available
in a lead (Pb) free, 6 pin MLP/DFN microleadframe package,
with an exposed pad for enhanced thermal dissipation.
A1442-DSW, Rev. 2
Features and Benefits
▪ Low voltage operation
▪ Reverse voltage protection on VDD and S
¯
¯
L
¯
¯
E
¯
¯
E
¯
¯
P
¯
pins
▪ Output short circuit and thermal shutdown protections
▪ Soft switching algorithm to reduce audible switching
noise and EMI interference
▪ Unidirectional working mode provides motor rotation in
one direction
▪ Hall chopper stabilization technique for precise signal
response over operating range
▪ Sleep mode pin allowing external logic signal enable/
disable to reduce average power consumption
▪ Antistall feature guarantees continuous rotation
▪ Low current consumption sleep mode
▪ Single-chip solution for high reliability
▪ Miniature MLP/DFN package
Low Voltage Full Bridge Brushless DC Motor Driver with Hall Commutation and
Soft Switching, and Reverse Battery, Short Circuit, and Thermal Shutdown Protection
Package: 6 pin MLP/DFN (suffix EW)
Functional Block Diagram
Approximate scale
A1442
1.5 mm × 2 mm, 0.40 mm maximum overall height
Am
Hall
Element
p
Reverse Battery
Power and Sleep
Mode Control
Active Braking
Control
Stall Detection
Drive Logic
and
Soft Switching
Control
GND
VDD
VOUT1
Output
Full Bridge
Q1 Q3
Q2
Q4
SLEEP
VOUT2
Thermal Shutdown
Protection
M
0.1 μF
Low Voltage Full Bridge Brushless DC Motor Driver
with Hall Commutation and Soft Switching,
and Reverse Battery, Short Circuit, and Thermal Shutdown Protection
A1442
2
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Absolute Maximum Ratings
Characteristic Symbol Notes Rating Units
Forward Supply Voltage VDD 5.0 V
Reverse Supply Voltage VRDD –5.0 V
Output Voltage VOUT VDD > 0 V 0 to VDD + 0.3 V
Reverse Output Voltage VROUT VDD > 0 V –0.3 V
¯
S
¯
¯
L
¯
¯
E
¯
¯
E
¯
¯
P
¯
Input Voltage VIN 0 to VDD + 0.3 V
Peak Output Current IOUTpk < 1 ms ±400 mA
Operating Ambient Temperature TA Range E –40 to 85 ºC
Junction Temperature TJ(max) 165 ºC
StorageTemperature Tstg –65 to 165 ºC
Selection Guide
Part Number Package1Packing
A1442EEWLT-P2MLP/DFN 1.5 mm × 2 mm, 0.4 mm maximum overall height 3000 pieces / 7 in. reel
1Contact Allegro® for additional packing options.
2Allegro products sold in DFN package types are not intended for automotive applications.
Pin-out Diagram Terminal List Table
Pin Name Function
1 VDD Supply voltage
2¯
S
¯
¯
L
¯
¯
E
¯
¯
E
¯
¯
P
¯ Toggle sleep/enabled modes
3 NC No connection
4 GND Ground
5 VOUT1 First output
6 VOUT2 Second output
VDD
SLEEP
NC
VOUT2
VOUT1
GND
PAD
6
5
4
1
2
3
Low Voltage Full Bridge Brushless DC Motor Driver
with Hall Commutation and Soft Switching,
and Reverse Battery, Short Circuit, and Thermal Shutdown Protection
A1442
3
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
OPERATING CHARACTERISTICS valid over the full VDD and TA range unless otherwise noted
Characteristic Symbol Test Conditions Min. Typ. Max. Units
Supply Voltage1VDD Operating, TJ < TJ(max); CBYP = 0.1 μF 2.0 – 4.2 V
Supply Current IDD(ON)
VIN >VINHI, , TA = 25°C, no load –4 6mA
VIN < VINLO , TA = 25°C –– 10A
Total Output On Resistance2,3 RDS(on)
VDD = 2 V, IOUT = 70 mA, TA = 25°C – 3.9 – Ω
VDD = 3 V, IOUT = 70 mA, TA = 25°C – 2.6 – Ω
VDD = 4 V, IOUT = 70 mA, TA = 25°C – 2.2 – Ω
Reverse Battery Current IRDD VRDD = –4.2 V – – –10 mA
Sleep Input Threshold VINHI 0.7×VDD –V
VINLO – – 0.2×VDD V
Sleep Input Current IIN VIN = 3.0 V – 1.0 5 A
Reverse Sleep Current IRIN VRIN = –4.2 V – – –10 mA
Restart Delay4tRS – 120 – ms
Hall Chopping Settling Time tS(CHOP) –80 – s
Magnetic Switchpoints2
BOP –35 75G
BRP –75 -35 – G
BHYS –70 – G
Output Polarity
VOUT1
B < BRP – LOW – V
B > BOP – HIGH – V
VOUT2
B < BRP – HIGH – V
B > BOP – LOW – V
1 A bypass capacitor of 0.1 μF is required between VDD and GND for proper device operation through the full specified voltage range.
2 Extended VDD range affects RDS(on) and Bx.
3 Total On Resistance equals either RDS(on)Q1 + RDS(on)Q4 or RDS(on)Q2 + RDS(on)Q3.
4 The Restart Delay is the time the outputs are on or off when the device is attempting a restart.
Low Voltage Full Bridge Brushless DC Motor Driver
with Hall Commutation and Soft Switching,
and Reverse Battery, Short Circuit, and Thermal Shutdown Protection
A1442
4
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Functional Description
Soft Switching The A1442 device includes a soft-switch-
ing algorithm that controls the output switching slew rate for
both output pins. As a result the A1442 device is ideal for use in
applications requiring low audible switching noise and low EMI
interference.
Sleep Mode The S
¯
¯
L
¯
¯
E
¯
¯
E
¯
¯
P
¯
pin accepts an external signal that
enables sleep mode. In sleep mode, the current consumption is
reduced to an extremely low level, conserving battery power in
portable electronics.
Antistall Algorithm If a stall condition occurs, the device will
execute an antistall algorithm.
Device Start-up The start-up behavior of the device output
is determined by the applied magnetic field, as specified in the
Operating Characteristics table.
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
VDD (V)
RDS(on) (Ω)
Total Output On-Resistance versus Supply Voltage
ILOAD = 150 mA
Characteristic Performance
Low Voltage Full Bridge Brushless DC Motor Driver
with Hall Commutation and Soft Switching,
and Reverse Battery, Short Circuit, and Thermal Shutdown Protection
A1442
5
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Application Information
Two typical application circuits are shown in figures 4 and 5. The
first application circuit shows the device S
¯
¯
L
¯
¯
E
¯
¯
E
¯
¯
P
¯
pin controlled
by the user. Figure 5 illustrates an application circuit where the
device VDD and S
¯
¯
L
¯
¯
E
¯
¯
E
¯
¯
P
¯
pin are connected together.
Note that:
No external diode is required for reverse battery protection
because the protection is fully integrated into the IC.
Thermal shutdown is integrated also.
A bypass capacitor of 0.1 μF is required between VDD and GND
for proper device operation through the full specified supply volt-
age range.
M
+
V
BATT
CBYP
A1442
NC
VDD
I/O
System Logic
Control
GND
VOUT1
SLEEP VOUT2
Figure 4. Application circuit showing user-controlled sleep/enable mode, while the
A1442 remains powered at all times
M
+
V
BATT
CBYP
A1442
NC
VDD
I/O
System Logic
Control
GND
VOUT1
SLEEP VOUT2
Figure 4. Application circuit showing simultaneous user control of power supply and
sleep mode.
Low Voltage Full Bridge Brushless DC Motor Driver
with Hall Commutation and Soft Switching,
and Reverse Battery, Short Circuit, and Thermal Shutdown Protection
A1442
6
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Power Derating
M
+
V
BATT
CBYP
0.1 μF
A1442
NC
VDD
IDD
I/O
System Logic
Control
GND
VOUT1
IL
SLEEP VOUT2
Figure 4. Typical application showing current paths
The device must be operated below the maximum junction tem-
perature of the device, TJ(max). Under certain combinations of
peak conditions, reliable operation may require derating supplied
power or improving the heat dissipation properties of the appli-
cation. This section presents a procedure for correlating factors
affecting operating TJ. (Thermal data is also available on the
Allegro MicroSystems Web site.) The package thermal resistance,
RθJA, is a figure of merit summarizing the ability of the appli-
cation and the device to dissipate heat from the junction (die),
through all paths to the ambient air. Its primary component is the
effective thermal conductivity, K, of the printed circuit board,
including adjacent devices and traces. Radiation from the die
through the device case, RθJC, is relatively small component of
RθJA. Ambient air temperature, TA, and air motion are significant
external factors, damped by overmolding. The effect of varying
power levels (power dissipation, PD) can be estimated. The fol-
lowing formulas represent the fundamental relationships used to
estimate TJ at given levels of PD.
Given:
P
D = VIN × IIN , (1)
ΔT = PD × RθJA , and (2)
T
J = TA + ΔT (3)
For a load of 30 Ω, given common conditions such as: TA= 25°C,
VDD = 3 V, IDD = 83 mA, VL = 2.43 V, IL = 81 mA and RθJA =
250 °C/W, then:
P
D = VDD × IDD – VLIL
= 3 V × 83 mA – 2.43 V × 81 mA = 52.17 mW ,
ΔT = PD × RθJA
= 52.17 mW × 250 °C/W = 13°C , and
TJ = TA + ΔT = 25°C + 13°C = 38°C
A worst-case estimate, PD(max), represents the maximum allow-
able power level, without exceeding TJ(max), at a selected RθJA
and TA.
Low Voltage Full Bridge Brushless DC Motor Driver
with Hall Commutation and Soft Switching,
and Reverse Battery, Short Circuit, and Thermal Shutdown Protection
A1442
7
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Package EW, 6 pin MLP/DFN
SEATING
PLANE
0.38 ±0.02
0.70 ±0.10 1.25 ±0.05
0.25 ±0.05
1.10 ±0.10
1.10
0.30
0.70 1.575
0.50
0.325
2.00 ±0.15
1.50 ±0.15
C0.08
7X
0.325 +0.055
–0.045
0.50 BSC
A
1
1
6
6
1
6
ATerminal #1 mark area
BExposed thermal pad (reference only, terminal #1
identifier appearance at supplier discretion)
For Reference Only, not for tooling use (refernce DWG-2856; similar to
JEDEC Type 1, MO-229X2BCD)
Dimensions in millimeters
Exact case and lead configuration at supplier discretion within limits shown
CReference land pattern layout (reference IPC7351
SON50P200X200X100-9M);
All pads a minimum of 0.20 mm from all adjacent pads; adjust as
necessary to meet application process requirements and PCB layout
tolerances; when mounting on a multilayer PCB, thermal vias at the
exposed thermal pad land can improve thermal dissipation (reference
EIA/JEDEC Standard JESD51-5)
Active Area Depth 0.15 mm REF
E
E
C
B
Hall Element (not to scale)
F
FF
F
0.89
0.99
PCB Layout Reference View
C
Branding scale and appearance at supplier discretion
G
G
D
DCoplanarity includes exposed thermal pad and terminals
Standard Branding Reference View
N = Last two digits of device part number
Y = Last digit of year of manufacture
W = Week of manufacture
NN
YWW
1
Low Voltage Full Bridge Brushless DC Motor Driver
with Hall Commutation and Soft Switching,
and Reverse Battery, Short Circuit, and Thermal Shutdown Protection
A1442
8
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
For the latest version of this document, visit our website:
www.allegromicro.com
Copyright ©2006-2011, Allegro MicroSystems, Inc.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to per-
mit improvements in the per for mance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the
information being relied upon is current.
Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the
failure of that life support device or system, or to affect the safety or effectiveness of that device or system.
The in for ma tion in clud ed herein is believed to be ac cu rate and reliable. How ev er, Allegro MicroSystems, Inc. assumes no re spon si bil i ty for its use;
nor for any in fringe ment of patents or other rights of third parties which may result from its use.
Revision History
Revision Revision Date Description of Revision
Rev. 2 October 26, 2011 Update Selection Guide
