Low Skew, 1-to-9
LVCMOS/LVTTL Fanout Buffer 83947I-147
Data Sheet
©2016 Integrated Device Technology, Inc Revision A March 18, 20161
GENERAL DESCRIPTION
The 83947I-147 is a low skew, 1-to-9 LVCMOS/LVTTL
Fanout Buffer. The low impedance LVCMOS/LVTTL outputs
are designed to drive 50 series or parallel terminated
transmission lines. The effective fanout can be increased from
9 to 18 by utilizing the ability of the outputs to drive two series
terminated lines.
Guaranteed output and part-to-part skew characteristics make
the 83947I-147 ideal for high performance, 3.3V or 2.5V single
ended applications.
BLOCK DIAGRAM PIN ASSIGNMENT
FEATURES
Nine LVCMOS/LVTTL outputs
Selectable CLK0 and CLK1 can accept the following
input levels: LVCMOS and LVTTL
Maximum output frequency: 250MHz
Output skew: 115ps (maximum)
Part-to-part skew: 500ps (maximum)
Additive phase jitter, RMS: 0.02ps (typical) @ 3.3V
Full 3.3V or 2.5V operating supply
-40°C to 85°C ambient operating temperature
Lead-free (RoHS 6) packaging
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
32 31 30 29 28 27 26 25
9 10 11 12 13 14 15 16
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
GND
Q3
VDDO
Q4
GND
Q5
VDDO
GND
GND
CLK_SEL
CLK0
CLK1
CLK_EN
OE
VDD
GND
GND
Q6
VDDO
Q7
GND
Q8
VDDO
GND
GND
Q2
VDDO
Q1
GND
Q0
VDDO
GND
ICS83947I-147
83947I-147 Data Sheet
©2016 Integrated Device Technology, Inc Revision A March 18, 20162
TABLE 1. PIN DESCRIPTIONS
TABLE 2. PIN CHARACTERISTICS
TABLE 3. OUTPUT ENABLE AND CLOCK ENABLE FUNCTION TABLE
Number Name Type Description
1, 8, 9, 12, 16, 17, 20,
24, 25, 29, 32 GND Power Power supply ground.
2 CLK_SEL Input Pullup Clock select input. When HIGH, selects CLK1. When LOW,
selects CLK0. LVCMOS / LVTTL interface levels.
3, 4 CLK0, CLK1 Input Pullup Reference clock inputs. LVCMOS / LVTTL interface levels.
5 CLK_EN Input Pullup Clock enable. LVCMOS / LVTTL interface levels.
6 OE Input Pullup Output enable. LVCMOS / LVTTL interface levels.
7V
DD Power Core supply pin.
10, 14, 18, 22, 27, 31 VDDO Power Output supply pins.
11, 13, 15, 19, 21, 23,
26, 28, 30
Q8, Q7, Q6, Q5, Q4,
Q3, Q2, Q1, Q0 Output Q0 thru Q8 clock outputs.
LVCMOS / LVTTL interface levels.
NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Control Inputs Output
OE CLK_EN Q0:Q8
0 X Hi-Z
1 0 LOW
1 1 Follows CLK input
Symbol Parameter Test Conditions Minimum Typical Maximum Units
CIN Input Capacitance 4 pF
CPD
Power Dissipation Capacitance
(per output) 12 pF
RPULLUP Input Pullup Resistor 51 KΩ
ROUT Output Impedance 7 Ω
83947I-147 Data Sheet
©2016 Integrated Device Technology, Inc Revision A March 18, 20163
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 3.3V±0.3V OR 2.5V±5%, TA = -40°C TO 85°C
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDO = 3.3V±0.3V, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VDD Core Supply Voltage 3.0 3.3 3.6 V
2.375 2.5 2.625 V
VDDO Output Supply Voltage 3.0 3.3 3.6 V
2.375 2.5 2.625 V
IDD Input Supply Current 50 mA
IDDO Output Supply Current 9mA
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
DD 4.6V
Inputs, VI -0.5V to VDD + 0.5 V
Outputs, VO -0.5V to VDDO + 0.5V
Package Thermal Impedance, θ
JA 47.9°C/W (0 lfpm)
Storage Temperature, T
STG -65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifi cations only. Functional
operation of product at these conditions or any conditions
beyond those listed in the DC Characteristics or AC Charac-
teristics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDO = 2.5V±5%, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VIH Input High Voltage 2 VDD + 0.3 V
VIL Input Low Voltage CLK0, CLK1 -0.3 1.3 V
CLK_SEL, CLK_EN, OE -0.3 0.8 V
IIH Input High Current CLK0, CLK1, OE, CLK_
SEL, CLK_EN VDD = VIN = 2.625V 5 µA
IIL Input Low Current CLK0, CLK1, OE, CLK_
SEL, CLK_EN
VDD = 32.625V,
VIN = 0V -150 µA
VOH Output High Voltage; NOTE 1 1.8 V
VOL Output Low Voltage; NOTE 1 0.5 V
NOTE 1: Outputs terminated with 50Ω to VDDO/2. See Parameter Measurement Information Section, 2.5V Output Load Test
Circuit Diagram.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VIH Input High Voltage 2 3.6 V
VIL Input Low Voltage 0.8 V
IIN Input Current CLK0, CLK1, OE,
CLK_SEL, CLK_EN -100 µA
VOH Output High Voltage; NOTE 1 IOH = -20mA 2.5 V
VOL Output Low Voltage; NOTE 1 IOL = 20mA 0.4 V
NOTE 1: Outputs terminated with 50Ω to VDDO/2. See Parameter Measurement Information Section, 3.3V Output Load Test
Circuit Diagram.
83947I-147 Data Sheet
©2016 Integrated Device Technology, Inc Revision A March 18, 20164
TABLE 5A. AC CHARACTERISTICS, VDD = VDDO = 3.3V±0.3V, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
fMAX Output Frequency 250 MHz
tPD Propagation Delay, NOTE 1 f 250MHZ 2 4.2 ns
tsk(o) Output Skew; NOTE 2, 5 Measured on
rising edge @VDDO/2 115 ps
tsk(pp) Part-to-Part Skew; NOTE 3, 5 Measured on
rising edge @VDDO/2 500 ps
tjit(Ø)
Buffer Additive Phase Jitter,
RMS; refer to Additive Phase
Jitter Section
(12KHz to 20MHz)
0.2 ps
tR / tFOutput Rise/Fall Time 0.8V to 2.0V 0.2 1 ns
tPW Output Pulse Width f > 133MHz tPeriod/2 - 1 tPeriod/2 + 1 ns
odc Output Duty Cycle f 133MHz 40 60 %
tEN Output Enable Time; NOTE 4 10 ns
tDIS Output Disable Time; NOTE 4 10 ns
tSClock Enable Setup Time 0 ns
tSClock Enable Hold Time 1 ns
All parameters measured at frequencies less than or equal to 250MHz unless noted otherwise.
NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output.
NOTE 2: Defi ned as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 3: Defi ned as skew between outputs on different devices operating at the same supply voltages and with
equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2.
NOTE 4: These parameters are guaranteed by characterization. Not tested in production.
NOTE 5: This parameter is defi ned in accordance with JEDEC Standard 65.
TABLE 5B. AC CHARACTERISTICS, VDD = VDDO = 2.5V ± 5%, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
fMAX Output Frequency 250 MHz
tPD Propagation Delay, NOTE 1 f 250MHZ 2.4 4.5 ns
tsk(o) Output Skew; NOTE 2, 5 Measured on
rising edge @VDDO/2 130 ps
tsk(pp) Part-to-Part Skew; NOTE 3, 5 Measured on
rising edge @VDDO/2 600 ps
tjit(Ø)
Buffer Additive Phase Jitter,
RMS; refer to Additive Phase
Jitter Section
(12KHz to 20MHz) 0.1 ps
tR / tFOutput Rise/Fall Time 20% - 80% 300 800 ps
tPW Output Pulse Width tPeriod/2 - 1.2 tPeriod/2 + 1.2 ns
tEN Output Enable Time; NOTE 4 10 ns
tDIS Output Disable Time; NOTE 4 10 ns
tSClock Enable Setup Time 0 ns
tSClock Enable Hold Time 1 ns
All parameters measured at frequencies less than or equal to 250MHz unless noted otherwise.
NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output.
NOTE 2: Defi ned as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 3: Defi ned as skew between outputs on different devices operating at the same supply voltages and with
equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2.
NOTE 4: These parameters are guaranteed by characterization. Not tested in production.
NOTE 5: This parameter is defi ned in accordance with JEDEC Standard 65.
83947I-147 Data Sheet
©2016 Integrated Device Technology, Inc Revision A March 18, 20165
ADDITIVE PHASE JITTER
The spectral purity in a band at a specifi c offset from the fun-
damental compared to the power of the fundamental is called
the dBc Phase Noise. This value is normally expressed using
a Phase noise plot and is most often the specifi ed plot in many
applications. Phase noise is defi ned as the ratio of the noise
power present in a 1Hz band at a specifi ed offset from the fun-
damental frequency to the power value of the fundamental. This
ratio is expressed in decibels (dBm) or a ratio of the power in the
As with most timing specifi cations, phase noise measurements
have issues. The primary issue relates to the limitations of the
equipment. Often the noise fl oor of the equipment is higher
than the noise fl oor of the device. This is illustrated above. The
1Hz band to the power in the fundamental. When the required
offset is specifi ed, the phase noise is called a dBc value, which
simply means dBm at a specifi ed offset from the fundamental.
By investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the
entire time record of the signal. It is mathematically possible to
calculate an expected bit error rate given a phase noise plot.
device meets the noise fl oor of what is shown, but can actually
be lower. The phase noise is dependant on the input source and
measurement equipment.
Additive Phase Jitter, RMS @
156.25MHz (12KHz to 20MHz)
= 0.01ps typical @ 2.5V
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
1k 10k 100k 1M 10M 100M
OFFSET FROM CARRIER FREQUENCY (HZ)
SSB PHASE NOISE dBc/HZ
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
1k 10k 100k 1M 10M 100M
OFFSET FROM CARRIER FREQUENCY (HZ)
SSB PHASE NOISE dBc/HZ
Additive Phase Jitter, RMS @
156.25MHz (12KHz to 20MHz)
= 0.02ps typical @ 3.3V
83947I-147 Data Sheet
©2016 Integrated Device Technology, Inc Revision A March 18, 20166
PARAMETER MEASUREMENT INFORMATION
2.5V OUTPUT LOAD AC TEST CIRCUIT3.3V OUTPUT LOAD AC TEST CIRCUIT
PART-TO-PART SKEW
PROPAGATION DELAY OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
OUTPUT SKEW
3.3V OUTPUT RISE/FALL TIME 2.5V OUTPUT RISE/FALL TIME
83947I-147 Data Sheet
©2016 Integrated Device Technology, Inc Revision A March 18, 20167
APPLICATION SCHEMATIC EXAMPLE
Figure 1 shows an example of 83947I-147 application sche-
matic. In this example, the device is operated at VCC=3.3V. The
decoupling capacitors should be located as close as possible
to the power pin. The input is driven by a 3.3V LVCMOS driver.
C4
0.1u
VCC
Zo = 50 Ohm
R3 43
R2 43
R1 43
C2
0.1u
(U1-22)
C3
0.1u
C1
0.1u
C3
0.1u
(U1-10)
VDDO
(U1-18)
C5
0.1u
VDDO
(U1-14)
Zo = 50
U1
ICS83947I-147
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
32
31
30
29
28
27
26
25
GND
CLK_SEL
CLK0
CLK1
CLK_EN
OE
VDD
GND
GND
VDDO
Q8
GND
Q7
VDDO
Q6
GND
GND
VDDO
Q5
GND
Q4
VDDO
Q3
GND
GND
VDDO
Q0
GND
Q1
VDDO
Q2
GND
VCC
VDD=3.3V
LVCMOS
Zo = 50
Zo = 50 Ohm
(U1-27)
VDD
V DDO=3.3V
LVCMOS
C2
0.1u
(U1-31)
R3 43
For the LVCMOS output drivers, only one termination example
is shown in this schematic. Additional termination approaches
are shown in the LVCMOS Termination Application Note (refer
to ICS website).
FIGURE 1. 83947I-147 SCHEMATIC LAYOUT
83947I-147 Data Sheet
©2016 Integrated Device Technology, Inc Revision A March 18, 20168
RELIABILITY INFORMATION
TRANSISTOR COUNT
The transistor count for 83947I-147 is: 1040
TABLE 6. θJAVS. AIR FLOW TABLE FOR 32 LEAD LQFP
θJA by Velocity (Linear Feet per Minute)
0 200 500
Single-Layer PCB, JEDEC Standard Test Boards 67.8°C/W 55.9°C/W 50.1°C/W
Multi-Layer PCB, JEDEC Standard Test Boards 47.9°C/W 42.1°C/W 39.4°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
83947I-147 Data Sheet
©2016 Integrated Device Technology, Inc Revision A March 18, 20169
PACKAGE OUTLINE - Y SUFFIX FOR 32 LEAD LQFP
TABLE 7. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
SYMBOL
BBA
MINIMUM NOMINAL MAXIMUM
N32
A-- -- 1.60
A1 0.05 -- 0.15
A2 1.35 1.40 1.45
b0.30 0.37 0.45
c0.09 -- 0.20
D9.00 BASIC
D1 7.00 BASIC
D2 5.60 Ref.
E9.00 BASIC
E1 7.00 BASIC
E2 5.60 Ref.
e0.80 BASIC
L0.45 0.60 0.75
θ0°-- 7°
ccc -- -- 0.10
Reference Document: JEDEC Publication 95, MS-026
83947I-147 Data Sheet
©2016 Integrated Device Technology, Inc Revision A March 18, 201610
TABLE 8. ORDERING INFORMATION
Part/Order Number Marking Package Shipping Packaging Temperature
83947AYI-147LF ICS947AI147L Lead-Free, 32 Lead LQFP Tray -40°C to 85°C
83947AYI-147LFTICS947AI147L Lead-Free, 32 Lead LQFP Tape & Reel -40°C to 85°C
83947I-147 Data Sheet
©2016 Integrated Device Technology, Inc Revision A March 18, 201611
REVISION HISTORY SHEET
Rev Table Page Description of Change Date
AT8 10
12
Updated datasheet’s header/footer with IDT from ICS.
Removed ICS prefi x from Part/Order Number column.
Added Contact Page.
8/12/10
AT8 10
Ordering Information Table - added lead-free ordering information.
Deleted non lead-free ordering information. Deleted tape & reel count. 2/27/13
ARemoved ICS from part numbers where needed.
Updated header and footer. 3/18/16
83947I-147 Data Sheet
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