

HIGH BANDWIDTH
SINGLE SUPPLY
OPERATIONAL AMPLIFIERS
Order this document by MC34071/D
D SUFFIX
PLASTIC PACKAGE
CASE 751
(SO–8)
P SUFFIX
PLASTIC PACKAGE
CASE 626
D SUFFIX
PLASTIC PACKAGE
CASE 751A
(SO–14)
P SUFFIX
PLASTIC PACKAGE
CASE 646
PIN CONNECTIONS
(Single, Top View)
(Dual, Top View)
Offset Null
VEE
NC
VCC
Output
Offset Null
Inputs
VEE
Inputs 1 Inputs 2
Output 2
Output 1 VCC
Inputs 1
Output 1
VCC
Inputs 2
Output 2
Output 4
Inputs 4
VEE
Inputs 3
Output 3
(Quad, Top View)
4
2
3
1
Inputs 3
–
1
2
3
4
8
7
6
5
–
–
+
+
1
2
3
4
8
7
6
5
PIN CONNECTIONS
1
2
3
4
5
6
78
9
10
11
12
13
14
+
–
+–
+
+
–+
–
1
81
8
14
114 1
1
MOTOROLA ANALOG IC DEVICE DATA
 "   
"   !#
  
Quality bipolar fabrication with innovative design concepts are employed
for the MC33071/72/74, MC34071/72/74 series of monolithic operational
amplifiers. This series of operational amplifiers offer 4.5 MHz of gain
bandwidth product, 13 V/µs slew rate and fast setting time without the use of
JFET device technology. Although this series can be operated from split
supplies, it is particularly suited for single supply operation, since the
common mode input voltage range includes ground potential (VEE). With A
Darlington input stage, this series exhibits high input resistance, low input
offset voltage and high gain. The all NPN output stage, characterized by no
deadband crossover distortion and large output voltage swing, provides high
capacitance drive capability, excellent phase and gain margins, low open
loop high frequency output impedance and symmetrical source/sink AC
frequency response.
The MC33071/72/74, MC34071/72/73 series of devices are available in
standard or prime performance (A Suffix) grades and are specified over the
commercial, industrial/vehicular or military temperature ranges. The
complete series of single, dual and quad operational amplifiers are available
in plastic DIP and SOIC surface mount packages.
•Wide Bandwidth: 4.5 MHz
•High Slew Rate: 13 V/µs
•Fast Settling Time: 1.1 µs to 0.1%
•Wide Single Supply Operation: 3.0 V to 44 V
•Wide Input Common Mode Voltage Range: Includes Ground (VEE)
•Low Input Offset Voltage: 3.0 mV Maximum (A Suffix)
•Large Output Voltage Swing: –14.7 V to +14 V (with ±15 V Supplies)
•Large Capacitance Drive Capability: 0 pF to 10,000 pF
•Low Total Harmonic Distortion: 0.02%
•Excellent Phase Margin: 60°
•Excellent Gain Margin: 12 dB
•Output Short Circuit Protection
•ESD Diodes/Clamps Provide Input Protection for Dual and Quad
ORDERING INFORMATION
Op Amp
Function Device Operating
Temperature Range Package
Single MC34071P, AP
MC34071D, AD TA = 0° to +70°CPlastic DIP
SO–8
MC33071P, AP
MC33071D, AD TA = –40° to +85°CPlastic DIP
SO–8
Dual MC34072P, AP
MC34072D, AD TA = 0° to +70°CPlastic DIP
SO–8
MC33072P, AP
MC33072D, AD TA = –40° to +85°CPlastic DIP
SO–8
Quad MC34074P, AP
MC34074D, AD TA = 0° to +70°CPlastic DIP
SO–14
MC33074P, AP
MC33074D, AD TA = –40° to +85°CPlastic DIP
SO–14
Motorola, Inc. 1996 Rev 0
MC34071,2,4,A MC33071,2,4,A
2MOTOROLA ANALOG IC DEVICE DATA
MAXIMUM RATINGS
Rating Symbol Value Unit
Supply Voltage (from VEE to VCC) VS+44 V
Input Differential Voltage Range VIDR Note 1 V
Input Voltage Range VIR Note 1 V
Output Short Circuit Duration (Note 2) tSC Indefinite sec
Operating Junction Temperature TJ+150 °C
Storage Temperature Range Tstg –60 to +150 °C
NOTES: 1.Either or both input voltages should not exceed the magnitude of VCC or VEE.
2.Power dissipation must be considered to ensure maximum junction temperature (TJ) is not
exceeded (see Figure 1).
Offset Null
(MC33071, MC34071 only)
Q1
Q2
Q3 Q4 Q5 Q6 Q7
Q17
Q18
D2
C2 D3
R6 R7
R8
R5
Q15 Q16
Q14
Q13
Q11
Q10
R2
C1
R1
Q9
Q8
Q12
D1
R3 R4
Inputs
VCC
Output
Current
Limit
VEE/Gnd
Base
Current
Cancellation
–
+Q19
Bias
Representative Schematic Diagram
(Each Amplifier)
MC34071,2,4,A MC33071,2,4,A
3
MOTOROLA ANALOG IC DEVICE DATA
ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = –15 V, RL = connected to ground, unless otherwise noted. See Note 3 for
TA = Tlow to Thigh)
A Suffix Non–Suffix
Characteristics Symbol Min Typ Max Min Typ Max Unit
Input Offset Voltage (RS = 100 Ω, VCM = 0 V, VO = 0 V)
VCC = +15 V, VEE = –15 V, TA = +25°C
VCC = +5.0 V, VEE = 0 V, TA = +25°C
VCC = +15 V, VEE = –15 V, TA = Tlow to Thigh
VIO —
—
—0.5
0.5
—
3.0
3.0
5.0
—
—
—1.0
1.5
—
5.0
5.0
7.0
mV
Average Temperature Coef ficient of Input Offset V oltage
RS = 10 Ω, VCM = 0 V, VO = 0 V,
TA = Tlow to Thigh
∆VIO/∆T — 10 — — 10 — µV/°C
Input Bias Current (VCM = 0 V, VO = 0 V)
TA = +25°C
TA = Tlow to Thigh
IIB —
—100
—500
700 —
—100
—500
700
nA
Input Offset Current (VCM = 0 V, VO = 0V)
TA = +25°C
TA = Tlow to Thigh
IIO —
—6.0
—50
300 —
—6.0
—75
300
nA
Input Common Mode Voltage Range
TA = +25°C
TA = Tlow to Thigh
VICR VEE to (VCC –1.8)
VEE to (VCC –2.2) VEE to (VCC –1.8)
VEE to (VCC –2.2)
V
Large Signal Voltage Gain (VO = ±10 V, RL = 2.0 kΩ)
TA = +25°C
TA = Tlow to Thigh
AVOL 50
25 100
——
—25
20 100
——
—
V/mV
Output Voltage Swing (VID = ±1.0 V)
VCC = +5.0 V, VEE = 0 V, RL = 2.0 kΩ, TA = +25°C
VCC = +15 V, VEE = –15 V, RL = 10 kΩ, TA = +25°C
VCC = +15 V, VEE = –15 V, RL = 2.0 kΩ,
TA = Tlow to Thigh
VOH 3.7
13.6
13.4
4.0
14
—
—
—
—
3.7
13.6
13.4
4.0
14
—
—
—
—
V
VCC = +5.0 V, VEE = 0 V, RL = 2.0 kΩ, TA = +25°C
VCC = +15 V, VEE = –15 V, RL = 10 kΩ, TA = +25°C
VCC = +15 V, VEE = –15 V, RL = 2.0 kΩ,
TA = Tlow to Thigh
VOL —
—
—
0.1
–14.7
—
0.3
–14.3
–13.5
—
—
—
0.1
–14.7
—
0.3
–14.3
–13.5
V
Output Short Circuit Current (VID = 1.0 V, VO = 0 V,
TA = 25°C)
Source
Sink
ISC
10
20 30
30 —
—10
20 30
30 —
—
mA
Common Mode Rejection
RS ≤ 10 kΩ, VCM = VICR, TA = 25°CCMR 80 97 — 70 97 — dB
Power Supply Rejection (RS = 100 Ω)
VCC/VEE = +16.5 V/–16.5 V to +13.5 V/–13.5 V,
TA = 25°C
PSR 80 97 — 70 97 — dB
Power Supply Current (Per Amplifier, No Load)
VCC = +5.0 V, VEE = 0 V, VO = +2.5 V, TA = +25°C
VCC = +15 V, VEE = –15 V, VO = 0 V, TA = +25°C
VCC = +15 V, VEE = –15 V, VO = 0 V,
TA = Tlow to Thigh
ID—
—
—
1.6
1.9
—
2.0
2.5
2.8
—
—
—
1.6
1.9
—
2.0
2.5
2.8
mA
NOTES: 3.Tlow = –40°C for MC33071, 2, 4, /A Thigh = +85°C for MC33071, 2, 4, /A
=0°C for MC34071, 2, 4, /A = +70°C for MC34071, 2, 4, /A
MC34071,2,4,A MC33071,2,4,A
4MOTOROLA ANALOG IC DEVICE DATA
AC ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = –15 V, RL = connected to ground. TA = +25°C, unless otherwise noted.)
A Suffix Non–Suffix
Characteristics Symbol Min Typ Max Min Typ Max Unit
Slew Rate (Vin = –10 V to +10 V, RL = 2.0 kΩ, CL = 500 pF)
AV = +1.0
AV = –1.0
SR 8.0
—10
13 —
—8.0
—10
13 —
—
V/µs
Setting Time (10 V Step, AV = –1.0)
To 0.1% (+1/2 LSB of 9–Bits)
To 0.01% (+1/2 LSB of 12–Bits)
ts—
—1.1
2.2 —
——
—1.1
2.2 —
—
µs
Gain Bandwidth Product (f = 100 kHz) GBW 3.5 4.5 — 3.5 4.5 — MHz
Power Bandwidth
AV = +1.0, RL = 2.0 kΩ, VO = 20 Vpp, THD = 5.0% BW — 160 — — 160 — kHz
Phase margin
RL = 2.0 kΩ
RL = 2.0 kΩ, CL = 300 pF
fm—
—60
40 —
——
—60
40 —
—
Deg
Gain Margin
RL = 2.0 kΩ
RL = 2.0 kΩ, CL = 300 pF
Am—
—12
4.0 —
——
—12
4.0 —
—
dB
Equivalent Input Noise Voltage
RS = 100 Ω, f = 1.0 kHz en— 32 — — 32 — nV/ Hz√
Equivalent Input Noise Current
f = 1.0 kHz in— 0.22 — — 0.22 — pA/ Hz√
Differential Input Resistance
VCM = 0 V Rin —150 — — 150 — MΩ
Differential Input Capacitance
VCM = 0 V Cin —2.5 — — 2.5 — pF
Total Harmonic Distortion
AV = +10, RL = 2.0 kΩ, 2.0 Vpp ≤ VO ≤ 20 Vpp, f = 10 kHz THD — 0.02 — — 0.02 — %
Channel Separation (f = 10 kHz) — — 120 — — 120 — dB
Open Loop Output Impedance (f = 1.0 MHz) |ZO| — 30 — — 30 — W
Figure 1. Power Supply Configurations Figure 2. Offset Null Circuit
Single Supply Split Supplies
1
2
3
4
VCC
VEE
VCC
VCC
VEE
VEE
1
2
3
4
3.0 V to 44 V VCC+|VEE|
≤
44 V
Offset nulling range is approximately
±
80 mV with a 10 k
potentiometer (MC33071, MC34071 only).
VCC
VEE
1
2
3
4
5
6
7
10 k
+
–
MC34071,2,4,A MC33071,2,4,A
5
MOTOROLA ANALOG IC DEVICE DATA
RL Connected
to Ground TA = 25
°
C
RL = 10 k RL = 2.0 k
VO, OUTPUT VOLTAGE SWING (Vpp)
Figure 3. Maximum Power Dissipation versus
Temperature for Package Types Figure 4. Input Offset Voltage versus
Temperature for Representative Units
Figure 5. Input Common Mode Voltage
Range versus Temperature Figure 6. Normalized Input Bias Current
versus Temperature
Figure 7. Normalized Input Bias Current versus
Input Common Mode Voltage Figure 8. Split Supply Output Voltage
Swing versus Supply Voltage
TA, AMBIENT TEMPERATURE (
°
C)
D
P , MAXIMUM POWER DISSIPATION (mW)
–55 –40 –20 0 20 40 60 80 100 120 140 160
8 & 14 Pin Plastic Pkg
SO–14 Pkg
SO–8 Pkg
TA, AMBIENT TEMPERATURE (
°
C)
IO
V , INPUT OFFSET VOLT AGE (mV)
–55 –25 0 25 50 75 100 125
VCC = +15 V
VEE = –15 V
VCM = 0
TA, AMBIENT TEMPERATURE (
°
C)
ICR
V , INPUT COMMON MODE VOLTAGE RANGE (V)
–55 –25 0 25 50 75 100 125
VCC VCC/VEE = +1.5 V/ –1.5 V to +22 V/ –22 V
VEE
TA, AMBIENT TEMPERATURE (
°
C)
IB
I , INPUT BIAS CURRENT (NORMALIZED)
–55 –25 0 25 50 75 100 125
VCC = +15 V
VEE = –15 V
VCM = 0
VIC, INPUT COMMON MODE VOLT AGE (V)
–12 –8.0 –4.0 0 4.0 8.0 12
VCC = +15 V
VEE = –15 V
TA = 25
°
C
VCC, |VEE|, SUPPLY VOLTAGE (V)
0 5.0 10 15 20 25
V
IB
I , INPUT BIAS CURRENT (NORMALIZED)
2400
2000
1600
1200
800
400
0
4.0
2.0
0
–2.0
–4.0
VCC
VCC –0.8
VCC –1.6
VCC –2.4
VEE +0.01
VEE
1.3
1.2
1.1
1.0
0.9
0.8
0.7
1.4
1.2
1.0
0.8
0.6
50
40
30
20
10
0
MC34071,2,4,A MC33071,2,4,A
6MOTOROLA ANALOG IC DEVICE DATA
VCC
VCC = +15 V
RL to VCC
TA = 25
°
C
Gnd
VCC
VCC = +15 V
RL = Gnd
TA = 25
°
C
Gnd
VO, OUTPUT VOLTAGE SWING (Vpp)
Figure 9. Single Supply Output Saturation
versus Load Resistance to VCC
60
Figure 10. Split Supply Output Saturation
versus Load Current
Figure 11. Single Supply Output Saturation
versus Load Resistance to Ground Figure 12. Output Short Circuit Current
versus Temperature
Figure 13. Output Impedance
versus Frequency Figure 14. Output Voltage Swing
versus Frequency
0 5.0 10 15 20
IL, LOAD CURRENT (
±
mA)
VCC
VEE
Sink
VCC/VEE = +5.0 V/ –5.0 V to +22 V/ –22 V
TA = 25
°
C
Source
RL, LOAD RESISTANCE TO GROUND (
Ω
)
100 1.0 k 10 k 100 k
sat
V , OUTPUT SATURATION VOLTAGE (V)
RL, LOAD RESISTANCE TO VCC (
Ω
)
100 1.0 k 10 k 100 k TA, AMBIENT TEMPERATURE (
°
C)
SC
I , OUTPUT CURRENT (mA)
–55 –25 0 25 50 75 100 125
VCC = +15 V
VEE = –15 V
RL
≤
0.1
Ω
∆
Vin = 1.0 V
Sink
Source
f, FREQUENCY (Hz)
O
Z , OUTPUT IMPEDANCE ( )
Ω
1.0 k 10 k 100 1.0 M 10 M
AV = 1000 AV = 100 AV = 10 AV = 1.0
VCC = +15 V
VEE = –15 V
VCM = 0
VO = 0
∆
IO =
±
0.5 mA
TA = 25
°
C
f, FREQUENCY (Hz)
3.0 k 10 k 30 k 100 k 300 k 1.0 M 3.0 M
VCC = +15 V
VEE = –15 V
AV = +1.0
RL = 2.0 k
THD
≤
1.0%
TA = 25
°
C
sat
V , OUTPUT SATURATION VOLTAGE (V)
sat
V , OUTPUT SATURATION VOLTAGE (V)
VCC
VCC –1.0
VCC –2.0
VEE +2.0
VEE +1.0
VEE
VCC –2.0
VCC –4.0
VCC
0.2
0.1
0
0
–0.4
–0.8
2.0
1.0
50
40
30
20
10
0
50
40
30
20
10
0
28
24
20
16
12
8.0
4.0
0
MC34071,2,4,A MC33071,2,4,A
7
MOTOROLA ANALOG IC DEVICE DATA
1. Phase RL = 2.0 k
2. Phase RL = 2.0 k, CL = 300 pF
3. Gain RL = 2.0 k
4. Gain RL = 2.0 k, CL = 300 pF
VCC = +15 V
VEE = 15 V
VO = 0 V TA = 25
°
C
Phase
Margin = 60
°
Gain
Margin = 12 dB
3
4
1
2
Gain
VCC = +15 V
VEE = –15 V
VO = 0 V
RL = 2.0 k
TA = 25
°
C
Phase
Phase
Margin
= 60
°
Figure 15. Total Harmonic Distortion
versus Frequency Figure 16. Total Harmonic Distortion
versus Output Voltage Swing
Figure 17. Open Loop Voltage Gain
versus Temperature Figure 18. Open Loop Voltage Gain and
Phase versus Frequency
Figure 19. Open Loop Voltage Gain and
Phase versus Frequency Figure 20. Normalized Gain Bandwidth
Product versus Temperature
f, FREQUENCY (Hz)
10 100 1.0 k 10 k 100 k
AV = 1000
AV = 100
AV = 10 AV = 1.0
VCC = +15 V
VEE = –15 V
VO = 2.0 Vpp
RL = 2.0 k
TA = 25
°
C
VO, OUTPUT VOLTAGE SWING (Vpp)
THD, TOTAL HARMONIC DIST ORTION (%)
0 4.0 8.0 12 16 20
VCC = +15 V
VEE = –15 V
RL = 2.0 k
TA = 25
°
C
AV = 1000
AV = 100
AV = 10
AV = 1.0
TA, AMBIENT TEMPERATURE (
°
C)
–55 –25 0 25 50 75 100 125
VCC = +15 V
VEE = –15 V
VO= –10 V to +10 V
RL = 10 k
f
≤
10Hz
f, FREQUENCY (Hz)
1.0 10 100 1.0 k 10 k 100 k 1.0 M 10 M 100 M
, EXCESS PHASE (DEGREES)
φ
, EXCESS PHASE (DEGREES)
φ
f, FREQUENCY (MHz)
1.0 2.0 3.0 5.0 7.0 10 20 30 TA, AMBIENT TEMPERATURE (
°
C)
GBW, GAIN BANDWIDTH PRODUCT (NORMALIED)
–55 –25 0 25 50 75 100 125
VCC = +15 V
VEE = –15 V
RL = 2.0 k
VOL
A , OPEN LOOP VOLTAGE GAIN (dB)
0.4
0.3
0.2
0.1
0
4.0
3.0
2.0
1.0
0
116
112
108
104
100
96
100
80
60
40
20
0
20
10
0
–10
–20
–30
–40
1.15
1.1
1.05
1.0
0.95
0.9
0.85
0
45
90
135
180
100
120
140
160
180
THD, TOTAL HARMONIC DIST ORTION (%)
VOL
A , OPEN LOOP VOLTAGE GAIN (dB)
VOL
A , OPEN LOOP VOLTAGE GAIN (dB)
MC34071,2,4,A MC33071,2,4,A
8MOTOROLA ANALOG IC DEVICE DATA
VCC = +15 V
VEE = –15 V
AV = +1.0
RL = 2.0 k to
R
VO = –10 V to +10 V
TA = 25
°
C
Figure 21. Percent Overshoot versus
Load Capacitance Figure 22. Phase Margin versus
Load Capacitance
Figure 23. Gain Margin versus Load Capacitance Figure 24. Phase Margin versus Temperature
Figure 25. Gain Margin versus Temperature Figure 26. Phase Margin and Gain Margin
versus Differential Source Resistance
PERCENT OVERSHOOT
CL, LOAD CAPACITANCE (pF)
10 100 1.0 k 10 k
VCC = +15 V
VEE = –15 V
RL = 2.0 k
VO = –10 V to +10 V
TA = 25
°
C
CL, LOAD CAPACITANCE (pF)
, PHASE MARGIN (DEGREES)
φ
m
10 100 1.0 k 10 k
VCC = +15 V
VEE = –15 V
AV = +1.0
RL = 2.0 k to
∞
VO = –10 V to +10 V
TA = 25
°
C
CL, LOAD CAPACITANCE (pF)
m
A , GAIN MARGIN (dB)
10 100 1.0 k 10 k
, PHASE MARGIN (DEGREES)
φ
m
TA, AMBIENT TEMPERATURE (
°
C)
–55 –25 0 25 50 75 100 125
VCC = +15 V
VEE = –15 V
AV = +1.0
RL = 2.0 k to
∞
VO = –10 V to +10 V
CL = 10 pF
CL = 100 pF
CL = 1,000 pF
CL = 10,000 pF
TA, AMBIENT TEMPERATURE (
°
C)
–55 –25 0 25 50 75 100 125
VCC = +15 V
VEE = –15 V
AV = +1.0
RL = 2.0 k to
∞
VO = –10 V to +10 V
CL = 10 pF
CL = 1,000 pF
m
A , GAIN MARGIN (dB)
CL = 100 pF
CL = 10,000 pF Phase
m
A , GAIN MARGIN (dB)
RT, DIFFERENTIAL SOURCE RESISTANCE (
Ω
)
1.0 100 1.0 k 10 k10 100 k
R1
R2
VO
+
–
VCC = +15 V
VEE = –15 V
RT = R1 + R2
AV = +100
VO = 0 V
TA = 25
°
C
Gain
, PHASE MARGIN (DEGREES)
φ
m
100
80
60
40
20
0
70
60
50
40
30
20
10
0
14
12
10
8.0
6.0
2.0
0
4.0
80
60
40
20
0
16
12
8.0
4.0
0
12
10
8.0
6.0
4.0
2.0
0
60
50
40
30
20
10
0
70
MC34071,2,4,A MC33071,2,4,A
9
MOTOROLA ANALOG IC DEVICE DATA
Figure 27. Normalized Slew Rate
versus Temperature Figure 28. Output Settling Time
Figure 29. Small Signal Transient Response Figure 30. Large Signal Transient Reponse
Figure 31. Common Mode Rejection
versus Frequency Figure 32. Power Supply Rejection
versus Frequency
TA, AMBIENT TEMPERATURE (
°
C)
SR, SLEW RATE (NORMALIZED)
–55 –25 0 25 50 75 100 125
VCC = +15 V
VEE = –15 V
AV = +1.0
RL = 2.0 k
CL = 500 pF
ts, SETTLING TIME (
µ
s)
O
V , OUTPUT VOLTAGE SWING FROM 0 V (V)
∆
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
VCC = +15 V
VEE = –15 V
AV = –1.0
TA = 25
°
C
10 mV 1.0 mV 1.0 mV
Compensated
Uncompensated
10 mV 1.0 mV
1.0 mV
50 mV/DIV
2.0
µ
s/DIV
VCC = +15 V
VEE = –15 V
AV = +1.0
RL = 2.0 k
CL = 300 pF
TA = 25
°
C
5.0 V/DIV
1.0
µ
s/DIV
f, FREQUENCY (Hz)
CMR, COMMON MODE REJECTION (dB)
0.1 1.0 10 100 1.0 k 10 k 100 k 1.0 M 10 M
TA = 25
°
CTA = 125
°
C
TA = –55
°
C
VCC = +15 V
VEE = –15 V
VCM = 0 V
∆
VCM =
±
1.5 V
f, FREQUENCY (Hz)
PSR, POWER SUPPLY REJECTION (dB)
0.1 1.0 10 100 1.0 k 10 k 100 k 1.0 M 10 M
VCC = +15 V
VEE = –15 V
TA = 25
°
C
(
∆
VCC = +1.5 V)
(
∆
VEE = +1.5 V)
+PSR
–PSR
VCC = +15 V
VEE = –15 V
AV = +1.0
RL = 2.0 k
CL = 300 pF
TA = 25
°
C
1.15
1.1
1.05
1.0
0.95
0.9
0.85
10
5.0
0
–5.0
–10
00
100
80
60
40
20
0
100
80
60
40
20
0
∆
VCM
∆
VO
ADM
CMR = 20 Log
∆
VCM
∆
VOx ADM
+
–
∆
VO
ADM
+
–
∆
VCC
∆
VEE
∆
VO/ADM
∆
VCC
+PSR = 20 Log
∆
VO/ADM
∆
VEE
–PSR = 20 Log
MC34071,2,4,A MC33071,2,4,A
10 MOTOROLA ANALOG IC DEVICE DATA
Figure 33. Supply Current versus
Supply Voltage Figure 34. Power Supply Rejection
versus Temperature
Figure 35. Channel Separation versus Frequency Figure 36. Input Noise versus Frequency
VCC, |VEE|, SUPPLY VOLTAGE (V)
CC
I , SUPPLY CURRENT (mA)
0 5.0 10 15 20 25
TA = 25
°
C
TA = 125
°
C
TA = –55
°
C
TA, AMBIENT TEMPERATURE (
°
C)
PSR, POWER SUPPLY REJECTION (dB)
–55 –25 0 25 50 75 100 125
VCC = +15 V
VEE = –15 V
(
∆
VCC = +1.5 V)
(
∆
VEE = +1.5 V)
+PSR
–PSR
f, FREQUENCY (kHz)
CHANNEL SEPARATION (dB)
10 20 30 50 70 100 200 300
VCC = +15 V
VEE = –15 V
TA = 25
°
C
f, FREQUENCY (kHz)
n
e , INPUT NOICE VOLTAGE (
i , INPUT NOISE CURRENT (pA )
10 100 1.0 k 10 k 100 k
nV Hz )
√
Hz
√
n
Voltage
Current
9.0
8.0
7.0
6.0
5.0
4.0
105
95
85
75
65
120
100
80
60
40
20
0
70
60
50
40
30
20
10
0
2.8
2.4
2.0
1.6
1.2
0.8
0.4
0
∆
VO
ADM
+
–
∆
VCC
∆
VEE
∆
VO/ADM
∆
VCC
+PSR = 20 Log
∆
VO/ADM
∆
VEE
–PSR = 20 Log
VCC = +15 V
VEE = –15 V
VCM = 0
TA = 25
°
C
APPLICATIONS INFORMATION
CIRCUIT DESCRIPTION/PERFORMANCE FEATURES
Although the bandwidth, slew rate, and settling time of the
MC34071 amplifier series are similar to op amp products
utilizing JFET input devices, these amplifiers offer other
additional distinct advantages as a result of the PNP
transistor differential input stage and an all NPN transistor
output stage.
Since the input common mode voltage range of this input
stage includes the VEE potential, single supply operation is
feasible to as low as 3.0 V with the common mode input
voltage at ground potential.
The input stage also allows differential input voltages up to
±44 V, provided the maximum input voltage range is not
exceeded. Specifically, the input voltages must range
between VEE and VCC supply voltages as shown by the
maximum rating table. In practice, although not
recommended, the input voltages can exceed the VCC
voltage by approximately 3.0 V and decrease below the VEE
voltage by 0.3 V without causing product damage, although
output phase reversal may occur . It is also possible to source
up to approximately 5.0 mA of current from VEE through
either inputs clamping diode without damage or latching,
although phase reversal may again occur.
If one or both inputs exceed the upper common mode
voltage limit, the amplifier output is readily predictable and
may be in a low or high state depending on the existing input
bias conditions.
MC34071,2,4,A MC33071,2,4,A
11
MOTOROLA ANALOG IC DEVICE DATA
Since the input capacitance associated with the small
geometry input device is substantially lower (2.5 pF) than the
typical JFET input gate capacitance (5.0 pF), better
frequency response for a given input source resistance can
be achieved using the MC34071 series of amplifiers. This
performance feature becomes evident, for example, in fast
settling D–to–A current to voltage conversion applications
where the feedback resistance can form an input pole with
the input capacitance of the op amp. This input pole creates
a 2nd order system with the single pole op amp and is
therefore detrimental to its settling time. In this context, lower
input capacitance is desirable especially for higher values of
feedback resistances (lower current DACs). This input pole
can be compensated for by creating a feedback zero with a
capacitance across the feedback resistance, if necessary, to
reduce overshoot. For 2.0 kΩ of feedback resistance, the
MC34071 series can settle to within 1/2 LSB of 8 bits in 1.0
µs, and within 1/2 LSB of 12–bits in 2.2 µs for a 10 V step. In
a inverting unity gain fast settling configuration, the
symmetrical slew rate is ±13 V/µs. In the classic noninverting
unity gain configuration, the output positive slew rate is +10
V/µs, and the corresponding negative slew rate will exceed
the positive slew rate as a function of the fall time of the input
waveform.
Since the bipolar input device matching characteristics are
superior to that of JFETs, a low untrimmed maximum offset
voltage of 3.0 mV prime and 5.0 mV downgrade can be
economically offered with high frequency performance
characteristics. This combination is ideal for low cost
precision, high speed quad op amp applications.
The all NPN output stage, shown in its basic form on the
equivalent circuit schematic, offers unique advantages over
the more conventional NPN/PNP transistor Class AB
output stage. A 10 kΩ load resistance can swing within 1.0 V
of the positive rail (VCC), and within 0.3 V of the negative
rail (VEE), providing a 28.7 Vpp swing from ±15 V supplies.
This large output swing becomes most noticeable at lower
supply voltages.
The positive swing is limited by the saturation voltage of
the current source transistor Q7, and VBE of the NPN pull up
transistor Q17, and the voltage drop associated with the short
circuit resistance, R7. The negative swing is limited by the
saturation voltage of the pull–down transistor Q16, the
voltage drop ILR6, and the voltage drop associated with
resistance R7, where IL is the sink load current. For small
valued sink currents, the above voltage drops are negligible,
allowing the negative swing voltage to approach within
millivolts of VEE. For large valued sink currents (>5.0 mA),
diode D3 clamps the voltage across R6, thus limiting the
negative swing to the saturation voltage of Q16, plus the
forward diode drop of D3 (≈VEE +1.0 V). Thus for a given
supply voltage, unprecedented peak–to–peak output voltage
swing is possible as indicated by the output swing
specifications.
If the load resistance is referenced to VCC instead of
ground for single supply applications, the maximum possible
output swing can be achieved for a given supply voltage. For
light load currents, the load resistance will pull the output to
VCC during the positive swing and the output will pull the load
resistance near ground during the negative swing. The load
resistance value should be much less than that of the
feedback resistance to maximize pull up capability.
Because the PNP output emitter–follower transistor has
been eliminated, the MC34071 series offers a 20 mA
minimum current sink capability , typically to an output voltage
of (VEE +1.8 V). In single supply applications the output can
directly source or sink base current from a common emitter
NPN transistor for fast high current switching applications.
In addition, the all NPN transistor output stage is inherently
fast, contributing to the bipolar amplifier’s high gain
bandwidth product and fast settling capability. The
associated high frequency low output impedance (30 Ω typ
@ 1.0 MHz) allows capacitive drive capability from 0 pF to
10,000 pF without oscillation in the unity closed loop gain
configuration. The 60° phase margin and 12 dB gain margin
as well as the general gain and phase characteristics are
virtually independent of the source/sink output swing
conditions. This allows easier system phase compensation,
since output swing will not be a phase consideration. The
high frequency characteristics of the MC34071 series also
allow excellent high frequency active filter capability,
especially for low voltage single supply applications.
Although the single supply specifications is defined at
5.0 V, these amplifiers are functional to 3.0 V @ 25°C
although slight changes in parametrics such as bandwidth,
slew rate, and DC gain may occur.
If power to this integrated circuit is applied in reverse
polarity or if the IC is installed backwards in a socket, large
unlimited current surges will occur through the device that
may result in device destruction.
Special static precautions are not necessary for these
bipolar amplifiers since there are no MOS transistors on
the die.
As with most high frequency amplifiers, proper lead dress,
component placement, and PC board layout should
be exercised for optimum frequency performance. For
example, long unshielded input or output leads may result in
unwanted input–output coupling. In order to preserve the
relatively low input capacitance associated with these
amplifiers, resistors connected to the inputs should be
immediately adjacent to the input pin to minimize additional
stray input capacitance. This not only minimizes the input
pole for optimum frequency response, but also minimizes
extraneous “pick up” at this node. Supply decoupling with
adequate capacitance immediately adjacent to the supply pin
is also important, particularly over temperature, since many
types of decoupling capacitors exhibit great impedance
changes over temperature.
The output of any one amplifier is current limited and thus
protected from a direct short to ground. However , under such
conditions, it is important not to allow the device to exceed
the maximum junction temperature rating. T ypically for ±15 V
supplies, any one output can be shorted continuously to
ground without exceeding the maximum temperature rating.
MC34071,2,4,A MC33071,2,4,A
12 MOTOROLA ANALOG IC DEVICE DATA
Figure 37. AC Coupled Noninverting Amplifer Figure 38. AC Coupled Inverting Amplifier
(Typical Single Supply Applications VCC = 5.0 V)
Figure 39. DC Coupled Inverting Amplifer
Maximum Output Swing Figure 40. Unity Gain Buffer TTL Driver
Figure 41. Active High–Q Notch Filter
Figure 42. Active Bandpass Filter
–
+
VCC
5.1 M
20 k Cin
Vin
1.0 M
MC34071
VO
03.7 Vpp
RL
10 k
AV = 101
100 k
1.0 k
BW (–3.0 dB) = 45 kHz
COVO
36.6 mVpp –
+
3.7 Vpp
0
VCC
VO
100 k
Cin 10 k
100 k CORL
10 k
68 k
Vin 370 mVpp
AV = 10 BW (–3.0 dB) = 450 kHz
+
–
4.75 Vpp
VO
VO
VCC
RL
100 k
91 k
5.1 k
1.0 M
AV = 10
Vin
2.63 V
5.1 k
BW (–3.0 dB) = 450 kHz
–
+
Vin
2.5 V
0 0 to 10,000 pF
Cable TTL Gate
–
+
Vin
VO
16 k
C
0.01
32 k 2.0 R
2.0 C
0.02
fo = 1.0 kHz
fo =
Vin
≥
0.2 Vdc
1
4
π
RC
2.0 C
0.02
16 k
RR
–
+
Vin VO
VCC
R3
2.2 k
C
0.047
R2
5.6 k
0.4 VCC
R1
fo = 30 kHz
Ho = 10
Ho = 1.0
1.1 k
Given fo = Center Frequency
AO = Gain at Center Frequency
Choose Value fo, Q, Ao, C
R3 = R1 = R2 =
Q R3 R1 R3
2Ho4Q2R1–R3
π
foC
For less than 10% error from operational amplifier Qofo
GBW < 0.1
where fo and GBW are expressed in Hz.
C
0.047
MC34071
MC34071
MC34071
MC34071
MC34071
MC54/74XX
Then:
GBW = 4.5 MHz Typ.
MC34071,2,4,A MC33071,2,4,A
13
MOTOROLA ANALOG IC DEVICE DATA
Figure 43. Low Voltage Fast D/A Converter Figure 44. High Speed Low Voltage Comparator
Figure 45. LED Driver Figure 46. Transistor Driver
Figure 47. AC/DC Ground Current Monitor Figure 48. Photovoltaic Cell Amplifier
5.0 k
10 k
Bit
Switches
CF
RF
VO
VCC
(R–2R) Ladder Network
Settling Time
1.0
µ
s (8–Bits, 1/2 LSB)
–
+
5.0 k5.0 k
10 k 10 k
–
+
VO
VO
Vin
1.0 V
2.0 k
RL
2.0 V
4.0 V
0.1
t
25 V/
µ
s
0.2
µ
s
Delay
Delay
1.0
µ
s
Vin
t
13 V/
µ
s
–
+
VCC
Vref
“ON”
Vin < Vref
“ON”
Vin > Vref
Vin –
+
VCC VCC
RL
RL
(A) PNP (B) NPN
–
+
–
+VO
ILoad
R1
R2
RS
Ground Current
Sense Resistor
VO = ILoad RS
BW ( –3.0 dB) = GBW
For VO > 0.1V
R1
R2
R1+R2
R2
–
+VO
MC34071
ICell
VCell = 0 V VO = ICell RF
VO > 0.1 V
RF
1+
MC34071
MC34071 MC34071 MC34071
MC34071 MC34071
MC34071,2,4,A MC33071,2,4,A
14 MOTOROLA ANALOG IC DEVICE DATA
Figure 49. Low Input Voltage Comparator
with Hysteresis Figure 50. High Compliance Voltage to
Sink Current Converter
Figure 51. High Input Impedance
Differential Amplifier Figure 52. Bridge Current Amplifier
Figure 53. Low Voltage Peak Detector Figure 54. High Frequency Pulse
Width Modulation
Vref
R2 VO
VOH
VOL
VinL VinH
Vref
Hysteresis
Vin
Vin
R1
MC34071
VinL =(V
OL–Vref)+Vref
R1
R1+R2
VinH =(V
OH–Vref)+Vref
VH =(V
OH –VOL)
+
–
R1
R1+R
R1
R1+R2
Vin
Iout
R
–
+
Iout = Vin
±
VIO
R
1/2
MC34072 –
+
+
R1 R2
R3
R4
VO
+V1
+V2
R2 R4
R3R1 (Critical to CMRR)
VO = 1 V2–V1
For (V2
≥
V1), V > 0
=
–
+R4
R3 R4
R3
–
+
+Vref RF
VO
RR
R
R =
∆
R
∆
R < < R
RF > > R (VO
≥
0.1 V)
RFVO = Vref
∆
R RF
2R2
–
+
Vin
Vin
RLVP10,000 pF
VO = Vin (pk)
+
VP
t
–+
+
VP
t
t
Iout
VP
+
–
0
+
ISC
Base Charge
Removal
±
IB
V+
47 k
100 k
C
R
Pulse Width
Control Group
OSC Comparator High Current
Output
fOSC
^
V
0.85
RC
–
100 k
IB
MC34071
MC34071
MC34071
1/2
MC34072
1/2
MC34072 1/2
MC34072
MC34071,2,4,A MC33071,2,4,A
15
MOTOROLA ANALOG IC DEVICE DATA
Figure 55. Second Order Low–Pass Active Filter Figure 56. Second Order High–Pass Active Filter
GENERAL ADDITIONAL APPLICATIONS INFORMATION VS = ±15.0 V
Figure 57. Fast Settling Inverter Figure 58. Basic Inverting Amplifier
Figure 59. Basic Noninverting Amplifier Figure 60. Unity Gain Buffer (AV = +1.0)
–
+
R1 R3
560 510
C2
C1
0.44
0.02
R2
5.6 k
MC34071 fo = 1.0 kHz
Ho = 10
Choose: fo, Ho, C2
Then: C1 = 2C2 (Ho+1)
R2 = R3 = R1 =
R2 Ho
Ho+14
π
foC2 R2
+
–
C2
0.05 C1
1.0
R1
46.1 k
R2
1.1 k fo = 100 Hz
Ho = 20
Choose: fo, Ho, C1 Then: R1 =
R2 =
C2 =
Ho+0.5
π
foC1
2
π
foC1 (1/Ho+2)
C
Ho
C1
1.0
+
–
CF*
VO = 10 V
Step
RF
2.0 k
I
High Speed
DAC
*Optional Compensation
Uncompensated
Compensated
ts = 1.0
µ
s
to 1/2 LSB (8–Bits)
ts = 2.2
µ
s
to 1/2 LSB (12–Bits)
SR = 13 V/
µ
s
VO
+
–
R1
R2
VO
Vin
RL
BW (–3.0 dB) = GBW
=
SR = 13 V/
µ
s
VO
Vin R2
R1 R1 +R2
R1
BW (–3.0 dB) = GBW R1 +R2
R1
+
–
Vin
VO
R2 RL
R1 =
VO
Vin R2
R1
1 +
+
–
Vin VO
BWp = 200 kHz
VO = 20 Vpp
SR = 10 V/
µ
s
MC34071
MC34071
MC34071
MC34071 MC34071
2
Ǹ
2
Ǹ
2
Ǹ
MC34071,2,4,A MC33071,2,4,A
16 MOTOROLA ANALOG IC DEVICE DATA
Figure 61. High Impedance Differential Amplifier
Figure 62. Dual Voltage Doubler
–R
RE
Example:
Let: R = RE = 12 k
Then: AV = 3.0
BW = 1.5 MHz AV = 1 + 2 R
RE
–
–
+
+
+VO
R
R
RR
R
MC34074
–
+
+
100 k 10
+10
–10
220 pF
–VO
+VO
RL+VO–VO
18.93 –18.78
10 k 18 –18
5.0 k 15.4 –15.4
∞
RL
100 k
100 k
RL
+
+
–
+
+
+
10 10
10
–
MC34074
MC34074
MC34074
MC34074
MC34074
MC34071,2,4,A MC33071,2,4,A
17
MOTOROLA ANALOG IC DEVICE DATA
P SUFFIX
PLASTIC PACKAGE
CASE 626–05
ISSUE K
D SUFFIX
PLASTIC PACKAGE
CASE 751–05
(SO–8)
ISSUE R
OUTLINE DIMENSIONS
NOTES:
1. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
2. PACKAGE CONTOUR OPTIONAL (ROUND OR
SQUARE CORNERS).
3. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
14
58
F
NOTE 2 –A–
–B–
–T–
SEATING
PLANE
H
J
GDK
N
C
L
M
M
A
M
0.13 (0.005) B M
T
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A9.40 10.16 0.370 0.400
B6.10 6.60 0.240 0.260
C3.94 4.45 0.155 0.175
D0.38 0.51 0.015 0.020
F1.02 1.78 0.040 0.070
G2.54 BSC 0.100 BSC
H0.76 1.27 0.030 0.050
J0.20 0.30 0.008 0.012
K2.92 3.43 0.115 0.135
L7.62 BSC 0.300 BSC
M––– 10 ––– 10
N0.76 1.01 0.030 0.040
__
SEATING
PLANE
14
58
A0.25 MCBSS
0.25 MBM
h
q
C
X 45
_
L
DIM MIN MAX
MILLIMETERS
A1.35 1.75
A1 0.10 0.25
B0.35 0.49
C0.18 0.25
D4.80 5.00
E1.27 BSCe3.80 4.00
H5.80 6.20
h
0 7
L0.40 1.25
q
0.25 0.50
__
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. DIMENSIONS ARE IN MILLIMETERS.
3. DIMENSION D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 TOTAL IN EXCESS
OF THE B DIMENSION AT MAXIMUM MATERIAL
CONDITION.
D
EH
A
Be
B
A1
CA
0.10
MC34071,2,4,A MC33071,2,4,A
18 MOTOROLA ANALOG IC DEVICE DATA
P SUFFIX
PLASTIC PACKAGE
CASE 646–06
ISSUE L
D SUFFIX
PLASTIC PACKAGE
CASE 751A–03
(SO–14)
ISSUE F
OUTLINE DIMENSIONS
NOTES:
1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE
POSITION AT SEATING PLANE AT MAXIMUM
MATERIAL CONDITION.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
4. ROUNDED CORNERS OPTIONAL.
17
14 8
B
A
F
HG D K
C
N
L
J
M
SEATING
PLANE
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A0.715 0.770 18.16 19.56
B0.240 0.260 6.10 6.60
C0.145 0.185 3.69 4.69
D0.015 0.021 0.38 0.53
F0.040 0.070 1.02 1.78
G0.100 BSC 2.54 BSC
H0.052 0.095 1.32 2.41
J0.008 0.015 0.20 0.38
K0.115 0.135 2.92 3.43
L0.300 BSC 7.62 BSC
M0 10 0 10
N0.015 0.039 0.39 1.01
____
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
–A–
–B–
G
P7 PL
14 8
71 M
0.25 (0.010) B M
S
B
M
0.25 (0.010) A S
T
–T–
F
RX 45
SEATING
PLANE
D14 PL K
C
J
M
_
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A8.55 8.75 0.337 0.344
B3.80 4.00 0.150 0.157
C1.35 1.75 0.054 0.068
D0.35 0.49 0.014 0.019
F0.40 1.25 0.016 0.049
G1.27 BSC 0.050 BSC
J0.19 0.25 0.008 0.009
K0.10 0.25 0.004 0.009
M0 7 0 7
P5.80 6.20 0.228 0.244
R0.25 0.50 0.010 0.019
____
MC34071,2,4,A MC33071,2,4,A
19
MOTOROLA ANALOG IC DEVICE DATA
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury
or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
Opportunity/Af firmative Action Employer .
MC34071,2,4,A MC33071,2,4,A
20 MOTOROLA ANALOG IC DEVICE DATA
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USA/EUROPE/Locations Not Listed: Motorola Literature Distribution; JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, 6F Seibu–Butsuryu–Center ,
P.O. Box 20912; Phoenix, Arizona 85036. 1–800–441–2447 or 602–303–5454 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–81–3521–8315
MFAX: RMF AX0@email.sps.mot.com – T OUCHTONE 602–244–6609 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park,
INTERNET: http://Design–NET.com 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298
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