FemtoClockTM Crystal-to-3.3V LVPECL Frequency Synthesizer ICS843253I-45 General Description Features The ICS843253I-45 is a two LVPECL output and one LVCMOS output Synthesizer optimized to HiPerClockSTM generate Ethernet reference clock frequencies and is a member of the HiPerClocksTM family of high performance clock solutions from IDT. Using a 25MHz, 18pF parallel resonant crystal, the following frequencies can be generated: 25MHz, 125MHz, and 156.25MHz. The ICS843253I-45 uses IDT's 3rd generation low phase noise VCO technology and can achieve 1ps or lower typical rms phase jitter, easily meeting Ethernet jitter requirements. The ICS843253I-45 is packaged in a small 16-pin TSSOP package. * Two differential LVPECL output pairs and one LVCMOS reference clock output * Crystal oscillator interface designed for a 25MHz, 18pF parallel resonant crystal * A 25MHz crystal generates output frequencies of: 25MHz, 125MHz and 156.25MHz * * VCO frequency: 625MHz * * * Full 3.3V supply mode ICS RMS Phase Jitter @ 156.25MHz, (1.875MHz - 20MHz) using a 25MHz crystal: 0.46ps (typical) -40C to 85C ambient operating temperature Available in both standard (RoHS 5) and lead-free (RoHS 6) packages Pin Assignment Block Diagram CLK_ENA Pullup QA XTAL_IN 25MHz /5 OSC Phase Detector nQA VCO 625MHz XTAL_OUT QB /4 nQB Feedback Divider /25 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 CLK_ENB VEE QB nQB VCCOB XTAL_IN XTAL_OUT VEE ICS843253I-45 CLK_ENB Pullup REF_OUT ICS843253AGI-45 REVISION A JULY 20, 2009 CLK_ENA VEE QA nQA VCCOA VCCA VCC REF_OUT 1 16-Lead TSSOP 4.4mm x 5.0mm x 0.925mm package body G Package (c)2009 Integrated Device Technology, Inc. ICS843253I-45 FEMTOCLOCKTM CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER Table 1. Pin Descriptions Number Name Type Description 1 CLK_ENA Input 2, 9, 15 VEE Power Negative supply pins. 3, 4 QA, nQA Output Differential output pair. LVPECL interface levels. 5 VCCOA Power Output supply pin for QA/nQA outputs. 6 VCCA Power Analog supply pin. 7 VCC Power Core supply pin. 8 REF_OUT Output Single-ended reference clock output. LVCMOS/LVTTL interface level. 20 typical output impedance. 10 11 XTAL_OUT XTAL_IN Input Crystal oscillator interface XTAL_IN is the input, XTAL_OUT is the output. 12 VCCOB Power Output supply pin for QB/nQB outputs. 13, 14 nQB, QB Output Differential output pair. LVPECL interface levels. 16 CLK_ENB Input Pullup Pullup Output enable pin for QA/nQA outputs. LVCMOS/LVTTL interface levels. See Table 3A. Output enable pin for QB/nQB outputs. LVCMOS/LVTTL interface levels. See Table 3B. NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum CIN Input Capacitance 4 pF RPULLUP Input Pullup Resistor 51 k ROUT Output impedance 20 REF_OUT Typical Maximum Units Function Tables Table 3A. CLK_ENA Function Table Input Table 3B. CLK_ENB Function Table Outputs Input Outputs CLK_ENA QA nQA CLK_ENB QB nQB 0 LOW HIGH 0 LOW HIGH 1 (default) Active Active 1 (default) Active Active ICS843253AGI-45 REVISION A JULY 20, 2009 2 (c)2009 Integrated Device Technology, Inc. ICS843253I-45 FEMTOCLOCKTM CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Rating Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VCC + 0.5V Outputs, IO Continuos Current Surge Current 50mA 100mA Package Thermal Impedance, JA 92.4C/W (0 mps) Storage Temperature, TSTG -65C to 150C DC Electrical Characteristics Table 4A. Power Supply DC Characteristics, VCC = VCCOA = VCCOB = 3.3V 5%, TA = -40C to 85C Symbol Parameter VCC Core Supply Voltage VCCA Test Conditions Minimum Typical Maximum Units 3.135 3.3 3.465 V Analog Supply Voltage VCC - 0.12 3.3 VCC V VCCOA, VCCOB Power Supply Voltage 3.135 3.3 3.465 V ICCA Analog Supply Current 12 mA IEE Power Supply Current 66 mA Table 4B. LVCMOS/LVTTL DC Characteristics,VCC = 3.3V 5%, TA = -40C to 85C Symbol Parameter Test Conditions VIH Input High Voltage VIL Input Low Voltage IIH Input High Current CLK_ENA, CLK_ENB VCC = VIN = 3.465V IIL Input Low Current CLK_ENA, CLK_ENB VCC = 3.465V, VIN = 0V -150 A VOH Output High Voltage VCC = 3.465V, IOH = -12mA 2.6 V VOL Output Low Voltage VCC = 3.465V, IOL = 12mA ICS843253AGI-45 REVISION A JULY 20, 2009 3 Minimum Typical Maximum Units 2 VCC + 0.3 V -0.3 0.8 V 5 A 0.5 V (c)2009 Integrated Device Technology, Inc. ICS843253I-45 FEMTOCLOCKTM CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER Table 4C. LVPECL DC Characteristics, VCC = VCCOA = VCCOB = 3.3V 5%, TA = -40C to 85C Symbol Parameter Test Conditions VOH Output High Voltage; NOTE 1 VOL Output Low Voltage; NOTE 1 VSWING Peak-to-Peak Output Voltage Swing Minimum Typical Maximum Units VCC - 1.4 VCC - 0.9 V VCC - 2.0 VCC - 1.7 V 0.6 1.0 V Maximum Units NOTE 1: Output termination with 50 to VCCOA,B - 2V. Table 5. Crystal Characteristics Parameter Test Conditions Minimum Mode of Oscillation Typical Fundamental Frequency 25 MHz Equivalent Series Resistance (ESR) 50 Shunt Capacitance 7 pF Maximum Units AC Electrical Characteristics Table 6. AC Characteristics, VCC = VCCOA = VCCOB = 3.3V 5%, TA = -40C to 85C Parameter fOUT tjit(O) Symbol Test Conditions Output Frequency RMS Phase Jitter (Random); NOTE 1 t R / tF Output Rise/Fall Time odc Output Duty Cycle QA, QB Minimum Typical QB/nQB 156.25 MHz QA/nQA 125 MHz REF_OUT 25 MHz 125MHz, Integration Range: 1.875MHz - 20MHz 0.44 ps 156.25MHz, Integration Range: 1.875MHz - 20MHz 0.57 ps 20% to 80% REF_OUT 200 700 ps 500 1400 ps QA, QB 48 52 % REF_OUT 46 54 % Using a 25MHz, 18pF quartz crystal. NOTE 1: Please refer to the Phase Noise plots. ICS843253AGI-45 REVISION A JULY 20, 2009 4 (c)2009 Integrated Device Technology, Inc. ICS843253I-45 FEMTOCLOCKTM CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER Typical Phase Noise at 125MHz Ethernet Filter Raw Phase Noise Data Noise Power dBc Hz 125MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.44ps (typical) Phase Noise Result by adding an Ethernet filter to raw data Offset Frequency (Hz) Typical Phase Noise at 156.25MHz 156.25MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.57ps (typical) Noise Power dBc Hz Ethernet Filter Raw Phase Noise Data Phase Noise Result by adding an Ethernet filter to raw data Offset Frequency (Hz) ICS843253AGI-45 REVISION A JULY 20, 2009 5 (c)2009 Integrated Device Technology, Inc. ICS843253I-45 FEMTOCLOCKTM CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER Parameter Measurement Information 2V 1.65V5 1.65V5 2V VCC, VCCOA, V VCCOB CCA Qx SCOPE SCOPE VCC V Qx CCA LVCMOS LVPECL GND nQx VEE -1.3V 0.165 -1.65V5 3.3V LVPECL Output Load AC Test Circuit 3.3V LVCMOS Output Load AC Test Circuit Phase Noise Plot Noise Power nQA, nQB QA, QB t PW Phase Noise Mask t odc = f1 Offset Frequency PERIOD t PW x 100% t PERIOD f2 RMS Jitter = Area Under the Masked Phase Noise Plot RMS Phase Jitter LVPECL Output Duty Cycle/Pulse Width/Period V nQA, nQB DD 80% 2 REF_OUT 80% VSW I N G t PW t odc = PERIOD t PW QA, QB, REF_OUT 20% 20% tR tF x 100% t PERIOD Output Rise/Fall Time LVCMOS Output Duty Cycle/Pulse Width/Period ICS843253AGI-45 REVISION A JULY 20, 2009 6 (c)2009 Integrated Device Technology, Inc. ICS843253I-45 FEMTOCLOCKTM CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER Application Information Recommendations for Unused Input Pins Inputs: Outputs: LVCMOS Control Pins LVPECL Outputs All control pins have internal pull-ups; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. LVCMOS Output The unused LVCMOS output can be left floating. There should be no trace attached. Power Supply Filtering Technique As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter perform- ance, power supply isolation is required. The ICS843253I-45 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC, VCCA, VCCOA and VCCOB should be individually connected to the power supply plane through vias, and 0.01F bypass capacitors should be used for each pin. Figure 1 illustrates this for a generic VCC pin and also shows that VCCA requires that an additional 10 resistor along with a 10F bypass capacitor be connected to the VCCA pin. 3.3V VCC .01F 10 .01F 10F VCCA Figure 1. Power Supply Filtering Crystal Input Interface The ICS843253I-45 has been characterized with 18pF parallel resonant crystals. The capacitor values, C1 and C2, shown in Figure 2 below were determined using a 25MHz, 18pF parallel resonant crystal and were chosen to minimize the ppm error. The optimum C1 and C2 values can be slightly adjusted for different board layouts. XTAL_IN C1 27p X1 18pF Parallel Crystal XTAL_OUT C2 27p Figure 2. Crystal Input Interface ICS843253AGI-45 REVISION A JULY 20, 2009 7 (c)2009 Integrated Device Technology, Inc. ICS843253I-45 FEMTOCLOCKTM CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER LVCMOS to XTAL Interface The XTAL_IN input can accept a single-ended LVCMOS signal through an AC coupling capacitor. A general interface diagram is shown in Figure 3. The XTAL_OUT pin can be left floating. The input edge rate can be as slow as 10ns. For LVCMOS signals, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. This configuration requires that the output VCC impedance of the driver (Ro) plus the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50 applications, R1 and R2 can be 100. This can also be accomplished by removing R1 and making R2 50. VCC R1 Ro 0.1f 50 Rs XTAL_IN R2 Zo = Ro + Rs XTAL_OUT Figure 3. General Diagram for LVCMOS Driver to XTAL Input Interface Termination for 3.3V LVPECL Outputs The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 4A and 4B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. The differential outputs are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 R3 125 3.3V 3.3V 3.3V R4 125 3.3V 3.3V Zo = 50 Zo = 50 + + _ LVPECL _ Input Zo = 50 LVPECL R1 50 R2 50 R1 84 VCC - 2V 1 RTT = * Zo ((VOH + VOL) / (VCC - 2)) - 2 R2 84 RTT Figure 4A. 3.3V LVPECL Output Termination ICS843253AGI-45 REVISION A JULY 20, 2009 Input Zo = 50 Figure 4B. 3.3V LVPECL Output Termination 8 (c)2009 Integrated Device Technology, Inc. ICS843253I-45 FEMTOCLOCKTM CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER Schematic Example Figure 5 shows an example of ICS843253I-45 application schematic. In this example, the device is operated at VCC = 3.3V. The 18pF parallel resonant 25MHz is used. The C1= 27pF and C2 = 27pF are recommended for frequency accuracy. For different board layout, the C1 and C2 may be slightly adjusted for optimizing frequency accuacy. Two examples of LVPECL terminations and one example of LVCMOS are shown in this schematic. Additional termination approaches are shown in the LVPECL Termination Application Note. 3.3V R1 133 Zo = 50 Ohm QA R2 133 TL1 U1 CLK_ENA VCCOA 0.1u VCC C6 VCC R5 - TL2 CLK_ENB 1 2 3 4 5 6 7 8 CLK_ENA VEE QA nQA VCCOA VCCA VCC REF_OUT CLK_ENB VEE QB nQB VCCOB XTAL_IN XTAL_OUT VEE 16 15 14 13 12 11 10 9 R3 82.5 QB nQB R4 82.5 VCCOB 0.1u C7 Zo = 50 Ohm + VCCA 10 C4 0.1u C3 0.1u C5 10u ICS843253I_45 Zo = 50 Ohm - VCC=3.3V C1 VCCOB=3.3V X1 25MHz 18pF Logic Input Pin Examples Set Logic Input to '1' RU1 1K Set Logic Input to '0' VCC R6 50 27pF VCCOA=3.3V VCC + Zo = 50 Ohm nQA Optional LVPECL Y-Termination C2 R7 50 R8 50 27pF RU2 Not Install To Logic Input pins RD1 Not Install To Logic Input pins REF_OUT R9 Zo = 50 33 RD2 1K Receiv er Figure 5. ICS843253I-45 Schematic Layout ICS843253AGI-45 REVISION A JULY 20, 2009 9 (c)2009 Integrated Device Technology, Inc. ICS843253I-45 FEMTOCLOCKTM CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER Power Considerations This section provides information on power dissipation and junction temperature for the ICS843253I-45. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS843253I-45 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. * Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 66mA = 228.7mW * Power (LVPECL outputs)MAX = 30mW/Loaded Output pair * Power (LVPECL output) = 2 * 30mW = 60mW LVCMOS Output Power Dissipation * Output Impedance ROUT Power Dissipation due to Loading 50 to VDDO/2 Output Current IOUT = VDDO_MAX / [2 * (50 + ROUT)] = 3.465V / [2 * (50 + 20)] = 24.75mA * Power Dissipation on the ROUT per LVCMOS output Power (ROUT) = ROUT * (IOUT)2 = 20 * (24.75mA)2 = 12.25mW per output Total Power Dissipation * Total Power = Power (core) + Power (LVPECL output) + Power (ROUT) = 228.7mW + 60mW + 12.25mW = 301.2mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockS devices is 125C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 92.4C/W per Table 7 below. Therefore, Tj for an ambient temperature of 85C with all outputs switching is: 85C + 0.301W * 92.4C/W = 112.8C. This is below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board. Table 7. Thermal Resistance JA for 16 Lead TSSOP, Forced Convection JA by Velocity Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards ICS843253AGI-45 REVISION A JULY 20, 2009 0 1 2.5 92.4C/W 88.0C/W 85.9C/W 10 (c)2009 Integrated Device Technology, Inc. ICS843253I-45 FEMTOCLOCKTM CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 6. VCCO Q1 VOUT RL 50 VCCO - 2V Figure 6. LVPECL Driver Circuit and Termination To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of VCC - 2V. * For logic high, VOUT = VOH_MAX = VCC_MAX - 0.9V (VCC_MAX - VOH_MAX) = 0.9V * For logic low, VOUT = VOL_MAX = VCO_MAX - 1.7V (VCC_MAX - VOL_MAX) = 1.7V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(VOH_MAX - (VCC_MAX - 2V))/RL] * (VCC_MAX - VOH_MAX) = [(2V - (VCC_MAX - VOH_MAX))/RL] * (VCC_MAX - VOH_MAX) = [(2V - 0.9V)/50] * 0.9V = 19.8mW Pd_L = [(VOL_MAX - (VCC_MAX - 2V))/RL] * (VCC_MAX - VOL_MAX) = [(2V - (VCC_MAX - VOL_MAX))/RL] * (VCC_MAX - VOL_MAX) = [(2V - 1.7V)/50] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW ICS843253AGI-45 REVISION A JULY 20, 2009 11 (c)2009 Integrated Device Technology, Inc. ICS843253I-45 FEMTOCLOCKTM CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER Reliability Information Table 8. JA vs. Air Flow Table for a 16 Lead TSSOP JA vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 92.4C/W 88.0C/W 85.9C/W Transistor Count The transistor count for ICS843253I-45 is: 2042 Package Outline and Package Dimensions Package Outline - G Suffix for 16-Lead TSSOP Table 9. Package Dimensions for 16 Lead TSSOP All Dimensions in Millimeters Symbol Minimum Maximum N 16 A 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 4.90 5.10 E 6.40 Basic E1 4.30 4.50 e 0.65 Basic L 0.45 0.75 0 8 aaa 0.10 Reference Document: JEDEC Publication 95, MO-153 ICS843253AGI-45 REVISION A JULY 20, 2009 12 (c)2009 Integrated Device Technology, Inc. ICS843253I-45 FEMTOCLOCKTM CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER Ordering Information Table 10. Ordering Information Part/Order Number 843253AGI-45LF 843253AGI-45LFT Marking 253AI45L 253AI45L Package "Lead-Free" 16 Lead TSSOP "Lead-Free" 16 Lead TSSOP Shipping Packaging Tube 2500 Tape & Reel Temperature -40C to 85C -40C to 85C NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. ICS843253AGI-45 REVISION A JULY 20, 2009 13 (c)2009 Integrated Device Technology, Inc. ICS843253I-45 FEMTOCLOCKTM CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER Revision History Sheet Rev A Table Page T10 8 13 Description of Change Date Updated Figures 4A & 4B. Ordering Information Table - corrected marking. ICS843253AGI-45 REVISION A JULY 20, 2009 14 7/20/09 (c)2009 Integrated Device Technology, Inc. ICS843253I-45 6024 Silver Creek Valley Road San Jose, California 95138 FEMTOCLOCKTM CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT Technical Support netcom@idt.com +480-763-2056 DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT's sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT's products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright 2009. All rights reserved.