Digital Input 2 W Class-D Audio Power Amplifier SSM2519 Data Sheet APPLICATIONS Filterless digital input Class-D amplifier Standalone operation or I2C control Serial digital audio interface supports common formats: I2S, left justified, right justified, TDM1-16, and PCM 2.31 W into 4 and 1.35 W into 8 at 5 V supply with 1% THD + N Available in 12-ball 1.4 mm x 1.7 mm x 0.4 mm pitch WLCSP Efficiency 90% at full scale into 8 9 mW loaded idle power at 1.8 V/3.6 V SNR = 98 dB, A-weighted PSRR = 80 dB at 217 Hz, dither input Supports wide range of sample rates: 8.0 kHz to 48.0 kHz Autosample rate and MCLK rate detection No BCLK required for operation 2.5 V to 5.5 V PVDD speaker operating supply voltage 1.5 V to 3.6 V VDD operating voltage Pop and click suppression Short-circuit and thermal protection with autorecovery Smart power-down when no input signal detected Power-on reset Low EMI emissions Mobile phones Portable media players Laptop PCs Wireless speakers Portable gaming Navigation systems TE FEATURES FUNCTIONAL BLOCK DIAGRAM VDD PVDD SD CLOCKING POWER CONTROL MCLK I2 C GAIN/SDA OUT+ OUT- SSM2519 LR_FORMAT/SCL 10750-001 SDATA DAC FULL BRIDGE POWER STAGE I2 S - CLASS-D MODULATOR BCLK VOLUME/GAIN LRCLK DIGITAL FILTERING POWER-ON RESET LE B SO GND Figure 1. GENERAL DESCRIPTION O The SSM2519 is a digital input, Class-D power amplifier that combines a digital-to-analog converter (DAC) and a sigma-delta (-) Class-D modulator. This unique architecture enables extremely low, real-world power consumption from digital audio sources with excellent audio performance. The SSM2519 is ideal for power sensitive applications, such as mobile phones and portable media players, where system noise can corrupt small analog signals such as those sent to an analog input audio amplifier. Using the SSM2519, audio data can be transmitted to the amplifier over a standard digital audio serial interface, thereby significantly reducing the effect of noise sources such as GSM interference or other digital signals on the transmitted audio. The closed-loop digital input design retains the benefits of a completely digital amplifier, yet enables very good PSRR and audio performance. The three-level, - Class-D modulator is designed to provide the least amount of EMI interference, the lowest quiescent power dissipation, and the highest audio efficiency without sacrificing audio quality. Input is provided via a serial audio interface, programmable to accept all common audio formats including I2S, left justified (LJ), right justified (RJ), TDM, and PCM. The SSM2519 is designed to operate with or without a control interface such as I2C, which is typically required for this type of device. Several control pins offer selection of operation when I2C control is not used. The SSM2519 can accept a variety of input MCLK frequencies and can use BCLK as the clock source in some configurations. Both the input sample rate and MCLK rates are automatically detected. The architecture of the SSM2519 provides a solution that offers lower power and higher performance than existing DAC plus Class-D solutions. Its digital interface also offers a better system solution for other products whose sole audio source is digital, such as wireless speakers, laptop PCs, portable digital televisions, and navigation systems. The SSM2519 is specified over the industrial temperature range of -40C to +85C. It has built-in thermal shutdown and output short-circuit protection. It is available in a 12-ball, 1.4 mm x 1.7 mm wafer level chip scale package (WLCSP). Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2012 Analog Devices, Inc. All rights reserved. SSM2519 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Volume Control .......................................................................... 14 Applications ....................................................................................... 1 Analog Gain ................................................................................ 14 Functional Block Diagram .............................................................. 1 Fault Detection and Recovery .................................................. 14 General Description ......................................................................... 1 Digital Audio Formats ................................................................... 15 Revision History ............................................................................... 2 Stereo Mode ................................................................................ 15 Specifications..................................................................................... 3 TDM, 50% Duty Cycle Mode ................................................... 15 Performance Specifications ......................................................... 3 TDM, Pulse Mode ...................................................................... 15 Power Supply Requirements ....................................................... 4 PCM, Multichannel Mode ........................................................ 16 PCM, Mono Mode ..................................................................... 16 TE Digital Input/Output .................................................................... 4 2 I C Configuration Interface .......................................................... 17 Absolute Maximum Ratings............................................................ 6 Overview ..................................................................................... 17 Thermal Resistance ...................................................................... 6 Register Summary .......................................................................... 19 ESD Caution .................................................................................. 6 Register Details ............................................................................... 20 Pin Configuration and Function Descriptions ............................. 7 Typical Performance Characteristics ............................................. 8 Software Reset and Master Software Power-Down Control Register ........................................................................................ 20 Theory of Operation ...................................................................... 12 Edge Speed, Power, and Clocking Control Register .............. 21 Overview...................................................................................... 12 Serial Audio Interface and Sample Rate Control Register .... 22 Standalone and I2C Operational Mode ................................... 12 Serial Audio Interface Control Register .................................. 23 Master and Bit Clock.................................................................. 12 Channel Mapping Control Register ......................................... 24 LE Digital Timing ............................................................................... 4 Volume Control Register ........................................................... 25 Channel Mapping ....................................................................... 13 Gain and Mute Control Register .............................................. 26 Power Supplies ............................................................................ 13 Fault Control Register ................................................................ 27 Power Control ............................................................................. 14 Outline Dimensions ....................................................................... 28 Power-On Reset/Voltage Supervisor ....................................... 14 Ordering Guide .......................................................................... 28 B SO Digital Input Serial Audio Interface......................................... 13 Low Power Modes ...................................................................... 14 O REVISION HISTORY 7/12--Revision 0: Initial Version Rev. 0 | Page 2 of 28 Data Sheet SSM2519 SPECIFICATIONS All conditions at PVDD = 5.0 V; VDD = 1.8 V; fS = 48 kHz; MCLK = 128 x fS; TA = 25oC; RL = 8 + 15 H; default I2C settings; volume control 0 dB setting, unless otherwise noted. PERFORMANCE SPECIFICATIONS Table 1. Symbol Test Conditions/Comments Min Typ POUT RL = 4 , THD + N = 1%, f = 1 kHz, BW = 20 kHz, PVDD = 5.0 V RL = 4 , THD + N = 10%, f = 1 kHz, BW = 20 kHz, PVDD = 5.0 V RL = 8 , THD + N = 1%, f = 1 kHz, BW = 20 kHz, PVDD = 5.0 V RL = 8 , THD + N = 10%, f = 1 kHz, BW = 20 kHz, PVDD = 5.0 V RL = 4 , THD + N = 1%, f = 1 kHz, BW = 20 kHz, PVDD = 3.6 V RL = 4 , THD + N = 10%, f = 1 kHz, BW = 20 kHz, PVDD = 3.6 V RL = 8 , THD + N = 1%, f = 1 kHz, BW = 20 kHz, PVDD = 3.6 V RL = 8 , THD + N = 10%, f = 1 kHz, BW = 20 kHz, PVDD = 3.6 V RL = 4 , THD + N = 1%, f = 1 kHz, BW = 20 kHz, PVDD = 2.5 V RL = 4 , THD + N = 10%, f = 1 kHz, BW = 20 kHz, PVDD = 2.5 V RL = 8 , THD + N = 1%, f = 1 kHz, BW = 20 kHz, PVDD = 2.5 V RL = 8 , THD + N = 10%, f = 1 kHz, BW = 20 kHz, PVDD = 2.5 V POUT = 2 W, 4 , PVDD = 5.0 V POUT = 1.4 W, 8 , PVDD = 5.0 V, normal operation POUT = 1 W into 8 , f = 1 kHz, PVDD = 5.0 V 2.31 2.75 1.35 1.68 1.13 1.4 0.69 0.85 0.48 0.6 0.31 0.39 84 90.2 0.03 W W W W W W W W W W W W % % % POUT = 0.5 W into 8 , f = 1 kHz, PVDD = 3.6 V 0.03 305 % kHz 1 82 mV dB 80 2.64 2.24 2.02 2.5 dB mA mA mA mA 200 1.14 0.6 86 5 200 37 41 nA mA mA A A nA V V 98 dB 4.94 4.21 3.69 1.98 V pk V pk V pk V pk Total Harmonic Distortion Plus Noise THD + N Average Switching Frequency Differential Output Offset Power Supply Rejection Ratio fSW B SO Efficiency LE TE Parameter DEVICE CHARACTERISTICS Output Power VOOS PSRRDC PSRRGSM IPVDD Supply Current, VDD IVDD O Supply Current, PVDD Output Noise Voltage en Signal-to-Noise Ratio Closed-Loop Gain SNR Gain PVDD = 2.5 V to 5.0 V VRIPPLE = 100 mV rms at 217 Hz, dither input Dither input, 8 + 15 H load, PVDD = 5.0 V Dither input, 8 + 15 H load, PVDD = 3.6 V Dither input, 8 + 15 H load, PVDD = 2.5 V Dither input, 8 + 15 H load, PVDD = 3.6 V (DAC_LPM = 0 and AMP_LPM = 0) Hardware shutdown Dither input, VDD = 3.3 V Dither input, VDD = 1.8 V Software shutdown, clock present, VDD = 1.8 V Software shutdown, clock removed, VDD = 1.8 V Hardware shutdown PVDD = 5.0 V, f = 20 Hz to 20 kHz, dither input, A-weighted PVDD = 3.6 V, f = 20 Hz to 20 kHz, dither input, A-weighted, gain = 3.6 V A-weighted reference to 0 dBFS, PVDD = 5.0 V 0 dBFS input, BTL output, f = 1 kHz Gain = 5.0 V Gain = 4.2 V Gain = 3.6 V Gain = 2 V Rev. 0 | Page 3 of 28 70 Max Unit SSM2519 Data Sheet POWER SUPPLY REQUIREMENTS Table 2. Parameter PVDD VDD Min 2.5 1.5 Typ 3.6 1.8 Max 5.5 3.6 Unit V V Min Typ Max Unit Test Conditions/Comments 3.6 5.5 +0.3 x VDD +0.35 V V V V MCLK, BCLK, LRCLK, SDATA SD, SDA, SCL MCLK, BCLK, LRCLK, SDATA SD, SDA, SCL A A Excluding MCLK Excluding MCLK and bidirectional pin DIGITAL INPUT/OUTPUT Parameter INPUT VOLTAGE High (VIH) 0.7 x VDD 1.35 -0.3 -0.3 Low (VIL) INPUT LEAKAGE CURRENT High (IIH) Low (IIL) MCLK INPUT LEAKAGE CURRENT High (IIH) Low (IIL) INPUT CAPACITANCE LE 1 1 TE Table 3. 3 3 5 DIGITAL TIMING A A pF Table 4. B SO All timing specifications are given for the default setting (I2S mode) of the serial input port. Limit Min Max Unit Description 74 148 136 271 ns ns MCLK period, 256 x fS mode (MCS = b0010) MCLK period, 128 x fS mode (MCS = b0001) ns ns ns ns ns ns BCLK low pulse width BCLK high pulse width Setup time from LRCLK or SDATA edge to BCLK rising edge Hold time from BCLK rising edge to LRCLK or SDATA edge SDATA setup time to BCLK rising SDATA hold time from BCLK rising kHz s s s s ns ns ns ns ns s SCL frequency SCL high SCL low Setup time; relevant for repeated start condition Hold time; after this period, the first clock is generated Data setup time SCL rise time SCL fall time SDA rise time SDA fall time Bus-free time (time between stop and start) 40 40 10 10 10 10 O Parameter MASTER CLOCK tMP tMP SERIAL PORT tBIL tBIH tLIS tLIH tSIS tSIH I2C PORT fSCL tSCLH tSCLL tSCS tSCH tDS tSCR tSCF tSDR tSDF tBFT 400 0.6 1.3 0.6 0.6 100 300 300 300 300 0.6 Rev. 0 | Page 4 of 28 Data Sheet SSM2519 Digital Timing Diagrams tBIH tBP BCLK tBIL tLIH tLIS LRCLK SDATA LEFT-JUSTIFIED MODE tSIS MSB MSB - 1 tSIH tSIS SDATA I2C-JUSTIFIED MODE MSB TE tSIH tSIS tSIS MSB LSB tSIH 10750-003 SDATA RIGHT-JUSTIFIED MODE tSIH Figure 2. Serial Input Port Timing tDS tSCR SCL tSCLL tSCS tSCF B SO START CONDITION tSCLH O Figure 3. I2C Port Timing Rev. 0 | Page 5 of 28 tBFT STOP CONDITION 10750-004 SDA tSCH LE tSCH SSM2519 Data Sheet ABSOLUTE MAXIMUM RATINGS Absolute maximum ratings apply at 25C, unless otherwise noted. THERMAL RESISTANCE Table 5. JA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Rating -0.3 V to 6 V -0.3 V to 3.6 V -0.3 V to 3.6 V Table 6. Thermal Resistance Package Type 12-ball, 1.4 mm x 1.7 mm WLCSP 4 kV -65C to +150C -40C to +85C -65C to +165C 300C JA 56.1 ESD CAUTION O B SO LE Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to 7absolute maximum rating conditions for extended periods may affect device reliability. TE Parameter PVDD Supply Voltage VDD Supply Voltage Input Voltage (MCLK, BCLK, SD, LRCLK, LR_FORMAT, GAIN, SDATA) ESD Susceptibility Storage Temperature Range Operating Temperature Range Junction Temperature Range Lead Temperature (Soldering, 60 sec) Rev. 0 | Page 6 of 28 Unit C/W Data Sheet SSM2519 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS BALL A1 INDICATOR 1 2 3 OUT+ OUT- MCLK PVDD VDD BCLK GND SD LRCLK LR_FORMAT/ SCL GAIN/ SDA A C D TE B SDATA TOP VIEW (BALL SIDE DOWN) Not to Scale 10750-002 LE SSM2519 Figure 4. Pin Configuration--Top View Table 7. Pin Function Descriptions Function1 O O I P P I P I I I I/O I Description Amplifier Output Positive Amplifier Output Negative Serial Audio Interface Master Clock 2.5 V to 5.5 V Amplifier Power 1.5 V to 3.6 V Digital and Analog Power I2S Bit Clock/Generated BCLK Rate Select Ground Power-Down Control--Active Low I2S Left/Right Frame Clock Left/Right Channel Selection and Serial Format Selection/I2C Clock Digital and Analog Gain Selection/I2C Serial Data I2S Serial Data B SO Pin Name OUT+ OUT- MCLK PVDD VDD BCLK GND SD LRCLK LR_FORMAT/SCL GAIN/SDA SDATA O Ball Number A1 A2 A3 B1 B2 B3 C1 C2 C3 D1 D2 D3 1 I = input, O = output, P = power. Rev. 0 | Page 7 of 28 SSM2519 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 100 100 2.5V 3.6V 5V 10 THD + N (%) 1 0.1 1 10 POUT (W) TE 0.01 0.01 0.001 10750-005 0.01 0.001 1 10 Figure 8. THD + N vs. Output Power into 8 , 3.6 V Gain Setting 100 2.5V 3.6V 5V LE 2.5V 3.6V 5V 0.1 POUT (W) Figure 5. THD + N vs. Output Power into 8 , 5.0 V Gain Setting 100 0.01 10750-008 0.1 0.1 10 THD + N (%) 10 0.01 0.001 0.01 0.1 1 10 POUT (W) 0.01 0.001 O 0.01 0.1 1 10 POUT (W) Figure 9. THD + N vs. Output Power into 4 , 3.6 V Gain Setting Figure 6. THD + N vs. Output Power into 4 , 5.0 V Gain Setting 250mW 500W 1W 1 0.1 10750-006 0.1 B SO 1 THD + N (%) 1 10750-009 THD + N (%) 10 1 2.5V 3.6V 5V 100 500mW 1W 10 THD + N (%) THD + N (%) 0.1 1 0.1 0.01 100 1k 10k FREQUENCY (Hz) 100k Figure 7. THD + N vs. Frequency into 8 , PVDD = 5.0 V 0.001 10 100 1k 10k FREQUENCY (Hz) Figure 10. THD + N vs. Frequency into 4 , PVDD = 5.0 V Rev. 0 | Page 8 of 28 100k 10750-010 0.001 10 10750-007 0.01 Data Sheet 1 SSM2519 100 500mW 250mW 125mW 250mW 125mW 10 THD + N (%) THD + N (%) 0.1 1 0.1 0.01 1k 10k 100k FREQUENCY (Hz) Figure 11. THD + N vs. Frequency into 8 , PVDD = 3.6 V 100 0.001 10 100 10k 100k Figure 14. THD + N vs. Frequency into 4 , PVDD = 2.5 V 10 500mW 250mW NO LOAD 8 4 9 8 LE QUIESCENT CURRENT (mA) 10 THD + N (%) 1k FREQUENCY (Hz) 10750-114 100 TE 0.001 10 10750-111 0.01 1 0.1 0.01 7 6 5 10k 100k FREQUENCY (Hz) 3 2.5 1.8 0.1 0.01 100 1k 5.0 8kHz 24kHz 48kHz 1.2 0.9 0.6 0.3 10k FREQUENCY (Hz) 100k 10750-113 0.001 10 4.5 1.5 QUIESCENT CURRENT (mA) O THD + N (%) 1 4.0 Figure 15. Quiescent Current vs. Supply Voltage PVDD 62.5mW 125mW 250mW 10 3.5 PVDD (V) Figure 12. THD + N vs. Frequency into 4 , PVDD = 3.6 V 100 3.0 10750-115 1k Figure 13. THD + N vs. Frequency into 8 , PVDD = 2.5 V 0 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 VDD (V) Figure 16. Quiescent Current vs. Supply Voltage VDD Rev. 0 | Page 9 of 28 3.6 10750-116 100 10750-112 0.001 10 B SO 4 SSM2519 Data Sheet 1.8 0.8 0.7 POWER SUPPLY CURRENT (A) 1.2 0.9 0.6 0.3 0.5 0.4 0.3 0.2 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 0 10750-117 1.6 0.5 0 1.0 1.5 2.0 2.5 3.0 POUT (W) Figure 17. Quiescent Current vs. Supply Voltage VDD 10750-120 0.1 VDD (V) Figure 20. Power Supply Current vs. POUT, 4 2.0 100 2.5V 3.6V 5V 80 1.5 THD + N = 10% EFFICIENCY (%) LE OUTPUT POWER (W) 0.6 TE QUIESCENT CURRENT (mA) 1.5 0 1.4 2.5V 3.6V 5V 1.0 THD + N = 1% 0.5 60 40 3.5 4.0 4.5 5.0 PVDD (V) 0 0 1.5 POWER SUPPLY CURRENT (A) 2.0 THD + N = 10% O THD + N = 1% 1.0 0.5 1.2 1.6 2.0 2.4 2.8 Figure 21. Class-D Efficiency vs. POUT, 4 0.8 2.5V 3.6V 5V 0.7 0.6 0.5 0.4 0.3 0.2 0 2.5 3.0 3.5 4.0 4.5 PVDD (V) 5.0 Figure 19. Maximum Output Power vs. PVDD (fIN = 1 kHz, RL = 4 ) 0 0 0.5 1.0 1.5 2.0 2.5 POUT (W) Figure 22. Power Supply Current vs. POUT, 8 Rev. 0 | Page 10 of 28 3.0 10750-122 0.1 10750-119 OUTPUT POWER (W) 2.5 0.8 POUT (W) Figure 18. Maximum Output Power vs. PVDD (fIN = 1 kHz, RL = 8 ) 3.0 0.4 10750-121 3.0 10750-118 0 2.5 B SO 20 Data Sheet 100 SSM2519 0 2.5V 3.6V 5V -10 80 PVDD = 5V PVDD = 3.6V PVDD = 2.5V -20 60 PSRR (dB) EFFICIENCY (%) -30 40 -40 -50 -60 -70 20 -80 0 -100 10 0.6 0.9 1.5 1.2 POUT (W) 0 -40 LE -100 -120 -140 -180 10 2.5V 3.6V 5V 100 1k 10k FREQUENCY (Hz) 100k 10750-024 -160 B SO OUTPUT SPECTRUM (dBV) -20 -80 1k 10k FREQUENCY (Hz) Figure 25. PSRR vs. Frequency Figure 23. Class-D Efficiency vs. POUT, 8 -60 100 O Figure 24. Output Spectrum, 100 mW, 8 Rev. 0 | Page 11 of 28 100k 10750-025 0.3 TE 0 10750-123 -90 SSM2519 Data Sheet THEORY OF OPERATION MASTER AND BIT CLOCK The SSM2519 is a fully integrated digital switching audio amplifier. The SSM2519 receives digital audio inputs and produces the PDM differential switching outputs using an internal power stage. The part has built-in protections against overtemperature as well as overcurrent. The SSM2519 also has built-in soft turn-on and soft turn-off for pop and click suppression. The SSM2519 requires an external clock present at the MCLK input pin to operate. This clock must be fully synchronous with the incoming digital audio on the serial interface. Internal to the IC, a clock frequency of 2.048 MHz to 24.576 MHz is required. This internal clock is derived from the external MCLK by dividing, passing through, or doubling in frequency the external MCLK signal. STANDALONE AND I2C OPERATIONAL MODE Different rates for MCLK are supported at different sample rates. Refer to Table 9 for all available options. The MCLK rate as well as sample rate can be automatically detected by setting the AMCS and ASR bits in Register 0x01, or they can be manually set (MCS bits in Register 0x00, and FS bits in Register 0x02) if AMCS or ASR is cleared. 2 The SSM2519 supports both standalone and I C control modes. The setting on the SD pin determines which mode is used. Table 8. SD Pin Settings Operation Tie to VDD Through 20 k Connect to VDD Without 20 k Connect to GND (Shorted or with 20 k) I2C Standalone mode Shutdown mode When in standalone mode or in I2C mode and auto clock rate detection is enabled (Register 0x01, Bit 1, AMCS = 1), the internal clock generation circuitry is automatically configured. When autosample rate detection is disabled (AMCS = 0), the MCS bits in Register 0x00 must be set with the correct value to generate the internal clock. LE SD Pin TE OVERVIEW B SO When the SSM2519 has entered its power-down state, it is possible to gate this clock to conserve additional system power. However, a master clock must be present for the audio amplifier to operate. If the serial interface bit clock (BCLK) is in the range of acceptable internal master clock frequencies (between 2.048 MHz and 6.144 MHz), it can serve as both master clock and the bit clock. Setting NO_BCLK (Bit 5 of Register 0x00) routes the signal on the MCLK pin to serve as the internal bit clock as well. In this case, tie the BCLK pin to ground. Table 9. Supported MCLK Rate for Different Sample Frequencies Supported MCLK Rates 256 x fS/512 x fS/1024 x fS/1536 x fS/2048 x fS 128 x fS/256 x fS/512 x fS/768 x fS/1024 x fS 64 x fS/128 x fS/256 x fS/384 x fS/512 x fS 400 x fS/800 x fS/1600 x fS 200 x fS/400 x fS/800 x fS 100 x fS/200 x fS/400 x fS O Sample Rates 8 kHz to 12 kHz 16 kHz to 24 kHz 32 kHz to 48 kHz 8 kHz to 12 kHz 16 kHz to 24 kHz 32 kHz to 48 kHz Rev. 0 | Page 12 of 28 Supported MCLK Frequencies 2.048 MHz to 24.576 MHz 2.048 MHz to 24.576 MHz 2.048 MHz to 24.576 MHz 3.2 MHz to 19.2 MHz 3.2 MHz to 19.2 MHz 3.2 MHz to 19.2 MHz Data Sheet SSM2519 Table 10. Master Clock Select (MCS) Bit Settings: MCLK, Ratio, and Frequency 12 kHz MCLK Ratio 16 kHz MCLK Ratio 22.05 kHz MCLK Ratio 24 kHz MCLK Ratio 32 kHz MCLK Ratio 44.1 kHz MCLK Ratio 48 kHz MCLK Ratio MCLK 1 Setting 0, b0000 256 x fS1 2.048 MHz 256 x fS1 2.822 MHz 256 x fS1 3.072 MHz 128 x fS1 2.048 MHz 1 128 x fS 2.822 MHz 128 x fS1 3.072 MHz 64 x fS1 2.048 MHz 64 x fS1 2.822 MHz 64 x fS1 3.072 MHz Setting 1, b0001 512 x fS 4.096 MHz 512 x fS Setting 2, b0010 1024 x fS 8.192 MHz 1024 x fS Setting 3, b0011 1536 x fS 12.288 MHz 1536 x fS Setting 4, b0100 2048 x fS 16.384 MHz 2048 x fS Setting 5, b0101 3072 x fS 24.576 MHz 3072 x fS Setting 6, b0110 400 x fS 3.20 MHz 400 x fS Setting 7, b0111 800 x fS 6.40 MHz 800 x fS Setting 8, b1000 1600 x fS 12.80 MHz 1600 x fS 5.6448 MHz 512 x fS 11.2896 MHz 1024 x fS 16.9344 MHz 1536 x fS 22.5792 MHz 2048 x fS 33.8688 MHz 3072 x fS 4.41 MHz 400 x fS 8.82 MHz 800 x fS 17.64 MHz 1600 x fS 6.144 MHz 256 x fS 12.288 MHz 384 x fS 18.432 MHz 768 x fS 24.576 MHz 1024 x fS 38.864 MHz 1536 x fS 4.80 MHz 200 x fS 9.60 MHz 400 x fS 19.20 MHz 800 x fS 4.096 MHz 256 x fS 8.192 MHz 512 x fS 12.288 MHz 768 x fS 16.384 MHz 1024 x fS 24.576 MHz 1536 x fS 3.20 MHz 200 x fS 6.40 MHz 400 x fS 12.80 MHz 800 x fS 5.6448 MHz 256 x fS 11.2896 MHz 512 x fS 16.9344 MHz 768 x fS 22.5792 MHz 1024 x fS 33.8688 MHz 1536 x fS 4.41 MHz 200 x fS 8.82 MHz 400 x fS 17.64 MHz 800 x fS 6.144 MHz 128 x fS 12.288 MHz 256 x fS 18.432 MHz 384 x fS 24.576 MHz 512 x fS 38.864 MHz 768 x fS 4.80 MHz 100 x fS 9.60 MHz 200 x fS 19.20 MHz 400 x fS 4.096 MHz 128 x fS 8.192 MHz 256 x fS 12.288 MHz 384 x fS 16.384 MHz 512 x fS 24.576 MHz 768 x fS 3.20 MHz 100 x fS 6.40 MHz 200 x fS 12.80 MHz 400 x fS 5.6448 MHz 128 x fS 11.2896 MHz 256 x fS 16.9344 MHz 384 x fS 22.5792 MHz 512 x fS 33.8688 MHz 768 x fS 4.41 MHz 100 x fS 8.82 MHz 200 x fS 17.64 MHz 400 x fS 6.144 MHz 12.288 MHz 4.80 MHz 9.60 MHz 19.20 MHz 18.432 MHz 24.576 MHz 38.864 MHz When using MCS = 0/64 fS mode, the chip automatically operates in low power mode. DIGITAL INPUT SERIAL AUDIO INTERFACE 2 CHANNEL MAPPING B SO It is capable of receiving stereo I S, left justified, or right justified data. Mono, stereo, and multichannel PCM/TDM interface formats are available. The data and interface formats are selected by adjusting the SDATA_FMT and SAI bits in Register 0x02. Note that, when operating in right justified mode, the proper data width must be chosen. The BCLK signal does not have to be provided to the SSM2519. It can internally generate the appropriate BCLK signal. To operate without a BCLK, the BCLK pin should be tied to VDD or GND to select the appropriate BCLK rate for the SDATA input. Table 11. BCLK Pin Connection Options Generation External O BCLK Pin Connected to External Clock Source Tied to VDD Tied to GND Internal Internal BCLK Rate Any 16 bit clocks/channel 32 bit clocks/channel When the SSM2519 is set up in standalone mode, a subset of serial interface formats are available. Selection of these serial formats and input channel are determined by the LR_FORMAT pin. Table 12. LR_FORMAT Pin Configuration Controls LR_FORMAT Pin Configuration Tie to VDD Tie to VDD Through 150 k Tie to VDD Through 47 k Tie to VDD Through 15 k Tie to GND 1 TE 11.025 kHz Ratio/ MCLK Ratio MCLK Ratio LE Input Sample Rate 8 kHz Stereo audio formats and TDM formats with two, four, eight, or 16 channels are available. In these modes, the amplifier audio can be chosen from any of the available TDM slots using the CH_SEL bits in Register 0x04. For most digital interface formats, many of these options are not present. For example, in stereo modes, only Channel 0 and Channel 1 are valid, and in four-slot TDM mode, only Channel 0, Channel 1, Channel 2, and Channel 3 are valid. POWER SUPPLIES The SSM2519 has two internal power supplies that must be provided. PVDD supplies power to the full-bridge power stage of MOSFETs and its associated drive, control, and protection circuitry. PVDD can operate from 2.5 V to 5.5 V and must be present to obtain audio output. Lowering the PVDD supply results in lower output power and correspondingly lower power consumption. This does not affect audio performance. VDD provides power to the digital logic, analog components, and I/O circuitry. VDD can operate from 1.5 V to 3.6 V and must be provided to obtain audio output. Lowering the supply voltage results in lower power consumption, but does not result in lower audio performance. Serial Format/Channel Select I2S/left channel Special gain case1 (I2S/left channel) PCM/left channel LJ/left channel I2S/right channel See Table 14. Rev. 0 | Page 13 of 28 SSM2519 Data Sheet POWER CONTROL VOLUME CONTROL The IC starts up in software power-down mode, where all blocks except for the I2C interface are disabled. To fully power up the amplifier, clear SPWDN (Bit 0 of Register 0x00). In addition to the software power-down, the software master mute control (M_MUTE) is enabled at the initial state of the amplifier; therefore, no audio is output until Bit 0 of Register 0x06 is cleared. The SSM2519 has a digital volume control. There are 255 levels available, providing a range from +24 dB to -71.25 dB in 0.375 dB increments. This is a soft volume control, meaning that the gain is adjusted continuously from one value to another. This continuously adjusted gain prevents the audible pop that occurs with an instantaneous gain adjustment. The SSM2519 contains a smart power-down feature that, when enabled, analyzes the incoming digital audio and, if the audio is zero for 512 consecutive samples, regardless of sample rate, places the IC in the smart power-down state. In this state, all circuitry except the I2S ports are placed in a low power state. After this state is entered, the I2S input and master clock (MCLK) can be removed to place the part in its lowest power state. When a single nonzero input is received, the SSM2519 leaves this state and resumes normal operation. The SSM2519 has selectable digital and analog gain. Selection of these gains occurs via the GAIN pin. The analog gain settings are optimized for operation at 2.5 V, 3.6 V, 4.2 V, or 5 V PVDD. POWER-ON RESET/VOLTAGE SUPERVISOR TE Table 13. GAIN Pin Configuration Control GAIN Pin Configuration Tie to VDD Tie to VDD Through 150 k Tie to VDD Through 47 k Tie to VDD Through 15 k Tie to GND Analog Gain/Digital Gain 5 V optimized analog/0 dB digital gain 5 V optimized analog/6 dB digital gain 4.2 V optimized analog/0 dB digital gain LE The SSM2519 can also be powered down to its lowest power state by pulling the SD pin low. ANALOG GAIN 3.6 V optimized analog/0 dB digital gain Table 14. Special Gain Case (LR_FORMAT Tied to VDD Through 150 k) GAIN Pin Configuration Control GAIN Pin Configuration Tie to VDD B SO The SSM2519 includes an internal power-on reset and voltage supervisor circuit. This circuit provides an internal reset to all circuitry during initial power-up. It also monitors the power supplies to the IC, mutes the output, and issues a reset when the voltages fall below the minimum operating range. This is done to ensure that no damage occurs due to low voltage operation and that no pops can occur under nearly any power removal condition. 3.6 V optimized analog/-3 dB digital gain Analog Gain/Digital Gain 2.5 V optimized analog/-6.75 dB digital gain 3.6 V optimized analog/0 dB digital gain Tie to GND LOW POWER MODES FAULT DETECTION AND RECOVERY Two low power modes are available. If DAC_LPM (Bit 5 of Register 0x01) is set, the digital-to-analog converter (DAC) runs at half speed, reducing the quiescent current. This half speed mode is also active when the MCS setting (Bits[4:1] of Register 0x00) is set to its lowest value (MCS = 0000) because the slowest acceptable MCLK rates can only support half speed DAC operation. Two fault conditions are detected by the SSM2519 fault detection system: overcurrent and overtemperature. When either of these is detected, the amplifier shuts down and a readonly I2C bit is set to indicate the cause of the shutdown. The OC and OT fault indicators are Bit 6 and Bit 5, respectively, of Register 0x07. An autorecovery feature can be enabled for temperature faults, current faults, or both, depending on the state of ARCV (Bits[1:0] of Register 0x07). O A soft reset of the chip can be issued through I2C by setting Bit 7 of Register 0x00 (S_RST). If AMP_LPM (Bit 6 of Register 0x01) is set, the - modulator runs in a special mode that offers lower quiescent current when the output power is small, at the expense of slightly degraded audio performance. Rev. 0 | Page 14 of 28 Data Sheet SSM2519 DIGITAL AUDIO FORMATS STEREO MODE 0x02[4:2], SAI = 0 (stereo: I2S, LJ, RJ) 0x02[6:5], SDATA_FMT = 0 (I2S), 1 (LJ), 2 (RJ 24-bit), 3 (RJ 16-bit) BCLK ANY NUMBER BCLKs LRCLK LEFT CHANNEL RIGHT CHANNEL 8 TO 32 BCLKs SDATA LJ 8 TO 32 BCLKs RIGHT CHANNEL LEFT CHANNEL 8 TO 32 BCLKs 8 TO 32 BCLKs SDATA RJ RIGHT CHANNEL LEFT CHANNEL 8 TO 32 BCLKs 8 TO 32 BCLKs 10750-011 SDATA I2S TE Figure 26. Stereo Modes: I2S, Left Justified, and Right Justified TDM, 50% DUTY CYCLE MODE 32/24/16 BCLKs LRCLK SDATA I2S CHANNEL 1 8 TO 32 BCLKs SDATA LJ CHANNEL 1 32/24/16 BCLKs CHANNEL 2 8 TO 32 BCLKs CHANNEL N 8 TO 32 BCLKs CHANNEL N CHANNEL 2 8 TO 32 BCLKs 8 TO 32 BCLKs B SO 8 TO 32 BCLKs SDATA RJ 32/24/16 BCLKs CHANNEL 1 CHANNEL 2 24 TO 16 BCLKs CHANNEL N 24 OR 16 BCLKs 24 OR 16 BCLKs 10750-012 BCLK LE 0x02[4:2], SAI = 1 (2 channels), 2 (4 channels), 3 (8 channels), 4 (16 channels) 0x02[6:5], SDATA_FMT = 0 (I2S), 1 (LJ), 2 (RJ 24-bit), 3 (RJ 16-bit) 0x03[1], BCLK_EDGE = 0 (rising BCLK edge used) 0x03[6], LRCLK_MODE = 0 (50% duty cycl LRCLK) 0x03[3:2], SLOT_WIDTH = 0 (32 BCLK cycles), 1 (24 BCLK cycles), 2 (16 BCLK cycles) Figure 27. TDM Modes with 50% Duty Cycle LRCLK TDM, PULSE MODE 0x02[4:2], SAI = 1 (2 channels), 2 (4 channels), 3 (8 channels), 4 (16 channels) 0x02[6:5], SDATA_FMT = 0 (I2S), 1 (LJ), 2 (RJ 24-bit), 3 (RJ 16-bit) 0x03[1], BCLK_EDGE = 0 (rising BCLK edge used) 0x03[6], LRCLK_MODE = 1 (pulse mode LRCLK) 0x03[3:2], SLOT_WIDTH = 0 (32 BCLK cycles), 1 (24 BCLK cycles), 2 (16 BCLK cycles) 32/24/16 BCLKs O LRCLK SDATA I2S 32/24/16 BCLKs 8 TO 32 BCLKs SDATA RJ 8 TO 32 BCLKs CHANNEL 2 CHANNEL 1 CHANNEL N CHANNEL 2 CHANNEL 1 8 TO 32 BCLKs SDATA LJ 32/24/16 BCLKs 8 TO 32 BCLKs CHANNEL N 8 TO 32 BCLKs CHANNEL 1 24 OR 16 BCLKs 8 TO 32 BCLKs CHANNEL 2 24 OR 16 BCLKs Figure 28. TDM Modes with Pulse Mode LRCLK Rev. 0 | Page 15 of 28 CHANNEL N 24 OR 16 BCLKs 10750-013 BCLK SSM2519 Data Sheet PCM, MULTICHANNEL MODE 0x02[4:2], SAI = 1 (2 channels), 2 (4 channels), 3 (8 channels), 4 (16 channels) 0x02[6:5], SDATA_FMT = 0 (I2S), 1 (LJ), 2 (RJ 24-bit), 3 (RJ 16-bit) 0x03[1], BCLK_EDGE = 1 (falling BCLK edge used) 0x03[6], LRCLK_MODE = 1 (pulse mode LRCLK) 0x03[3:2], SLOT_WIDTH = 0 (32 cycles), 1 (24 cycles), 2 (16 cycles) BCLK 32/24/16 BCLKs 32/24/16 BCLKs 32/24/16 BCLKs LRCLK CHANNEL 1 CHANNEL 2 CHANNEL 1 8 TO 32 BCLKs SDATA RJ 8 TO 32 BCLKs 8 TO 32 BCLKs CHANNEL N 8 TO 32 BCLKs 8 TO 32 BCLKs CHANNEL 1 CHANNEL N CHANNEL 2 24 OR 16 BCLKs 24 OR 16 BCLKs 24 OR 16 BCLKs Figure 29. Multichannel PCM Modes PCM, MONO MODE BCLK LE 0x02[4:2], SAI = 5 0x02[6:5], SDATA_FMT = 0 (I2S), 1 (LJ), 2 (RJ 24-bit), 3 (RJ 16-bit) 0x03[1], BCLK_EDGE = 1 (falling BCLK edge used) 0x03[6], LRCLK_MODE = 1 (pulse mode LRCLK) ANY NUMBER BCLKs LRCLK MONO CHANNEL SDATA LJ MONO CHANNEL B SO SDATA I2S 8 TO 32 BCLKs MONO CHANNEL 8 TO 32 BCLKs O Figure 30. Mono PCM Modes Rev. 0 | Page 16 of 28 10750-015 8 TO 32 BCLKs SDATA RJ 10750-014 SDATA LJ CHANNEL N CHANNEL 2 8 TO 32 BCLKs TE SDATA I2S Data Sheet SSM2519 I2C CONFIGURATION INTERFACE The SSM2519 supports a 2-wire serial (I2C-compatible) microprocessor bus driving multiple peripherals. Two pins, serial data (SDA) and serial clock (SCL), carry information between the SSM2519 and the system I2C master controller. The SSM2519 is always a slave on the bus, meaning it cannot initiate a data transfer. Each slave device is recognized by a unique device address. The device address byte format is shown in Figure 31. The address resides in the first seven bits of the I2C write. The LSB (Bit 7) of this byte sets either a read or write operation. LE Logic Level 1 corresponds to a read operation, and Logic Level 0 corresponds to a write operation. The full byte addresses are shown in Figure 31, where the subaddresses are automatically incremented at word boundaries and can be used for writing large amounts of data to contiguous memory locations. This increment happens automatically after a single word write, unless a stop condition is encountered. A data transfer is always terminated by a stop condition. BIT 1 BIT 2 BIT 3 BIT 4 1 1 1 0 0 BIT 5 0 BIT 6 0 BIT 7 R/W B SO BIT 0 10750-016 Both SDA and SCL should have a 2.2 k pull-up resistor on the lines connected to them. The device address is 0x70. Figure 31. I2C Device Address Byte Format Addressing Initially, each device on the I2C bus is in an idle state, monitoring the SDA and SCL lines for a start condition and the proper address. The I2C master initiates a data transfer by establishing a start condition, defined by a high-to-low transition on SDA while SCL remains high. This indicates that an address/data stream follows. All devices on the bus respond to the start condition and shift the next eight bits (the 7-bit address plus the R/W bit) MSB first. The device that recognizes the transmitted address responds by pulling the data line low during the ninth clock pulse. This ninth bit is known as an acknowledge bit. All other devices withdraw from the bus at this point and return to the idle condition. The R/W bit determines the direction of the data. A Logic 0 on the LSB of the first byte means that the master writes information to the peripheral, whereas a Logic 1 means that the master reads information from the peripheral after writing the subaddress and repeating the start address. A data transfer takes place until a stop condition is encountered. A stop condition occurs when SDA transitions from low to high while SCL is held high. The timing for the I2C port is shown in Figure 3. O Stop and start conditions can be detected at any stage during the data transfer. If these conditions are asserted out of sequence with normal read and write operations, the SSM2519 immediately jumps to the idle condition. During a given SCL high period, the user should issue only one start condition, one stop condition, or a single stop condition followed by a single start condition. If an invalid subaddress is issued by the user, the SSM2519 does not issue an acknowledge and returns to the idle condition. If the user exceeds the highest subaddress while in auto-increment mode, one of two actions is taken. In read mode, the SSM2519 outputs the highest subaddress register contents until the master device issues a no acknowledge, indicating the end of a read. A no acknowledge condition is where the SDA line is not pulled low on the ninth clock pulse of SCL. If the highest subaddress location is reached while in write mode, the data for the invalid byte is not loaded into any subaddress register, a no acknowledge is issued by the SSM2519, and the part returns to the idle condition. TE OVERVIEW I2C Read and Write Operations Figure 33 shows the timing of a single-word write operation. Every ninth clock, the SSM2519 issues an acknowledge by pulling SDA low. Figure 34 shows the timing of a burst mode write sequence. This figure shows an example where the target destination registers are two bytes. The SSM2519 knows to increment its subaddress register every byte because the requested subaddress corresponds to a register or memory area with a byte word length. The timing of a single-word read operation is shown in Figure 35. Note that the first R/W bit is 0, indicating a write operation. This is because the subaddress still needs to be written to set up the internal address. After the SSM2519 acknowledges the receipt of the subaddress, the master must issue a repeated start command followed by the chip address byte with the R/W bit set to 1 (read). This causes the SSM2519 SDA to reverse and begin driving data back to the master. The master then responds every ninth pulse with an acknowledge pulse to the SSM2519. Figure 36 shows the timing of a burst mode read sequence. This figure shows an example where the target destination registers are two bytes. The SSM2519 knows to increment its subaddress register at every byte because the requested subaddress corresponds to a register or memory area with a byte word length. Rev. 0 | Page 17 of 28 SSM2519 Data Sheet SCL SDA R/W START BY MASTER ACK ACK FRAME 2 SUBADDRESS BYTE FRAME 1 CHIP ADDRESS BYTE SCL (CONTINUED) ACK ACK FRAME 3 DATA BYTE 1 STOP BY MASTER FRAME 4 DATA BYTE 2 CHIP ADDRESS R/W = 0 (7 BITS) ACK BY SLAVE SUBADDRESS (8 BITS) ACK BY SLAVE DATA BYTE 1 (8 BITS) STOP BIT 10750-018 START BIT TE Figure 32. I2C Read/Write Timing CHIP ADDRESS ACK BY SUBADDRESS SLAVE R/W = 0 ACK BY SLAVE DATA- ACK BY WORD 1 SLAVE DATA- ACK BY WORD 2 SLAVE STOP BIT 10750-019 START BIT LE Figure 33. Single-Word I2C Write Format CHIP ADDRESS ACK BY SUBADDRESS SLAVE R/W = 0 ACK BY SLAVE START BIT CHIP ADDRESS R/W = 1 B SO START BIT ACK BY SLAVE DATA BYTE 1 ACK BY MASTER STOP BIT 10750-020 Figure 34. Burst Mode I2C Write Format START BIT CHIP ADDRESS ACK BY SUBADDRESS SLAVE R/W = 0 ACK BY SLAVE START BIT CHIP ADDRESS R/W = 1 ACK BY SLAVE O Figure 36. Burst Mode I2C Read Format Rev. 0 | Page 18 of 28 DATAWORD 1 ACK BY MASTER STOP BIT 10750-021 Figure 35. Single-Word I2C Read Format 10750-017 SDA (CONTINUED) Data Sheet SSM2519 REGISTER SUMMARY Table 15. Register Summary Name PWR_CTRL SYS_CTRL SAI_FMT1 SAI_FMT2 CH_SEL VOL_CTRL GAIN_CTRL FAULT_CTRL1 Bits [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] Bit 7 S_RST HPF_EN RESERVED BCLK_GEN Bit 6 Bit 5 RESERVED NO_BCLK AMP_LPM DAC_LPM SDATA_FMT LRCLK_MODE LRCLK_POL RESERVED AMUTE RESERVED RESERVED OC Bit 4 Bit 3 Bit 2 MCS EDGE APWDN_EN Bit 1 AMCS SAI SAI_MSB SLOT_WIDTH BCLK_EDGE CH_SEL Bit 0 SPWDN ASR FS RESERVED VOL OT ANA_GAIN MRCV RESERVED MAX_AR M_MUTE ARCV O B SO LE TE Reg 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 Rev. 0 | Page 19 of 28 Reset 0x05 0x30 0x02 0x00 0x00 0x40 0x11 0x0C RW RW RW RW RW RW RW RW RW SSM2519 Data Sheet REGISTER DETAILS SOFTWARE RESET AND MASTER SOFTWARE POWER-DOWN CONTROL REGISTER Table 16. Bit Descriptions for PWR_CTRL Bit Name S_RST Settings 0 1 6 5 RESERVED NO_BCLK 0 1 [4:1] MCS O 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 0 Description Software reset. The software reset bit resets all internal blocks, including I2C registers, to their default states. Normal operation Software reset Reserved. No BCLK operational mode. MCLK also used as BCLK. BCLK used as BCLK MCLK used as BCLK. No signal needed on BCLK pin. Master clock select. MCS must be set according to the input MCLK ratio relative to the input sample frequency. Refer to Table 10. 64 x fS MCLK 128 x fS MCLK 256 x fS MCLK 384 x fS MCLK 512 x fS MCLK 768 x fS MCLK 100 x fS MCLK 200 x fS MCLK 400 x fS MCLK Reserved Master software power-down. Software power-down puts all blocks except the I2C interface in a low power state. Normal operation Software master power-down B SO Bits 7 LE TE Address: 0x00, Reset: 0x05, Name: PWR_CTRL SPWDN 0 1 Rev. 0 | Page 20 of 28 Reset 0x0 Access RW 0x0 0x0 RW RW 0x2 RW 0x1 RW Data Sheet SSM2519 EDGE SPEED, POWER, AND CLOCKING CONTROL REGISTER Table 17. Bit Descriptions for SYS_CTRL Bit Name HPF_EN Settings 0 1 6 AMP_LPM 0 1 5 DAC_LPM 0 1 APWDN_EN O 4 [3:2] 0 1 EDGE 00 01 10 11 1 AMCS 0 1 0 Description DC blocking high-pass filter enable. The SSM2519 contains a selectable high-pass filter. The -3 dB frequency is at 6 Hz with a 48 kHz sample rate. This frequency increases linearly with lower sample rates. High-pass filter off High-pass filter on Amplifier low power mode. Normal operation Low power (return to zero) Class-D mode DAC low power mode. Normal operation Low power operation mode. DAC runs at half speed. Auto power-down enable. Auto power-down automatically puts the IC in a low power state when 2048 consecutive zero input samples have been received. Auto power-down disabled Auto power-down enabled Edge rate control. This controls the edge speed of the power stage. The low EMI operation mode reduces the edge speed, lowering EMI and power efficiency. Normal operation Lower EMI mode operation Lower EMI mode operation Lowest EMI mode operation Auto MCLK select. Master clock rate determined by MCS bits in Register 0x00 Master clock rate automatically detected Autosample rate. Sample rate setting determined by FS bit in Register 0x02 Autosample and MCLK rate detection enabled B SO Bits 7 LE TE Address: 0x01, Reset: 0x30, Name: SYS_CTRL ASR 0 1 Rev. 0 | Page 21 of 28 Reset 0x0 Access RW 0x0 RW 0x1 RW 0x1 RW 0x0 RW 0x0 RW 0x0 RW SSM2519 Data Sheet SERIAL AUDIO INTERFACE AND SAMPLE RATE CONTROL REGISTER Table 18. Bit Descriptions for SAI_FMT1 Bits 7 [6:5] Bit Name RESERVED SDATA_FMT Settings [4:2] SAI O 000 001 010 011 100 101 110 111 [1:0] Description Reserved. Serial data format. I2S, BCLK delay by 1 Left justified Right justified 24-bit data Right justified 16-bit data Serial audio interface format. Stereo: I2S, LJ, RJ TDM2 TDM4 TDM8 TDM16 Mono PCM Reserved Reserved Sample rate selection. 8 kHz to 12 kHz 16 kHz to 24 kHz 32 kHz to 48 kHz Reserved B SO 00 01 10 11 LE TE Address: 0x02, Reset: 0x02, Name: SAI_FMT1 FS 00 01 10 11 Rev. 0 | Page 22 of 28 Reset 0x0 0x0 Access RW RW 0x0 RW 0x2 RW Data Sheet SSM2519 SERIAL AUDIO INTERFACE CONTROL REGISTER Table 19. Bit Descriptions for SAI_FMT2 Bit Name BCLK_GEN Settings 0 1 6 LRCLK_MODE 0 1 5 LRCLK_POL 0 1 SAI_MSB O 4 [3:2] 1 0 1 SLOT_WIDTH 00 01 10 11 BCLK_EDGE 0 1 0 Description BCLK internal generation. When BCLK_GEN is enabled, an internally generated BCLK is used. Therefore, routing the BCLK signal to the pin is not required. External BCLK used Internally generated BCLK used LRCLK mode selection for TDM operation. 50% duty cycle LRCLK Pulse mode LRCLK LRCLK polarity control. Normal LRCLK operation Inverted LRCLK operation SDATA bit stream order. MSB first SDATA LSB first SDATA BCLK cycles per frame in TDM modes select. 32 BCLK cycles per slot 24 BCLK cycles per slot 16 BCLK cycles per slot Reserved BCLK active edge select. Rising BCLK edge used Falling BCLK edge used Reserved. B SO Bits 7 LE TE Address: 0x03, Reset: 0x00, Name: SAI_FMT2 RESERVED Rev. 0 | Page 23 of 28 Reset 0x0 Access RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW SSM2519 Data Sheet CHANNEL MAPPING CONTROL REGISTER Address: 0x04, Reset: 0x00, Name: CH_SEL B SO LE TE Note that not all the settings of CH_SEL are available in all serial interface modes. For example, in stereo and TDM2 modes, only Setting 0000 (Channel 0) and Setting 0001 (Channel 1) are valid because these modes can only contain two channels. In TDM4, Setting 0000 to Setting 0011 are supported. In TDM8, Setting 0000 to Setting 0111 are supported. In TDM16, Setting 0000 to Setting 1111 are supported. Table 20. Bit Descriptions for CH_SEL Bit Name RESERVED CH_SEL Settings 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 O Bits [7:4] [3:0] Description Reserved. Channel mapping select. Select input SDATA channel to map to left channel output. Channel 0 from SAI to output Channel 1 from SAI to output Channel 2 from SAI to output Channel 3 from SAI to output Channel 4 from SAI to output Channel 5 from SAI to output Channel 6 from SAI to output Channel 7 from SAI to output Channel 8 from SAI to output Channel 9 from SAI to output Channel 10 from SAI to output Channel 11 from SAI to output Channel 12 from SAI to output Channel 13 from SAI to output Channel 14 from SAI to output Channel 15 from SAI to output Rev. 0 | Page 24 of 28 Reset 0x0 0x0 Access RW RW Data Sheet SSM2519 VOLUME CONTROL REGISTER Table 21. Bit Descriptions for VOL_CTRL Bits [7:0] Bit Name VOL Settings Description Volume control. +24 dB +23.625 dB +23.35 dB +22.875 dB +22.5 dB Decreasing in 0.375 dB steps +0.375 dB 0 -0.375 dB Decreasing in 0.375 dB steps -70.875 dB -71.25 dB Mute O B SO 00000000 00000001 00000010 00000011 00000100 00000101 00111111 01000000 01000001 01000010 11111101 11111110 11111111 LE TE Address: 0x05, Reset: 0x40, Name: VOL_CTRL Rev. 0 | Page 25 of 28 Reset 0x40 Access RW SSM2519 Data Sheet GAIN AND MUTE CONTROL REGISTER TE Address: 0x06, Reset: 0x11, Name: GAIN_CTRL Table 22. Bit Descriptions for GAIN_CTRL Bit Name AMUTE Settings 0 1 RESERVED ANA_GAIN B SO 6 [5:4] 00 01 10 11 RESERVED M_MUTE 0 1 O [3:1] 0 Description Automatic mute enable. When the automatic mute function is enabled, after 2048 consecutive zero input samples have been received, the outputs are automatically muted. Automute enabled Automute disabled Reserved. Analog gain control. This controls the analog gain of the Class-D modulator. There are two settings optimized for 3.6 V operation from a lithium ion battery and for 5 V operation. 2 V gain 3.6 V gain 4.2 V gain 5 V gain Reserved. Master mute control. Setting the master mute control bit soft-mutes both channels. Normal operation Master mute LE Bits 7 Rev. 0 | Page 26 of 28 Reset 0x0 Access RW 0x0 0x1 RW RW 0x0 0x1 RW RW Data Sheet SSM2519 FAULT CONTROL REGISTER Bits 7 6 B SO Table 23. Bit Descriptions for FAULT_CTRL1 Bit Name RESERVED OC Settings 0 1 5 OT 0 1 4 MRCV LE TE Address: 0x07, Reset: 0x0C, Name: FAULT_CTRL1 O 0 1 Description Reserved. Overcurrent fault. Normal operation Overcurrent fault Overtemperture fault status. Normal operation Overtemperature fault Manual fault recovery. Normal operation Writing Logic 1 causes a manual fault recovery attempt when ARCV = 11 Maximum fault recovery attempts. The maximum automatic fault recovery bit determines how many attempts at autorecovery are performed. One autorecovery attempt Three autorecovery attempts Seven autorecovery attempts Unlimited autorecovery attempts Autofault recovery control. Autofault recovery for overtemperature and overcurrent faults Autofault recovery for overtemperature fault only Autofault recovery for overcurrent fault only No autofault recovery [3:2] MAX_AR 00 01 10 11 [1:0] ARCV 00 01 10 11 Rev. 0 | Page 27 of 28 Reset 0x0 0x0 Access RW R 0x0 R 0x0 W 0x3 RW 0x0 RW SSM2519 Data Sheet OUTLINE DIMENSIONS 1.455 1.415 1.375 BOTTOM VIEW (BALL SIDE UP) 3 2 1 A BALL A1 IDENTIFIER 1.705 1.665 1.625 1.20 REF B C D 0.40 BSC TOP VIEW (BALL SIDE DOWN) END VIEW COPLANARITY 0.05 0.300 0.260 0.220 0.230 0.200 0.170 05-16-2012-A SEATING PLANE 0.80 REF TE 0.560 0.500 0.440 ORDERING GUIDE Package Description 12-Ball Wafer Level Chip Scale Package [WLCSP] 12-Ball Wafer Level Chip Scale Package [WLCSP] Evaluation Board Z = RoHS Compliant Part. O 1 Temperature Range -40C to +85C -40C to +85C B SO Model1 SSM2519ACBZ-R7 SSM2519ACBZ-RL EVAL-SSM2519Z LE Figure 37. 12-Ball Wafer Level Chip Scale Package [WLCSP] (CB-12-6) Dimensions shown in millimeters (c)2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D10750-0-7/12(0) Rev. 0 | Page 28 of 28 Package Option CB-12-6 CB-12-6 Branding Y4B Y4B