The safety architecture includes Dual CPUs in lockstep, CPU and Memory Built-In Self Test (BIST) logic,

peripheral IOs.

The TMS570LSxxx4 integrates the ARM®Cortex™-R4F Floating Point CPU which offers an efficient 1.6

DMIPS/MHz, and has configurations which can run up to 180MHz providing up to 288 DMIPS. The device

supports the big-endian [BE32] format.

The TMS570LSxxx4 has up to 3MB integrated Flash and up to 256KB data RAM configurations with

The SRAM supports single-cycle read/write accesses in byte, halfword, and word modes.

capture or compare inputs, or general-purpose I/O. It is especially well suited for applications requiring

multiple sensor information and drive actuators with complex and accurate time pulses. A High End Timer

Transfer Unit (HET-TU) can perform DMA type transactions to transfer N2HET data to or from main

memory. A Memory Protection Unit (MPU) is built into the HET-TU.

The device has two 12-bit-resolution MibADCs with 24 total channels and 64 words of parity protected

sequential conversion sequences. Sixteen channels are shared between the two MibADCs. There are

three separate groupings. Each sequence can be converted once when triggered or configured for

continuous conversion mode.

The device has multiple communication interfaces: three MibSPIs, up to two SPIs, one LIN, one SCI, three

communications between similar shift-register type devices. The LIN supports the Local Interconnect

multiplexed wiring. The Ethernet module supports MII and MDIO interfaces.

The I2C module is a multi-master communication module providing an interface between the

microcontroller and an I2C compatible device via the I2C serial bus. The I2C supports both 100 Kbps and

400 Kbps speeds.

frequency reference to a higher frequency for internal use. The FMPLL provides one of the seven possible

clock source inputs to the global clock module (GCM). The GCM module manages the mapping between

the available clock sources and the device clock domains.

The device also has an external clock prescaler (ECP) module that when enabled, outputs a continuous

external clock on the ECLK pin/ball. The ECLK frequency is a user-programmable ratio of the peripheral

external Error pin/ball is triggered when a fault is detected. The nERROR can be monitored externally as

an indicator of a fault condition in the microcontroller.

memories or other slave devices.

to the built in ARM Cortex™-R4F CoreSight™debug features. An External Trace Macrocell (ETM)

provides instruction and data trace of program execution. For instrumentation purposes, a RAM Trace Port

or any other master. A Data Modification Module (DMM) gives the ability to write external data into the

To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all

devices and support tools. Each commercial family member has one of three prefixes: TMX, TMP, or TMS

support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development

from engineering prototypes (TMX/TMDX) through fully qualified production devices/tools (TMS/TMDS).

The figure below illustrates the numbering and symbol nomenclature for the TMS570LSxxx4 .

Orderable Part # Part # Flash RAM EMAC FlexRay

The device identification code register identifies several aspects of the device including the silicon version.

The details of the device identification code register are shown in Table 1-2. The device identification code

register value for this device is:

The four die ID registers at addresses 0xFFFFE1F0, 0xFFFFE1F4, 0xFFFFE1F8 and FFFFE1FC form a

128-bit dieid with the information as shown in Table Table 1-3.