1Copyright © 2017 Everspin Technologies MR25H256 / MR25H256A Rev. 1.4, 2/2017
MR25H256 / MR25H256A
MR25H256A has been released for mass production and is recommended for all new designs.
MR25H256 remains in mass production but will be subject to eventual phase out and end of life
and is not recommended for new designs.Both versions have the same specications.
256Kb Serial SPI MRAM
FEATURES
• No write delays
• Unlimited write endurance
• Data retention greater than 20 years
• Automatic data protection on power loss
• Block write protection
• Fast, simple SPI interface with up to 40 MHz clock rate
• 2.7 to 3.6 Volt power supply range
• Low current sleep mode
• Industrial and Automotive Grade 1 and Grade 3 tempera-
tures
• Available in 8-DFN or 8-DFN Small Flag RoHS-compliant
package.
• Direct replacement for serial EEPROM, Flash, FeRAM
• Industrial Grade and AEC-Q100 Grade 1 and Grade 3 options
• Moisture Sensitivity MSL-3
Small Flag 8-DFN
RoHS
8-DFN
Product Versions and Options
MR25H256A Product Options
Grade Temperature Package
Industrial -40 to +85 C 8-DFN Small Flag
Automotive AEC-Q100 Grade 3 -40 to +85 C 8-DFN Small Flag
Automotive AEC-Q100 Grade 1 -40 to +125 C 8-DFN Small Flag
MR25H256 Product Options (Not recommended for new designs)
Grade Temperature Package
Industrial -40 to +85 C 8-DFN Small Flag
8-DFN
Automotive AEC-Q100 Grade 1 -40 to +125 C 8-DFN Small Flag
8-DFN
2Copyright © 2017 Everspin Technologies MR25H256 / MR25H256A Rev. 1.4, 2/2017
MR25H256 / MR25H256A
TABLE OF CONTENTS
OVERVIEW ............................................................................................................................................4
Figure 1 – Block Diagram ........................................................................................................................................... 4
System Conguration .....................................................................................................................4
Figure 2 – System Conguration ............................................................................................................................. 4
DEVICE PIN ASSIGNMENT ...................................................................................................................5
Figure 3 – Pin Diagram All 8-DFN Packages ........................................................................................................ 5
Table 1 – Pin Functions All 8-DFN Packages ....................................................................................................... 5
SPI COMMUNICATIONS PROTOCOL ...................................................................................................6
Table 2 – Command Codes ....................................................................................................................................... 6
Status Register and Block Write Protection ..................................................................................6
Table 3 – Status Register Bit Assignments ........................................................................................................... 6
Table 4 – Block Memory Write Protection ............................................................................................................ 7
Table 5 – Memory Protection Modes .................................................................................................................... 7
Read Status Register (RDSR) ...........................................................................................................7
Figure 4 – RDSR ............................................................................................................................................................. 7
Write Enable (WREN) .......................................................................................................................8
Figure 5 – WREN ............................................................................................................................................................ 8
Write Disable (WRDI) .......................................................................................................................8
Figure 6 – WRDI ............................................................................................................................................................. 8
Write Status Register (WRSR) .........................................................................................................9
Figure 7 – WRSR ............................................................................................................................................................. 9
Read Data Bytes (READ) ............................................................................................................... 10
Figure 8 – READ ...........................................................................................................................................................10
Write Data Bytes (WRITE) ............................................................................................................. 11
Figure 9 – WRITE ..........................................................................................................................................................11
Enter Sleep Mode (SLEEP) ............................................................................................................ 12
Figure 10 – SLEEP ........................................................................................................................................................12
3Copyright © 2017 Everspin Technologies MR25H256 / MR25H256A Rev. 1.4, 2/2017
MR25H256 / MR25H256A
Exit Sleep Mode (WAKE) ............................................................................................................... 12
Figure 11 – WAKE ........................................................................................................................................................12
ELECTRICAL SPECIFICATIONS ......................................................................................................... 13
Absolute Maximum Ratings ........................................................................................................ 13
Table 6 – Absolute Maximum Ratings .................................................................................................................13
Table 7 – Operating Conditions .............................................................................................................................14
Table 8 – DC Characteristics ....................................................................................................................................14
Table 9 – Power Supply Characteristics ..............................................................................................................14
TIMING SPECIFICATIONS ................................................................................................................. 15
Table 10 – Capacitance ............................................................................................................................................. 15
Table 11 – AC Measurement Conditions ............................................................................................................15
Figure 12 – Output Load for Impedance Parameter Measurements .......................................................15
Figure 13 – Output Load for All Other Parameter Measurements ............................................................ 15
Power-Up Timing .......................................................................................................................... 16
Table 12 – Power-Up ..................................................................................................................................................16
Figure 14 – Power-Up Timing ................................................................................................................................ 16
Synchronous Data Timing ............................................................................................................ 17
Table 13 – AC Timing Parameters .........................................................................................................................17
Figure 15 – Synchronous Data Timing ................................................................................................................19
Figure 16 – HOLD Timing ........................................................................................................................................ 19
ORDERING INFORMATION ............................................................................................................... 20
Table 14 – Ordering Part Number Decoder Table ...........................................................................................20
Table 15 – Ordering Part Numbers .......................................................................................................................20
PACKAGE OUTLINE DRAWINGS ....................................................................................................... 21
Figure 17 – 8-DFN Small Flag Package ................................................................................................................21
Figure 18 – 8-DFN Package .....................................................................................................................................22
REVISION HISTORY ........................................................................................................................... 23
HOW TO REACH US ........................................................................................................................... 24
Table of Contents - Continued
4Copyright © 2017 Everspin Technologies MR25H256 / MR25H256A Rev. 1.4, 2/2017
MR25H256 / MR25H256A
The MR25H256/MR25H256A is a serial MRAM with memory array logically organized as 32Kx8 using the four
pin interface of chip select (CS), serial input (SI), serial output (SO) and serial clock (SCK) of the serial periph-
eral interface (SPI) bus. Serial MRAM implements a subset of commands common to today’s SPI EEPROM
and Flash components allowing MRAM to replace these components in the same socket and interoperate
on a shared SPI bus. Serial MRAM oers superior write speed, unlimited endurance, low standby & operating
power, and more reliable data retention compared to available serial memory alternatives.
32KB
MRAM ARRAY
Instruction Decode
Clock Generator
Control Logic
Write Protect
WP
CS
HOLD
SCK
SI
Instruction Register
Address Register
Counter
SO
Data I/O Register
Nonvolatile Status
Register
15 8
4
Figure 1 – Block Diagram
Single or multiple devices can be connected to the bus as shown in Figure 2. Pins SCK, SO and SI are com-
mon among devices. Each device requires CS and HOLD pins to be driven separately.
MOSI
MISO
MOSI = Master Out Slave In
MISO = Master In Slave Out
SCK
SCKSISO SCKSISO
HOLD
CS
HOLD
CS
2
2
1
1
HOLD HOLDCS CS
SPI
Micro Controller EVERSPIN SPI MRAM 1 EVERSPIN SPI MRAM 2
Figure 2 – System Conguration
OVERVIEW
System Conguration
5Copyright © 2017 Everspin Technologies MR25H256 / MR25H256A Rev. 1.4, 2/2017
MR25H256 / MR25H256A
Signal Name Pin I/O Function Description
CS 1 Input Chip Select
An active low chip select for the serial MRAM. When chip select is high, the
memory is powered down to minimize standby power, inputs are ignored
and the serial output pin is Hi-Z. Multiple serial memories can share a com-
mon set of data pins by using a unique chip select for each memory.
SO 2 Output Serial Output
The data output pin is driven during a read operation and remains Hi-Z at
all other times. SO is Hi-Z when HOLD is low. Data transitions on the data
output occur on the falling edge of SCK.
WP 3 Input Write Protect A low on the write protect input prevents write operations to the Status
Register.
VSS 4 Supply Ground Power supply ground pin.
SI 5 Input Serial Input
All data is input to the device through this pin. This pin is sampled on the
rising edge of SCK and ignored at other times. SI can be tied to SO to create
a single bidirectional data bus if desired.
SCK 6 Input Serial Clock
Synchronizes the operation of the MRAM. The clock can operate up to 40
MHz to shift commands, address, and data into the memory. Inputs are
captured on the rising edge of clock. Data outputs from the MRAM occur
on the falling edge of clock. The serial MRAM supports both SPI Mode 0
(CPOL=0, CPHA=0) and Mode 3 (CPOL=1, CPHA=1). In Mode 0, the clock is
normally low. In Mode 3, the clock is normally high. Memory operation is
static so the clock can be stopped at any time.
HOLD 7 Input Hold
A low on the Hold pin interrupts a memory operation for another task.
When HOLD is low, the current operation is suspended. The device will
ignore transitions on the CS and SCK when HOLD is low. All transitions of
HOLD must occur while CS is low.
VDD 8 Supply Power Supply Power supply voltage from +2.7 to +3.6 volts.
CS
SO
WP
V
V
HOLD
SCK
SI
1
2
3
4
8
7
6
5
SS
DD
Table 1 – Pin Functions All 8-DFN Packages
Figure 3 – Pin Diagram All 8-DFN Packages
Top View
DEVICE PIN ASSIGNMENT
6Copyright © 2017 Everspin Technologies MR25H256 / MR25H256A Rev. 1.4, 2/2017
MR25H256 / MR25H256A
SPI COMMUNICATIONS PROTOCOL
Instruction Description Binary Code Hex Code Address Bytes Data Bytes
WREN Write Enable 0000 0110 06h 0 0
WRDI Write Disable 0000 0100 04h 0 0
RDSR Read Status Register 0000 0101 05h 0 1
WRSR Write Status Register 0000 0001 01h 0 1
READ Read Data Bytes 0000 0011 03h 2 1 to ∞
WRITE Write Data Bytes 0000 0010 02h 2 1 to ∞
SLEEP Enter Sleep Mode 1011 1001 B9h 0 0
WAKE Exit Sleep Mode 1010 1011 ABh 0 0
Table 2 – Command Codes
The status register consists of the 8 bits listed in table 2.2. Status register bits BP0 and BP1 dene the mem-
ory block arrays that are protected as described in table 2.3. The Status Register Write Disable bit (SRWD)
is used in conjunction with bit 1 (WEL) and the Write Protection pin (WP) as shown in table 2.4 to enable
writes to status register bits. The fast writing speed of MR25H256/MR25H256A does not require write status
bits. The state of bits 6,5,4, and 0 can be user modied and do not aect memory operation. All bits in the
status register are pre-set from the factory to the “0” state.
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
SRWD Don’t Care Don’t Care Don’t Care BP1 BP0 WEL Don’t Care
Table 3 – Status Register Bit Assignments
MR25H256/MR25H256A can be operated in either SPI Mode 0 (CPOL=0, CPHA =0) or SPI Mode 3 (CPOL=1,
CPHA=1). For both modes, inputs are captured on the rising edge of the clock and data outputs occur on
the falling edge of the clock. When not conveying data, SCK remains low for Mode 0; while in Mode 3, SCK
is high. The memory determines the mode of operation (Mode 0 or Mode 3) based upon the state of the
SCK when CS falls.
All memory transactions start when CS is brought low to the memory. The rst byte is a command code. De-
pending upon the command, subsequent bytes of address are input. Data is either input or output. There
is only one command performed per CS active period. CS must go inactive before another command can
be accepted. To ensure proper part operation according to specications, it is necessary to terminate each
access by raising CS at the end of a byte (a multiple of 8 clock cycles from CS dropping) to avoid partial or
aborted accesses.
Status Register and Block Write Protection
7Copyright © 2017 Everspin Technologies MR25H256 / MR25H256A Rev. 1.4, 2/2017
MR25H256 / MR25H256A
WEL SRWD WP Protected Blocks Unprotected Blocks Status
Register
0 X X Protected Protected Protected
1 0 X Protected Writable Writable
1 1 Low Protected Writable Protected
1 1 High Protected Writable Writable
Status Register Memory Contents
BP1 BP0 Protected Area Unprotected Area
0 0 None All Memory
0 1 Upper Quarter Lower Three-Quarters
1 0 Upper Half Lower Half
1 1 All None
The Read Status Register (RDSR) command allows the Status Register to be read. The Status Register can be
read at any time to check the status of write enable latch bit, status register write protect bit, and block write
protect bits. For MR25H256/MR25H256A, the write in progress bit (bit 0) is not written by the memory be-
cause there is no write delay. The RDSR command is entered by driving CS low, sending the command code,
and then driving CS high.
Figure 4 – RDSR
When WEL is reset to 0, writes to all blocks and the status register are protected. When WEL is set to 1, BP0
and BP1 determine which memory blocks are protected. While SRWD is reset to 0 and WEL is set to 1, status
register bits BP0 and BP1 can be modied. Once SRWD is set to 1, WP must be high to modify SRWD, BP0 and
BP1.
SCK
SI
SO
CS
Status Register Out
High Impedance High Z
Mode 3
Mode 0
10 2 3 4 5 6 7 0 1 2 3 4 5 6 7
00000101
MSB
MSB
76543210
Table 4 – Block Memory Write Protection
Table 5 – Memory Protection Modes
Read Status Register (RDSR)
8Copyright © 2017 Everspin Technologies MR25H256 / MR25H256A Rev. 1.4, 2/2017
MR25H256 / MR25H256A
The Write Enable (WREN) command sets the Write Enable Latch (WEL) bit in the status register to 1. The WEL
bit must be set prior to writing in the status register or the memory. The WREN command is entered by driv-
ing CS low, sending the command code, and then driving CS high.
The Write Disable (WRDI) command resets the WEL bit in the status register to 0. This prevents writes to
status register or memory. The WRDI command is entered by driving CS low, sending the command code,
and then driving CS high.
The WEL bit is reset to 0 on power-up or completion of WRDI.
Figure 6 – WRDI
Figure 5 – WREN
SCK
SI
SO
CS
Instruction (06h)
High Impedance
Mode 3
Mode 0
Mode 3
Mode 0
10 234567
00000110
SCK
SI
SO
CS
Instruction (04h)
High Impedance
Mode 3
Mode 0
Mode 3
Mode 0
10 234567
00000100
Write Enable (WREN)
Write Disable (WRDI)
9Copyright © 2017 Everspin Technologies MR25H256 / MR25H256A Rev. 1.4, 2/2017
MR25H256 / MR25H256A
Figure 7 – WRSR
SCK
SI
SO
CS
Status Register In
High Impedance
Mode 3
Mode 0
Instruction (01h)
0000000176543210
MSB
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
The Write Status Register (WRSR) command allows new values to be written to the Status Register. The
WRSR command is not executed unless the Write Enable Latch (WEL) has been set to 1 by executing a WREN
command while pin WP and bit SRWD correspond to values that make the status register writable as seen in
table 2.4. Status Register bits are non-volatile with the exception of the WEL which is reset to 0 upon power
cycling.
The WRSR command is entered by driving CS low, sending the command code and status register write data
byte, and then driving CS high.
Write Status Register (WRSR)
10Copyright © 2017 Everspin Technologies MR25H256 / MR25H256A Rev. 1.4, 2/2017
MR25H256 / MR25H256A
The Read Data Bytes (READ) command allows data bytes to be read starting at an address specied by the
16-bit address. Only address bits 0-14 are decoded by the memory. The data bytes are read out sequentially
from memory until the read operation is terminated by bringing CS high The entire memory can be read in a
single command. The address counter will roll over to 0000h when the address reaches the top of memory.
The READ command is entered by driving CS low and sending the command code. The memory drives the
read data bytes on the SO pin. Reads continue as long as the memory is clocked. The command is terminat-
ed by bring CS high.
Figure 8 – READ
SCK
SI
SO
CS
16-Bit Address
High Impedance
Instruction (03h)
Data Out 1 Data Out 2
00000011X 3
765432107
210
MSB
MSB
0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 31
14 13
Read Data Bytes (READ)
11Copyright © 2017 Everspin Technologies MR25H256 / MR25H256A Rev. 1.4, 2/2017
MR25H256 / MR25H256A
The Write Data Bytes (WRITE) command allows data bytes to be written starting at an address specied by
the 16-bit address. Only address bits 0-14 are decoded by the memory. The data bytes are written sequen-
tially in memory until the write operation is terminated by bringing CS high. The entire memory can be
written in a single command. The address counter will roll over to 0000h when the address reaches the top
of memory.
Unlike EEPROM or Flash Memory, MRAM can write data bytes continuously at its maximum rated clock
speed without write delays or data polling. Back to back WRITE commands to any random location in mem-
ory can be executed without write delay. MRAM is a random access memory rather than a page, sector, or
block organized memory making it ideal for both program and data storage.
The WRITE command is entered by driving CS low, sending the command code, and then sequential write
data bytes. Writes continue as long as the memory is clocked. The command is terminated by bringing CS
high.
Figure 9 – WRITE
SCK
SI
SO
CS
16-Bit Address
High Impedance
Instruction (02h)
00000010X 321076543210
MSB MSB
012345678910 20 21 22 23 24 25 26 27 28 29 30 31
14 13
SCK
SI
SO
CS
Data Byte 3
High Impedance
Data Byte NData Byte 2
34 210 76543210
MSB
76543210765
MSB
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 Mode 3
Mode 0
Write Data Bytes (WRITE)
12Copyright © 2017 Everspin Technologies MR25H256 / MR25H256A Rev. 1.4, 2/2017
MR25H256 / MR25H256A
The Enter Sleep Mode (SLEEP) command turns o all MRAM power regulators in order to reduce the overall
chip standby power to 3 μA typical. The SLEEP command is entered by driving CS low, sending the com-
mand code, and then driving CS high. The standby current is achieved after time, tDP. If power is removed
when the part is in sleep mode, upon power restoration, the part enters normal standby. The only valid
command following SLEEP mode entry is a WAKE command.
The Exit Sleep Mode (WAKE) command turns on internal MRAM power regulators to allow normal operation.
The WAKE command is entered by driving CS low, sending the command code, and then driving CS high.
The memory returns to standby mode after tRDP. The CS pin must remain high until the tRDP period is over.
Figure 10 – SLEEP
Figure 11 – WAKE
SCK
SI
SO
CS
Standby CurrentActive Current
Mode 3
Mode 0
Sleep Mode Current
Instruction (B9h)
10111001
01234567
DP
t
SCK
SI
SO
CS
Sleep Mode Current
Mode 3
Mode 0
Standby Current
Instruction (ABh)
10101 011
01234567
RDP
t
Enter Sleep Mode (SLEEP)
Exit Sleep Mode (WAKE)
13Copyright © 2017 Everspin Technologies MR25H256 / MR25H256A Rev. 1.4, 2/2017
MR25H256 / MR25H256A
ELECTRICAL SPECIFICATIONS
This device contains circuitry to protect the inputs against damage caused by high static voltages or electric
elds; however, it is advised that normal precautions be taken to avoid application of any voltage greater
than maximum rated voltages to these high-impedance (Hi-Z) circuits.
The device also contains protection against external magnetic elds. Precautions should be taken to avoid
application of any magnetic eld more intense than the eld intensity specied in the maximum ratings.
Symbol Parameter Conditions Value 1Unit
VDD Supply voltage 2All -0.5 to 4.0 V
VIN Voltage on any pin 2All -0.5 to VDD + 0.5 V
IOUT Output current per pin All ±20 mA
PDPackage power dissipation 3All 0.600 W
TBIAS Temperature under bias
Industrial -45 to 95 °C
AEC-Q100 Grade 3 -45 to 95 °C
AEC-Q100 Grade 1 -45 to 135 °C
Tstg Storage Temperature All -55 to 150 °C
TLead
Lead temperature during solder (3
minute max) All 260 °C
Hmax_write Maximum magnetic eld (Write) During Write 12,000 A/m
Hmax_read
Maximum magnetic eld (Read or
Standby)
During Read or
Standby 12,000 A/m
Notes:
1. Permanent device damage may occur if absolute maximum ratings are exceeded. Functional opera-
tion should be restricted to recommended operating conditions. Exposure to excessive voltages or
magnetic elds could aect device reliability.
2. All voltages are referenced to VSS. The DC value of VIN must not exceed actual applied VDD by more
than 0.5V. The AC value of VIN must not exceed applied VDD by more than 2V for 10ns with IIN limited
to less than 20mA.
3. Power dissipation capability depends on package characteristics and use environment.
Table 6 – Absolute Maximum Ratings
Absolute Maximum Ratings
14Copyright © 2017 Everspin Technologies MR25H256 / MR25H256A Rev. 1.4, 2/2017
MR25H256 / MR25H256A
Symbol Parameter Grade Min Typical Max Unit
VDD Power supply voltage
Industrial 2.7 - 3.6 V
AEC-Q100 Grade 3 2.7 - 3.6 V
AEC-Q100 Grade1 3.0 - 3.6 V
VIH Input high voltage All 2.2 - VDD + 0.3 V
VIL Input low voltage All -0.5 - 0.8 V
TATemperature under bias
Industrial -40 - 85 °C
AEC-Q100 Grade 3 -40 - 85 °C
AEC-Q100 Grade 1 1-40 - 125 °C
1. AEC-Q100 Grade 1 temperature profile assumes 10 percent duty cycle at maximum temperature (2 years
out of 20-year life.)
Table 7 – Operating Conditions
Symbol Parameter Conditions Min Typical Max Unit
ILI Input leakage current All - - ±1 μA
ILO Output leakage current All - - ±1 μA
VOL Output low voltage
IOL = +4 mA - - 0.4 V
IOL = +100 μA - - VSS + 0.2v V
VOH Output high voltage
IOH = -4 mA 2.4 - - V
IOH = -100 μA VDD - 0.2 - - V
Table 8 – DC Characteristics
Table 9 – Power Supply Characteristics
Symbol Parameter Conditions Typical Max Unit
IDDR Active Read Current
@ 1 MHz 2.5 3 mA
@ 40 MHz 6 10 mA
IDDW Active Write Current
@ 1 MHz 8 13 mA
@ 40 MHz 23 27 mA
ISB Standby Current CS High 190 115 μA
IZZ Standby Sleep Mode Current CS High 7 30 μA
1. ISB current is specied with CS high and the SPI bus inactive.
15Copyright © 2017 Everspin Technologies MR25H256 / MR25H256A Rev. 1.4, 2/2017
MR25H256 / MR25H256A
TIMING SPECIFICATIONS
Table 10 – Capacitance
Symbol Parameter Typical Max 1Unit
CIn Control input capacitance - 6 pF
CI/O Input/Output capacitance - 8 pF
1. ƒ = 1.0 MHz, dV = 3.0 V, TA = 25 °C, periodically sampled rather than 100% tested.
Table 11 – AC Measurement Conditions
Figure 12 – Output Load for Impedance Parameter Measurements
Parameter Value Unit
Logic input timing measurement reference level 1.5 V
Logic output timing measurement reference level 1.5 V
Logic input pulse levels 0 or 3.0 V
Input rise/fall time 2 ns
Output load for low and high impedance parameters See Figure 4.1
Output load for all other timing parameters See Figure 4.2
V
Output
L= 1.5 V
RL= 50 Ω
ZD= 50 Ω
Output
435 Ω
590 Ω
30 pF
3.3 V
Figure 13 – Output Load for All Other Parameter Measurements
16Copyright © 2017 Everspin Technologies MR25H256 / MR25H256A Rev. 1.4, 2/2017
MR25H256 / MR25H256A
The MR25H256/MR25H256A is not accessible for a start-up time tPU = 400 μs after power up. Users must
wait this time from the time when VDD (min) is reached until the rst CS low to allow internal voltage refer-
ences to become stable. The CS signal should be pulled up to VDD so that the signal tracks the power supply
during power-up sequence.
Symbol Parameter Min Typical Max Unit
VWI Write Inhibit Voltage 2.2 - 2.7 V
tPU Startup Time 400 - - μs
Table 12 – Power-Up
VDD
VDD
V
(max)
VDD(min)
WI
tPU
Time
Normal Operation
Chip Selection not allowed
Reset state
of the
device
Figure 14 – Power-Up Timing
Power-Up Timing
17Copyright © 2017 Everspin Technologies MR25H256 / MR25H256A Rev. 1.4, 2/2017
MR25H256 / MR25H256A
Over the Operating Temperature Range and CL = 30 pF
Symbol Parameter Min Max Unit
fSCK SCK Clock Frequency 0 40 MHz
tRI Input Rise Time - 50 ns
tRF Input Fall Time - 50 ns
tWH SCK High Time 11 - ns
tWL SCK Low Time 11 - ns
Synchronous Data Timing (See “Figure 15 – Synchronous Data Timing” on page 19
tCS CS High Time 40 - ns
tCSS CS Setup Time 10 - ns
tCSH CS Hold Time 10 - ns
tSU Data In Setup Time 5 - ns
tHData In Hold Time 5 - ns
tVOutput Valid
Industrial Grade
VDD = 2.7 to 3.6v. 0 10 ns
VDD = 3.0 to 3.6v. 0 9 ns
AEC Q-100 Grade 3
VDD = 2.7 to 3.6v. 0 10 ns
VDD = 3.0 to 3.6v. 0 9 ns
AEC Q-100 Grade 1 VDD = 3.0 to 3.6v. 0 10 ns
Table continues next page.
Table 13 – AC Timing Parameters
Synchronous Data Timing
18Copyright © 2017 Everspin Technologies MR25H256 / MR25H256A Rev. 1.4, 2/2017
MR25H256 / MR25H256A
Symbol Parameter Min Max Unit
tHO Output Hold Time 0 - ns
HOLD Timing
tHD HOLD Setup Time 10 - ns
tCD HOLD Hold Time 10 - ns
tLZ HOLD to Output Low Impedance - 20 ns
tHZ HOLD to Output High Impedance - 20 ns
Other Timing Specications (See “Figure 16 – HOLD Timing” on page 19)
tWPS WP Setup To CS Low 5 - ns
tWPH WP Hold From CS High 5 - ns
tDP Sleep Mode Entry Time 3 - μs
tRDP Sleep Mode Exit Time 400 - μs
tDIS Output Disable Time 12 - ns
AC Timing Parameters (Continued)
19Copyright © 2017 Everspin Technologies MR25H256 / MR25H256A Rev. 1.4, 2/2017
MR25H256 / MR25H256A
Figure 16 – HOLD Timing
SCK
SO
CS
HOLD
HD
t
HZ
t
HD
t
CD
t
CD
t
LZ
t
Figure 15 – Synchronous Data Timing
SCK
SI
SO
CS
High Impedance
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
CSS
t
SU
tH
t
V
t
WH
tWL
t
CSH
t
CS
t
HO
tDIS
t
V
t
20Copyright © 2017 Everspin Technologies MR25H256 / MR25H256A Rev. 1.4, 2/2017
MR25H256 / MR25H256A
ORDERING INFORMATION
Table 14 – Ordering Part Number Decoder Table
Table 15 – Ordering Part Numbers
Grade Temperature Package Shipping Container Order Part Number
Industrial -40 to +85 C 8-DFN Small Flag Trays MR25H256ACDF
Tape and Reel MR25H256ACDFR
AEC-Q100 Grade 3 -40 to +85 C 8-DFN Small Flag Trays MR25H256APDF
Tape and Reel MR25H256APDFR
AEC-Q100 Grade 1 -40 to +125 C 8-DFN Small Flag Trays MR25H256AMDF
Tape and Reel MR25H256AMDFR
Industrial -40 to +85 C 8-DFN Small Flag Trays MR25H256CDF 1
Tape and Reel MR25H256CDFR 1
Industrial -40 to +85 C 8-DFN Trays MR25H256CDC 1
Tape and Reel MR25H256CDCR 1
AEC-Q100 Grade 1 -40 to +125 C 8-DFN Small Flag Trays MR25H256MDF 1
Tape and Reel MR25H256MDFR 1
AEC-Q100 Grade 1 -40 to +125 C 8-DFN Trays MR25H256MDC 1
Tape and Reel MR25H256MDCR 1
Note:
1. Not recommended for new designs.
Memory Speed Voltage Density Revision Temp Package Grade
Example Ordering Part Number MR 25 H 256 A C DF
Everspin MRAM MR
40 MHz 25
3.0v. Vdd H
256 Kb 256
No Revision Blank
Revision A A
Revision B B
Industrial -40 to 85°C C
AEC Q-100 Grade 3 -40 to 85°C P
AEC-Q100 Grade 1 -40 to 125°C M
8-pin DFN DC
8-pin DFN Tape and Reel DCR
8-pin DFN (small flag) in Tray DF
8-pin DFN (small flag) Tape and Reel DFR
Engineering Samples ES
Customer Samples CS
Mass Producon Blank
21Copyright © 2017 Everspin Technologies MR25H256 / MR25H256A Rev. 1.4, 2/2017
MR25H256 / MR25H256A
A
D
B
C
G
KF
H
L
M
E
F1
4
5
J
I
Detail A
Detail A
Pin 1 Index
0.10 C2X
0.10 C2X
8
NOTE:
1. All dimensions are in mm. Angles in degrees.
2. Coplanarity applies to the exposed pad as well as the terminals. Coplanarity shall be
within 0.08 mm.
3. Refer to JEDEC MO-229-E
PACKAGE OUTLINE DRAWINGS
Figure 17 – 8-DFN Small Flag Package
Exposed metal Pad. Do not con-
nect anything except VSS
Dimension A B C D E F G H I J K L M
Max 5.10 6.10 0.90 - 0.45 0.05 1.54 0.70 2.10 2.10 0.210 - -
Nominal 5.00 6.00 0.85
1.27
BSC
0.40 - 1.40 0.60 2.00 2.00 0.200 C0.45 R0.20
Min 4.90 5.90 0.80 - 0.35 0.00 1.26 0.50 1.90 1.90 0.190 - -
22Copyright © 2017 Everspin Technologies MR25H256 / MR25H256A Rev. 1.4, 2/2017
MR25H256 / MR25H256A
A
D
B
C
G
K
N
H
DAP Size
4.4 x 4.4
L
M
E
F1
4
58
J
I
Detail A
Detail A
Pin 1 Index
NOTE:
1. All dimensions are in mm. Angles in degrees.
2. Coplanarity applies to the exposed pad as well as the terminals. Coplanarity shall be
within 0.08 mm.
3. Warpage shall not exceed 0.10 mm.
4. Refer to JEDEC MO-229-E
Figure 18 – 8-DFN Package
Exposed metal Pad. Do not
connect anything except VSS
Dimension A B C D E F G H I J K L M N
Max.
Min.
5.10
4.90
6.10
5.90
1.00
0.90
1.27
BSC
0.45
0.35
0.05
0.00
0.35
Ref.
0.70
0.50
4.20
4.00
4.20
4.00
0.261
0.195
C0.35 R0.20
0.05
0.00
Not Recommended for New Designs
23Copyright © 2017 Everspin Technologies MR25H256 / MR25H256A Rev. 1.4, 2/2017
MR25H256 / MR25H256A
Revision Date Description of Change
0.1 June 1, 2015 First Draft
0.2 September 29,
2015 Added Grade 3 parameters to Table 4.4 and reformatted the table.
0.3 November 2, 2015 Revised Part Number Decoder Table.
1.0 October 1, 2016
Production release. Removed all Preliminary status statements and
indications. Added nominal values to DFN package outline dimensions
table.
1.1 October 12, 2016 Combined with MR25H256 to make single data sheet for both product
families.
1.2 December 13,
2016 Revised product name in header.
1.3 December 20,
2016 Minor Revisions. 8-DFN package option will remain.
1.4 February 1, 2017 Added tHO and tV relationship to Synchronous Data Timing
REVISION HISTORY
24Copyright © 2017 Everspin Technologies MR25H256 / MR25H256A Rev. 1.4, 2/2017
MR25H256 / MR25H256A
Information in this document is provided solely to enable system and soft-
ware implementers to use Everspin Technologies products. There are no
express or implied licenses granted hereunder to design or fabricate any
integrated circuit or circuits based on the information in this document.
Everspin Technologies reserves the right to make changes without further
notice to any products herein. Everspin makes no warranty, representa-
tion or guarantee regarding the suitability of its products for any particu-
lar purpose, nor does Everspin Technologies assume any liability arising
out of the application or use of any product or circuit, and specically
disclaims any and all liability, including without limitation consequential
or incidental damages. “Typical” parameters, which may be provided in
Everspin Technologies data sheets and/or specications can and do vary
in dierent applications and actual performance may vary over time. All
operating parameters including “Typicals” must be validated for each cus-
tomer application by customer’s technical experts. Everspin Technologies
does not convey any license under its patent rights nor the rights of oth-
ers. Everspin Technologies products are not designed, intended, or au-
thorized for use as components in systems intended for surgical implant
into the body, or other applications intended to support or sustain life, or
for any other application in which the failure of the Everspin Technologies
product could create a situation where personal injury or death may oc-
cur. Should Buyer purchase or use Everspin Technologies products for any
such unintended or unauthorized application, Buyer shall indemnify and
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penses, and reasonable attorney fees arising out of, directly or indirectly,
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was negligent regarding the design or manufacture of the part. Everspin™
and the Everspin logo are trademarks of Everspin Technologies, Inc. All
other product or service names are the property of their respective owners.
Copyright © 2017 Everspin Technologies, Inc.
Everspin Technologies, Inc.
HOW TO REACH US
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Filename:
EST02896 MR25H256-MR25H256A Combined Datasheet_Rev1.4 020117
