R10DS0169EJ0203 Rev. 2.03 Page 1 of 37
Feb 01, 2019
Data Sheet
R1QAA7236ABB / R1QAA7218ABB
R1QDA7236ABB / R1QDA7218ABB
72-Mbit QDR™II+ SRAM
4-word Burst
Description
The R1Q#A7236 is a 2,097,152-word by 36-bit and the R1Q#A7218 is a 4,194,304-word by 18-bit
synchronous quad data rate static RAM fabricated with advanced CMOS technology using full CMOS six-
transistor memory cell. It integrates unique synchronous peripheral circuitry and a burst counter. All input
registers are controlled by an input clock pair (K and /K) and are latched on the positive edge of K and /K.
These products are suitable for applications which require synchronous operation, high speed, low voltage,
high density and wide bit configuration. These products are packaged in 165-pin plastic FBGA package.
# = A: Read Latency =2.5, w/o ODT
# = D: Read Latency =2.5, w/ ODT
Features
Power Supply
• 1.8 V for core (VDD), 1.4 V to VDD for I/O (VDDQ)
Clock
• Fast clock cycle time for high bandwidth
• Two input clocks (K and /K) for precise DDR timing at clock rising edges only
• Two output echo clocks (CQ and /CQ) simplify data capture in high-speed systems
• Clock-stop capability with s restart
I/O
• Separate independent read and write data ports with concurrent transactions
• 100% bus utilization DDR read and write operation
• HSTL I/O
• User programmable output impedance
• DLL/PLL circuitry for wide output data valid window and future frequency scaling
• Data valid pin (QVLD) to indicate valid data on the output
Function
• Four-tick burst for reduced address frequency
• Internally self-timed write control
• Simple control logic for easy depth expansion
• JTAG 1149.1 compatible test access port
Package
• 165 FBGA package (13 x 15 x 1.4 mm)
• RoHS Compliance Level = 6/6
R10DS0169EJ0203
Rev. 2.03
Feb 01, 2019
R1QAA7236ABB, R1QAA7218ABB, R1QDA7236ABB, R1QDA7218ABB
R10DS0169EJ0203 Rev. 2.03 Page 2 of 37
Feb 01, 2019
Part Number Definition
Column No.
0
1
2
3
4
5
6
7
8
10
11
-
12
13
14
15
16
Example
R
1
Q
A
A
7
2
1
8
B
B
-
1
9
I
B
1
The above part number is just example for 72M QDRII+ B4 x18 533MHz, 13x15mm
PKG, Pb-free part.
No.
-
Comments
No.
-
Comments
0-1
R1
Renesas Memory Prefix
9
A
2nd Generation
2-3
Q2
QDR II B2[*1] (L15)[*2]
10-11
BB
PKG = BGA 13x15 mm
Q3
QDR II B4 (L15)
12-13
40
Frequency = 250MHz
Q4
DDR II B2 (L15)
33
Frequency = 300MHz
QA
QDR II+ B4 L25
25
Frequency = 400MHz
QB
DDR II+ B2 L25
20
Frequency = 500MHz
QD
QDR II+ B4 L25 w/ ODT[*3]
19
Frequency = 533MHz
QE
DDR II+ B2 L25 w/ ODT
14
I
Industrial temp.
Ta range = -40oC to 85oC
QG
QDR II+ B2 L20
QH
DDR II+ B2 L20
15
B
Pb-free and Tray
4
A
VDD = 1.8 V
16
0 to 9,
A to Z
or None
Renesas internal use
5-6
72
Density = 72Mb
7-8
09
Data width = 9bit
18
Data width = 18bit
36
Data width = 36bit
Notes[*] 1. B=Burst length (B2: Burst length=2, B4: Burst length=4)
2. L=Read Latency (L15: Read Latency = 1.5 cycle, L20: 2.0 cycle, L25: 2.5 cycle)
3. ODT=On Die Termination
R1QAA7236ABB, R1QAA7218ABB, R1QDA7236ABB, R1QDA7218ABB
R10DS0169EJ0203 Rev. 2.03 Page 3 of 37
Feb 01, 2019
72M QDR/DDR SRAM (R1Q*A72 Series) Lineup
Renesas supports or plans to support the parts listed below.
No
Product
Type
Burst
Length
Latency
(Cycle)
ODT
Organi-
zation
Frequency (max)
(MHz)
533
500
400
300
250
Cycle Time (min)
(ns)
1.875
2.00
2.50
3.30
4.00
1
QDRII
B2
1.5
No
x 9
R1Q2A7209ABB-yy
-40
2
x18
R1Q2A7218ABB-yy
3
x36
R1Q2A7236ABB-yy
4
B4
x18
R1Q3A7218ABB-yy
-33
5
x36
R1Q3A7236ABB-yy
6
DDRII
B2
x18
R1Q4A7218ABB-yy
-33
7
x36
R1Q4A7236ABB-yy
8
QDRII+
B4
2.5
No
x18
R1QAA7218ABB-yy
-19
-20
9
x36
R1QAA7236ABB-yy
10
DDRII+
B2
x18
R1QBA7218ABB-yy
-19
-20
11
x36
R1QBA7236ABB-yy
12
QDRII+
B4
Yes
x18
R1QDA7218ABB-yy
-19
-20
13
x36
R1QDA7236ABB-yy
14
DDRII+
B2
x18
R1QEA7218ABB-yy
-19
-20
15
x36
R1QEA7236ABB-yy
16
QDRII+
B4
2.0
No
x18
R1QGA7218ABB-yy
-25
17
x36
R1QGA7236ABB-yy
18
DDRII+
B2
x18
R1QHA7218ABB-yy
-25
19
x36
R1QHA7236ABB-yy
Notes 1. "yy" represents the speed bin. "R1QDA7236ABB-20" can operate at 500 MHz(max) of frequency,
for example.
2. The part which is not listed above is not supported, as of the day when this datasheet was issued,
in spite of the existence of the part number or datasheet.
R1QAA7236ABB, R1QAA7218ABB, R1QDA7236ABB, R1QDA7218ABB
R10DS0169EJ0203 Rev. 2.03 Page 4 of 37
Feb 01, 2019
Pin Arrangement
R1QAA7236 series
(Top View)
1
2
3
4
5
6
7
8
9
10
11
A
/CQ
NC
SA
/W
/BW2
/K
/BW1
/R
SA
NC
CQ
B
Q27
Q18
D18
SA
/BW3
K
/BW0
SA
D17
Q17
Q8
C
D27
Q28
D19
VSS
SA
NC
SA
VSS
D16
Q7
D8
D
D28
D20
Q19
VSS
VSS
VSS
VSS
VSS
Q16
D15
D7
E
Q29
D29
Q20
VDDQ
VSS
VSS
VSS
VDDQ
Q15
D6
Q6
F
Q30
Q21
D21
VDDQ
VDD
VSS
VDD
VDDQ
D14
Q14
Q5
G
D30
D22
Q22
VDDQ
VDD
VSS
VDD
VDDQ
Q13
D13
D5
H
/DOFF
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
J
D31
Q31
D23
VDDQ
VDD
VSS
VDD
VDDQ
D12
Q4
D4
K
Q32
D32
Q23
VDDQ
VDD
VSS
VDD
VDDQ
Q12
D3
Q3
L
Q33
Q24
D24
VDDQ
VSS
VSS
VSS
VDDQ
D11
Q11
Q2
M
D33
Q34
D25
VSS
VSS
VSS
VSS
VSS
D10
Q1
D2
N
D34
D26
Q25
VSS
SA
SA
SA
VSS
Q10
D9
D1
P
Q35
D35
Q26
SA
SA
QVLD
SA
SA
Q9
D0
Q0
R
TDO
TCK
SA
SA
SA
NC
SA
SA
SA
TMS
TDI
Notes 1. Address expansion order for future higher density SRAMs: 10A → 2A → 7A → 5B.
2. NC pins can be left floating or connected to 0V ～ VDDQ.
R1QAA7236ABB, R1QAA7218ABB, R1QDA7236ABB, R1QDA7218ABB
R10DS0169EJ0203 Rev. 2.03 Page 5 of 37
Feb 01, 2019
R1QAA7218 series
(Top View)
1
2
3
4
5
6
7
8
9
10
11
A
/CQ
NC
SA
/W
/BW1
/K
NC
/R
SA
SA
CQ
B
NC
Q9
D9
SA
NC
K
/BW0
SA
NC
NC
Q8
C
NC
NC
D10
VSS
SA
NC
SA
VSS
NC
Q7
D8
D
NC
D11
Q10
VSS
VSS
VSS
VSS
VSS
NC
NC
D7
E
NC
NC
Q11
VDDQ
VSS
VSS
VSS
VDDQ
NC
D6
Q6
F
NC
Q12
D12
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
Q5
G
NC
D13
Q13
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
D5
H
/DOFF
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
J
NC
NC
D14
VDDQ
VDD
VSS
VDD
VDDQ
NC
Q4
D4
K
NC
NC
Q14
VDDQ
VDD
VSS
VDD
VDDQ
NC
D3
Q3
L
NC
Q15
D15
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
Q2
M
NC
NC
D16
VSS
VSS
VSS
VSS
VSS
NC
Q1
D2
N
NC
D17
Q16
VSS
SA
SA
SA
VSS
NC
NC
D1
P
NC
NC
Q17
SA
SA
QVLD
SA
SA
NC
D0
Q0
R
TDO
TCK
SA
SA
SA
NC
SA
SA
SA
TMS
TDI
Notes 1. Address expansion order for future higher density SRAMs: 10A → 2A → 7A → 5B.
2. NC pins can be left floating or connected to 0V ～ VDDQ.
R1QAA7236ABB, R1QAA7218ABB, R1QDA7236ABB, R1QDA7218ABB
R10DS0169EJ0203 Rev. 2.03 Page 6 of 37
Feb 01, 2019
R1QDA7236 series
(Top View)
1
2
3
4
5
6
7
8
9
10
11
A
/CQ
NC
SA
/W
/BW2
/K
/BW1
/R
SA
NC
CQ
B
Q27
Q18
D18
SA
/BW3
K
/BW0
SA
D17
Q17
Q8
C
D27
Q28
D19
VSS
SA
NC
SA
VSS
D16
Q7
D8
D
D28
D20
Q19
VSS
VSS
VSS
VSS
VSS
Q16
D15
D7
E
Q29
D29
Q20
VDDQ
VSS
VSS
VSS
VDDQ
Q15
D6
Q6
F
Q30
Q21
D21
VDDQ
VDD
VSS
VDD
VDDQ
D14
Q14
Q5
G
D30
D22
Q22
VDDQ
VDD
VSS
VDD
VDDQ
Q13
D13
D5
H
/DOFF
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
J
D31
Q31
D23
VDDQ
VDD
VSS
VDD
VDDQ
D12
Q4
D4
K
Q32
D32
Q23
VDDQ
VDD
VSS
VDD
VDDQ
Q12
D3
Q3
L
Q33
Q24
D24
VDDQ
VSS
VSS
VSS
VDDQ
D11
Q11
Q2
M
D33
Q34
D25
VSS
VSS
VSS
VSS
VSS
D10
Q1
D2
N
D34
D26
Q25
VSS
SA
SA
SA
VSS
Q10
D9
D1
P
Q35
D35
Q26
SA
SA
QVLD
SA
SA
Q9
D0
Q0
R
TDO
TCK
SA
SA
SA
NC
SA
SA
SA
TMS
TDI
Notes 1. Address expansion order for future higher density SRAMs: 10A → 2A → 7A → 5B.
2. NC pins can be left floating or connected to 0V ～ VDDQ.
R1QAA7236ABB, R1QAA7218ABB, R1QDA7236ABB, R1QDA7218ABB
R10DS0169EJ0203 Rev. 2.03 Page 7 of 37
Feb 01, 2019
R1QDA7218 series
(Top View)
1
2
3
4
5
6
7
8
9
10
11
A
/CQ
NC
SA
/W
/BW1
/K
NC
/R
SA
SA
CQ
B
NC
Q9
D9
SA
NC
K
/BW0
SA
NC
NC
Q8
C
NC
NC
D10
VSS
SA
NC
SA
VSS
NC
Q7
D8
D
NC
D11
Q10
VSS
VSS
VSS
VSS
VSS
NC
NC
D7
E
NC
NC
Q11
VDDQ
VSS
VSS
VSS
VDDQ
NC
D6
Q6
F
NC
Q12
D12
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
Q5
G
NC
D13
Q13
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
D5
H
/DOFF
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
J
NC
NC
D14
VDDQ
VDD
VSS
VDD
VDDQ
NC
Q4
D4
K
NC
NC
Q14
VDDQ
VDD
VSS
VDD
VDDQ
NC
D3
Q3
L
NC
Q15
D15
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
Q2
M
NC
NC
D16
VSS
VSS
VSS
VSS
VSS
NC
Q1
D2
N
NC
D17
Q16
VSS
SA
SA
SA
VSS
NC
NC
D1
P
NC
NC
Q17
SA
SA
QVLD
SA
SA
NC
D0
Q0
R
TDO
TCK
SA
SA
SA
NC
SA
SA
SA
TMS
TDI
Notes 1. Address expansion order for future higher density SRAMs: 10A → 2A → 7A → 5B.
2. NC pins can be left floating or connected to 0V ～ VDDQ.
R1QAA7236ABB, R1QAA7218ABB, R1QDA7236ABB, R1QDA7218ABB
R10DS0169EJ0203 Rev. 2.03 Page 8 of 37
Feb 01, 2019
Pin Description
Name
I/O type
Descriptions
Notes
SA
Input
Synchronous address inputs: These inputs are registered and must meet
the setup and hold times around the rising edge of K. All transactions
operate on a burst-of-four words (two clock periods of bus activity).
These inputs are ignored when device is deselected.
/R
Input
Synchronous read: When low, this input causes the address inputs to be
registered and a READ cycle to be initiated. This input must meet setup
and hold times around the rising edge of K, and is ignored on the
subsequent rising edge of K.
/W
Input
Synchronous write: When low, this input causes the address inputs to be
registered and a WRITE cycle to be initiated. This input must meet setup
and hold times around the rising edge of K, and is ignored on the
subsequent rising edge of K.
/BWx
Input
Synchronous byte writes: When low, these inputs cause their respective
byte to be registered and written during WRITE cycles. These signals
are sampled on the same edge as the corresponding data and must
meet setup and hold times around the rising edges of K and /K for each
of the two rising edges comprising the WRITE cycle. See Byte Write
Truth Table for signal to data relationship.
K, /K
Input
Input clock: This input clock pair registers address and control inputs on
the rising edge of K, and registers data on the rising edge of K and the
rising edge of /K. /K is ideally 180 degrees out of phase with K. All
synchronous inputs must meet setup and hold times around the clock
rising edges. These balls cannot remain VREF level.
/DOFF
Input
DLL/PLL disable: When low, this input causes the DLL/PLL to be
bypassed for stable, low frequency operation.
TMS
TDI
Input
IEEE1149.1 test inputs: 1.8 V I/O levels. These balls may be left not
connected if the JTAG function is not used in the circuit.
TCK
Input
IEEE1149.1 clock input: 1.8 V I/O levels. This ball must be tied to VSS if
the JTAG function is not used in the circuit.
ZQ
Input
Output impedance matching input: This input is used to tune the device
outputs to the system data bus impedance. Q and CQ output impedance
are set to 0.2 RQ, where RQ is a resistor from this ball to ground. This
ball can be connected directly to VDDQ, which enables the minimum
impedance mode. This ball cannot be connected directly to VSS or left
unconnected.
In ODT (On Die Termination) enable devices, the ODT termination
values tracks the value of RQ. The ODT range is selected by ODT
control input.
ODT
Input
ODT control: When low;
[Option 1] Low range mode is selected. The impedance range is
between 52 and 105 (Thevenin equivalent), which follows 0.3 x RQ
for 175 ≤ RQ ≤ 350 .
[Option 2] ODT is disabled.
When high;
High range mode is selected. The impedance range is between 105
and 150 (Thevenin equivalent), which follows 0.6 x RQ for 175 ≤ RQ
≤ 250 .
When floating;
[Option 1] High range mode is selected.
[Option 2] ODT is disabled.
1
R1QAA7236ABB, R1QAA7218ABB, R1QDA7236ABB, R1QDA7218ABB
R10DS0169EJ0203 Rev. 2.03 Page 9 of 37
Feb 01, 2019
Name
I/O type
Descriptions
Notes
D0 to Dn
Input
Synchronous data inputs: Input data must meet setup and hold times
around the rising edges of K and /K during WRITE operations. See Pin
Arrangement figures for ball site location of individual signals.
The x9 device uses D0~D8. D9~D35 should be treated as NC pin.
The x18 device uses D0~D17. D18~D35 should be treated as NC pin.
The x36 device uses D0~D35.
CQ, /CQ
Output
Synchronous echo clock outputs: The edges of these outputs are tightly
matched to the synchronous data outputs and can be used as a data
valid indication. These signals run freely and do not stop when Q tri-
states.
TDO
Output
IEEE 1149.1 test output: 1.8 V I/O level.
Q0 to Qn
Output
Synchronous data outputs: Output data is synchronized to the respective
C and /C, or to the respective K and /K if C and /C are tied high. This bus
operates in response to /R commands. See Pin Arrangement figures for
ball site location of individual signals.
The x9 device uses Q0~Q8. Q9~Q35 should be treated as NC pin.
The x18 device uses Q0~Q17. Q18~Q35 should be treated as NC pin.
The x36 device uses Q0~Q35.
QVLD
Output
Valid output indicator: The Q Valid indicates valid output data. QVLD is
edge aligned with CQ and /CQ.
VDD
Supply
Power supply: 1.8 V nominal. See DC Characteristics and Operating
Conditions for range.
2
VDDQ
Supply
Power supply: Isolated output buffer supply. Nominally 1.5 V. See DC
Characteristics and Operating Conditions for range.
2
VSS
Supply
Power supply: Ground.
2
VREF
-
HSTL input reference voltage: Nominally VDDQ/2, but may be adjusted to
improve system noise margin. Provides a reference voltage for the HSTL
input buffers.
NC
-
No connect: These pins can be left floating or connected to 0V ～ VDDQ.
Notes 1. Renesas status: Option 1 = Available, Option 2 = Possible.
2. All power supply and ground balls must be connected for proper operation of the device
R1QAA7236ABB, R1QAA7218ABB, R1QDA7236ABB, R1QDA7218ABB
R10DS0169EJ0203 Rev. 2.03 Page 10 of 37
Feb 01, 2019
Block Diagram
R1QAA7236 / R1QAA7218 / R1QDA7236 / R1QDA7218 series
Note 1. C and /C pins do not exist in II+ series parts.
Address
/R
/W
K
/K
/W
/BWx
D
(Data in)
/R
K
/K
72
/36
/18 144
/72
/36
19/20/21
36/18/9
36/18/9
Q
(Data out)
19/20/21
KC,/C
or
K,/K
ZQ
2
CQ
/CQ
72
/36
/18
Address
Registry
and
Logic
Data
Registry
and
Logic
Memory
Array
Write
Register
Output
Register
Output
Select
Output
Buffer
Write Driver
Sense Amp
MUX
MUX
72
/36
/18
72
/36
/18
4/2/1
C
or
K
R1QAA7236ABB, R1QAA7218ABB, R1QDA7236ABB, R1QDA7218ABB
R10DS0169EJ0203 Rev. 2.03 Page 11 of 37
Feb 01, 2019
General Description
Power-up and Initialization Sequence
- VDD must be stable before K, /K clocks are applied.
- Recommended voltage application sequence : VSS → VDD → VDDQ & VREF → VIN. (0 V to VDD, VDDQ < 200 ms)
- Apply VREF after VDDQ or at the same time as VDDQ.
- Then execute either one of the following three sequences.
1. Single Clock Mode (C and /C tied high)
- Drive /DOFF high (/DOFF can be tied high from the start).
- Then provide stable clocks (K, /K) for at least 1024 cycles (II series) or 20 us (II+ series).
These meet the QDR common specification of 20 us.
When the operating frequency is less than 180 MHz, 2048 cycles are required (II series).
Status
Power Up &
Unstable Stage
NOP &
Set
-
up Stage
Normal
Operation
V
DD
SET
-
UP Cycle
V
DDQ
V
REF
/DOFF
K, /K
Fix High (=VDDQ)
R1QAA7236ABB, R1QAA7218ABB, R1QDA7236ABB, R1QDA7218ABB
R10DS0169EJ0203 Rev. 2.03 Page 12 of 37
Feb 01, 2019
2. Double Clock Mode (C and /C control outputs) (II series only)
- Drive /DOFF high (/DOFF can be tied high from the start)
- Then provide stable clocks (K, /K, C, /C) for at least 1024 cycles.
This meets the QDR common specification of 20 us.
When the operating frequency is less than 180 MHz, 2048 cycles are required.
3. DLL/PLL Off Mode (/DOFF tied low)
- In the "NOP and setup stage", provide stable clocks (K, /K) for at least 1024 cycles (II series) or 20 us (II+
series). These meet the QDR common specification of 20 us.
DLL/PLL Constraints
1. DLL/PLL uses K clock as its synchronizing input. The input should have low phase jitter which is specified
as tKC var.
2. The lower end of the frequency at which the DLL/PLL can operate is 120 MHz.
(Please refer to AC Characteristics table for detail.)
3. When the operating frequency is changed or /DOFF level is changed, setup cycles are required again.
Programmable Output Impedance
1. Output buffer impedance can be programmed by terminating the ZQ ball to VSS through a precision
resistor (RQ). The value of RQ is five times the output impedance desired. The allowable range of RQ to
guarantee impedance matching with a tolerance of 15% is 250 typical. The total external capacitance of
ZQ ball must be less than 7.5 pF.
QVLD (Valid data indicator)
1. QVLD is provided on the QDR-II+ and DDR-II+ to simplify data capture on high speed systems. The Q
Valid indicates valid output data. QVLD is activated half cycle before the read data for the receiver to be
ready for capturing the data. QVLD is inactivated half cycle before the read finish for the receiver to stop
capturing the data. QVLD is edge aligned with CQ and /CQ.
Status
Power Up &
Unstable Stage
NOP &
Set
-
up Stage
Normal
Operation
V
DD
SET
-
UP Cycle
V
DDQ
V
REF
/DOFF
K, /K
Fix High (=VDDQ)
C, /C
R1QAA7236ABB, R1QAA7218ABB, R1QDA7236ABB, R1QDA7218ABB
R10DS0169EJ0203 Rev. 2.03 Page 13 of 37
Feb 01, 2019
ODT (On Die Termination)
R1QD, R1QE series
1. To reduce reflection which produces noise and lowers signal quality, the signals should be terminated,
especially at high frequency. Renesas offers ODT on the input signals to QDR-II+ and DDR-II+ family of
devices. (See the ODT pin table)
2. In ODT enable devices, the ODT termination values tracks the value of RQ. The ODT range is selected by
ODT control input. (See the ODT range table)
3. In DDR-II+ devices having common I/O bus, ODT is automatically enabled when the device inputs data
and disabled when the device outputs data.
4. There is no difference in AC timing characteristics between the SRAMs with ODT and SRAMs without
ODT.
5. There is no increase in the IDD of SRAMs with ODT, however, there is an increase in the IDDQ (current
consumption from the I/O voltage supply) with ODT.
ODT range
ODT control pin
Thevenin equivalent resistance (RTHEV)
Unit
Notes
Option 1
Option 2
-
6
Low
0.3 RQ
(ODT disable)
1, 4
High
0.6 RQ
0.6 RQ
2, 5
Floating
0.6 RQ
(ODT disable)
3
Notes 1. Allowable range of RQ for Option 1 to guarantee impedance matching a tolerance of 20 % is
175 ≤ RQ ≤ 350 .
2. Allowable range of RQ to guarantee impedance matching a tolerance of 20 % is 175 ≤ RQ ≤
250 .
3. Allowable range of RQ for Option 1 to guarantee impedance matching a tolerance of 20 % is
175 ≤ RQ ≤ 250 .
4. At option 1, ODT control pin is connected to VDDQ through 3.5 k. Therefore it is recommended to
connect it to VSS through less than 100 to make it low.
5. At option 2, ODT control pin is connected to VSS through 3.5 k. Therefore it is recommended to
connect it to VDDQ through less than 100 to make it high.
6. Renesas status: Option 1 = Available, Option 2 = Possible. If you need devices with option 2,
please contact Renesas sales office.
R1QAA7236ABB, R1QAA7218ABB, R1QDA7236ABB, R1QDA7218ABB
R10DS0169EJ0203 Rev. 2.03 Page 14 of 37
Feb 01, 2019
Thevenin termination
ODT pin
R1QD, R1QE series
Pin name
ODT On/Off timing
Notes
Option 1
Option 2
3
ODT pin = High
ODT pin = Low
or Floating
D0 ~ Dn in separate I/O devices
Always On
Always Off
1
DQ0 ~ DQn
in common I/O devices
Off: First Read Command
+ Read Latency
- 0.5 cycle
On: Last Read Command
+ Read Latency
+ BL/2 cycle + 0.5 cycle
(See below timing chart)
Always Off
2
/BWx
Always On
Always Off
K, /K
Always On
Always Off
Notes 1. Separate I/O devices is R1QD series.
2. Common I/O devices is R1QE series.
3. Renesas status: Option 1 = Available, Option 2 = Possible. If you need devices with option 2,
please contact Renesas sales office.
Output
Buffer
SRAM with ODT
2 RTHEV
2 RTHEV
VDDQ
Other LSI
Input
Buffer
VSS
ZQ
VSS
RQ
R1QAA7236ABB, R1QAA7218ABB, R1QDA7236ABB, R1QDA7218ABB
R10DS0169EJ0203 Rev. 2.03 Page 15 of 37
Feb 01, 2019
K Truth Table
Operation
K
/LD
R-/W
D or Q
Write Cycle : Load
address, input write
data on consecutive
K and /K rising
edges
↑
H*7
L*8
Data in
Input data
D(A+0)
D(A+1)
D(A+2)
D(A+3)
Input clock
K(t+1) ↑
/K(t+1) ↑
K(t+2) ↑
/K(t+2) ↑
Read Cycle : Load
address, output read
data on consecutive
C and /C rising
edges
↑
L*8
Data out
Output data
Q(A+0)
Q(A+1)
Q(A+2)
Q(A+3)
Input
clock
for Q
RL*9 =
1.5
/C(t+1) ↑
C(t+2) ↑
/C(t+2) ↑
C(t+3) ↑
RL =
2.0
C(t+2) ↑
/C(t+2) ↑
C(t+3) ↑
/C(t+3) ↑
RL =
2.5
/C(t+2) ↑
C(t+3) ↑
/C(t+3) ↑
C(t+4) ↑
NOP (No operation)
↑
H
H
D = or Q = High-Z
Standby
(Clock stopped)
Stopped
Previous state
Notes 1. H: high level, L: low level, : don’t care, ↑: rising edge.
2. Data inputs are registered at K and /K rising edges. Data outputs are delivered at C and /C rising
edges, except if C and /C are high, then data outputs are delivered at K and /K rising edges.
3. /R and /W must meet setup/hold times around the rising edges (low to high) of K and are
registered at the rising edge of K.
4. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
5. Refer to state diagram and timing diagrams for clarification.
6. When clocks are stopped, the following cases are recommended; the case of K = low, /K = high,
C = low and /C = high, or the case of K = high, /K = low, C = high and /C = low. This condition is
not essential, but permits most rapid restart by overcoming transmission line charging
symmetrically.
7. If this signal was low to initiate the previous cycle, this signal becomes a “don’t care” for this
operation; however, it is strongly recommended that this signal be brought high, as shown in the
truth table.
8. This signal was high on previous K clock rising edge. Initiating consecutive READ or WRITE
operations on consecutive K clock rising edges is not permitted. The device will ignore the second
request.
9. RL = Read Latency (unit = cycle).
R1QAA7236ABB, R1QAA7218ABB, R1QDA7236ABB, R1QDA7218ABB
R10DS0169EJ0203 Rev. 2.03 Page 16 of 37
Feb 01, 2019
Byte Write Truth Table (x36)
Operation
K
/K
/BW0
/BW1
/BW2
/BW3
Write D0 to D35
↑
-
L
L
L
L
-
↑
L
L
L
L
Write D0 to D8
↑
-
L
H
H
H
-
↑
L
H
H
H
Write D9 to D17
↑
-
H
L
H
H
-
↑
H
L
H
H
Write D18 to D26
↑
-
H
H
L
H
-
↑
H
H
L
H
Write D27 to D35
↑
-
H
H
H
L
-
↑
H
H
H
L
Write nothing
↑
-
H
H
H
H
-
↑
H
H
H
H
Notes 1. H: high level, L: low level, ↑: rising edge.
2. Assumes a WRITE cycle was initiated. /BWx can be altered for any portion of the BURST WRITE
operation provided that the setup and hold requirements are satisfied.
Byte Write Truth Table (x18)
Operation
K
/K
/BW0
/BW1
Write D0 to D17
↑
-
L
L
-
↑
L
L
Write D0 to D8
↑
-
L
H
-
↑
L
H
Write D9 to D17
↑
-
H
L
-
↑
H
L
Write nothing
↑
-
H
H
-
↑
H
H
Notes 1. H: high level, L: low level, ↑: rising edge.
2. Assumes a WRITE cycle was initiated. /BWx can be altered for any portion of the BURST WRITE
operation provided that the setup and hold requirements are satisfied.
R1QAA7236ABB, R1QAA7218ABB, R1QDA7236ABB, R1QDA7218ABB
R10DS0169EJ0203 Rev. 2.03 Page 17 of 37
Feb 01, 2019
Bus Cycle State Diagram
Notes 1. The address is concatenated with two additional internal LSBs to facilitate burst operation. The
address order is always fixed as: xxx…xxx+0, xxx…xxx+1, xxx…xxx+2, xxx…xxx+3.
Bus cycle is terminated at the end of this sequence (burst count = 4).
2. Read and write state machines can be active simultaneously. Read and write cannot be
simultaneously initiated. Read takes precedence.
3. State machine control timing sequence is controlled by K.
Read Port NOP
RInit = 0 Read Double
RCount
= RCount + 2
Load New
Read Address
RCount = 0
RInit = 1
Power Up
/R = H
Write Port NOP
/W = H
Supply voltage
provided
Supply voltage
provided
/R = L Always
/R = L
&
RCount = 4
Increment
Read Address
by Two*1
RInit = 0
Always
RCount
= 2
/R = H & RCount = 4
Write Double
WCount
= WCount + 2
Load New
Write Address
WCount = 0
/W = L
RInit = 0
Always
/W = L
&
WCount = 4
Increment
Write Address
by Two*1
Always
WCount
= 2
/W = H & WCount = 4
R1QAA7236ABB, R1QAA7218ABB, R1QDA7236ABB, R1QDA7218ABB
R10DS0169EJ0203 Rev. 2.03 Page 18 of 37
Feb 01, 2019
Absolute Maximum Ratings
Parameter
Symbol
Rating
Unit
Notes
Input voltage on any ball
VIN
-0.5 to VDD + 0.5
(2.5 V max.)
V
1, 4
Input/output voltage
VI/O
-0.5 to VDDQ + 0.5
(2.5 V max.)
V
1, 4
Core supply voltage
VDD
-0.5 to 2.5
V
1, 4
Output supply voltage
VDDQ
-0.5 to VDD
V
1, 4
Junction temperature
Tj
+125 (max)
oC
5
Storage temperature
TSTG
-55 to +125
oC
Notes 1. All voltage is referenced to VSS.
2. Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional
operation should be restricted the Operation Conditions. Exposure to higher than recommended
voltages for extended periods of time could affect device reliability.
3. These CMOS memory circuits have been designed to meet the DC and AC specifications shown in
the tables after thermal equilibrium has been established.
4. The following supply voltage application sequence is recommended: VSS, VDD, VDDQ, VREF then VIN.
Remember, according to the Absolute Maximum Ratings table, VDDQ is not to exceed 2.5 V,
whatever the instantaneous value of VDDQ.
5. Some method of cooling or airflow should be considered in the system. (Especially for high
frequency or ODT parts)
Recommended DC Operating Conditions
Parameter
Symbol
Min
Typ
Max
Unit
Notes
Power supply voltage – core
VDD
1.7
1.8
1.9
V
1
Power supply voltage – I/O
VDDQ
1.4
1.5
VDD
V
1, 2
Input reference voltage – I/O
VREF
0.68
0.75
0.95
V
3
Input high voltage
VIH(DC)
VREF + 0.1
-
VDDQ + 0.3
V
1, 4, 5
Input low voltage
VIL(DC)
-0.3
-
VREF – 0.1
V
1, 4, 5
Notes 1. At power-up, VDD and VDDQ are assumed to be a linear ramp from 0V to VDD(min.) or VDDQ(min.)
within 200ms. During this time VDDQ < VDD and VIH < VDDQ. During normal operation, VDDQ must not
exceed VDD.
2. Please pay attention to Tj not to exceed the temperature shown in the absolute maximum ratings
table due to current from VDDQ.
3. Peak to peak AC component superimposed on VREF may not exceed 5% of VREF.
4. These are DC test criteria. The AC VIH / VIL levels are defined separately to measure timing
parameters.
5. Overshoot: VIH(AC) VDDQ + 0.5 V for t tKHKH/2
Undershoot: VIL(AC) -0.5 V for t tKHKH/2
During normal operation, VIH(DC) must not exceed VDDQ and VIL(DC) must not be lower than VSS.
R1QAA7236ABB, R1QAA7218ABB, R1QDA7236ABB, R1QDA7218ABB
R10DS0169EJ0203 Rev. 2.03 Page 19 of 37
Feb 01, 2019
DC Characteristics
Ta = -40 ~ +85C
VDD = 1.8V 0.1V, VDDQ = 1.5V, VREF = 0.75V
Operating Supply Current (Write / Read)
Symbol = IDD. Unit = mA.
No
Product
Type
Burst
Length
Latency
(Cycle)
ODT
Organi-
zation
Frequency (max)
(MHz)
533
500
400
300
250
200
Cycle Time (min)
(ns)
1.875
2.00
2.50
3.30
4.00
5.00
Speed bin
-19
-20
-25
-33
-40
1
QDR II
B2
1.5
No
x 9
R1Q2A7209ABB-yy
760
670
2
x18
R1Q2A7218ABB-yy
890
780
3
x36
R1Q2A7236ABB-yy
950
830
4
B4
x18
R1Q3A7218ABB-yy
820
730
5
x36
R1Q3A7236ABB-yy
850
750
6
DDR II
B2
x18
R1Q4A7218ABB-yy
700
630
7
x36
R1Q4A7236ABB-yy
760
680
8
QDR II+
B4
2.0
No
x18
R1QAA7218ABB-yy
1220
1160
1070
9
x36
R1QAA7236ABB-yy
1280
1220
1130
10
DDR II+
B2
x18
R1QBA7218ABB-yy
1030
990
920
11
x36
R1QBA7236ABB-yy
1110
1060
990
12
QDR II+
B4
Yes
x18
R1QDA7218ABB-yy
1220
1160
1070
13
x36
R1QDA7236ABB-yy
1280
1220
1130
14
DDR II+
B2
x18
R1QEA7218ABB-yy
1030
990
920
15
x36
R1QEA7236ABB-yy
1110
1060
990
16
QDR II+
B4
2.5
No
x18
R1QGA7218ABB-yy
980
17
x36
R1QGA7236ABB-yy
1060
18
DDR II+
B2
x18
R1QHA7218ABB-yy
850
19
x36
R1QHA7236ABB-yy
910
Notes 1. "yy" represents the speed bin. "R1QDA7236ABB-20" can operate at 500 MHz(max) of frequency,
for example.
2. All inputs (except ZQ, VREF) are held at either VIH or VIL.
3. IOUT = 0 mA. VDD = VDD max, tKHKH = tKHKH min.
4. Operating supply currents (IDD) are measured at 100% bus utilization. IDD of QDR family is current
of device with 100% write and 100% read cycle. IDD of DDR family is current of device with 100%
write cycle (if IDD(Write) > IDD(Read)) or 100% read cycle (if IDD(Write) < IDD(Read)).
R1QAA7236ABB, R1QAA7218ABB, R1QDA7236ABB, R1QDA7218ABB
R10DS0169EJ0203 Rev. 2.03 Page 20 of 37
Feb 01, 2019
Standby Supply Current (NOP)
Symbol = ISB1. Unit = mA.
No
Product
Type
Burst
Length
Latency
(Cycle)
ODT
Organi-
zation
Frequency (max)
(MHz)
533
500
400
300
250
200
Cycle Time (min)
(ns)
1.875
2.00
2.50
3.30
4.00
5.00
Speed bin
-19
-20
-25
-33
-40
1
QDR II
B2
1.5
No
x 9
R1Q2A7209ABB-yy
570
510
2
x18
R1Q2A7218ABB-yy
670
600
3
x36
R1Q2A7236ABB-yy
710
630
4
B4
x18
R1Q3A7218ABB-yy
590
520
5
x36
R1Q3A7236ABB-yy
610
540
6
DDR II
B2
x18
R1Q4A7218ABB-yy
610
560
7
x36
R1Q4A7236ABB-yy
670
610
8
QDR II+
B4
2.0
No
x18
R1QAA7218ABB-yy
870
830
780
9
x36
R1QAA7236ABB-yy
910
870
810
10
DDR II+
B2
x18
R1QBA7218ABB-yy
870
840
780
11
x36
R1QBA7236ABB-yy
960
920
860
12
QDR II+
B4
Yes
x18
R1QDA7218ABB-yy
870
830
780
13
x36
R1QDA7236ABB-yy
910
870
810
14
DDR II+
B2
x18
R1QEA7218ABB-yy
870
840
780
15
x36
R1QEA7236ABB-yy
960
920
860
16
QDR II+
B4
2.5
No
x18
R1QGA7218ABB-yy
720
17
x36
R1QGA7236ABB-yy
770
18
DDR II+
B2
x18
R1QHA7218ABB-yy
720
19
x36
R1QHA7236ABB-yy
790
Notes 1. "yy" represents the speed bin. "R1QDA7236ABB-20" can operate at 500 MHz(max) of frequency,
for example.
2. IOUT = 0 mA. VDD = VDD max, tKHKH = tKHKH min.
3. All address / data inputs are static at either VIN > VIH or VIN < VIL.
4. Reference value. (Condition = NOP currents are valid when entering NOP after all pending READ
and WRITE cycles are completed.)
R1QAA7236ABB, R1QAA7218ABB, R1QDA7236ABB, R1QDA7218ABB
R10DS0169EJ0203 Rev. 2.03 Page 21 of 37
Feb 01, 2019
Leakage Currents & Output Voltage
Parameter
Symbol
Min
Max
Unit
Test condition
Notes
Input leakage current
ILI
-2
2
A
10
Output leakage current
ILO
-5
5
A
11
Output high voltage
VOH
(Low)
VDDQ – 0.2
VDDQ
V
|IOH| 0.1 mA
8, 9
VOH
VDDQ/2 – 0.12
VDDQ/2 + 0.12
V
6, 8, 9
Output low voltage
VOL
(Low)
VSS
0.2
V
IOL 0.1 mA
8, 9
VOL
VDDQ/2 – 0.12
VDDQ/2 + 0.12
V
7, 8, 9
Notes 1. All inputs (except ZQ, VREF) are held at either VIH or VIL.
2. IOUT = 0 mA. VDD = VDD max, tKHKH = tKHKH min.
3. Operating supply currents (IDD) are measured at 100% bus utilization. IDD of QDR family is current
of device with 100% write and 100% read cycle. IDD of DDR family is current of device with 100%
write cycle (if IDD(Write) > IDD(Read)) or 100% read cycle (if IDD(Write) < IDD(Read)).
4. All address / data inputs are static at either VIN > VIH or VIN < VIL.
5. Reference value. (Condition = NOP currents are valid when entering NOP after all pending READ
and WRITE cycles are completed.)
6. Outputs are impedance-controlled. |IOH| = (VDDQ/2)/(RQ/5) for values of 175 RQ 350 .
7. Outputs are impedance-controlled. IOL = (VDDQ/2)/(RQ/5) for values of 175 RQ 350 .
8. AC load current is higher than the shown DC values. AC I/O curves are available upon request.
9. HSTL outputs meet JEDEC HSTL Class I and Class II standards.
10. 0 VIN VDDQ for all input balls (except VREF, ZQ, TCK, TMS, TDI ball).
If R1QD and R1QE series, balls with ODT do not follow this spec.
11. 0 VOUT VDDQ (except TDO ball), output disabled.
Thermal Resistance
Parameter
Symbol
Airflow
Typ
Unit
Test condition
Notes
Junction to Ambient
JA
1 m/s
11.0
oC/W
EIA/JEDEC JESD51
1
Junction to Case
JA
-
4.4
Notes 1. These parameters are calculated under the condition. These are reference values.
2. Tj = Ta + θJA × Pd
Tj = Tc + θJC × Pd
where
Tj : Junction temperature when the device has achieved a steady-state after application of Pd (°C)
Ta : Ambient temperature (°C)
Tc : Temperature of external surface of the package or case (°C)
θJA : Thermal resistance from junction-to-ambient (°C/W)
θJC : Thermal resistance from junction-to-case (package) (°C/W)
Pd : Power dissipation that produced change in junction temperature (W) (cf.JESD51-2A)
R1QAA7236ABB, R1QAA7218ABB, R1QDA7236ABB, R1QDA7218ABB
R10DS0169EJ0203 Rev. 2.03 Page 22 of 37
Feb 01, 2019
Capacitance
Ta = +25C, Frequency = 1.0MHz, VDD = 1.8V, VDDQ = 1.5V
Parameter
Symbol
Min
Typ
Max
Unit
Test condition
Notes
Input capacitance
(SA, /R, /W, /BW, D(separate))
CIN
-
4
5
pF
VIN = 0 V
1, 2
Clock input capacitance
(K, /K, C, /C)
CCLK
-
4
5
pF
VCLK = 0 V
1, 2
Output capacitance
(Q(separate), DQ(common), CQ, /CQ)
CI/O
-
5
6
pF
VI/O = 0 V
1, 2
Notes 1. These parameters are sampled and not 100% tested.
2. Except JTAG (TCK, TMS, TDI, TDO) pins.
AC Test Conditions
Input waveform
Rise/fall time 0.3 ns
Output waveform
1.25V
0.25V
0.75V 0.75VTest points
VDDQ/2 Test points VDDQ/2
R1QAA7236ABB, R1QAA7218ABB, R1QDA7236ABB, R1QDA7218ABB
R10DS0169EJ0203 Rev. 2.03 Page 23 of 37
Feb 01, 2019
Output load conditions
AC Operating Conditions
Parameter
Symbol
Min
Typ
Max
Unit
Notes
Input high voltage
VIH(AC)
VREF + 0.2
-
-
V
1, 2, 3, 4
Input low voltage
VIL(AC)
-
-
VREF – 0.2
V
1, 2, 3, 4
Notes 1. All voltages referenced to VSS (GND).
During normal operation, VDDQ must not exceed VDD.
2. These conditions are for AC functions only, not for AC parameter test.
3. Overshoot: VIH(AC) VDDQ + 0.5 V for t tKHKH/2
Undershoot: VIL(AC) -0.5 V for t tKHKH/2
Control input signals may not have pulse widths less than tKHKL(min) or operate at cycle rates less
than tKHKH(min).
4. To maintain a valid level, the transitioning edge of the input must:
a. Sustain a constant slew rate from the current AC level through the target AC level, VIL(AC) or VIH(AC).
b. Reach at least the target AC level.
c. After the AC target level is reached, continue to maintain at least the target DC level, VIL(DC) or VIH(DC).
50
ZQ
Q
VREF
250
Z0
= 50
SRAM
VDDQ
/ 2
= 0.75V
V
DDQ
/ 2
=
0.75 V
V
DD
V
DDQ
V
SS
1.8V
0.1V
1.5V
R1QAA7236ABB, R1QAA7218ABB, R1QDA7236ABB, R1QDA7218ABB
R10DS0169EJ0203 Rev. 2.03 Page 24 of 37
Feb 01, 2019
AC Characteristics (QDR-II+, DDR-II+ series, Read Latency = 2.5cycle)
Ta = -40 ~ +85C
VDD = 1.8V 0.1V, VDDQ = 1.5V, VREF = 0.75V
Parameter
Symbol
-19
-20
U
n
I
t
N
o
t
e
s
533 MHz
500 MHz
450 MHz
200 MHz
375 MHz
333 MHz
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Clock
Average
clock
cycle time
(K, /K)
tKHKH
1.875
4.00
2.00
4.00
2.22
4.00
2.50
4.00
2.66
4.00
3.00
4.00
ns
Clock high
time
(K, /K)
tKHKL
0.40
-
0.40
-
0.40
-
0.40
-
0.40
-
0.40
-
Cy
cle
Clock low
time
(K, /K)
tKLKH
0.40
-
0.40
-
0.40
-
0.40
-
0.40
-
0.40
-
Cy
cle
Clock to
/clock
(K to /K)
tKH/KH
0.425
-
0.425
-
0.425
-
0.425
-
0.425
-
0.425
-
Cy
cle
/Clock to
clock
(/K to K)
t/KHKH
0.425
-
0.425
-
0.425
-
0.425
-
0.425
-
0.425
-
Cy
cle
DLL / PLL timing
Clock phase
jitter
(K, /K)
tKC var
-
0.15
-
0.15
-
0.15
-
0.20
-
0.20
-
0.20
ns
3
Lock time
(K)
tKC lock
20
-
20
-
20
-
20
-
20
-
20
-
us
2
K static to
DLL/PLL
reset
tKC reset
30
-
30
-
30
-
30
-
30
-
30
-
ns
7
Output times
K, /K high to
output valid
tCHQV
-
0.45
-
0.45
-
0.45
-
0.45
-
0.45
-
0.45
ns
K, /K high to
output hold
tCHQX
-0.45
-
-0.45
-
-0.45
-
-0.45
-
-0.45
-
-0.45
-
ns
K, /K high to
echo clock
valid
tCHCQV
-
0.45
-
0.45
-
0.45
-
0.45
-
0.45
-
0.45
ns
K, /K high to
echo clock
hold
tCHCQX
-0.45
-
-0.45
-
-0.45
-
-0.45
-
-0.45
-
-0.45
-
ns
CQ, /CQ
high to
output valid
tCQHQV
-
0.15
-
0.15
-
0.15
-
0.20
-
0.20
-
0.20
ns
4,
7
CQ, /CQ
high to
output hold
tCQHQX
-0.15
-
-0.15
-
-0.15
-
-0.20
-
-0.20
-
-0.20
-
ns
4,
7
K, /K high to
output high-
Z
tCHQZ
-
0.45
-
0.45
-
0.45
-
0.45
-
0.45
-
0.45
ns
5,
6
K, /K high to
output low-Z
tCHQX1
-0.45
-
-0.45
-
-0.45
-
-0.45
-
-0.45
-
-0.45
-
ns
5
CQ high to
QVLD valid
tQVLD
-0.15
0.15
-0.15
0.15
-0.15
0.15
-0.20
0.20
-0.20
0.20
-0.20
0.20
ns
7
R1QAA7236ABB, R1QAA7218ABB, R1QDA7236ABB, R1QDA7218ABB
R10DS0169EJ0203 Rev. 2.03 Page 25 of 37
Feb 01, 2019
Parameter
Symbol
-19
-20
U
n
I
t
N
o
t
e
s
533 MHz
500 MHz
450 MHz
200 MHz
375 MHz
333 MHz
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Setup times
Address
valid to
K rising
edge
tAVKH
0.3
-
0.33
-
0.4
-
0.4
-
0.4
-
0.4
-
ns
1,
8
Control
inputs
valid to
K rising
edge
tIVKH
0.3
-
0.33
-
0.4
-
0.4
-
0.4
-
0.4
-
ns
1,
8
Data-in valid
to
K, /K rising
edge
tDVKH
0.2
-
0.22
-
0.25
-
0.28
-
0.28
-
0.28
-
ns
1,
9
Hold times
K rising
edge
to address
hold
tKHAX
0.3
-
0.33
-
0.4
-
0.4
-
0.4
-
0.4
-
ns
1,
8
K rising
edge
to control
inputs
hold
tKHIX
0.3
-
0.33
-
0.4
-
0.4
-
0.4
-
0.4
-
ns
1,
8
K, /K rising
edge
to data-in
hold
tKHDX
0.2
-
0.22
-
0.25
-
0.28
-
0.28
-
0.28
-
ns
1,
9
Notes 1. This is a synchronous device. All addresses, data and control lines must meet the specified setup
and hold times for all latching clock edges.
2. VDD and VDDQ slew rate must be less than 0.1 V DC per 50 ns for DLL/PLL lock retention. DLL/PLL
lock time begins once VDD, VDDQ and input clock are stable.
It is recommended that the device is kept inactive during these cycles.
This specification meets the QDR common spec. of 20 us.
3. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.
4. Echo clock is very tightly controlled to data valid / data hold. By design, there is a 0.1 ns variation
from echo clock to data. The datasheet parameters reflect tester guardbands and test setup
variations.
5. Transitions are measured 100 mV from steady-state voltage.
6. At any given voltage and temperature tCHQZ is less than tCHQX1 and tCHQV.
7. These parameters are sampled.
8. tAVKH, tIVKH, tKHAX, tKHIX spec is determined by the actual frequency regardless of Part Number
(Marking Name). The following is the spec for the actual frequency.
0.30 ns for ≤533MHz & >500MHz
0.33 ns for ≤500MHz & >450MHz
0.40 ns for ≤450MHz & ≥250MHz
R1QAA7236ABB, R1QAA7218ABB, R1QDA7236ABB, R1QDA7218ABB
R10DS0169EJ0203 Rev. 2.03 Page 26 of 37
Feb 01, 2019
9. tDVKH, tKHDX spec is determined by the actual frequency regardless of Part Number (Marking Name).
The following is the spec for the actual frequency.
0.20 ns for ≤533MHz & >500MHz
0.22 ns for ≤500MHz & >450MHz
0.25 ns for ≤450MHz & >400MHz
0.28 ns for ≤400MHz & ≥250MHz
Remarks 1. Test conditions as specified with the output loading as shown in AC Test Conditions unless
otherwise noted.
2. Control input signals may not be operated with pulse widths less than tKHKL (min).
3. VDDQ is +1.5 V DC. VREF is +0.75 V DC.
4. Control signals are /R, /W (QDR series), /LD, R-/W (DDR series), /BW, /BW0, /BW1, /BW2 and
/BW3. Setup and hold times of /BWx signals must be the same as those of Data-in signals.
R1QAA7236ABB, R1QAA7218ABB, R1QDA7236ABB, R1QDA7218ABB
R10DS0169EJ0203 Rev. 2.03 Page 27 of 37
Feb 01, 2019
Timing Waveforms
Read and Write Timing (QDRII+, B4, Read Latency = 2.5 cycle)
tQVLD
-tQVLD tQVLD
-tQVLD
Q00Qx3 Q01 Q02 Q03 Q20 Q21 Q22 Q23Qx2Qx1
tCHQV
-tCHQX tCHQV
-tCHQX tCQHQV
-tCQHQX
-tCHQX1
tCHQZ
tCHCQV
-tCHCQX
tCHCQV
-tCHCQX
K
A0
D10
A1 A2 A3
D11 D12 D13 D30 D31 D32 D33
NOP READ WRITE READ WRITE NOP NOP NOP
tKHIX
tIVKH
tKHIX
tIVKH
tKHAX
tAVKH
tKHDX
tDVKH tKHDX
tDVKH
/K
/R
/W
Address
Data in
tKHKH tKHKL
tKLKH tKH/KH
t/KHKH
Data out
CQ
/CQ
1 2 3 4 5 6 7 8 9
QVLD
R1QAA7236ABB, R1QAA7218ABB, R1QDA7236ABB, R1QDA7218ABB
R10DS0169EJ0203 Rev. 2.03 Page 28 of 37
Feb 01, 2019
Notes 1. Q00 refers to output from address A0+0. Q01 refers to output from the next internal burst address
following A0, i.e., A0+1.
2. Outputs are disabled (High-Z) N clock cycle after the last read cycle. Here, N = Read Latency +
Burst Length 0.5.
3. In this example, if address A2 = A1, then data Q20 = D10, Q21 = D11. Write data is forwarded
immediately as read results.
4. To control read and write operations, /BW signals must operate at the same timing as Data-in
signals.
JTAG Specification
These products support a limited set of JTAG functions as in IEEE standard 1149.1.
Disabling the Test Access Port
It is possible to use this device without utilizing the TAP. To disable the TAP controller without interfering with
normal operation of the device, TCK must be tied to VSS to preclude mid level inputs.
TDI and TMS are internally pulled up and may be unconnected, or may be connected to VDD through a pull
up resistor.
TDO should be left unconnected.
Test Access Port (TAP) Pins
Symbol I/O
Pin assignments
Description
Notes
TCK
2R
Test clock input. All inputs are captured on the rising edge of
TCK and all outputs propagate from the falling edge of TCK.
TMS
10R
Test mode select. This is the command input for the TAP
controller state machine.
TDI
11R
Test data input. This is the input side of the serial registers
placed between TDI and TDO. The register placed between
TDI and TDO is determined by the state of the TAP controller
state machine and the instruction that is currently loaded in
the TAP instruction.
TDO
1R
Test data output. Output changes in response to the falling
edge of TCK. This is the output side of the serial registers
placed between TDI and TDO.
Note 1. The device does not have TRST (TAP reset). The Test-Logic Reset state is entered while TMS is
held high for five rising edges of TCK. The TAP controller state is also reset on SRAM POWER-UP.
R1QAA7236ABB, R1QAA7218ABB, R1QDA7236ABB, R1QDA7218ABB
R10DS0169EJ0203 Rev. 2.03 Page 29 of 37
Feb 01, 2019
TAP DC Operating Characteristics
Ta = -40 ~ +85C
VDD = 1.8V 0.1V
Parameter
Symbol
Min
Typ
Max
Unit
Notes
Input high voltage
VIH
+1.3
-
VDD + 0.3
V
Input low voltage
VIL
-0.3
-
+0.5
V
Input leakage current
ILI
-5.0
-
+5.0
A
0 V VIN VDD
Output leakage current
ILO
-5.0
-
+5.0
A
0 V VIN VDD,
output disabled
Output low voltage
VOL1
-
-
0.2
V
IOLC = 100 A
VOL2
-
-
0.4
V
IOLT = 2 mA
Output high voltage
VOH1
1.6
-
-
V
|IOHC| = 100 A
VOH2
1.4
-
-
V
|IOHT| = 2 mA
Notes 1. All voltages referenced to VSS (GND).
2. At power-up, VDD and VDDQ are assumed to be a linear ramp from 0V to VDD(min.) or VDDQ(min.)
within 200ms. During this time VDDQ < VDD and VIH < VDDQ. During normal operation, VDDQ must not
exceed VDD.
TAP AC Test Conditions
Parameter
Symbol
Conditions
Unit
Notes
Input timing measurement reference levels
VREF
0.9
V
Input pulse levels
VIL, VIH
0 to 1.8
V
Input rise/fall time
tr, tf
1.0
ns
Output timing measurement reference levels
0.9
V
Test load termination supply voltage (VTT)
0.9
V
Output load
See figures
Input waveform
1.8V
0V
0.9V 0.9VTest points
R1QAA7236ABB, R1QAA7218ABB, R1QDA7236ABB, R1QDA7218ABB
R10DS0169EJ0203 Rev. 2.03 Page 30 of 37
Feb 01, 2019
Output waveform
Output load condition
TAP AC Operating Characteristics
Ta = -40 ~ +85C
VDD = 1.8V 0.1V
Parameter
Symbol
Min
Typ
Max
Unit
Notes
Test clock (TCK) cycle time
tTHTH
50
-
-
ns
TCK high pulse width
tTHTL
20
-
-
ns
TCK low pulse width
tTLTH
20
-
-
ns
Test mode select (TMS) setup
tMVTH
5
-
-
ns
TMS hold
tTHMX
5
-
-
ns
Capture setup
tCS
5
-
-
ns
1
Capture hold
tCH
5
-
-
ns
1
TDI valid to TCK high
tDVTH
5
-
-
ns
TCK high to TDI invalid
tTHDX
5
-
-
ns
TCK low to TDO unknown
tTLQX
0
-
-
ns
TCK low to TDO valid
tTLQV
-
-
10
ns
Note 1. tCS + tCH defines the minimum pause in RAM I/O pad transitions to assure pad data capture.
0.9V Test points 0.9V
External Load at Test
50
VTT = 0.9V
TDO Z0= 50
DUT
20pF
R1QAA7236ABB, R1QAA7218ABB, R1QDA7236ABB, R1QDA7218ABB
R10DS0169EJ0203 Rev. 2.03 Page 31 of 37
Feb 01, 2019
TAP Controller Timing Diagram
Test Access Port Registers
Register name
Length
Symbol
Notes
Instruction register
3 bits
IR [2:0]
Bypass register
1 bit
BP
ID register
32 bits
ID [31:0]
Boundary scan register
109 bits
BS [109:1]
TCK
TDI
TMS
TDO
PI
(SRAM)
tTHTLtTHTH tTLTH
tMVTH tTHMX
tDVTH tTHDX
tCS tCH
tTLQV
tTLQX
R1QAA7236ABB, R1QAA7218ABB, R1QDA7236ABB, R1QDA7218ABB
R10DS0169EJ0203 Rev. 2.03 Page 32 of 37
Feb 01, 2019
TAP Controller Instruction Set
IR2
IR1
IR0
Instruction
Description
Notes
0
0
0
EXTEST
The EXTEST instruction allows circuitry external to the
component package to be tested. Boundary scan register
cells at output balls are used to apply test vectors, while
those at input balls capture test results. Typically, the first
test vector to be applied using the EXTEST instruction will
be shifted into the boundary scan register using the
PRELOAD instruction. Thus, during the Update-IR state of
EXTEST, the output driver is turned on and the PRELOAD
data is driven onto the output balls.
1, 2,
3, 5
0
0
1
IDCODE
The IDCODE instruction causes the ID ROM to be loaded
into the ID register when the controller is in capture-DR
mode and places the ID register between the TDI and TDO
balls in shift-DR mode. The IDCODE instruction is the
default instruction loaded in at power up and any time the
controller is placed in the Test-Logic-Reset state.
0
1
0
SAMPLE-Z
If the SAMPLE-Z instruction is loaded in the instruction
register, all RAM outputs are forced to an inactive drive
state (High-Z), moving the TAP controller into the capture-
DR state loads the data in the RAMs input into the
boundary scan register, and the boundary scan register is
connected between TDI and TDO when the TAP controller
is moved to the shift-DR state.
3, 4, 5
0
1
1
RESERVED
The RESERVED instructions are not implemented but are
reserved for future use. Do not use these instructions.
1
0
0
SAMPLE
(/PRELOAD)
When the SAMPLE instruction is loaded in the instruction
register, moving the TAP controller into the capture-DR
state loads the data in the RAMs input and I/O buffers into
the boundary scan register. Because the RAM clock(s) are
independent from the TAP clock (TCK) it is possible for the
TAP to attempt to capture the I/O ring contents while the
input buffers are in transition (i.e., in a metastable state).
Although allowing the TAP to SAMPLE metastable input will
not harm the device, repeatable results cannot be
expected. Moving the controller to shift-DR state then
places the boundary scan register between the TDI and
TDO balls.
3, 5
1
0
1
RESERVED
-
1
1
0
RESERVED
-
1
1
1
BYPASS
The BYPASS instruction is loaded in the instruction register
when the bypass register is placed between TDI and TDO.
This occurs when the TAP controller is moved to the shift-
DR state. This allows the board level scan path to be
shortened to facilitate testing of other devices in the scan
path.
Notes 1. Data in output register is not guaranteed if EXTEST instruction is loaded.
2. After performing EXTEST, power-up conditions are required in order to return part to normal
operation.
3. RAM input signals must be stabilized for long enough to meet the TAPs input data capture setup
plus hold time (tCS plus tCH). The RAMs clock inputs need not be paused for any other TAP
operation except capturing the I/O ring contents into the boundary scan register.
4. Clock recovery initialization cycles are required after boundary scan.
5. For R1QD and R1QE series, ODT is disabled in EXTEST, SAMPLE-Z or SAMPLE mode.
R1QAA7236ABB, R1QAA7218ABB, R1QDA7236ABB, R1QDA7218ABB
R10DS0169EJ0203 Rev. 2.03 Page 33 of 37
Feb 01, 2019
Boundary Scan Order
Bit #
Ball ID
Signal names
Bit #
Ball ID
Signal names
x18
x36
x18
x36
1
6R
NC / ODT
NC / ODT
36
10E
D6
D6
2
6P
QVLD
QVLD
37
10D
NC
D15
3
6N
SA
SA
38
9E
NC
Q15
4
7P
SA
SA
39
10C
Q7
Q7
5
7N
SA
SA
40
11D
D7
D7
6
7R
SA
SA
41
9C
NC
D16
7
8R
SA
SA
42
9D
NC
Q16
8
8P
SA
SA
43
11B
Q8
Q8
9
9R
SA
SA
44
11C
D8
D8
10
11P
Q0
Q0
45
9B
NC
D17
11
10P
D0
D0
46
10B
NC
Q17
12
10N
NC
D9
47
11A
CQ
CQ
13
9P
NC
Q9
48
10A
SA
NC
14
10M
Q1
Q1
49
9A
SA
SA
15
11N
D1
D1
50
8B
SA
SA
16
9M
NC
D10
51
7C
SA
SA
17
9N
NC
Q10
52
6C
NC
NC
18
11L
Q2
Q2
53
8A
/R
/R
19
11M
D2
D2
54
7A
NC
/BW1
20
9L
NC
D11
55
7B
/BW0
/BW0
21
10L
NC
Q11
56
6B
K
K
22
11K
Q3
Q3
57
6A
/K
/K
23
10K
D3
D3
58
5B
NC
/BW3
24
9J
NC
D12
59
5A
/BW1
/BW2
25
9K
NC
Q12
60
4A
/W
/W
26
10J
Q4
Q4
61
5C
SA
SA
27
11J
D4
D4
62
4B
SA
SA
28
11H
ZQ
ZQ
63
3A
SA
SA
29
10G
NC
D13
64
2A
NC
NC
30
9G
NC
Q13
65
1A
/CQ
/CQ
31
11F
Q5
Q5
66
2B
Q9
Q18
32
11G
D5
D5
67
3B
D9
D18
33
9F
NC
D14
68
1C
NC
D27
34
10F
NC
Q14
69
1B
NC
Q27
35
11E
Q6
Q6
70
3D
Q10
Q19
R1QAA7236ABB, R1QAA7218ABB, R1QDA7236ABB, R1QDA7218ABB
R10DS0169EJ0203 Rev. 2.03 Page 34 of 37
Feb 01, 2019
Bit #
Ball ID
Signal names
Bit #
Ball ID
Signal names
x18
x36
x18
x36
71
3C
D10
D19
91
2L
Q15
Q24
72
1D
NC
D28
92
3L
D15
D24
73
2C
NC
Q28
93
1M
NC
D33
74
3E
Q11
Q20
94
1L
NC
Q33
75
2D
D11
D20
95
3N
Q16
Q25
76
2E
NC
D29
96
3M
D16
D25
77
1E
NC
Q29
97
1N
NC
D34
78
2F
Q12
Q21
98
2M
NC
Q34
79
3F
D12
D21
99
3P
Q17
Q26
80
1G
NC
D30
100
2N
D17
D26
81
1F
NC
Q30
101
2P
NC
D35
82
3G
Q13
Q22
102
1P
NC
Q35
83
2G
D13
D22
103
3R
SA
SA
84
1H
/DOFF
/DOFF
104
4R
SA
SA
85
1J
NC
D31
105
4P
SA
SA
86
2J
NC
Q31
106
5P
SA
SA
87
3K
Q14
Q23
107
5N
SA
SA
88
3J
D14
D23
108
5R
SA
SA
89
2K
NC
D32
109
-
Internal
Internal
90
1K
NC
Q32
Notes In boundary scan mode,
1. Clock balls (K, /K, C, /C) are referenced to each other and must be at opposite logic levels for
reliable operation.
2. CQ and /CQ data are synchronized to the respective C and /C (except EXTEST, SAMPLE-Z).
3. If C and /C tied high, CQ is generated with respect to K and /CQ is generated with respect to /K
(except EXTEST, SAMPLE-Z).
R1QAA7236ABB, R1QAA7218ABB, R1QDA7236ABB, R1QDA7218ABB
R10DS0169EJ0203 Rev. 2.03 Page 35 of 37
Feb 01, 2019
ID Register
TAP Controller State Diagram
Note 1. The value adjacent to each state transition in this figure represents the signal present at TMS at the
time of a rising edge at TCK. No matter what the original state of the controller, it will enter Test-
Logic-Reset when TMS is held high for at least five rising edges of TCK.
↓
↓
#31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Symbol
R R R 0 C M M M A W W 0 1 Q Q Q B O S 0 0 1 0 0 0 1 0 0 0 1 1 1
R R R Q
0 0 0 0
0 0 1 1
0 1 0 Q
0 1 1 0
1
C Q
0 0
1 1
M M M B
0 1 0 0
0 1 1 1
1 0 1 O
1 1 0 0
A 1
0 S
1 0
W W 1
0 0
1 0
1 1
x18
x9
(11 : 1)
II+ (QDR-II+, DDR-II+)
DDR
QDR
with ODT
without ODT
x36
36M&72M w/o ODT, 144M,288M
36M&72M w/ ODT
144M&288M w/o ODT, 36M,72M
144M&288M w/ ODT
Burst Length = 4 word burst
Density = 144Mb
Density = 288Mb
Common I/O
Separate I/O
-
Revision
number
(31 :29)
Type number
(28 : 12)
Revison 0
II (QDR-II, DDR-II)
Revison 1
Revison 2
Revison 3
Start bit (0) →┓
Vendor JEDEC code
:
:
Density = 72Mb
Density = 36Mb
Latency=1.5 (@II), Latency=2.0 (@II+)
Latency=2.5 (@II+)
Burst Length = 2 word burst
Select IR Scan
Capture IR
Shift IR
Exit1 IR
Pause IR
Exit2 IR
Update IR
0
0
1
0
1
1
0
1
0
0
1
Select DR Scan
Capture DR
Shift DR
Exit1 DR
Pause DR
Exit2 DR
Update DR
0
0
1
0
1
1
0
1
0
0
1
Run Test/Idle
01 01
Test Logic Reset
1
1
0
01 1
R1QAA7236ABB, R1QAA7218ABB, R1QDA7236ABB, R1QDA7218ABB
R10DS0169EJ0203 Rev. 2.03 Page 36 of 37
Feb 01, 2019
Package Dimensions and Marking Information
JEITA Package Code
Renesas Code
Previous Code
Mass (typ.)
P-LBGA165-13x15-1.00
PLBG0165FE-A
165FHG
0.5g
- y S
- Øx(M) S AB
Top View
Side View
Bottom View
Marking Information
1st row : Vender name (RENESAS)
2nd row: Part number
3rd row : Y : Year code
WW : Week code
XXXX : Renesas
internal use
4th row : Country name (JAPAN)
+ “H" --- Non-Halogenated
+ "PB-F" --- Pb-free parts
S
A1
A
ZE
ZD
A B C D E F G H J K L M N P R
1 2 3 4 5 6 7 8 9 10 11
[e]
[e]
Øb
Index Mark
AD
Index Mark
(Laser Mark)
B
E
R1QAA7218ABB-19I
YWWXXXX
JAPAN H PB-F
This part
number or
mark is just
one example.
Reference
Symbol Dimension in mm
Min Nom Max
D 12.9 13.0 13.1
E 14.9 15.0 15.1
A - - 1.4
A1 0.31 0.36 0.41
[e] - 1.0 -
b 0.45 0.5 0.6
x - - 0.2
y - - 0.15
ZD- 2.5 -
ZE- 1.5 -
All trademarks and registered trademarks are the property of their respective owners.
Revision History
R1QAA7236ABB, R1QAA7218ABB
R1QDA7236ABB, R1QDA7218ABB
Rev.
Date
Description
Page
Summary
1.00
-
-
Applied new document format.
2.00
’17.05.15
-
Reflected the information related change to non-halogenated package and
merger some speed bin.
2.01
’17.06.09
P.15
-
Deleted ODT on / off Timing Chart.
Fixed some typo.
2.02
’18.12.01
P.15
Fixed K Truth Table
2.03
’19.02.01
-
Deleted description other than current Renesas 72M QDR Lineup.
Fixed some typo and orthographical variants.
http://www.renesas.com
Refer to "http://www.renesas.com/" for the latest and detailed information.
Renesas Electronics Corporation
TOYOSU FORESIA, 3-2-24 Toyosu, Koto-ku, Tokyo 135-0061, Japan
Renesas Electronics America Inc.
1001 Murphy Ranch Road, Milpitas, CA 95035, U.S.A.
Tel: +1-408-432-8888, Fax: +1-408-434-5351
Renesas Electronics Canada Limited
9251 Yonge Street, Suite 8309 Richmond Hill, Ontario Canada L4C 9T3
Tel: +1-905-237-2004
Renesas Electronics Europe Limited
Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K
Tel: +44-1628-651-700
Renesas Electronics Europe GmbH
Arcadiastrasse 10, 40472 Düsseldorf, Germany
Tel: +49-211-6503-0, Fax: +49-211-6503-1327
Renesas Electronics (China) Co., Ltd.
Room 1709 Quantum Plaza, No.27 ZhichunLu, Haidian District, Beijing, 100191 P. R. China
Tel: +86-10-8235-1155, Fax: +86-10-8235-7679
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Unit 301, Tower A, Central Towers, 555 Langao Road, Putuo District, Shanghai, 200333 P. R. China
Tel: +86-21-2226-0888, Fax: +86-21-2226-0999
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Unit 1601-1611, 16/F., Tower 2, Grand Century Place, 193 Prince Edward Road West, Mongkok, Kowloon, Hong Kong
Tel: +852-2265-6688, Fax: +852 2886-9022
Renesas Electronics Taiwan Co., Ltd.
13F, No. 363, Fu Shing North Road, Taipei 10543, Taiwan
Tel: +886-2-8175-9600, Fax: +886 2-8175-9670
Renesas Electronics Singapore Pte. Ltd.
80 Bendemeer Road, Unit #06-02 Hyflux Innovation Centre, Singapore 339949
Tel: +65-6213-0200, Fax: +65-6213-0300
Renesas Electronics Malaysia Sdn.Bhd.
Unit 1207, Block B, Menara Amcorp, Amcorp Trade Centre, No. 18, Jln Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia
Tel: +60-3-7955-9390, Fax: +60-3-7955-9510
Renesas Electronics India Pvt. Ltd.
No.777C, 100 Feet Road, HAL 2nd Stage, Indiranagar, Bangalore 560 038, India
Tel: +91-80-67208700, Fax: +91-80-67208777
Renesas Electronics Korea Co., Ltd.
17F, KAMCO Yangjae Tower, 262, Gangnam-daero, Gangnam-gu, Seoul, 06265 Korea
Tel: +82-2-558-3737, Fax: +82-2-558-5338
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Colophon 7.2
(Rev.4.0-1 November 2017)
Notice
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