NCP139AFCT110T2G - APTINA IMAGING

April, 2019 − Rev. 6

1Publication Order Number:

NCP139/D

NCP139

1 A, Very Low Dropout Bias

Rail CMOS Voltage

Regulator

The NCP139 is a 1 A VLDO equipped with NMOS pass transistor

and a separate bias supply voltage (VBIAS). The device provides very

stable, accurate output voltage with low noise suitable for space

constrained, noise sensitive applications. In order to optimize

performance for battery operated portable applications, the NCP139

features low IQ consumption. The WLCSP6 1.2 mm x 0.8 mm Chip

Scale package is optimized for use in space constrained applications.

Features

•Input Voltage Range: VOUT to 5.5 V

•Bias Voltage Range: 3.0 V to 5.5 V

•Adjustable and Fixed Voltage Version Available

•Output Voltage Range: 0.4 V to 1.8 V (Fixed)

Output Voltage Range: 0.5 V to 3.0 V (Adjustable)

•±1% Accuracy over Temperature, 0.5% VOUT @ 25°C

•Ultra−Low Dropout: Typ. 50 mV at 1 A

•Very Low Bias Input Current of Typ. 35 mA

•Very Low Bias Input Current in Disable Mode: Typ. 0.5 mA

•Logic Level Enable Input for ON/OFF Control

•Output Active Discharge Option Available

•Stable with a 10 mF Ceramic Capacitor

•Available in WLCSP6 − 1.2 mm x 0.8 mm, 0.4 mm pitch Package

•These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS

Compliant

Typical Applications

•Battery−powered Equipment

•Smartphones, Tablets

•Cameras, DVRs, STB and Camcorders

Figure 1. Typical Application Schematics

BIAS

OUT

GND

10 mF

VOUT

0.9 V up to 1 Adc,

1.3 A peaks

VBIAS

≥3.0 V

VIN

VEN

4.7 mF

1 mFNCP139 − ADJ

BIAS

OUT

GND

10 mF

VOUT

0.9 V up to 1 Adc,

1.3 A peaks

VBIAS

≥3.0 V

VIN

VEN

4.7 mF

1 mFNCP139

SNS

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See detailed ordering, marking and shipping information on

page 7 of this data sheet.

ORDERING INFORMATION

MARKING

DIAGRAM

PIN CONNECTIONS

WLCSP6, 1.2x0.8

CASE 567MV

VOUT VIN

SNS/FB

GND

VBIAS

Top View

XX = Specific Device Code

M = Month Code

G= Pb−Free Package

XXMG

NCP139

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CURRENT

LIMIT

THERMAL

LIMIT

UVLO

−

VOLTAGE

REFERENCE

BIAS

GND

OUT

*Active

DISCHARGE

ENABLE

BLOCK

*Active output discharge function is present only in NCP139A option devices.

Figure 2. Simplified Schematic Block Diagram − Adjustable Version

150 W

VREF

CURRENT

LIMIT

THERMAL

LIMIT

UVLO

−

VOLTAGE

REFERENCE

BIAS

GND

OUT

*Active

DISCHARGE

ENABLE

BLOCK

*Active output discharge function is present only in NCP139A option devices.

Figure 3. Simplified Schematic Block Diagram − Fixed Version

150 W

SNS

NCP139

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PIN FUNCTION DESCRIPTION

Pin No.

WLCSP6 Pin Name Description

A1 VOUT Regulated Output Voltage pin

A2 VIN Input Voltage Supply pin

(ADJ devices)

FB Adjustable Regulator Feedback Input. Connect to output voltage resistor divider central node.

(Fix Volt devices)

SNS Output voltage Sensing Input. Connect to Output on the PCB to output the voltage

corresponding to the part version.

B2 EN Enable pin. Driving this pin high enables the regulator. Driving this pin low puts the regulator

into shutdown mode.

C1 GND Ground pin

C2 VBIAS Bias voltage supply for internal control circuits. This pin is monitored by internal Under-Voltage

Lockout Circuit.

ABSOLUTE MAXIMUM RATINGS

Rating Symbol Value Unit

Input Voltage (Note 1) VIN −0.3 to 6 V

Output Voltage VOUT −0.3 to (VIN+0.3) ≤ 6 V

Chip Enable, Bias, FB and SNS Input VEN, VBIAS, VFB, VSNS −0.3 to 6 V

Output Short Circuit Duration tSC unlimited s

Maximum Junction Temperature TJ150 °C

Storage Temperature TSTG −55 to 150 °C

ESD Capability, Human Body Model (Note 2) ESDHBM 2000 V

ESD Capability, Machine Model (Note 2) ESDMM 200 V

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be affected.

1. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.

2. This device series incorporates ESD protection (except OUT pin) and is tested by the following methods:

ESD Human Body Model tested per EIA/JESD22−A114

ESD Machine Model tested per EIA/JESD22−A115

Latchup Current Maximum Rating tested per JEDEC standard: JESD78.

THERMAL CHARACTERISTICS

Rating Symbol Value Unit

Thermal Characteristics, WLCSP6 1.2 mm x 0.8 mm

Thermal Resistance, Junction−to−Air (Note 3)

RqJA 69 °C/W

3. This junction−to−ambient thermal resistance under natural convection was derived by thermal simulations based on the JEDEC JESD51

series standards methodology. Only a single device mounted at the center of a high_K (2s2p) 80 mm x 80 mm multilayer board with 1−ounce

internal planes and 2−ounce copper on top and bottom. Top copper layer has a dedicated 1.6 sqmm copper area.

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ELECTRICAL CHARACTERISTICS −40°C ≤ TJ ≤ 85°C; VBIAS = 3.0 V or (VOUT + 1.6 V), whichever is greater, VIN = VOUT(NOM) +

0.3 V, IOUT = 1 mA, VEN = 1 V, CIN = 10 mF, COUT = 10 mF, CBIAS = 1 mF, unless otherwise noted. Typical values are at TJ = +25°C.

Min/Max values are for −40°C ≤ TJ ≤ 85°C unless otherwise noted. (Notes 4, 5)

Parameter Test Conditions Symbol Min Typ Max Unit

Operating Input Voltage

Range

VIN VOUT +

VDO

5.5 V

Operating Bias Voltage

Range

VBIAS (VOUT +

1.60) ≥ 3.0

5.5 V

Undervoltage Lock−out VBIAS Rising

Hysteresis

UVLO 1.6

0.2

Reference Voltage

(Adj devices)

NCP139Axxxx05ADJT2G, TJ = +25°CVREF 0.500 V

NCP139Axxxx06ADJT2G, TJ = +25°C 0.600

Output Voltage Accuracy VOUT ±0.5 %

Output Voltage Accuracy −40°C ≤ TJ ≤ 85°C, VOUT(NOM) + 0.3 V ≤ VIN ≤

VOUT(NOM) + 1.0 V, 3.0 V or (VOUT(NOM) +

1.6 V), whichever is greater < VBIAS < 5.5 V,

1 mA < IOUT < 1.0 A

VOUT −1.0 +1.0 %

VIN Line Regulation VOUT(NOM) + 0.3 V ≤ VIN ≤ 5.0 V LineReg 0.01 %/V

VBIAS Line Regulation 3.0 V or (VOUT(NOM) + 1.6 V), whichever is

greater < VBIAS < 5.5 V

LineReg 0.01 %/V

Load Regulation IOUT = 1 mA to 1.0 A LoadReg 2.0 mV

VIN Dropout Voltage IOUT = 1.0 A (Notes 6, 7) VDO 50 80 mV

VBIAS Dropout Voltage IOUT = 1.0 A, VIN = VBIAS (Notes 6, 8, 9) VDO 1.05 1.5 V

Output Current Limit VOUT = 90% VOUT(NOM) ICL 1500 2000 2600 mA

VOUT = 90% VOUT(NOM), −30°C ≤ TJ ≤ 85°C ICL 1550 2000 2600 mA

FB/SNS Pin Operating

Current

IFB, ISNS 0.1 0.5 mA

Bias Pin Quiescent

Current

VBIAS = 3.0 V, IOUT = 0 mA IBIASQ 35 50 mA

Bias Pin Disable Current VEN ≤ 0.4 V IBIAS(DIS) 0.5 1 mA

Vinput Pin Disable

Current

VEN ≤ 0.4 V IVIN(DIS) 0.5 1 mA

EN Pin Threshold Voltage EN Input Voltage “H” VEN(H) 0.9 V

EN Input Voltage “L” VEN(L) 0.4

EN Pull Down Current VEN = 5.5 V IEN 0.3 1 mA

Turn−On Time From assertion of VEN to VOUT =

98% VOUT(NOM). VOUT(NOM) = 1.0 V,

COUT = 10 mF

tON 160 ms

Power Supply Rejection

Ratio

(Adj devices)

VIN to VOUT

, f = 1 kHz, IOUT = 10 mA,

VIN ≥ VOUT +0.5 V, VOUT(NOM) = 1.0 V,

COUT = 10 mF

PSRR(VIN) 70 dB

VBIAS to VOUT

, f = 1 kHz, IOUT = 10 mA,

VIN ≥ VOUT +0.5 V, VOUT(NOM) = 1.0 V,

COUT = 10 mF

PSRR(VBIAS) 85 dB

Output Noise Voltage

(Adj devices)

VIN = VOUT +0.5 V, f = 10 Hz to 100 kHz,

VOUT(NOM) = 1.0 V, COUT = 10 mF

VN35 x

VOUT/VREF

mVRMS

4. Performance guaranteed over the indicated operating temperature range by design and/or characterization. Production tested at TA =

25°C. Low duty cycle pulse techniques are used during the testing to maintain the junction temperature as close to ambient as possible.

5. Adjustable devices tested at VOUT = VREF unless otherwise noted; external resistor tolerance is not taken into account.

6. Dropout voltage is characterized when VOUT falls 3% below VOUT(NOM).

7. For adjustable devices, VIN dropout voltage tested at VOUT(NOM) = 2 x VREF

8. For adjustable devices, VBIAS dropout voltage tested at VOUT(NOM) = 3 x VREF due to a minimum Bias operating voltage of 3.0 V.

9. For Fixed Voltages below 1.8 V, VBIAS dropout voltage does not apply due to a minimum Bias operating voltage of 3.0 V.

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ELECTRICAL CHARACTERISTICS −40°C ≤ TJ ≤ 85°C; VBIAS = 3.0 V or (VOUT + 1.6 V), whichever is greater, VIN = VOUT(NOM) +

0.3 V, IOUT = 1 mA, VEN = 1 V, CIN = 10 mF, COUT = 10 mF, CBIAS = 1 mF, unless otherwise noted. Typical values are at TJ = +25°C.

Min/Max values are for −40°C ≤ TJ ≤ 85°C unless otherwise noted. (Notes 4, 5)

Parameter UnitMaxTypMinSymbolTest Conditions

Power Supply Rejection

Ratio (Fixed Voltage

devices)

VIN to VOUT, f = 1 kHz, IOUT = 10 mA, VIN ≥

VOUT +0.5 V, VOUT(NOM) = 1.8 V, COUT = 10 mF

PSRR(VIN) 75 dB

VBIAS to VOUT, f = 1 kHz, IOUT = 10 mA, VIN ≥

VOUT +0.5 V, VOUT(NOM) = 1.8 V, VBIAS = 4.0 V,

COUT = 10 mF

PSRR(VBIAS) 85 dB

Output Noise Voltage

(Fixed Voltage devices)

VIN = VOUT +0.5 V, f = 10 Hz to 100 kHz,

VOUT(NOM) = 1.8 V, COUT = 10 mF

VN48 mVRMS

Thermal Shutdown

Threshold

Temperature increasing 160 °C

Temperature decreasing 140

Output Discharge

Pull−Down

VEN ≤ 0.4 V, VOUT = 0.5 V, NCP139A options

only

RDISCH 150 W

4. Performance guaranteed over the indicated operating temperature range by design and/or characterization. Production tested at TA =

25°C. Low duty cycle pulse techniques are used during the testing to maintain the junction temperature as close to ambient as possible.

5. Adjustable devices tested at VOUT = VREF unless otherwise noted; external resistor tolerance is not taken into account.

6. Dropout voltage is characterized when VOUT falls 3% below VOUT(NOM).

7. For adjustable devices, VIN dropout voltage tested at VOUT(NOM) = 2 x VREF

8. For adjustable devices, VBIAS dropout voltage tested at VOUT(NOM) = 3 x VREF due to a minimum Bias operating voltage of 3.0 V.

9. For Fixed Voltages below 1.8 V, VBIAS dropout voltage does not apply due to a minimum Bias operating voltage of 3.0 V.

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

NCP139

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APPLICATIONS INFORMATION

EN FB

GND

Processor

I/O

BIAS

OUT

GND

NCP139

LOAD

VBAT

1.5 V

1.0 V

To other circuits

I/O

Figure 4. Typical Application: Low−Voltage DC/DC Post−Regulator with ON/OFF Functionality

Switch−mode DC/DC

VOUT = 1.5 V

The NCP139 dual−rail very low dropout voltage regulator

is using NMOS pass transistor for output voltage regulation

from VIN voltage. All the low current internal control

circuitry is powered from the VBIAS voltage.

The use of an NMOS pass transistor offers several

advantages in applications. Unlike PMOS topology devices,

the output capacitor has reduced impact on loop stability.

Vin to Vout operating voltage difference can be very low

compared with standard PMOS regulators in very low Vin

applications.

The NCP139 offers smooth monotonic start-up. The

controlled voltage rising limits the inrush current.

The Enable (EN) input is equipped with internal

hysteresis. NCP139 Voltage linear regulator Fixed and

Adjustable version is available.

Output Voltage Adjust

The required output voltage of Adjustable devices can be

adjusted from VREF to 3.0 V using two external resistors.

Typical application schematics is shown in Figure 5.

BIAS

OUT

GND

CBIAS

μF

CIN

NCP139  ADJ

VBIAS

VIN

VEN

VOUT

Figure 5. Typical Application Schematics

VOUT +VREF ǒ1)R1ńR2Ǔ

It is recommended to keep the total serial resistance of

resistors (R1 + R2) no greater than 100 kW.

Dropout Voltage

Because of two power supply inputs VIN and VBIAS and

one VOUT regulator output, there are two Dropout voltages

specified.

The first, the VIN Dropout voltage is the voltage

difference (VIN – VOUT) when VOUT starts to decrease by

percent specified in the Electrical Characteristics table.

VBIAS is high enough; specific value is published in the

Electrical Characteristics table.

The second, VBIAS dropout voltage is the voltage

difference (VBIAS – VOUT) when VIN and VBIAS pins are

joined together and VOUT starts to decrease.

Input and Output Capacitors

The device is designed to be stable for ceramic output

capacitors with Effective capacitance in the range from

10 mF to 22 mF. The device is also stable with multiple

capacitors in parallel, having the total effective capacitance

in the specified range.

In applications where no low input supplies impedance

available (PCB inductance in VIN and/or VBIAS inputs as

example), the recommended CIN = 1 mF and CBIAS = 0.1 mF

or greater. Ceramic capacitors are recommended. For the

best performance all the capacitors should be connected to

the NCP139 respective pins directly in the device PCB

copper layer, not through vias having not negligible

impedance.

When using small ceramic capacitor, their capacitance is

not constant but varies with applied DC biasing voltage,

temperature and tolerance. The effective capacitance can be

much lower than their nominal capacitance value, most

importantly in negative temperatures and higher LDO

output voltages. That is why the recommended Output

capacitor capacitance value is specified as Effective value in

the specific application conditions.

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Enable Operation

The enable pin will turn the regulator on or off. The

threshold limits are covered in the electrical characteristics

table in this data sheet. If the enable function is not to be used

then the pin should be connected to VIN or VBIAS.

Current Limitation

The internal Current Limitation circuitry allows the

device to supply the full 1 A nominal current and short time

current peaks up to 1.3 A but protects the device against

Current Overload or Short.

Thermal Protection

Internal thermal shutdown (TSD) circuitry is provided to

protect the integrated circuit in the event that the maximum

junction temperature is exceeded. When TSD activated , the

regulator output turns off. When cooling down under the low

temperature threshold, device output is activated again. This

TSD feature is provided to prevent failures from accidental

overheating.

Activation of the thermal protection circuit indicates

excessive power dissipation or inadequate heatsinking. For

reliable operation, junction temperature should be limited to

+85°C maximum.

ORDERING INFORMATION

Device

Nominal

Output

Voltage

Reference

Voltage Marking Option Package Shipping†

NCP139AFCT05ADJT2G ADJ 0.5 V AY Output Active Discharge

WLCSP6

(Pb−Free) 5000 / Tape & Reel

NCP139AFCTC05ADJT2G ADJ 0.5 V AY Output Active Discharge,

Back Side Coating

NCP139AFCT06ADJT2G ADJ 0.6 V A6 Output Active Discharge

NCP139AFCTC06ADJT2G ADJ 0.6 V A6 Output Active Discharge,

Back Side Coating

NCP139AFCT100T2G 1.00 V −AK Output Active Discharge

NCP139AFCT105T2G 1.05 V −AC Output Active Discharge

NCP139AFCT110T2G 1.10 V −AJ Output Active Discharge

NCP139AFCTC110T2G 1.10 V −AJ Output Active Discharge,

Back Side Coating

NCP139AFCT120T2G 1.20 V −AL Output Active Discharge

NCP139AFCT180T2G 1.80 V −AZ Output Active Discharge

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Spe-

cifications Brochure, BRD8011/D.

To order other package and voltage variants, please contact your ON Semiconductor sales representative

WLCSP6, 1.20x0.80

CASE 567MV

ISSUE B DATE 05 JUN 201

SEATING

PLANE

0.05 C

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. COPLANARITY APPLIES TO SPHERICAL

CROWNS OF SOLDER BALLS.

2X DIM

AMIN MAX

−−−

MILLIMETERS

D1.20 BSC

b0.24 0.30

e0.40 BSC

0.33

PIN A1

REFERENCE

A0.05 BC

0.03 C

0.05 C

6X b

0.05 C A

0.04 0.08

0.80 BSC

SCALE 4:1

PITCH

0.20

DIMENSIONS: MILLIMETERS

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

0.40

0.05 C

2X TOP VIEW

SIDE VIEW

BOTTOM VIEW

NOTE 3

A2 0.23 REF

RECOMMENDED

A1 PACKAGE

OUTLINE

PITCH

XX = Specific Device Code

M = Month Code

*This information is generic. Please refer to

device data sheet for actual part marking.

Pb−Free indicator, “G” or microdot “ G”,

may or may not be present.

GENERIC

MARKING DIAGRAM*

XXM

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

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DOCUMENT NUMBER:

DESCRIPTION:

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