FUNCTIONAL BLOCK DIAGRAM
REV. D
a
14-Bit 128 kSPS
Complete Sampling ADC
AD679
FEATURES
AC and DC Characterized and Specified
(K, B, T Grades)
128k Conversions per Second
1 MHz Full Power Bandwidth
500 kHz Full Linear Bandwidth
78 dB S/N+D (K, B, T Grades)
Twos Complement Data Format (Bipolar Mode)
Straight Binary Data Format (Unipolar Mode)
10 M Input Impedance
8-Bit Bus Interface
On-Board Reference and Clock
10 V Unipolar or Bipolar Input Range
Pin Compatible with AD678 12-Bit, 200 kSPS ADC
MIL-STD-883 Compliant Versions Available
PRODUCT HIGHLIGHTS
1. COMPLETE INTEGRATION: The AD679 minimizes
external component requirements by combining a high
speed sample-and-hold amplifier (SHA), ADC, 5 V refer-
ence, clock, and digital interface on a single chip. This
provides a fully specified sampling A/D function unattain-
able with discrete designs.
2. SPECIFICATIONS: The AD679K, B, and T grades provide
fully specified and tested ac and dc parameters. The AD679J,
A, and S grades are specified and tested for ac parameters; dc
accuracy specifications are shown as typicals. DC specifica-
tions (such as INL, gain, and offset) are important in control
and measurement applications. AC specifications (such as
S/N+D ratio, THD, and IMD) are of value in signal process-
ing applications.
3. EASE OF USE: The pinout is designed for easy board layout,
and the two-read output provides compatibility with 8-bit
buses. Factory trimming eliminates the need for calibration
modes or external trimming to achieve rated performance.
4. RELIABILITY: The AD679 utilizes Analog Devices’ mono-
lithic BiMOS technology. This ensures long-term reliability
compared to multichip and hybrid designs.
5. UPGRADE PATH: The AD679 provides the same pinout as
the 12-bit, 200 kSPS AD678 ADC.
6. The AD679 is available in versions compliant with MIL-
STD-883. Refer to the Analog Devices Military Products
Databook or current AD679/883B data sheet for detailed
specifications.
GENERAL DESCRIPTION
The AD679 is a complete, multipurpose 14-bit monolithic
analog-to-digital converter, consisting of a sample-and-hold am-
plifier (SHA), a microprocessor-compatible bus interface, a volt-
age reference, and clock generation circuitry.
The AD679 is specified for ac (or dynamic) parameters such as
S/N+D ratio, THD, and IMD, which are important in signal
processing applications. In addition, the AD679K, B, and T
grades are fully specified for dc parameters that are important in
measurement applications.
The 14 data bits are accessed in two read operations (8 + 6),
with left justification. Data format is straight binary for unipolar
mode and twos complement binary for bipolar mode. The input
has a full-scale range of 10 V with a full power bandwidth of
1 MHz and a full linear bandwidth of 500 kHz. High input
impedance (10 MΩ) allows direct connection to unbuffered
sources without signal degradation. Conversions can be initiated
either under microprocessor control or by an external clock
asynchronous to the system clock.
This product is fabricated on Analog Devices’ BiMOS process,
combining low power CMOS logic with high precision, low
noise bipolar circuits; laser-trimmed thin-film resistors provide
high accuracy. The converter utilizes a recursive subranging
algorithm that includes error correction and flash converter
circuitry to achieve high speed and resolution.
The AD679 operates from +5 V and ±12 V supplies and dissipates
560 mW (typ). The part is available in 28-lead plastic DIP,
ceramic DIP, and 44 J-leaded ceramic surface-mount packages.
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 www.analog.com
Fax: 781/326-8703 © 2004 Analog Devices, Inc. All rights reserved.
AD679–SPECIFICATIONS
AC SPECIFICATIONS
AD679J/A/S AD679K/B/T
Parameter Min Typ Max Min Typ Max Unit
SIGNAL-TO-NOISE AND DISTORTION (S/N+D) RATIO
2
–0.5 dB Input (Referred to –0 dB Input) 76 79 78 81 dB
–20 dB Input (Referred to –20 dB Input) 58 59 60 61 dB
–60 dB Input (Referred to –60 dB Input) 18 19 20 21 dB
TOTAL HARMONIC DISTORTION (THD)
3
@ 25°C–90 –82 –90 –82 dB
0.003 0.006 0.003 0.006 %
T
MIN
to T
MAX
–88 –82 –88 –82 dB
0.004 0.008 0.004 0.008 %
PEAK SPURIOUS OR PEAK HARMONIC COMPONENT –90 –82 –90 –82 dB
FULL POWER BANDWIDTH 1 1 MHz
FULL LINEAR BANDWIDTH 500 500 kHz
INTERMODULATION DISTORTION (IMD)
4
2nd Order Products –90 –82 –90 –82 dB
3rd Order Products –90 –82 –90 –82 dB
NOTES
1
f
lN
amplitude = –0.5 dB (9.44 V p-p) bipolar mode full scale unless otherwise indicated. All measurements referred to a –0 dB (9.997 V p-p) input signal
unless otherwise noted.
2
See TPC 3 for higher frequencies and other input amplitudes.
3
See TPCs 1 and 2 for higher frequencies and other input amplitudes.
4
f
A
= 9.08 kHz, f
B
= 9.58 kHz, with f
SAMPLE
100 kSPS. See Definition of Specifications section.
Specifications subject to change without notice.
DIGITAL SPECIFICATIONS
Parameter Test Conditions Min Max Unit
LOGIC INPUTS
V
IH
High Level Input Voltage 2.0 V
DD
V
V
IL
Low Level Input Voltage 0 0.8 V
I
IH
High Level Input Current V
IN
= 5 V –10 +10 µA
I
IL
Low Level Input Current V
IN
= 0 V –10 +10 µA
C
IN
Input Capacitance 10 pF
LOGIC OUTPUTS
V
OH
High Level Output Voltage I
OH
= 0.1 mA 4.0 V
I
OH
= 0.5 mA 2.4 V
V
OL
Low Level Output Voltage I
OL
= 1.6 mA 0.4 V
I
OZ
High Z Leakage Current V
IN
= 0 or 5 V –10 +10 µA
C
OZ
High Z Output Capacitance 10 pF
NOTES
1
f
lN
amplitude = –0.5 dB (9.44 V p-p) bipolar mode full scale unless otherwise indicated. All measurements referred to a –0 dB (9.997 V p-p) input signal
unless otherwise noted.
2
See TPC 3 for higher frequencies and other input amplitudes.
3
See TPCs 1 and 2 for higher frequencies and other input amplitudes.
4
f
A
= 9.08 kHz, f
B
= 9.58 kHz, with f
SAMPLE
100 kSPS. See Definition of Specifications section.
Specifications subject to change without notice.
REV. D
–2–
(All device types TMIN to TMAX, VCC = +12 V 5%, VEE = –12 V 5%, VDD = +5 V 10%)
(TMIN to TMAX, VCC = +12 V 5%, VEE = –12 V 5%, VDD = +5 V 10%, fSAMPLE = 128 kSPS, fIN = 10.009 kHz,
unless otherwise noted)1
(TMIN to TMAX, VCC = +12 V 5%, VEE = –12 V 5%, VDD = +5 V 10%, unless otherwise noted)
AD679
REV. D –3–
DC SPECIFICATIONS
AD679J/A/S AD679K/B/T
Parameter Min Typ Max Min Typ Max Unit
TEMPERATURE RANGE
J, K Grades 0 70 0 70 °C
A, B Grades –40 +85 –40 +85 °C
S, T Grades –55 +125 –55 +125 °C
ACCURACY
Resolution 14 14 Bits
Integral Nonlinearity (INL) 212.5 LSB
Differential Nonlinearity (DNL) 14 14 Bits
Unipolar Zero Error
1
(@ 25°C) 0.08 0.05 0.07 % FSR
2
Bipolar Zero Error
1
(@ 25°C) 0.08 0.05 0.07 % FSR
Gain Error
1, 3
(@ 25°C) 0.12 0.09 0.11 % FSR
Temperature Drift
Unipolar Zero
4
J, K Grades 0.04 0.04 0.05 % FSR
A, B Grades 0.05 0.05 0.07 % FSR
S, T Grades 0.09 0.09 0.10 % FSR
Bipolar Zero
4
J, K Grades 0.02 0.02 0.04 % FSR
A, B Grades 0.04 0.04 0.05 % FSR
S, T Grades 0.08 0.08 0.09 % FSR
Gain
4
J, K Grades 0.09 0.09 0.11 % FSR
A, B Grades 0.10 0.10 0.16 % FSR
S, T Grades 0.20 0.20 0.25 % FSR
Gain
5
J, K Grades 0.04 0.04 0.05 % FSR
A, B Grades 0.05 0.05 0.07 % FSR
S, T Grades 0.09 0.09 0.10 % FSR
ANALOG INPUT
Input Ranges
Unipolar Mode 0+10 0 +10 V
Bipolar Mode –5 +5 –5 +5 V
Input Resistance 10 10 MΩ
Input Capacitance 10 10 pF
Input Settling Time 1.5 1.5 µs
Aperture Delay 10 10 ns
Aperture Jitter 150 150 ps
INTERNAL VOLTAGE REFERENCE
Output Voltage
6
4.98 5.02 4.98 5.02 V
External Load
Unipolar Mode 1.5 1.5 mA
Bipolar Mode 0.5 0.5 mA
POWER SUPPLIES
Power Supply Rejection
V
CC
= +12 V ± 5% 66LSB
V
EE
= –12 V ± 5% 66LSB
V
DD
= +5 V ± 10% 66LSB
Operating Current
I
CC
18 20 18 20 mA
I
EE
25 34 25 34 mA
I
DD
812 812 mA
Power Consumption 560 745 560 745 m
W
NOTES
1
Adjustable to zero. See Figures 5 and 6.
2
% FSR = percent of full-scale range.
3
Includes internal voltage reference error.
4
Includes internal voltage reference drift.
5
Excludes internal voltage reference drift.
6
With maximum external load applied.
Specifications shown in boldface are tested on all devices at final electrical test with worst case supply voltages at T
MIN
, 25°C and T
MAX
. Results from those tests are used to
calculate outgoing quality levels. All min and max specifications are guaranteed, although only those shown in boldface are tested.
Specifications subject to change without notice.
AD679
REV. D
–4–
Parameter Symbol Min Max Unit
SC Delay t
SC
50 ns
Conversion Time t
C
6.3 µs
Conversion Rate
1
t
CR
7.8 µs
Convert Pulse Width t
CP
0.097 3.0 µs
Aperture Delay t
AD
520ns
Status Delay t
SD
0400 ns
Access Time
2, 3
t
BA
10 100 ns
10 57
4
ns
Float Delay
5
t
FD
10 80 ns
Output Delay t
OD
0ns
Format Setup t
FS
100 ns
OE Delay t
OE
20 ns
Read Pulse Width t
RP
195 ns
Conversion Delay t
CD
400 ns
EOCEN Delay t
EO
50 ns
NOTES
1
Includes acquisition time.
2
Measured from the falling edge of OE/EOCEN (0.8 V) to the time at which the
data lines/EOC cross 2.0 V or 0.8 V. See Figure 4.
3
C
OUT
= 100 pF.
4
C
OUT
= 50 pF.
5
Measured from the rising edge of OE/EOCEN (2.0 V) to the time at which the output voltage changes by 0.5. See Figure 4; C
OUT
= 10 pF.
Specifications subject to change without notice.
(All device types TMIN to TMAX, VCC = +12 V 5%, VEE = –12 V
5%, VDD = +5 V 10%)
NOTES
1IN ASYNCHRONOUS MODE, STATE OF CS DOES NOT AFFECT OPERATION.
SEE THE START CONVERSION TRUTH TABLE FOR DETAILS.
2EOCEN = LOW (SEE FIGURE 3). IN SYNCHRONOUS MODE, EOC IS A THREE-
STATE OUTPUT. IN ASYNCHRONOUS MODE, EOC IS AN OPEN DRAIN OUTPUT.
3DATA SHOULD NOT BE ENABLED DURING A CONVERSION.
Figure 1. Conversion Timing
Figure 2. Output Timing
NOTE
1EOC IS A THREE-STATE OUTPUT IN SYNCHRONOUS MODE
AND AN OPEN DRAIN OUTPUT IN ASYNCHRONOUS. ACCESS (tBA)
AND FLOAT (tFD) TIMING SPECIFICATIONS DO NOT APPLY IN
ASYNCHRONOUS MODE WHERE THEY ARE A FUNCTION OF THE
TIME CONSTANT FORMED BY THE 10pF OUTPUT CAPACITANCE
AND THE PULL-UP RESISTOR.
Figure 3. EOC Timing
TEST VCP C
OUT
ACCESS TIME HIGH Z TO LOGIC LOW 5V 100pF
FLOAT TIME LOGIC HIGH TO HIGH Z 0V 10pF
ACCESS TIME HIGH Z TO LOGIC HIGH 0V 100pF
FLOAT TIME LOGIC LOW TO HIGH Z 5V 10pF
IOL
IOH
DOUT VCP
COUT
Figure 4. Load Circuit for Bus Timing Specifications
TIMING SPECIFICATIONS
AD679
REV. D –5–
ABSOLUTE MAXIMUM RATINGS
1
With
Respect
Specification To Min Max Unit
V
CC
AGND –0.3 +18 V
V
EE
AGND –18 +0.3 V
V
CC2
V
EE
–0.3 +26.4 V
V
DD
DGND 0 +7 V
AGND DGND –1 +1 V
AIN, REF
IN
AGND V
EE
V
CC
V
Digital Inputs DGND –0.5 +7 V
Digital Outputs DGND –0.5 V
DD
+ 0.3 V
Max Junction
Temperature 175 °C
With
Respect
Specification To Min Max Unit
Operating
Temperature
J and K Grades 0 70 °C
A and B Grades –40 +85 °C
S and T Grades –55 +125 °C
Storage Temperature –65 +150 °C
Lead Temperature
(10 sec max) 300 °C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2
The AD679 is not designed to operate from ⫾15 V supplies.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD679 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
ORDERING GUIDE
1
Temperature Tested and Package
Model Package Range Specified Option
2
AD679JN 28-Pin Plastic DIP 0°C to +70°CAC N-28
AD679KN 28-Pin Plastic DIP 0°C to +70°CAC + DC N-28
AD679JD 28-Pin Ceramic DIP 0°C to +70°CAC D-28
AD679KD 28-Pin Ceramic DIP 0°C to +70°CAC + DC D-28
AD679AD 28-Pin Ceramic DIP –40°C to +85°CAC D-28
AD679BD 28-Pin Ceramic DIP –40°C to +85°CAC + DC D-28
AD679SD 28-Pin Ceramic DIP –55°C to +125°CAC D-28
AD679TD 28-Pin Ceramic DIP –55°C to +125°CAC + DC D-28
AD679AJ 44-Lead Ceramic JLCC –40°C to +85°CAC J-44
AD679BJ 44-Lead Ceramic JLCC –40°C to +85°CAC + DC J-44
AD679SD/883B
3
NOTES
1
For parallel read (14-bits) interface to 16-bit buses, see AD779.
2
N = Plastic DIP; D = Ceramic DIP; J = J-Leaded Ceramic Chip Carrier.
3
For details, grade, and package offerings screened in accordance with MIL-STD-883, refer to the
Analog Devices Military Products Databook or the current AD679/883B data sheet.
AD679
REV. D
–6–
PIN FUNCTION DESCRIPTIONS
28-Lead 44-Lead
DIP JLCC
Mnemonic Pin No. Pin No. Type Name and Function
AGND 7 11 P Analog Ground. This is the ground return for AIN only.
AIN 6 10 AI Analog Signal Input.
BIPOFF 10 15 AI Bipolar Offset. Connect to AGND for +10 V input unipolar mode and straight
binary output coding. Connect to REF
OUT
for ⫾5 V input bipolar mode and
twos complement binary output coding.
CS 46 DI Chip Select. Active LOW.
DGND 12, 14 23 P Digital Ground.
DB7–DB0 26–19 40, 39, 37, 36, DO Data Bits. These pins provide all 14 bits in two bytes (8 + 6 bits). Active HIGH.
35, 34, 33, 31
EOC 27 42 DO End-of-Convert. EOC goes LOW when a conversion starts and goes HIGH
when the conversion finishes. In asynchronous mode, EOC is an open-drain
output and requires an external 3 kΩ pull-up resistor. See EOCEN and SYNC
pins for information on EOC gating.
EOCEN 11 DI End-of-Convert Enable. Enables EOC pin. Active LOW.
HBE 15 25 DI High Byte Enable. If LOW, output contains high byte. If HIGH, output
contains low byte (corresponding to the most recently read high byte).
OE 23 DI Output Enable. A down-going transition on OE enables DB7 to DB0. Gated
with CS. Active LOW.
REF
IN
914AIReference Input. 5 V input gives 10 V full-scale range.
REF
OUT
812AO5 V Reference Output. Tied to REF
IN
for normal operation.
SC 35 DI Start Convert. Active LOW. See SYNC pin for gating.
SYNC 13 21 DI SYNC Control. If tied to V
DD
(synchronous mode), SC and EOCEN are gated
by CS. If tied to DGND (asynchronous mode), SC and EOCEN are indepen-
dent of CS, and EOC is an open-drain output. EOC requires an external 3 kΩ
pull-up resistor in asynchronous mode.
V
CC
11 17 P 12 V Analog Power.
V
EE
58 P–12 V Analog Power.
V
DD
28 43 P 5 V Digital Power.
—16UTie to DGND.
—17–18 2, 4, 7, 9, 13, U These pins are unused and should be connected to DGND or V
DD
.
16, 18, 19, 20,
22, 24, 26, 27,
28, 29, 30, 32,
38, 41, 44
Type: AI = Analog Input. AO = Analog Output. DI = Digital Input (TTL and 5 V CMOS compatible). DO = Digital Output (TTL and 5 V CMOS compatible).
All DO pins are three-state drivers. P = Power. U = Unused.
DIP Package
TOP VIEW
(Not to Scale)
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
AD679
DGND
SYNC
DGND
VCC
BIPOFF
REFIN
REFOUT
EOCEN
OE
SC
CS
AGND
AIN
VEE
HBE
DGND
DGND
DGND
DB0
DB1
DB2
VDD
EOC
DB7
DB6
DB3
DB4
DB5
PIN CONFIGURATIONS
JLCC Package
NC
AGND
REFOUT
NC
REFIN
BIPOFF
NC
VEE
AIN
NC
VCC
18 19 20 21 22 23 24 25 26 27 28
77
11
10
9
8
12
16
15
14
13
17
39
35
36
37
38
34
30
31
32
33
29
DB6
NC
DB5
DB4
DB3
DB2
DB1
NC
DB0
NC
NC
PIN 1
IDENTIFIER
TOP VIEW
(Not to Scale)
AD679
CS
SC
NC
OE
NC
EOCE
N
VDD
EOC
NC
DB7
NC
NC
NC
NC
SYNC
NC
DGND
HBE
NC
NC
NC
NC
6543214443 42 41 40
NC = NO CONNECT
AD679
REV. D –7–
DEFINITIONS OF SPECIFICATIONS
Nyquist Frequency
An implication of the Nyquist sampling theorem, the Nyquist
frequency of a converter is the input frequency that is one-half
the sampling frequency of the converter.
Signal-to-Noise and Distortion (S/N+D) Ratio
S/N+D is the ratio of the rms value of the measured input signal
to the rms sum of all other spectral components below the
Nyquist frequency, including harmonics but excluding dc.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first six harmonic compo-
nents to the rms value of a full-scale input signal and is expressed
as a percentage or in decibels. For input signals or harmonics
above the Nyquist frequency, the aliased component is used.
Peak Spurious or Peak Harmonic Component
The peak spurious or peak harmonic component is the largest
spectral component excluding the input signal and dc. This
value is expressed in decibels relative to the rms value of a full-
scale input signal.
Intermodulation Distortion (IMD)
With inputs consisting of sine waves at two frequencies, fa and
fb, any device with nonlinearities will create distortion products,
of order (m + n) at sum and difference frequencies of mfa ⫾
nfb, where m, n = 0, 1, 2, 3.... Intermodulation terms are those
for which m or n is not equal to zero. For example, the second
order terms are (fa + fb) and (fa – fb) and the third order terms
are (2 fa + fb), (2 fa – fb), (fa + 2 fb) and (fa – 2 fb). The IMD
products are expressed as the decibel ratio of the rms sum of
the measured input signals to the rms sum of the distortion
terms. The two signals applied to the converter are of equal
amplitude, and the peak value of their sum is –0.5 dB from full-
scale (9.44 V p-p). The IMD products are normalized to a 0 dB
input signal.
Bandwidth
The full-power bandwidth is the input frequency at which the
amplitude of the reconstructed fundamental is reduced by 3 dB
for a full-scale input.
The full-linear bandwidth is the input frequency at which the
slew rate limit of the sample-and-hold amplifier (SHA) is
reached. At this point, the amplitude of the reconstructed fun-
damental has degraded by less than –0.1 dB. Beyond this fre-
quency, distortion of the sampled input signal increases
significantly.
The AD679 has been designed to optimize input bandwidth,
allowing it to undersample input signals with frequencies signifi-
cantly above the converter’s Nyquist frequency.
Aperture Delay
Aperture delay is a measure of the SHA’s performance and is
measured from the falling edge of start convert (SC) to when
the input signal is held for conversion. In synchronous mode,
chip select (CS) should be LOW before SC to minimize aper-
ture delay.
Aperture Jitter
Aperture jitter is the variation in aperture delay for successive
samples and is manifested as noise on the input to the A/D.
Input Setting Time
Settling time is a function of the SHA’s ability to track fast slew-
ing signals. This is specified as the maximum time required in
track mode after a full-scale step input to guarantee rated con-
version accuracy.
Differential Nonlinearity (DNL)
In an ideal ADC, code transitions are 1 LSB apart. Differential
linearity is the deviation from this ideal value. It is often speci-
fied in terms of resolution for which no missing codes (NMC)
are guaranteed.
Integral Nonlinearity (INL)
The ideal transfer function for a linear ADC is a straight line
drawn between zero and full scale. The point used as zero occcurs
1/2 LSB before the first code transition. Full scale is defined as
a level 1 1/2 LSB beyond the last code transition. Integral linear-
ity error is the worst case deviation of a code from the straight
line. The deviation of each code is measured from the middle of
that code.
Note that the linearity error is not user adjustable.
Power Supply Rejection
Variations in power supply will affect the full-scale transition,
but not the converter’s linearity. Power Supply Rejection is the
maximum change in the full-scale transition point due to a
change in power supply voltage from the nominal value.
Temperature Drift
This is the maximum change in the parameter from the initial
value (@ 25°C) to the value at T
MIN
or T
MAX
.
Unipolar Zero Error
In unipolar mode, the first transition should occur at a level
1/2 LSB above analog ground. Unipolar zero error is the devia-
tion of the actual transition from that point. This error can be
adjusted as discussed in the Input Connections and Calibration
section.
Bipolar Zero Error
In the bipolar mode, the major carry transition (11 1111 1111
1111 to 00 0000 0000 0000 ) should occur at an analog value
1/2 LSB below analog ground. Bipolar zero error is the devia-
tion of the actual transition from that point. This error can be
adjusted as discussed in the Input Connections and Calibration
section.
Gain Error
The last transition should occur at an analog value 1 1/2 LSB
below the nominal full scale (9.9991 V for a 0 V to 10 V range,
4.9991 V for a ⫾5 V range). The gain error is the deviation of
the actual level at the last transition from the ideal level with the
zero error trimmed out. This error can be adjusted as shown in
the Input Connections and Calibration section.
AD679
REV. D
–8–
INPUT FREQUENCY (Hz)
AMPLITUDE (dB)
TPC 1. Harmonic Distortion vs. Input Frequency
(–0.5 dB Input)
INPUT FREQUENCY (Hz)
THD (dB)
TPC 2. Total Harmonic Distortion vs. Input
Frequency and Amplitude
INPUT FREQUENCY (Hz)
S/(N+D) (dB)
TPC 3. S/(N+D) vs. Input Frequency and Amplitude
–Typical Performance Characteristics
FREQUENCY (kHz)
AMPLITUDE (dB)
TPC 4. 5-Plot Averaged 2048 Point FFT at 128 kSPS,
f
IN
= 10.009 kHz
FREQUENCY (kHz)
AMPLITUDE (dB)
TPC 5. Nonaveraged IMD Plot for f
IN
= 9.08 kHz (f
a
),
9.58 kHz (f
b
) at 128 kSPS
RIPPLE FREQUENCY (kHz)
S/(N+D) (dB)
TPC 6. Power Supply Rejection (f
IN
= 10 kHz, f
SAMPLE
=
128 kSPS, V
RIPPLE
= 0.1 V p-p)
AD679
REV. D –9–
CONVERSION CONTROL
In synchronous mode (SYNC = HIGH), both chip select (CS)
and start convert (SC) must be brought LOW to start a conver-
sion. CS should be LOW t
SC
before SC is brought LOW. In
asynchronous mode (SYNC = LOW), a conversion is started by
bringing SC low, regardless of the state of CS.
Before a conversion is started, end-of-convert (EOC) is HIGH
and the sample-and-hold is in track mode. After a conversion is
started, the sample-and-hold goes into hold mode and EOC
goes LOW, signifying that a conversion is in progress. During
the conversion, the sample-and-hold will go back into track
mode and start acquiring the next sample.
In track mode, the sample-and-hold will settle to ⫾0.003%
(14 bits) in 1.5 µs maximum. The acquisition time does not
affect the throughput rate as the AD679 goes back into track
mode more than 2 µs before the next conversion. In multichan-
nel systems, the input channel can be switched as soon as EOC
goes LOW.
Bringing OE LOW t
OE
after CS goes LOW makes the output
register contents available on the output data bits (DB7–DB0).
A period of time, t
CD
, is required after OE is brought HIGH
before the next SC instruction is issued.
If SC is held LOW, conversion accuracy may deteriorate. For
this reason, SC should not be held low in an attempt to operate
in a continuously converting mode.
Table I. Start Conversion Truth Table
Inputs
SYNC CS SC Status
Synchronous 1 1 X No Conversion
Mode 1 0 fStart Conversion
1f0Start Conversion
(Not Recommended)
100Continuous Conversion
(Not Recommended)
Asynchronous 0 X 1 No Conversion
Mode 0 X fStart Conversion
0X0Continuous Conversion
(Not Recommended)
1= HIGH voltage level.
0= LOW voltage level.
X= Don’t care.
f= HIGH to LOW transition. Must stay low for t = t
CP
.
Table II. 14-Bit Mode Coding Format (1 LSB = 0.61 mV)
Unipolar Coding Bipolar Coding
(Straight Binary) (Twos Complement)
V
IN
*Output Code V
IN
* (V) Output Code
0.00000 V 000 . . . 0 –5.00000 100 . . . 0
5.00000 V 100 . . . 0 –0.00061 111 . . . 1
9.99939 V 111 . . . 1 0.00000 000 . . . 0
+2.50000 010 . . . 0
+4.99939 011 . . . 1
*Code center.
END-OF-CONVERT
In asynchronous mode, end-of-convert (EOC) is an open-drain
output (requiring a minimum 3 kΩ pull-up resistor) enabled by
end-of-convert enable (EOCEN). In synchronous mode, EOC
is a three-state output that is enabled by EOCEN and CS. See
Table III. Access (t
BA
) and float (t
FD
) timing specifications do
not apply in asynchronous mode where they are a function of
the time constant formed by the external load capacitance and
the pull-up resistor.
OUTPUT ENABLE OPERATION
The data bits (DB7–DB0) are three-state outputs that are enabled
by chip select (CS) and output enable (OE). CS should be
LOW t
OE
before OE is brought LOW.
When EOC goes HIGH, the conversion is completed and the
output data may be read. The output is read in two steps as a
16-bit word, with the high byte read first, followed by the low
byte. High byte enable (HBE) controls the output sequence.
The 14-bit result is left justified within the 16-bit field.
In unipolar mode (BIPOFF tied to AGND), the output coding
is straight binary. In bipolar mode (BIPOFF tied to REF
OUT
),
output coding is twos complement binary.
POWER-UP
The AD679 typically requires 10 µs after power-up to reset
internal logic.
Table III. Conversion Status Truth Table
Inputs Output
SYNC CS EOCEN EOC Status
Synchronous 1 0 0 0 Converting
Mode 1 0 0 1 Not Converting
11 XHigh Z Either
1X 1High Z Either
Asynchronous
0X 00 Converting
Mode*0X 0High Z Not Converting
0X 1High Z Either
1 = HIGH voltage level.
0 = LOW voltage level.
X = Don’t care.
*EOC requires a pull-up resistor in asynchronous mode.
Table IV. Output Enable Truth Table
Inputs Outputs
HBE (CS U OE)DB7 . . . DB0
X1 ←High Z →
Unipolar or 0 0 a b c d e f g h
Bipolar 1 0 i j k l m n 0 0
1= HIGH voltage level. a = MSB.
0= LOW voltage level. n = LSB.
X= Don’t care.
U = Logical OR.
Data coding is binary for unipolar mode and twos complement binary for
bipolar mode.
AD679
REV. D
–10–
INPUT CONNECTIONS AND CALIBRATION
The high (10 MΩ) input impedance of the AD679 eases the
task of interfacing to high source impedances or multiplexer
channel-to-channel mismatches of up to 300 Ω. The 10 V p-p
full-scale input range accepts the majority of signal voltages
without the need for voltage divider networks that could deterio-
rate the accuracy of the ADC.
The AD679 is factory trimmed to minimize offset, gain, and
linearity errors. In unipolar mode, the only external component
that is required is a 50 Ω ⫾1% resistor. Two resistors are required
in bipolar mode. If offset and gain are not critical (as in some ac
applications), even these components can be eliminated.
In some applications, offset and gain errors need to be trimmed
out completely. The following sections describe the correct pro-
cedure for these various situations.
Bipolar Range Inputs
The connections for the bipolar mode are shown in Figure 5. In
this mode, data output coding is twos complement binary. This
circuit allows approximately ⫾25 mV of offset trim range (⫾40
LSB) and ⫾0.5% of gain trim range (⫾80 LSB).
Either or both of the trim pots can be replaced with 50 Ω ⫾1%
fixed resistors if the AD679 accuracy limits are sufficient for
application. If the pins are shorted together, the additional offset
and gain error is approximately 80 LSB.
To trim bipolar zero to its nominal value, apply a signal 1/2 LSB
below midrange (–0.305 mV for a ⫾5 V range) and adjust R1
until the major carry transition is located (11 1111 1111 1111 to
00 0000 0000 0000). To trim the gain, apply a signal 1 1/2 LSB
below full scale (+4.9991 V for a ⫾5 V range) and adjust R2 to
give the last positive transition (01 1111 1111 1110 to 01 1111
1111 1111). These trims are interactive so several iterations may
be necessary for convergence.
A single pass calibration can be done by substituting a bipolar
offset trim (error at minus full scale) for the bipolar zero trim
(error at midscale) using the same circuit. First, apply a
signal 1/2 LSB above minus full scale (–4.9997 V for a ⫾5 V
range) and adjust R1 until the minus full-scale transition is lo-
cated (10 0000 0000 0000 to 10 000 000 0001). Then perform
the gain error trim as outlined above.
Figure 5. Bipolar Input Connections with Gain and
Offset Trims
Unipolar Range Inputs
Offset and gain errors can be trimmed out by using the configu-
ration shown in Figure 6. This circuit allows approximately
⫾25 mV of offset trim range (⫾40 LSB) and ⫾0.5% of gain
trim range (⫾80 LSB).
The nominal offset is 1/2 LSB so that the analog range that cor-
responds to each code is centered in the middle of that code
(halfway between the transitions to the codes above and below
it). Thus the first transition (from 00 0000 0000 0000 to 00
0000 0000 0001) should nominally occur for an input level of
+1/2 LSB (0.305 mV above ground for a 10 V range). To trim
unipolar zero to this nominal value, apply a 0.305 mV signal to
AIN and adjust R1 until the first transition is located.
The gain trim is done by adjusting R2. If the nominal value is
required, apply a signal 1 1/2 LSB below full scale (9.9997 V for
a 10 V range) and adjust R2 until the last transition is located
(11 1111 1111 1110 to 11 1111 1111 1111).
If offset adjustment is not required, BIPOFF should be con-
nected directly to AGND. If gain adjustment is not required, R2
should be replaced with a fixed 50 Ω ⫾1% metal film resistor. If
REF
OUT
is connected directly to REF
IN
, the additional gain
error is approximately 1%.
Figure 6. Unipolar Input Connections with Gain and
Offset Trims
REFERENCE DECOUPLING
It is recommended that a 10 µF tantalum capacitor be con-
nected between REF
IN
(Pin 9) and ground. This has the effect
of improving the S/N+D ratio through filtering possible broad-
band noise contributions from the voltage reference.
BOARD LAYOUT
Designing with high resolution data converters requires careful
attention to board layout. Trace impedance is a significant issue.
A 1.22 mA current through a 0.5 Ω trace will develop a voltage
drop of 0.6 mV, which is 1 LSB at the 14-bit level for a 10 V
full-scale span. In addition to ground drops, inductive and
capacitive coupling need to be considered, especially when high
accuracy analog signals share the same board with digital signals.
Finally, power supplies need to be decoupled in order to filter
out ac noise.
Analog and digital signals should not share a common path.
Each signal should have an appropriate analog or digital return
routed close to it. Using this approach, signal loops enclose a
small area, minimizing the inductive coupling of noise. Wide PC
tracks, large gauge wire, and ground planes are highly recom-
mended to provide low impedance signal paths. Separate analog
AD679
REV. D –11–
and digital ground planes are also desirable, with a single inter-
connection point to minimize ground loops. Analog signals
should be routed as far as possible from digital signals and
should cross them at right angles.
The AD679 incorporates several features to help the user’s lay-
out. Analog pins (V
EE
, AIN, AGND, REF
OUT
, REF
IN
, BIPOFF,
V
CC
) are adjacent to help isolate analog from digital signals. In
addition, the 10 MΩ input impedance of AIN minimizes input
trace impedance errors. Finally, ground currents have been
minimized by careful circuit architecture. Current through
AGND is 200 µA, with no code dependent variation. The cur-
rent through DGND is dominated by the return current for
DB7–DB0 and EOC.
SUPPLY DECOUPLING
The AD679 power supplies should be well filtered, well regu-
lated, and free from high frequency noise. Switching power sup-
plies are not recommended due to their tendency to generate
spikes that can induce noise in the analog system.
Decoupling capacitors should be used in very close layout prox-
imity between all power supply pins and analog ground. A 10 µF
tantalum capacitor in parallel with a 0.1 µF ceramic capacitor
provides adequate decoupling.
An effort should be made to minimize the trace length between
the capacitor leads and the respective converter power supply
and common pins. The circuit layout should attempt to locate
the AD679, associated analog input circuitry, and interconnec-
tions as far as possible from logic circuitry. A solid analog
ground plane around the AD679 isolates large switching ground
currents. For these reasons, the use of wire wrap circuit con-
struction is not recommended; careful printed circuit construc-
tion is preferred.
GROUNDING
If a single AD679 is used with separate analog and digital
ground planes, connect the analog ground plane to AGND and
the digital ground plane to DGND, keeping lead lengths as
short as possible. Then connect AGND and DGND together at
the AD679. If multiple AD679s are used or if the AD679 shares
analog supplies with other components, connect the analog and
digital returns together once at the power supplies rather than at
each chip. This prevents large ground loops, which inductively
couple noise and allow digital currents to flow through the ana-
log system.
USE OF EXTERNAL VOLTAGE REFERENCE
The AD679 features an on-chip voltage reference. For improved
gain accuracy over temperature, a high performance external
voltage reference may be used in place of the on-chip reference.
The AD586 and AD588 are popular references appropriate for
use with high resolution converters. The AD586 is a low cost
reference that utilizes a buried Zener architecture to provide low
noise and drift. The AD588 is a higher performance reference
that uses a proprietary implanted buried Zener diode in con-
junction with laser-trimmed thin-film resistors for low offset and
low drift.
Figure 7 shows the use of the AD586 with the AD679 in a bipolar
input mode. Over the 0°C to 70°C range, the AD586 L-grade
exhibits less than a 2.25 mV output change from its initial value
at 25°C. REF
IN
(Pin 9) scales its input by a factor of two; thus,
this change becomes effectively 4.5 mV. When applied to the
AD679, this results in a total gain drift of 0.09% FSR, which is
an improvement over the on-chip reference performance of
0.11% FSR. A noise-reduction capacitor, C
N
, has been shown.
This capacitor reduces the broadband noise of the AD586 out-
put, thereby optimizing the overall ac and dc performance of the
AD679.
Figure 7. Bipolar Input with Gain and Offset Trims
Figure 8 shows the AD679 in unipolar input mode with the
AD588 reference. The AD588 output is accurate to 0.65 mV
from its value at 25°C over the 0°C to 70°C range. This results
in a 0.06% FSR total gain drift for the AD679, a substantial im-
provement over the on-chip reference performance of 0.11%
FSR. A noise-reduction network on Pins 4, 6, and 7 has been
shown. The 1 µF capacitors form low-pass filters with the inter-
nal resistance of the AD588 Zener and amplifier cells and exter-
nal resistance. This reduces the high frequency (to 1 MHz)
noise of the AD588, providing optimum ac and dc performance
of the AD679.
REFIN
Figure 8. Unipolar Input with Gain and Offset Trims
AD679
REV. D
–12–
INTERFACING THE AD679 TO MICROPROCESSORS
The I/O capabilities of the AD679 allow direct interfacing to
general-purpose and DSP microprocessor buses. The asynchro-
nous conversion control feature allows complete flexibility and
control with minimal external hardware.
The following examples illustrate typical AD679 interface
configurations.
AD679 to TMS320C25
In Figure 9, the AD679 is mapped into the TMS320C25 I/O
space. AD679 conversions are initiated by issuing an OUT
instruction to Port 1. EOC status and the conversion result are
read in with an IN instruction to Port 1. A single wait state is
inserted by generating the processor READY input from IS,
Port 1, and MSC. Address line A0 provides HBE decoding to
select between the high and low bytes of data. This configura-
tion supports processor clock speeds of 20 MHz and is capable
of supporting processor clock speeds of 40 MHz if a NOP instruc-
tion follows each AD679 read instruction.
Figure 9. AD679 to TMS320C25 Interface
AD679 to 80186
Figure 10 shows the AD679 interfaced to the 80186 micropro-
cessor. This interface allows the 80186’s built-in DMA control-
ler to transfer the AD679 output into a RAM based FIFO buffer
of any length, with no microprocessor intervention.
In this application the AD679 is configured in the asynchronous
mode, which allows conversions to be initiated by an external
trigger source independent of the microprocessor clock. After
each conversion, the AD679 EOC signal generates a DMA
request to Channel 1 (DRQ1). The subsequent DMA READ
sequences the high and low byte AD679 data and resets the
interrupt latch. The system designer must assign a sufficient
priority to the DMA channel to ensure that the DMA request is
serviced before the next conversion is completed. This configu-
ration can be used with 6 MHz and 8 MHz 80186
processors.
Figure 10. AD679 to 80186 DMA Interface
AD679 to Analog Devices ADSP-2101
Figure 11 demonstrates the AD679 interfaced to an ADSP-2101.
With a clock frequency of 12.5 MHz, and instruction execution in
one 80 ns cycle, the digital signal processor supports the AD679
interface with one wait state.
The converter is configured to run asynchronously using a sam-
pling clock. The EOC output of the AD679 gets asserted at the
end of each conversion and causes an interrupt. Upon interrupt,
the ADSP-2101 immediately asserts its FO pin LOW. In the
following cycle, the processor starts a data memory read by pro-
viding an address on the DMA bus. The decoded address gener-
ates OE for the converter, and the high byte of the conversion
result is read over the data bus. The read operation is extended
with one wait state and thus started and completed within two
processor cycles (160 ns). Next, the ADSP-2101 asserts its FO
HIGH. This allows the processor to start reading the lower byte
of data. This read operation executes in a similar manner to the
first and is completed during the next 160 ns.
Figure 11. AD679 to ADSP-2101 Interface
AD679
REV. D –13–
AD679 to Analog Devices ADSP-2100A
Figure 12 demonstrates the AD679 interfaced to an ADSP-2100A.
With a clock frequency of 12.5 MHz, and instruction execution in
one 80 ns cycle, the digital signal processor supports the AD679
data memory interface with three hardware wait states.
The converter is configured to run asynchronously using a sam-
pling clock. The EOC output of the AD679 gets asserted at the
end of each conversion and causes an interrupt. Upon interrupt,
the ADSP-2100A immediately executes a data memory write
instruction, which asserts HBE. In the following cycle, the pro-
cessor starts a data memory read (high byte read) by providing
an address on the DMA bus. The decoded address generates
OE for the converter. OE, together with logic and latch, is used
to force the ADSP-2100A into a one cycle wait state by generat-
ing DMACK. The read operation is thus started and completed
within two processor cycles (160 ns). HBE is released during
high byte read. This allows the processor to read the lower byte
of data as soon as high byte read is complete. The low byte read
operation executes in a similar manner to the first and is com-
pleted during the next 160 ns.
Figure 12. AD679 to ADSP-2100A Interface
AD679
REV. D
–14–
OUTLINE DIMENSIONS
28-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP]
(D-28)
Dimensions shown in inches and (millimeters)
28
114
15
0.610 (15.49)
0.580 (12.73)
PIN 1
0.100 (2.54)
MAX
0.005 (0.13)
MIN
SEATING
PLANE
0.026 (0.66)
0.014 (0.36)
0.060 (1.52)
0.015 (0.38)
0.085 (2.16)
MAX
0.200 (5.08)
0.125 (3.18) 0.070 (1.78)
0.030 (0.76)
0.150
(3.81)
MIN
1.490 (37.85) MAX
0.100 (2.54)
0.620 (15.75)
0.590 (14.99)
0.018 (0.46)
0.008 (0.20)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
28-Lead Plastic Dual In-Line Package [PDIP]
Wide Body
(N-28)
Dimensions shown in inches and (millimeters)
28
114
15
0.610 (15.49)
0.580 (12.73)
PIN 1
0.100 (2.54)
MAX
0.005 (0.13)
MIN
SEATING
PLANE
0.026 (0.66)
0.014 (0.36)
0.060 (1.52)
0.015 (0.38)
0.085 (2.16)
MAX
0.200 (5.08)
0.125 (3.18) 0.070 (1.78)
0.030 (0.76)
0.150
(3.81)
MIN
1.490 (37.85) MAX
0.100 (2.54)
0.620 (15.75)
0.590 (14.99)
0.018 (0.46)
0.008 (0.20)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
AD679
REV. D –15–
Revision History
Location Page
6/04—Data Sheet changed from REV. C to REV. D.
Updated Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal
Changes to FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Changes to AC SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Changes to DC SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
44-Lead Ceramic Leaded Chip Carrier, J-Formed Leads [JLCC]
(J-44)
Dimensions shown in inches and (millimeters)
40 29 28
18
177
39
PIN 1
TOP VIEW
6
0.662 (16.82)
0.628 (15.95)SQ
0.700 (17.78)
0.680 (17.27)SQ
0.050
(1.27)
BSC 0.500 (12.70)
0.492 (12.50)
0.650 (16.51)
0.610 (15.49)
0.023 (0.58)
0.013 (0.33)
0.025 (0.64)
MIN
0.078 (1.98)
0.054 (1.37)
0.135 (3.43)
0.100 (2.54)
0.032 (0.81)
0.020 (0.51)
0.040 (1.02)
REF
x 45
3 PLACES
0.020 (0.51)
REF
x 45
BOTTOM VIEW
PIN 1 INDEX
0.065 (1.65)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETERS DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
OUTLINE DIMENSIONS
C00812–0–6/04(D)
–16–
