LM6125,LM6225,LM6325 LM6125/LM6225/LM6325 High Speed Buffer Literature Number: SNOSC09 LM6125/LM6225/LM6325 High Speed Buffer General Description The LM6125 family of high speed unity gain buffers slew at 800 V/s and have a small signal bandwidth of 50 MHz while driving a 50 load. These buffers drive 300 mA peak and do not oscillate while driving large capacitive loads. The LM6125 contains unique features not found in power buffers; these include current limit, thermal shutdown, electronic shutdown, and an error flag that warns of fault conditions. These buffers are built with National's VIPTM (Vertically Integrated PNP) process which provides fast PNP transistors that are true complements to the already fast NPN devices. This advanced junction-isolated process delivers high speed performance without the need for complex and expensive dielectric isolation. n n n n n n High output current: 300 mA Stable with large capacitive loads Current and thermal limiting Electronic shutdown 5V to 15V operation guaranteed Fully specified to drive 50 lines Applications n Line Driving n Radar n Sonar Features n High slew rate: 800 V/s Simplified Schematic and Block Diagram DS009222-1 DS009222-2 Numbers in () are for 14-pin N DIP. VIPTM is a trademark of National Semiconductor Corporation. (c) 1999 National Semiconductor Corporation DS009222 www.national.com LM6125/LM6225/LM6325 High Speed Buffer December 1994 Pin Configurations DS009222-4 Note: Pin 4 connected to case DS009222-3 Top View Order Number LM6125H/883 (Note 1) or LM6125H See NS Package Number H08C *Heat sinking pins. Internally connected to V-. Order Number LM6225N or LM6325N See NS Package Number N14A www.national.com Note 1: Available per 5962-9081501 2 Absolute Maximum Ratings (Note 2) ESD Tolerance (Note 9) JA (Note 4) H Package N Package Maximum Junction Temperature (TJ) Operating Temperature Range LM6125 LM6225 LM6325 Operating Supply Voltage Range If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage Input to Output Voltage (Note 2) Input Voltage Output Short-Circuit to GND (Note 3) Flag Output Voltage Storage Temperature Range Lead Temperature (Soldering, 10 seconds) 36V ( 18V) 7V Vsupply Continuous GND Vflag +Vsupply -65C to +150C 1500V 150C/W 40C/W 150C -55C to +125C -40C to +85C 0C to +70C 4.75V to 16V 260C DC Electrical Characteristics The following specifications apply for Supply Voltage = 15V, VCM = 0, RL 100 k and RS = 50 unless otherwise noted. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25C. Symbol AV1 AV2 AV3 VOS IB Parameter Voltage Gain 1 Voltage Gain 2 Offset Voltage RL = 1 k Input Bias Current Input Resistance Input Capacitance RO Output Resistance IS/D RL = 50, VIN = 10V (Note 6) RIN IS2 RL = 1k, VIN = 10V RL = 50, V+ = 5V VIN = 2 VPP (1.5 VPP) Voltage Gain 3 CIN IS1 Conditions Supply Current 1 Supply Current 2 Supply Current Typ 0.990 0.900 0.840 15 RL = 1 k, RS = 10 k 1 RL = 50 LM6125 LM6225 LM6325 Limit Limit Limit (Notes 5, 10) (Note 5) (Note 5) 0.980 0.980 0.970 0.970 0.950 0.950 0.860 0.860 0.850 V/V 0.800 0.820 0.820 Min 0.780 0.780 0.750 0.750 0.700 0.700 30 30 50 mV 50 60 100 Max 4 4 5 A 7 7 7 Max 5 M 3.5 IOUT = 10 mA 3 RL = 15 RL = , V+ = 5V 14 RL = , V = 15V 1.1 in Shutdown Units pF 5 5 5 10 10 6 Max 18 18 20 20 20 22 16 16 18 mA 18 18 20 Max 1.5 1.5 1.5 2.0 2.0 2.0 13.3 13.2 VO1 Output Swing 1 RL = 1 k 13.5 13.3 13 13 13 VO2 Output Swing 2 RL = 100 12.7 11.5 11.5 11 V 10 10 10 Min 11 11 10 9 9 9 1.6 1.6 1.6 VPP 1.3 1.4 1.5 Min 60 60 60 dB 55 50 50 Min 300 300 340 mV 400 400 400 Max VO3 VO4 PSRR Output Swing 3 Output Swing 4 Power Supply RL = 50 12 RL = 50 1.8 V+ = 5V (Note 6) 70 Rejection Ratio VOL Flag Pin Output Low Voltage V = 5V to 15V VS/D = 0V 3 www.national.com DC Electrical Characteristics (Continued) The following specifications apply for Supply Voltage = 15V, VCM = 0, RL 100 k and RS = 50 unless otherwise noted. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25C. Symbol IOH Parameter Flag Pin Output VOH Flag Pin = 15V High Current (Note 6) VTH Shutdown Threshold VIH Shutdown Pin VIL IIL Conditions Typ 0.01 LM6325 Limit Limit Units (Notes 5, 10) (Note 5) (Note 5) 10 10 10 A 20 20 20 Max 2.0 2.0 2.0 V Min V Trip Point High 2.0 2.0 2.0 Shutdown Pin 0.8 0.8 0.8 V Trip Point Low 0.8 0.8 0.8 Max Shutdown Pin VS/D = 0V -0.07 Shutdown Pin VS/D = 5V -0.05 Input High Current IO LM6225 Limit 1.4 Input Low Current IIH LM6125 Bi-State Output Current Shutdown Pin = 0V VOUT = +5V or -5V 1 -10 -10 -10 A -20 -20 -20 Max -10 -10 -10 A -20 -20 -20 Max A 50 50 100 2000 100 200 AC Electrical Characteristics The following specifications apply for Supply Voltage = 15V, VCM = 0, RL 100 k and RS = 50 unless otherwise noted. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25C. Symbol Parameter SR1 Slew Rate 1 SR2 Slew Rate 2 SR3 Slew Rate 3 BW -3 dB Bandwidth tr, tf Rise Time Fall Time tPD Propagation Delay Time OS VFT Overshoot VIN, VOUT Feedthrough in Shutdown Conditions Typ VIN = 11V, RL = 1 k VIN = 11V, RL = 50 (Note 8) VIN = 2 VPP, RL = 50 V+ = 5V (Note 6) VIN = 100 mVPP RL = 50, CL 10 pF RL = 50, CL 10 pF VO = 100 mVPP LM6125 LM6225 LM6325 Limit Limit Limit (Note 5) (Note 5) (Note 5) 550 550 550 V/s Min 30 30 30 MHz 1200 800 Units 50 50 Min RL = 50, CL 10 pF VO = 100 mVPP RL = 50, CL 10 pF VO = 100 mVPP Shutdown Pin = 0V VIN = 4 VPP, 1 MHz 8.0 ns 4.0 ns 10 % -50 dB 30 pF 700 ns RL = 50 COUT Output Capacitance Shutdown Pin = 0V in Shutdown tSD Shutdown Response Time Note 2: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating the device beyond its rated operating conditions. Note 3: During current limit, thermal limit, or electronic shutdown the input current will increase if the input to output differential voltage exceeds 8V. See Overvoltage Protection in Application Hints. Note 4: The LM6125 series buffers contain current limit and thermal shutdown to protect against fault conditions. www.national.com 4 AC Electrical Characteristics (Continued) Note 5: For operation at elevated temperature, these devices must be derated based on a thermal resistance of JA and TJ max, TJ = TA + JA PD. JC for the LM6125H and LM6225H is 17C/W. The thermal impedance JA of the device in the N package is 40C/W when soldered directly to a printed circuit board, and the heat-sinking pins (pins 3, 4, 5, 10, 11, and 12) are connected to 2 square inches of 2 oz. copper. When installed in a socket, the thermal impedance JA of the N package is 60C/W. Note 6: Limits are guaranteed by testing or correlation. Note 7: The input is biased to +2.5V, and VIN swings VPP about this value. The input swing is 2 VPP at all temperatures except for the AV3 test at -55C where it is reduced to 1.5 VPP. Note 8: The Error Flag is set (low) during current limit or thermal fault detection in addition to being set by the Shutdown pin. It is an open-collector output which requires an external pullup resistor. Note 9: Slew rate is measured with a 11V input pulse and 50 source impedance at 25C. Since voltage gain is typically 0.9 driving a 50 load, the output swing will be approximately 10V. Slew rate is calculated for transitions between 5V levels on both rising and falling edges. A high speed measurement is done to minimize device heating. For slew rate versus junction temperature see typical performance curves. The input pulse amplitude should be reduced to 10V for measurements at temperature extremes. For accurate measurements, the input slew rate should be at least 1700 V/s. Note 10: The test circuit consists of the human body model of 120 pF in series with 1500. Note 11: A military RETS specification is available on request. At the time of printing, the LM6125H/883 RETS spec complied with the Boldface limits in this column. The LM6125H/883 may also be procured as Standard Military Drawing specification #5962-9081501MXX. Typical Performance Characteristics TA = 25C, VS= 15V unless otherwise specified Frequency Response Frequency Response DS009222-9 Overshoot vs Capacitive Load DS009222-10 Large Signal Response (RL = 1 k) DS009222-11 Large Signal Response (RL = 50) DS009222-13 DS009222-12 Supply Current Slew Rate vs Temperature -3 dB Bandwidth DS009222-14 Slew Rate DS009222-15 DS009222-16 5 DS009222-17 www.national.com Typical Performance Characteristics Slew Rate TA = 25C, VS= 15V unless otherwise specified (Continued) Power Bandwidth Input Return Gain (S11) DS009222-19 DS009222-18 DS009222-20 Forward Transmission Gain (S21) Current Limit DS009222-22 DS009222-21 Typical Connection Diagram DS009222-6 www.national.com 6 Application Hints down is activated, or the shutdown (S/D) pin is driven low by external logic. Flag voltage returns to its HIGH state when normal operation resumes. POWER SUPPLY DECOUPLING The method of supply bypassing is not critical for stability of the LM6125 series buffers. However, their high current output combined with high slew rate can result in significant voltage transients on the power supply lines if much inductance is present. For example, a slew rate of 900 V/s into a 50 load produces a di/dt of 18 A/s. Multiplying this by a wiring inductance of 50 nH results in a 0.9V transient. To minimize this problem use high quality decoupling very close to the device. Suggested values are a 0.1 F ceramic in parallel with one or two 2.2 F tantalums. A ground plane is recommended. If the S/D pin is not to be used, it should be connected to V+. OVERVOLTAGE PROTECTION The LM6125 may be severely damaged or destroyed if the Absolute Maximum Rating of 7V between input and output pins is exceeded. If the buffer's input-to-output differential voltage is allowed to exceed 7V, a base-emitter junction will be in reverse-breakdown, and will be in series with a forward-biased base-emitter junction. Referring to the LM6125 simplified schematic, the transistors involved are Q1 and Q3 for positive inputs, and Q2 and Q4 for negative inputs. If any current is allowed to flow through these junctions, localized heating of the reverse-biased junction will occur, potentially causing damage. The effect of the damage is typically increased offset voltage, increased bias current, and/or degraded AC performance. The damage is cumulative, and may eventually result in complete device failure. LOAD IMPEDANCE The LM6125 is stable into any load when driven by a 50 source. As shown in the Overshoot vs Capacitive Load graph, worst case is a purely capacitive load of about 1000 pF. Shunting the load capacitance with a resistor will reduce overshoot. SOURCE INDUCTANCE Like any high-frequency buffer, the LM6125 can oscillate at high values of source inductance. The worst case condition occurs at a purely capacitive load of 50 pF where up to 100 nH of source inductance can be tolerated. With a 50 load, this goes up to 200 nH. This sensitivity may be reduced at the expense of a slight reduction in bandwidth by adding a resistor in series with the buffer input. A 100 resistor will ensure stability with source inductances up to 400 nH with any load. The device is best protected by the insertion of the parallel combination of a 100 k resistor (R1) and a small capacitor (C1) in series with the buffer input, and a 100 k resistor (R2) from input to output of the buffer (see Figure 1). This network normally has no effect on the buffer output. However, if the buffer's current limit or shutdown is activated, and the output has a ground-referred load of significantly less than 100 k, a large input-to-output voltage may be present. R1 and R2 then form a voltage divider, keeping the input-output differential below the 7V Maximum Rating for input voltages up to 14V. This protection network should be sufficient to protect the LM6125 from the output of nearly any op amp which is operated on supply voltages of 15V or lower. ERROR FLAG LOGIC The Error Flag pin is an open-collector output which requires an external pull-up resistor. Flag voltage is HIGH during operation, and is LOW during a fault condition. A fault condition occurs if either the internal current limit or the thermal shut- DS009222-8 FIGURE 1. LM6125 with Overvoltage Protection 7 www.national.com Physical Dimensions inches (millimeters) unless otherwise noted Metal Can Package (H) Order Number LM6125H/883 or LM6125H NS Package Number H08C Molded Dual-In-Line Package (N) Order Number LM6225N or LM6325N NS Package Number N14A www.national.com 8 LM6125/LM6225/LM6325 High Speed Buffer Notes LIFE SUPPORT POLICY NATIONAL'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: support@nsc.com www.national.com National Semiconductor Europe Fax: +49 (0) 1 80-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 1 80-530 85 85 English Tel: +49 (0) 1 80-532 78 32 Francais Tel: +49 (0) 1 80-532 93 58 Italiano Tel: +49 (0) 1 80-534 16 80 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: sea.support@nsc.com National Semiconductor Japan Ltd. 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