LM6125,LM6225,LM6325
LM6125/LM6225/LM6325 High Speed Buffer
Literature Number: SNOSC09
LM6125/LM6225/LM6325
High Speed Buffer
General Description
The LM6125 family of high speed unity gain buffers slew at
800 V/µs and have a small signal bandwidth of 50 MHz while
driving a 50Ωload. These buffers drive ±300 mA peak and
do not oscillate while driving large capacitive loads. The
LM6125 contains unique features not found in power buffers;
these include current limit, thermal shutdown, electronic
shutdown, and an error flag that warns of fault conditions.
These buffers are built with National’s VIP™(Vertically Inte-
grated PNP) process which provides fast PNP transistors
that are true complements to the already fast NPN devices.
This advanced junction-isolated process delivers high speed
performance without the need for complex and expensive di-
electric isolation.
Features
nHigh slew rate: 800 V/µs
nHigh output current: ±300 mA
nStable with large capacitive loads
nCurrent and thermal limiting
nElectronic shutdown
n5V to ±15V operation guaranteed
nFully specified to drive 50Ωlines
Applications
nLine Driving
nRadar
nSonar
Simplified Schematic and Block Diagram
VIP™is a trademark of National Semiconductor Corporation.
DS009222-1
DS009222-2
Numbers in () are for 14–pin N DIP.
December 1994
LM6125/LM6225/LM6325 High Speed Buffer
© 1999 National Semiconductor Corporation DS009222 www.national.com
Pin Configurations
Note 1: Available per 5962-9081501
DS009222-3
*Heat sinking pins.
Internally connected to V−.
Order Number LM6225N
or LM6325N
See NS Package Number N14A
DS009222-4
Note: Pin 4 connected to case
Top View
Order Number LM6125H/883 (Note 1)
or LM6125H
See NS Package Number H08C
www.national.com 2
Absolute Maximum Ratings (Note 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage 36V (±18V)
Input to Output Voltage (Note 2) ±7V
Input Voltage ±Vsupply
Output Short-Circuit to GND
(Note 3) Continuous
Flag Output Voltage GND ≤Vflag ≤+Vsupply
Storage Temperature Range −65˚C to +150˚C
Lead Temperature
(Soldering, 10 seconds) 260˚C
ESD Tolerance (Note 9) ±1500V
θ
JA
(Note 4)
H Package 150˚C/W
N Package 40˚C/W
Maximum Junction
Temperature (T
J
) 150˚C
Operating Temperature Range
LM6125 −55˚C to +125˚C
LM6225 −40˚C to +85˚C
LM6325 0˚C to +70˚C
Operating Supply Voltage Range 4.75V to ±16V
DC Electrical Characteristics
The following specifications apply for Supply Voltage =±15V, V
CM
=0, R
L
≥100 kΩand R
S
=50Ωunless otherwise noted.
Boldface limits apply for T
A
=T
J
=T
MIN
to T
MAX
; all other limits T
A
=T
J
=25˚C.
Symbol Parameter Conditions Typ LM6125 LM6225 LM6325 Units
Limit Limit Limit
(Notes 5, 10) (Note 5) (Note 5)
A
V1
Voltage Gain 1 R
L
=1kΩ,V
IN
=±10V 0.990 0.980 0.980 0.970
0.970 0.950 0.950
A
V2
Voltage Gain 2 R
L
=50Ω,V
IN
=±10V 0.900 0.860 0.860 0.850 V/V
0.800 0.820 0.820 Min
A
V3
Voltage Gain 3 R
L
=50Ω,V+=5V 0.840 0.780 0.780 0.750
(Note 6) V
IN
=2V
PP
(1.5 V
PP
) 0.750 0.700 0.700
V
OS
Offset Voltage R
L
=1kΩ15 30 30 50 mV
50 60 100 Max
I
B
Input Bias Current R
L
=1kΩ,R
S
=10 kΩ14 45µA
777Max
R
IN
Input Resistance R
L
=50Ω5MΩ
C
IN
Input Capacitance 3.5 pF
R
O
Output Resistance I
OUT
=±10 mA 3 5 5 5 Ω
10 10 6 Max
I
S1
Supply Current 1 R
L
=∞15 18 18 20
20 20 22
I
S2
Supply Current 2 R
L
=∞,V+=5V 14 16 16 18 mA
18 18 20 Max
I
S/D
Supply Current R
L
=∞,V
±=±
15V 1.1 1.5 1.5 1.5
in Shutdown 2.0 2.0 2.0
V
O1
Output Swing 1 R
L
=1kΩ13.5 13.3 13.3 13.2
13 13 13
V
O2
Output Swing 2 R
L
=100Ω12.7 11.5 11.5 11 ±V
10 10 10 Min
V
O3
Output Swing 3 R
L
=50Ω12 11 11 10
999
V
O4
Output Swing 4 R
L
=50Ω1.8 1.6 1.6 1.6 V
PP
1.3 1.4 1.5 Min
PSRR Power Supply V+ =5V (Note 6) 70 60 60 60 dB
Rejection Ratio 55 50 50 Min
V
OL
Flag Pin Output V±=±5V to ±15V 300 300 340 mV
Low Voltage V
S/D
=0V 400 400 400 Max
www.national.com3
DC Electrical Characteristics (Continued)
The following specifications apply for Supply Voltage =±15V, V
CM
=0, R
L
≥100 kΩand R
S
=50Ωunless otherwise noted.
Boldface limits apply for T
A
=T
J
=T
MIN
to T
MAX
; all other limits T
A
=T
J
=25˚C.
Symbol Parameter Conditions Typ LM6125 LM6225 LM6325 Units
Limit Limit Limit
(Notes 5, 10) (Note 5) (Note 5)
I
OH
Flag Pin Output V
OH
Flag Pin =15V 0.01 10 10 10 µA
High Current (Note 6) 20 20 20 Max
V
TH
Shutdown Threshold 1.4 V
V
IH
Shutdown Pin 2.0 2.0 2.0 V
Trip Point High 2.0 2.0 2.0 Min
V
IL
Shutdown Pin 0.8 0.8 0.8 V
Trip Point Low 0.8 0.8 0.8 Max
I
IL
Shutdown Pin V
S/D
=0V −0.07 −10 −10 −10 µA
Input Low Current −20 −20 −20 Max
I
IH
Shutdown Pin V
S/D
=5V −0.05 −10 −10 −10 µA
Input High Current −20 −20 −20 Max
I
O
Bi-State Output
Current Shutdown Pin =0V 1 50 50 100 µA
V
OUT
=+5V or −5V 2000 100 200
AC Electrical Characteristics
The following specifications apply for Supply Voltage =±15V, V
CM
=0, R
L
≥100 kΩand R
S
=50Ωunless otherwise noted.
Boldface limits apply for T
A
=T
J
=T
MIN
to T
MAX
; all other limits T
A
=T
J
=25˚C.
Symbol Parameter Conditions Typ LM6125 LM6225 LM6325 Units
Limit Limit Limit
(Note 5) (Note 5) (Note 5)
SR
1
Slew Rate 1 V
IN
=±11V, R
L
=1kΩ1200 V/µs
Min
SR
2
Slew Rate 2 V
IN
=±11V, R
L
=50Ω800 550 550 550
(Note 8)
SR
3
Slew Rate 3 V
IN
=2V
PP
,R
L
=50Ω50
V+ =5V (Note 6)
BW −3 dB Bandwidth V
IN
=100 mV
PP
50 30 30 30 MHz
R
L
=50Ω,C
L
≤10 pF Min
t
r
,t
f
Rise Time R
L
=50Ω,C
L
≤10 pF 8.0 ns
Fall Time V
O
=100 mV
PP
t
PD
Propagation R
L
=50Ω,C
L
≤10 pF 4.0 ns
Delay Time V
O
=100 mV
PP
O
S
Overshoot R
L
=50Ω,C
L
≤10 pF 10 %
V
O
=100 mV
PP
V
FT
V
IN
,V
OUT
Feedthrough Shutdown Pin =0V
in Shutdown V
IN
=4V
PP
, 1 MHz −50 dB
R
L
=50Ω
C
OUT
Output Capacitance Shutdown Pin =0V 30 pF
in Shutdown
t
SD
Shutdown 700 ns
Response Time
Note 2: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its rated operating conditions.
Note 3: During current limit, thermal limit, or electronic shutdown the input current will increase if the input to output differential voltage exceeds 8V. See Overvoltage
Protection in Application Hints.
Note 4: The LM6125 series buffers contain current limit and thermal shutdown to protect against fault conditions.
www.national.com 4
AC Electrical Characteristics (Continued)
Note 5: For operation at elevated temperature, these devices must be derated based on a thermal resistance of θJA and TJmax, TJ=TA+θJA PD.θJC for the
LM6125H and LM6225H is 17˚C/W. The thermal impedance θJA of the device in the N package is 40˚C/W when soldered directly to a printed circuit board, and the
heat-sinking pins (pins 3, 4, 5, 10, 11, and 12) are connected to 2 square inches of 2 oz. copper. When installed in a socket, the thermal impedance θJA of the N pack-
age is 60˚C/W.
Note 6: Limits are guaranteed by testing or correlation.
Note 7: The input is biased to +2.5V, and VIN swings VPP about this value. The input swing is 2 VPP at all temperatures except for the AV3 test at −55˚C where it
is reduced to 1.5 VPP.
Note 8: The Error Flag is set (low) during current limit or thermal fault detection in addition to being set by the Shutdown pin. It is an open-collector output which re-
quires an external pullup resistor.
Note 9: Slew rate is measured with a ±11V input pulse and 50Ωsource impedance at 25˚C. Since voltage gain is typically 0.9 driving a 50Ωload, the output swing
will be approximately ±10V. Slew rate is calculated for transitions between ±5V levels on both rising and falling edges.Ahigh speed measurement is done to minimize
device heating. For slew rate versus junction temperature see typical performance curves. The input pulse amplitude should be reduced to ±10V for measurements
at temperature extremes. For accurate measurements, the input slew rate should be at least 1700 V/µs.
Note 10: The test circuit consists of the human body model of 120 pF in series with 1500Ω.
Note 11: A military RETS specification is available on request.At the time of printing, the LM6125H/883 RETS spec complied with the Boldface limits in this column.
The LM6125H/883 may also be procured as Standard Military Drawing specification #5962-9081501MXX.
Typical Performance Characteristics T
A
= 25˚C, V
S
=±15V unless otherwise specified
Frequency Response
DS009222-9
Frequency Response
DS009222-10
Slew Rate vs Temperature
DS009222-11
Overshoot vs Capacitive Load
DS009222-12
Large Signal Response
(R
L
=1kΩ)
DS009222-13
Large Signal Response
(R
L
=50Ω)
DS009222-14
Supply Current
DS009222-15
−3 dB Bandwidth
DS009222-16
Slew Rate
DS009222-17
www.national.com5
Typical Performance Characteristics T
A
= 25˚C, V
S
=±15V unless otherwise specified (Continued)
Typical Connection Diagram
Slew Rate
DS009222-18
Power Bandwidth
DS009222-19
Input Return Gain
(S11)
DS009222-20
Forward Transmission
Gain (S21)
DS009222-21
Current Limit
DS009222-22
DS009222-6
www.national.com 6
Application Hints
POWER SUPPLY DECOUPLING
The method of supply bypassing is not critical for stability of
the LM6125 series buffers. However, their high current out-
put combined with high slew rate can result in significant
voltage transients on the power supply lines if much induc-
tance is present. For example, a slew rate of 900 V/µs into a
50Ωload produces a di/dt of 18 A/µs. Multiplying this by a
wiring inductance of 50 nH results in a 0.9V transient. To
minimize this problem use high quality decoupling very close
to the device. Suggested values are a 0.1 µF ceramic in par-
allel with one or two 2.2 µF tantalums. Aground plane is rec-
ommended.
LOAD IMPEDANCE
The LM6125 is stable into any load when driven by a 50Ω
source. As shown in the
Overshoot vs Capacitive Load
graph, worst case is a purely capacitive load of about
1000 pF. Shunting the load capacitance with a resistor will
reduce overshoot.
SOURCE INDUCTANCE
Like any high-frequency buffer, the LM6125 can oscillate at
high values of source inductance. The worst case condition
occurs at a purely capacitive load of 50 pF where up to
100 nH of source inductance can be tolerated. With a 50Ω
load, this goes up to 200 nH. This sensitivity may be reduced
at the expense of a slight reduction in bandwidth by adding a
resistor in series with the buffer input.A100Ωresistor will en-
sure stability with source inductances up to 400 nH with any
load.
ERROR FLAG LOGIC
The Error Flag pin is an open-collector output which requires
an external pull-up resistor. Flag voltage is HIGH during op-
eration, and is LOW during a fault condition.A fault condition
occurs if either the internal current limit or the thermal shut-
down is activated, or the shutdown (S/D) pin is driven low by
external logic. Flag voltage returns to its HIGH state when
normal operation resumes.
If the S/D pin is not to be used, it should be connected to V
+
.
OVERVOLTAGE PROTECTION
The LM6125 may be severely damaged or destroyed if the
Absolute Maximum Rating of 7V between input and output
pins is exceeded.
If the buffer’s input-to-output differential voltage is allowed to
exceed 7V, a base-emitter junction will be in
reverse-breakdown, and will be in series with a
forward-biased base-emitter junction. Referring to the
LM6125 simplified schematic, the transistors involved are
Q1 and Q3 for positive inputs, and Q2 and Q4 for negative
inputs. If any current is allowed to flow through these junc-
tions, localized heating of the reverse-biased junction will oc-
cur, potentially causing damage. The effect of the damage is
typically increased offset voltage, increased bias current,
and/or degraded AC performance. The damage is cumula-
tive, and may eventually result in complete device failure.
The device is best protected by the insertion of the parallel
combination of a 100 kΩresistor (R1) and a small capacitor
(C1) in series with the buffer input, and a 100 kΩresistor
(R2) from input to output of the buffer (see
Figure 1
). This
network normally has no effect on the buffer output. How-
ever, if the buffer’s current limit or shutdown is activated, and
the output has a ground-referred load of significantly less
than 100 kΩ, a large input-to-output voltage may be present.
R1 and R2 then form a voltage divider, keeping the
input-output differential below the 7V Maximum Rating for in-
put voltages up to 14V. This protection network should be
sufficient to protect the LM6125 from the output of nearly any
op amp which is operated on supply voltages of ±15V or
lower.
DS009222-8
FIGURE 1. LM6125 with Overvoltage Protection
www.national.com7
Physical Dimensions inches (millimeters) unless otherwise noted
Metal Can Package (H)
Order Number LM6125H/883 or LM6125H
NS Package Number H08C
Molded Dual-In-Line Package (N)
Order Number LM6225N or LM6325N
NS Package Number N14A
www.national.com 8
Notes
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www.national.com
LM6125/LM6225/LM6325 High Speed Buffer
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
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