The RF MOSFET Line
N–Channel Enhancement–Mode
Designed for broadband commercial and military applications using single
ended circuits at frequencies to 400 MHz. The high power, high gain and
broadband performance of each device makes possible solid state transmitters
for FM broadcast or TV channel frequency bands.
•Guaranteed Performance
MRF175LU @ 28 V, 400 MHz (“U” Suffix)
Output Power — 100 Watts
Power Gain — 10 dB Typ
Efficiency — 55% Typ
•100% Ruggedness Tested At Rated Output Power
•Low Thermal Resistance
•Low Crss — 20 pF Typ @ VDS = 28 V
MAXIMUM RATINGS
Rating Symbol Value Unit
Drain–Source Voltage VDSS 65 Vdc
Gate–Source Voltage VGS ±40 Vdc
Drain Current — Continuous ID13 Adc
Total Device Dissipation @ TC = 25°C
Derate above 25°CPD270
1.54 Watts
W/°C
Storage Temperature Range Tstg –65 to +150 °C
Operating Junction Temperature TJ200 °C
THERMAL CHARACTERISTICS
Characteristic Symbol Max Unit
Thermal Resistance, Junction to Case RθJC 0.65 °C/W
ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted)
Characteristic Symbol Min Typ Max Unit
OFF CHARACTERISTICS
Drain–Source Breakdown Voltage
(VGS = 0, ID = 50 mA) V(BR)DSS 65 — — Vdc
Zero Gate Voltage Drain Current
(VDS = 28 V, VGS = 0) IDSS — — 2.5 mAdc
Gate–Body Leakage Current
(VGS = 20 V, VDS = 0) IGSS — — 1.0 µAdc
(continued)
Handling and Packaging — MOS devices are susceptible to damage from electrostatic charge. Reasonable precautions in handling and
packaging MOS devices should be observed.
100 W, 28 V, 400 MHz
N–CHANNEL
BROADBAND
RF POWER FETs
CASE 333–04, STYLE 2
Order this document
by MRF175LU/D
SEMICONDUCTOR TECHNICAL DATA
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ELECTRICAL CHARACTERISTICS — continued (TC = 25°C unless otherwise noted)
Characteristic Symbol Min Typ Max Unit
ON CHARACTERISTICS
Gate Threshold Voltage (VDS = 10 V, ID = 100 mA) VGS(th) 1.0 3.0 6.0 Vdc
Drain–Source On–Voltage (VGS = 10 V, ID = 5.0 A) VDS(on) 0.1 0.9 1.5 Vdc
Forward Transconductance (VDS = 10 V, ID = 2.5 A) gfs 2.0 3.0 — mhos
DYNAMIC CHARACTERISTICS
Input Capacitance (VDS = 28 V, VGS = 0, f = 1.0 MHz) Ciss — 180 — pF
Output Capacitance (VDS = 28 V, VGS = 0, f = 1.0 MHz) Coss — 200 — pF
Reverse Transfer Capacitance (VDS = 28 V, VGS = 0, f = 1.0 MHz) Crss — 20 — pF
FUNCTIONAL CHARACTERISTICS — MRF175LU (Figure 2)
Common Source Power Gain
(VDD = 28 Vdc, Pout = 100 W, f = 400 MHz, IDQ = 100 mA) Gps 8.0 10 — dB
Drain Efficiency
(VDD = 28 Vdc, Pout = 100 W, f = 400 MHz, IDQ = 100 mA) η50 55 — %
Electrical Ruggedness
(VDD = 28 Vdc, Pout = 100 W, f = 400 MHz, IDQ = 100 mA,
VSWR 30:1 at all Phase Angles)
ψNo Degradation in Output Power
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Figure 2. 400 MHz Test Circuit
Figure 3. Common Source Unity Current Gain
Frequency versus Drain Current Figure 4. DC Safe Operating Area
″
″
°
C1, C8 — 270 pF ATC Chip Cap
C2, C4, C6, C7 — 1.0–20 pF Trimmer Cap
C3 — 15 pF Mini Unelco Cap
C5 — 33 pF Mini Unelco Cap
C9, C12 — 0.1 µF Ceramic Cap
C11, C14 — 680 pF Feed Thru Cap
C13 — 50 µF Tantalum Cap
L1 — Hairpin Inductor #18 Wire
L2 — 12 Turns #18 Wire 0.450″ ID
L3 — Ferroxcube VK200 20/4B
R1 — 10 k 1/4 W Resistor
R2 — 1 k 1/4 W Resistor
R3 — 1.5 k 1/4 W Resistor
Z1 — Microstrip Line 0.950″ x 0.250″
Z2 — Microstrip Line 1″ x 0.250″
Z3 — Microstrip Line 0.550″ x 0.250″
Board Material — 0.062″ Teflon —
fiberglass, εr = 2.56, 1 oz. copper
clad both sides
TYPICAL CHARACTERISTICS
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Figure 5. Drain Current versus Gate Voltage
(Transfer Characteristics) Figure 6. Gate–Source Voltage versus
Case Temperature
°
Figure 7. Capacitance versus Drain–Source Voltage
TYPICAL CHARACTERISTICS
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TYPICAL CHARACTERISTICS
Figure 9. Output Power versus Supply Voltage
Figure 10. Power Gain versus Frequency Figure 11. Output Power versus Input Power
MRF175LU
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INPUT AND OUTPUT IMPEDANCE
Ω
Figure 12.
RF POWER MOSFET CONSIDERATIONS
MOSFET CAPACITANCES
The physical structure of a MOSFET results in capacitors
between the terminals. The metal oxide gate structure deter-
mines the capacitors from gate–to–drain (Cgd), and gate–to–
source (Cgs). The PN junction formed during the fabrication
of the FET results in a junction capacitance from drain–to–
source (Cds).
These capacitances are characterized as input (Ciss), out-
put (Coss) and reverse transfer (Crss) capacitances on data
sheets. The relationships between the inter–terminal capaci-
tances and those given on data sheets are shown below. Th e
Ciss can be specified in two ways:
1. Drain shorted to source and positive voltage at the gate.
2. Positive voltage of the drain in respect to source and zero
volts at the gate. In the latter case the numbers are lower.
However, neither method represents the actual operat-
ing conditions in RF applications.
LINEARITY AND GAIN CHARACTERISTICS
In addition to the typical IMD and power gain data present-
ed, Figure 3 may give the designer additional information on
the capabilities of this device. The graph represents the
small signal unity current gain frequency at a given drain cur-
rent level. This is equivalent to fT for bipolar transistors.
Since this test is performed at a fast sweep speed, heating of
the device does not occur. Thus, in normal use, the higher
temperatures may degrade these characteristics to some ex-
tent.
DRAIN CHARACTERISTICS
One figure of merit for a FET is its static resistance in the
full–on condition. This on–resistance, VDS(on), occurs in the
linear region of the output characteristic and is specified un-
der specific test conditions for gate–source voltage and drain
current. For MOSFETs, VDS(on) has a positive temperature
coefficient and constitutes an important design consideration
at high temperatures, because it contributes to the power
dissipation within the device.
GATE CHARACTERISTICS
The gate of the FET is a polysilicon material, and is electri-
cally isolated from the source by a layer of oxide. The input
resistance is very high — on the order of 109 ohms — result-
ing in a leakage current of a few nanoamperes.
Gate control is achieved by applying a positive voltage
slightly in excess of the gate–to–source threshold voltage,
VGS(th).
Gate Voltage Rating — Never exceed the gate voltage
rating. Exceeding the rated VGS can result in permanent
damage to the oxide layer in the gate region.
Gate Termination — The gates of these devices are es-
sentially capacitors. Circuits that leave the gate open–cir-
cuited or floating should be avoided. These conditions can
result in turn–on of the devices due to voltage build–up on
the input capacitor due to leakage currents or pickup.
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Gate Protection — These devices do not have an internal
monolithic zener diode from gate–to–source. If gate protec-
tion is required, an external zener diode is recommended.
Using a resistor to keep the gate–to–source impedance
low also helps damp transients and serves another important
function. Voltage transients on the drain can be coupled to
the gate through the parasitic gate–drain capacitance. If the
gate–to–source impedance and the rate of voltage change
on the drain are both high, then the signal coupled to the gate
may be large enough to exceed the gate–threshold voltage
and turn the device on.
HANDLING CONSIDERATIONS
When shipping, the devices should be transported only in
antistatic bags or conductive foam. Upon removal from the
packaging, careful handling procedures should be adhered
to. Those handling the devices should wear grounding straps
and devices not in the antistatic packaging should be kept in
metal tote bins. MOSFETs should be handled by the case
and not by the leads, and when testing the device, all leads
should make good electrical contact before voltage is ap-
plied. As a final note, when placing the FET into the system it
is designed for, soldering should be done with a grounded
iron.
DESIGN CONSIDERATIONS
The MRF175L is a RF power N–channel enhancement
mode field–effect transistor (FETs) designed for HF, VHF and
UHF power amplifier applications. M/A-COM FETs feature
a vertical structure with a planar design.
Motorola Application Note AN211A, FETs in Theory and
Practice, is suggested reading for those not familiar with the
construction and characteristics of FETs.
The major advantages of RF power FETs include high
gain, low noise, simple bias systems, relative immunity from
thermal runaway, and the ability to withstand severely mis-
matched loads without suffering damage. Power output can
be varied over a wide range with a low power dc control sig-
nal.
DC BIAS
The MRF175L is an enhancement mode FET and, there-
fore, does not conduct when drain voltage is applied. Drain
current flows when a positive voltage is applied to the gate.
RF power FETs require forward bias for optimum perfor-
mance. The value of quiescent drain current (IDQ) is not criti-
cal for many applications. The MRF175L was characterized
at IDQ = 100 mA, each side, which is the suggested minimum
value of IDQ. For special applications such as linear amplifi-
cation, IDQ may have to be selected to optimize the critical
parameters.
The gate is a dc open circuit and draws no current. There-
fore, the gate bias circuit may be just a simple resistive divid-
er network. Some applications may require a more elaborate
bias sytem.
GAIN CONTROL
Power output of the MRF175L may be controlled from its
rated value down to zero (negative gain) by varying the dc
gate voltage. This feature facilitates the design of manual
gain control, AGC/ALC and modulation systems.
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PACKAGE DIMENSIONS
CASE 333–04
ISSUE E
D
SOURCE
DRAIN
SOURCE
GATE
NQ2 PL
–A–
K
K
–B–
P
F
G
H–T–
N
JN
C
8
Specifications subject to change without notice.
n North America: Tel. (800) 366-2266, Fax (800) 618-8883
n Asia/Pacific: Tel.+81-44-844-8296, Fax +81-44-844-8298
n Europe: Tel. +44 (1344) 869 595, Fax+44 (1344) 300 020
Visit www.macom.com for additional data sheets and product information.
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