3.3 V, 50 Mbps to 4.25 Gbps,
Single-Loop, Laser Diode Driver
ADN2873
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
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Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2008 Analog Devices, Inc. All rights reserved.
FEATURES
SFP/SFF and SFF-8472 MSA compliant
SFP reference design available
50 Mbps to 4.25 Gbps operation
Automatic average power control
Typical 60 ps output rise/fall time
VCSEL, DFB, and FP laser support
Bias current range: from 2 mA to 100 mA
Modulation current range: from 5 mA to 90 mA
Laser fail alarm and automatic laser shutdown (ALS)
Bias and modulation current monitoring
Voltage setpoint control
Resistor setpoint control
3.3 V supply
24-lead 4 mm × 4 mm LFCSP
Pin compatible with ADN2870
APPLICATIONS
1×/2×/4× Fibre Channel SFP/SFF modules
Multirate OC3 to OC48-FEC SFP/SFF modules
LX-4 modules
DWDM/CWDM laser transmitters
HDTV (SMPTE family) laser transmitters
GENERAL DESCRIPTION
Like the ADN2870, the ADN2873 laser diode driver (LDD) is
designed for advanced SFP and SFF modules, using SFF-8472
digital diagnostics. The ADN2873 supports NRZ data
transmission operation from 50 Mbps up to 4.25 Gbps. With a
new alarm scheme, this device avoids the shutdown issue
caused by the system transient generated from various lasers.
The ADN2873 monitors the laser bias and modulation currents
and it provides fail alarms and ALS. Using setup voltages of a
microcontroller DAC or a trimmable resistor voltage divider,
the ADN2873 can set up a laser optical average output power and
extinction ratio. The optical average power control loop consists
of an optical feedback from a photodiode, the comparator, and a
status holder. The ADN2873 works easily with the Analog
Devices, Inc., ADuC7019/ADuC702x family of MicroConverter®
devices and with the ADN289x family of limiting amplifiers to
make a complete SFP/SFF transceiver chipset solution.
The ADN2873 is pin compatible with the ADN2870 dual-loop
LDD, allowing the same design to work with either device. For
dual-loop control applications, refer to the ADN2870 data sheet.
The product is available in a space-saving 24-lead, 4 mm × 4 mm
LFCSP specified over the −40°C to +85°C temperature range.
Figure 1 shows an application diagram of the voltage setpoint
control with single-ended laser interface. Figure 36 shows a
differential laser interface.
APPLICATIONS DIAGRAM
ANALOG DEVICES
MICROCONTROLLER
T
x_DISABL
E
Tx_FAULT
CONTROL
PAVREF
PAVSET
ADN2873
RPAV
GND
DAC
DAC
VCC
MPD
ERREF
ERSET
GND
IMOD
DATAP
IMODP
DATAN
IMODN
IBMON IMMON
ALSFAIL
IBIAS
100Ω
CCBIAS
V
CC
LASER
L
R
V
CC
V
CC
VCC
GND GND
PAVCAP
470Ω1kΩGND
GND
NC
1kΩ
1kΩ
ADC
V
CC
×100
V
CC
R
Z
07493-001
Figure 1.
ADN2873
Rev. 0 | Page 2 of 20
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Applications Diagram ...................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
SFP Timing Specifications ........................................................... 5
Absolute Maximum Ratings ............................................................ 6
ESD Caution .................................................................................. 6
Pin Configuration and Function Descriptions ............................. 7
Typical Performance Characteristics ............................................. 8
Single-Ended Output ................................................................... 8
Differential Output ....................................................................... 9
Performance Characteristics ..................................................... 10
Optical Waveforms ......................................................................... 12
Theory of Operation ...................................................................... 13
Laser Control .............................................................................. 13
Control Methods ........................................................................ 13
Voltage Setpoint Calibration ..................................................... 13
Resistor Setpoint Calibration .................................................... 15
IMPD Monitoring .......................................................................... 15
Loop Bandwidth Selection ........................................................ 16
Power Consumption .................................................................. 16
Automatic Laser Shutdown (TX_Disable) .............................. 16
Bias and Modulation Monitor Currents .................................. 16
IBIAS Pin ..................................................................................... 16
Data Inputs .................................................................................. 17
Laser Diode Interfacing ............................................................. 17
Alarms .......................................................................................... 18
Outline Dimensions ....................................................................... 19
Ordering Guide .......................................................................... 19
REVISION HISTORY
6/08—Revision 0: Initial Version
ADN2873
Rev. 0 | Page 3 of 20
SPECIFICATIONS
VCC = 3.0 V to 3.6 V. All specifications TMIN to TMAX1, unless otherwise noted. Typical values are specified at 25°C.
Table 1.
Parameter Min Typ Max Unit Conditions/Comments
LASER BIAS CURRENT (IBIAS)
Output Current IBIAS 2 100 mA
Compliance Voltage 1.2 VCC V
IBIAS when ALS Is High 0.1 mA
MODULATION CURRENT (IMODP, IMODN)2
Output Current IMOD 5 90 mA
Compliance Voltage 1.5 VCC V
IMOD when ALS Is High 0.1 mA 5 mA < IMOD < 90 mA
Rise Time Single-Ended Output2, 3 60 104 ps 5 mA < IMOD < 90 mA
Fall Time Single-Ended Output2, 3 60 96 ps 5 mA < IMOD < 90 mA
Random Jitter Single-Ended Output2, 3 0.8 1.1 ps (rms) 5 mA < IMOD < 90 mA
Deterministic Jitter Single-Ended Output3, 4 19 35 ps 20 mA < IMOD < 90 mA
Pulse Width Distortion2, 3 Single-Ended Output 21 30 ps 20 mA < IMOD < 90 mA
Rise Time Differential Output3, 5 47.1 ps 5 mA < IMOD < 30 mA
Fall Time Differential Output3, 5 46 ps 5 mA < IMOD < 30 mA
Random Jitter Differential Output3, 5 0.64 ps (rms) 5 mA < IMOD < 30 mA
Deterministic Jitter Differential Output3, 6 12 ps 5 mA < IMOD < 30 mA
Pulse Width Distortion Differential Output3, 5 2.1 ps 5 mA < IMOD < 30 mA
Rise Time Differential Output3, 5 56 ps 5 mA < IMOD < 90 mA
Fall Time Differential Output3, 5 55 ps 5 mA < IMOD < 90 mA
Random Jitter Differential Output3, 5 0.61 ps (rms) 5 mA < IMOD < 90 mA
Deterministic Jitter Differential Output3, 7 17 ps 5 mA < IMOD < 90 mA
Pulse Width Distortion Differential Output3, 5 1.6 ps 5 mA < IMOD < 90 mA
AVERAGE POWER SET (PAVSET)
Pin Capacitance 80 pF
Voltage 1.1 1.2 1.3 V
Photodiode Monitor Current (Average Current) 50 1200 μA Resistor setpoint mode
EXTINCTION RATIO SET INPUT (ERSET)
Resistance Range 1.5 25 kΩ Resistor setpoint mode
0.99 1 1.01 kΩ Voltage setpoint mode
AVERAGE POWER REFERENCE VOLTAGE INPUT (PAVREF)
Voltage Range 0.07 1 V Voltage setpoint mode (RPAV fixed at 1 kΩ)
Photodiode Monitor Current (Average Current) 70 1000 μA Voltage setpoint mode (RPAV fixed at 1 kΩ)
EXTINCTION RATIO REFERENCE VOLTAGE INPUT (ERREF)
Voltage Range 0.05 0.9 V Voltage setpoint mode (RERSET fixed at 1 kΩ)
ERREF Voltage to IMOD Gain 100 mA/V
DATA INPUTS (DATAP, DATAN)8
Input Voltage Swing (Differential) 0.4 2.4 V p-p AC-coupled
Input Impedance (Single-Ended) 50 Ω
LOGIC INPUTS (ALS)
VIH 2 V
VIL 0.8 V
ALARM OUTPUT (FAIL)9
VOFF >1.8 V Voltage required at FAIL for IBIAS and
IMOD to turn off when FAIL asserted
VON <1.3 V Voltage required at FAIL for IBIAS and
IMOD to stay on when FAIL asserted
ADN2873
Rev. 0 | Page 4 of 20
Parameter Min Typ Max Unit Conditions/Comments
IBMON, IMMON DIVISION RATIO
IBIAS/IBMON3 76 98 112 A/A 2 mA < IBIAS < 11 mA
IBIAS/IBMON3 85 98 115 A/A 11 mA < IBIAS < 50 mA
IBIAS/IBMON3 92 100 108 A/A 50 mA < IBIAS < 100 mA
IBIAS/IBMON STABILITY3, 10 ±5 % 10 mA < IBIAS < 100 mA
IMOD/IMMON 42 A/A
IBMON Compliance Voltage 0 1.3 V
SUPPLY
ICC11 31 mA When IBIAS = IMOD = 0 mA
VCC (with Respect to GND)12 3.0 3.3 3.6 V
1 Temperature range is from −40°C to +85°C.
2 Measured into a single-ended 15 Ω load (22 Ω resistor in parallel with digital scope 50 Ω input) using a 1111111100000000 pattern at 2.5 Gbps, shown in Figure 2.
3 Guaranteed by design and characterization. Not production tested.
4 Measured into a single-ended 15 Ω load using a K28.5 pattern at 2.5 Gbps, shown in Figure 2.
5 Measured into a differential 30 Ω (43 Ω differential resistor in parallel with a digital scope of 50 Ω input) load using a 1111111100000000 pattern at 4.25 Gbps, as
shown in Figure 3.
6 Measured into a differential 30 Ω load using a K28.5 pattern at 4.25 Gbps, as shown in Figure 3.
7 Measured into a differential 30 Ω load using a K28.5 pattern at 2.7 Gbps, as shown in Figure 3.
8 When the voltage on DATAP is greater than the voltage on DATAN, the modulation current flows into the IMODP pin.
9 Guaranteed by design. Not production tested.
10 IBIAS/IBMON ratio stability is defined in SFF-8472 Revision 9 over temperature and supply variation.
11 See the ICC minimum for power calculation in the Power Consumption section.
12 All VCC pins should be shorted together.
ADN2873
IMODP
BIAS TEE
80kHz → 27GHz
VCC VCC
TO HIGH SPEED
DIGITAL
OSCILLOSCOPE
50Ω INPUT
R
22ΩC
L
07493-002
Figure 2. High Speed Electrical Test Single-Ended Output Circuit
ADN2873
IMODN
BIAS TEE
80kHz → 27GHz
V
CC
TO HIGH SPEED
DIGITAL
OSCILLOSCOPE
50Ω DIFFERENTIAL INPUT
R
43Ω
C
L
V
CC
IMODP
LC
BIAS TEE
80kHz → 27GHz
07493-003
Figure 3. High Speed Electrical Test Differential Output Circuit
ADN2873
Rev. 0 | Page 5 of 20
SFP TIMING SPECIFICATIONS
Table 2.
Parameter Symbol Min Typ Max Unit Conditions/Comments
ALS Assert Time t_off 1 5 μs Time for the rising edge of ALS (Tx_DISABLE) to when
the bias current falls below 10% of nominal
ALS Negate Time1 t_on 0.15 0.4 ms
Time for the falling edge of ALS to when the modulation
current rises above 90% of nominal
Time to Initialize, Including Reset of FAIL1 t_init 25 275 ms From power-on or negation of FAIL using ALS
FAIL Assert Time t_fault 100 μs Time to fault to FAIL on
ALS to Reset Time t_reset 5 μs Time Tx_DISABLE must be held high to reset Tx_FAULT
1 Guaranteed by design and characterization. Not production tested.
DATAP
DATAN
DATAP – DATAN
V p-p
DIFF
= 2 × V
SE
V
SE
0V
07493-004
Figure 4. Signal Level Definition
0.1µF 0.1µF 10µF
1µH
3.3V
SFP HOST BOARD
SFP MODULE
V
CC
_Tx
07493-005
Figure 5. Recommended SFP Supply
ADN2873
Rev. 0 | Page 6 of 20
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Rating
VCC to GND 4.2 V
IMODN, IMODP −0.3 V to +4.8 V
All Other Pins −0.3 to +3.9 V
Junction Temperature 150°C
Operating Temperature Range, Industrial −40°C to +85°C
Storage Temperature Range –65°C to +150°C
Junction Temperature (TJ max) 125°C
Power Dissipation1 (TJ max − TA)/θJA W
θJA Thermal Impedance2 30°C/W
θJC Thermal Impedance 29.5°C/W
Lead Temperature (Soldering, 10 sec) 300°C
1 Power consumption equations are provided in the Power Consumption
section.
2 θJA is defined when the part is soldered on a four-layer board.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
ADN2873
Rev. 0 | Page 7 of 20
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
NOTES
1. NC = NO CONNECT.
2
. THE LFCSP HAS AN EXPOSED PADDLE THAT MUST BE CONNECTED
TO GND.
07493-006
PIN 1
INDICATOR
1CCBIAS
2PAVSET
3GND
4VCC
5PAVREF
6RPAV
15 ERREF
16 VCC
17 IBMON
18 FAIL
14 IMMON
13 ERSET
7
NC
8
PAVCAP
9
GND
11
DATAN
12
ALS
10
DATAP 21 IMODP
22 IMODN
23 GND
24 IBIAS
20 VCC
19 GND
TOP VIEW
(Not to Scale)
ADN2873
Figure 6. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1 CCBIAS Not Used (Internally Connected to VCC)
2 PAVSET Average Optical Power Set Pin
3 GND Supply Ground
4 VCC Supply Voltage
5 PAVREF Reference Voltage Input for Average Optical Power Control
6 RPAV Average Power Resistor when Using PAVREF
7 NC No Connect
8 PAVCAP Average Power Loop Capacitor
9 GND Supply Ground
10 DATAP Data, Positive Differential Input
11 DATAN Data, Negative Differential Input
12 ALS Automatic Laser Shutdown
13 ERSET Extinction Ratio Set Pin
14 IMMON Modulation Current Monitor Current Source
15 ERREF Reference Voltage Input for Extinction Ratio Control
16 VCC Supply Voltage
17 IBMON Bias Current Monitor Current Source
18 FAIL FAIL Alarm Output
19 GND Supply Ground
20 VCC Supply Voltage
21 IMODP Modulation Current Positive Output (Current Sink), Connect to Laser Diode
22 IMODN Modulation Current Negative Output (Current Sink)
23 GND Supply Ground
24 IBIAS Laser Diode Bias (Current Sink to Ground)
ADN2873
Rev. 0 | Page 8 of 20
TYPICAL PERFORMANCE CHARACTERISTICS
SINGLE-ENDED OUTPUT
These performance characteristics were measured using the high speed electrical single-ended output circuit shown in Figure 2.
90
0
30
60
0408020 60 100
MODULATION CURRENT (mA)
RISE TIME (ps)
0
7493-012
Figure 7. Rise Time vs. Modulation Current, IIBIAS = 20 mA
0
20
40
60
80
0408020 60 100
MODULATION CURRENT (mA)
FALL TIME (ps)
0
7493-013
Figure 8. Fall Time vs. Modulation Current, IIBIAS = 20 mA
0
1.2
1.0
0.8
0.6
0.4
0.2
0 20406080100
MODULATION CURRENT (mA)
RANDOM JITTER (rms)
0
7493-014
Figure 9. Random Jitter vs. Modulation Current, IIBIAS = 20 mA
0
45
40
35
30
25
20
15
10
5
20 40 8060 100
MODULATION CURRENT (mA)
DETERMINISTIC JITTER (ps)
0
7493-015
Figure 10. Deterministic Jitter at 2.488 Gbps vs. Modulation Current, IIBIAS = 20 mA
ADN2873
Rev. 0 | Page 9 of 20
DIFFERENTIAL OUTPUT
These performance characteristics were measured using the high speed electrical differential output circuit shown in Figure 3.
90
0
0100
MODULATION CURRENT (mA)
RISE TIME (ps)
60
30
20 40 60 80
07493-016
Figure 11. Rise Time vs. Modulation Current, IIBIAS = 20 mA
80
0
0100
MODULATION CURRENT (mA)
FALL TIME (ps)
20 40 60 80
60
40
20
07493-017
Figure 12. Fall Time vs. Modulation Current, IIBIAS = 20 mA
1.2
0
0100
MODULATION CURRENT (mA)
RANDOM JITTER (rms)
20 40 60 80
1.0
0.8
0.6
0.4
0.2
07493-018
Figure 13. Random Jitter vs. Modulation Current, IIBIAS = 20 mA
40
0
0100
MODULATION CURRENT (mA)
DETERMINISTIC JITTER (ps)
20 40 60 80
35
30
25
20
15
10
5
07493-019
Figure 14. Deterministic Jitter at 4.25 Gbps vs. Modulation Current, IIBIAS = 20 mA
ADN2873
Rev. 0 | Page 10 of 20
PERFORMANCE CHARACTERISTICS
40
240
180
100
220
160
120
140
100
60
80
0 1020406080100
MODULATION CURRENT (mA)
TOTAL SUPPLY CURRENT (mA)
07493-020
I
IBIAS
= 90mA
I
IBIAS
= 40mA
I
IBIAS
= 20mA
I
IBIAS
= 10mA
Figure 15. Total Supply Current vs. Modulation Current
Total Supply Current = IVCC + IIBIAS + IIMOD
80
120
115
110
105
100
95
90
85
–40 25 85
TEMPERATURE (°C)
IIBIAS/IIBMON GAIN
0
7493-021
Figure 16. IIBIAS/IIBMON Gain vs. Temperature, IIBIAS = 11 mA
OC48 PRBS31
DATA TRANSMISSION
ALS
07493-022
t
_OFF
LESS THAN 1µs
Figure 17. ALS Assert Time, 5 μs/DIV
20
40
30
32
34
36
38
28
26
24
22
–40 25 85
TEMPERATURE (°C)
SUPPLY CURRENT (I
CC
)
07493-023
Figure 18. Supply Current (ICC) vs. Temperature with ALS Asserted, IIBIAS = 11 mA
55
30
–50 110
TEMPERATURE (°C)
I
IMOD
/I
IMMON
GAIN
50
45
40
35
–30 –10 10 30 50 70 90
07493-024
Figure 19. IIMOD/IIMMON Gain vs. Temperature, IIMOD = 30 mA
TRANSMISSION
t
_ON
ALS
07493-025
Figure 20. ALS Negate Time, 50 μs/DIV
ADN2873
Rev. 0 | Page 11 of 20
FAULT FORCED ON PAVSET
FAIL ASSERTED
07493-026
Figure 21. FAIL Assert Time,1 μs/DIV
POWER SUPPLY TURNED ON
TRANSMISSION ON
07493-027
Figure 22. Time to Initialize, Including Reset, 40 ms/DIV
ADN2873
Rev. 0 | Page 12 of 20
OPTICAL WAVEFORMS
VCC = 3.3 V and TA = 25°C, unless otherwise noted. Note that there was no change to PAVCAP and ERCAP values when different data
rates were tested. Figure 23, Figure 24, and Figure 25 show multirate performance using the low cost Fabry Perot TOSA NEC NX7315UA;
Figure 26 and Figure 27 show performance over temperature using the DFB TOSA Sumitomo SLT2486.
(ACQ LIMIT TEST) W
A
V
EFORMS 1000
07493-007
Figure 23. Optical Eye 2.488 Gbps, 65 ps/DIV, PRBS 231 − 1
PAV = −4.5 dBm, ER = 9 dB, Mask Margin 25%
(ACQ LIMIT TEST) W
A
V
EFORMS 1000
07493-008
Figure 24. Optical Eye 622 Mbps, 264 ps/DIV, PRBS 231 − 1
PAV = −4.5 dBm, ER = 9 dB, Mask Margin 50%
(ACQ LIMIT TEST) W
A
V
EFORMS 1000
07493-009
Figure 25. Optical Eye 155 Mbps,1.078 ns/DIV, PRBS 231 − 1
PAV = −4.5 dBm, ER = 9 dB, Mask Margin 50%
(ACQ LIMIT TEST) W
A
V
EFORMS 1001
07493-010
Figure 26. Optical Eye 2.488 Gbps, 65 ps/DIV, PRBS 231 − 1
PAV = 0 dBm, ER = 9 dB, Mask Margin 22%, TA = 25°C
(ACQ LIMIT TEST) W
A
V
EFORMS 1001
07493-011
Figure 27. Optical Eye 2.488 Gbps, 65 ps/DIV, PRBS 231 − 1
PAV = −0.2 dBm, ER = 8.96 dB, Mask Margin 21%, TA = 85°C
ADN2873
Rev. 0 | Page 13 of 20
THEORY OF OPERATION
Laser diodes have a current-in to light-out transfer function, as
shown in Figure 28. Two key characteristics of this transfer
function are the threshold current, ITH, and the laser slope in the
linear region beyond the threshold current, referred to as the
slope efficiency, LI.
OPTICAL POWER
P1
P
AV
P
O
I
TH
CURRENT
P
AV
=
ΔP
ΔI
ER = P1
P
O
2
P1 + P
O
LI = ΔP
ΔI
07493-028
Figure 28. Laser Transfer Function
LASER CONTROL
Typically, laser threshold current and slope efficiency are both
functions of temperature. For FP-type and/or DFB-type lasers,
the threshold current increases and the slope efficiency decreases
with increasing temperature. In addition, these parameters vary
as the laser ages. To maintain a constant optical average power
and a constant optical extinction ratio over temperature and
laser lifetime, it is necessary to vary the applied electrical bias
current and modulation current to compensate for the changing
LI characteristics of the laser.
Average Power Control Loop (APCL)
The APCL compensates for changes in ITH and LI by varying
IBIAS. Average power control is performed by measuring the
monitor photodiode (MPD) current, IMPD. This current is
bandwidth limited by the MPD. This is not a problem because
the APCL is required to respond to the average current from the
MPD.
Extinction Ratio (ER) Control
ER control is implemented by adjusting the modulation current.
Temperature calibration is required to adjust the modulation
current to compensate for variations of the laser characteristics
with temperature.
CONTROL METHODS
The ADN2873 has two methods for setting the average power
(PAV) and ER. The laser optical output average power and
extinction ratio are configurable by using the voltage setting or
the resistor setting. In voltage setting mode, a microcontroller
DAC can drive the PAVREF and ERREF pins with programmable
voltages. Alternatively, in resistor setting mode, the resistor
divider or potentiometers can set proper voltages at the PAVSET
and ERSET pins. Refer to Figure 29 and Figure 30 for details.
VOLTAGE SETPOINT CALIBRATION
The ADN2873 allows interface to a microcontroller for both
control and monitoring (see Figure 29). The average power and
extinction ratio can be set using the microcontroller DACs to
provide controlled reference voltages, PAVREF and ERREF.
PAVREF = PAV × RSP × RPAV (V)
100
ERSET
MOD R
I
ERREF
×
= (V)
where:
PAV is the laser optical average power output required.
RSP is the optical responsivity (in amperes per watt).
RPAV = RERSET = 1 kΩ.
IMOD is the modulation current.
In voltage setpoint mode, RPAV and RERSET must be 1 kΩ resistors
with a 1% tolerance and a temperature coefficient of 50 ppm/°C.
Power-On Sequence in Voltage Setpoint Mode
During power-up, an initial sequence allows 25 ms before
enabling the alarms. Therefore, the user must ensure that the
voltages applied to PAVREF and ERREF are stabilized within
20 ms after ramp-up of the power supply. If supplying the
PAVREF and ERREF voltages after the 25 ms, the alarms and
FAIL circuitry kick in before the voltages are stabilized to
PAVREF and ERREF, which causes an unexpected failure.
ADN2873
Rev. 0 | Page 14 of 20
ANALOG DEVICES
MICROCONTROLLER
Tx_DISABLE
Tx_FAULT
CONTROL
PAVREF
PAVSET
ADN2873
RPAV
GND
DAC
DAC
V
CC
MPD
ERREF
ERSET
GND
IMOD
DATAP
IMODP
DATAN
IMODN
IBMON IMMON
ALSFAIL
IBIAS
100Ω
CCBIAS
V
CC
LASER
L
R
V
CC
V
CC
VCC
GND GND
PAVCAP
470Ω1kΩ
GND
GND
NC
1kΩ
1kΩ
ADC
V
CC
×100
V
CC
R
Z
07493-029
Figure 29. Using Microconverter Voltage Setpoint Calibration and Monitoring
L
V
CC
ADN2873
ERSET
V
CC
RPAV
PAVREF
V
CC
MPD DATAP
IMODP
DATAN
IMODN
IBMON IMMON
ALSFAIL
IBIAS
V
CC
LASER
V
CC
VCC
GND GND
PAVCAP
GND
GND
NC
GND
GND
PAVSET 100Ω
CCBIAS
R
470Ω1kΩ
V
CC
CONTROL
IMOD
×100
V
CC
ERREF
V
REF
V
CC
R
Z
07493-030
Figure 30. Using Resistor Setpoint Calibration of Average Power and Extinction Ratio
ADN2873
Rev. 0 | Page 15 of 20
RESISTOR SETPOINT CALIBRATION
In resistor setpoint calibration, the PAVREF, ERREF, and RPAV
pins must all be tied to VCC. The average power and extinction
ratio can be set using the PAVSET and ERSET pins, respectively.
A resistor is placed between the pin and GND to set the current
flowing in each pin, as shown in Figure 30. The ADN2873
ensures that both PAVSET and ERSET are kept 1.23 V above
GND. The PAVSET and ERSET resistors are given by
SPAV
PAVSET RP
R×
=V2.1 (kΩ)
MOD
ERSET I
R100V2.1 ×
= (kΩ)
where:
PAV is the average power required (mW).RSP is the optical
responsivity (in mA/mW).
IMOD is the modulation current required (mA).
Power-On Sequence in Resistor Setpoint Mode
Note that during power-up, the ADN2873 starts an initial process
sequence that allows 25 ms before enabling the device alarms.
The resistors connected to the PAVSET and ERSET pins should
be stable within 20 ms after turning on the power supply. The
ADN2873 alarm may kick in and assert FAIL, provided the
PAVSET and ERSET resistors are stabilized 20 ms after turning
on the power supply.
IMPD MONITORING
IMPD monitoring can be implemented for voltage setpoint and
resistor setpoint as described in the following sections.
Voltage Setpoint
In voltage setpoint calibration, two methods can be used for
IMPD monitoring: measuring voltage at RPAV and measuring
IMPD across a sense resistor.
Method 1: Measuring Voltage at RPAV
The IMPD current is equal to the voltage at RPAV divided by the
value of RPAV (see Figure 31) as long as the laser is on and is
being controlled by the control loop. This method does not
provide a valid IMPD reading when the laser is in shutdown or fail
mode. A microconverter-buffered ADC input can be connected to
RPAV to make this measurement. No decoupling or filter capaci-
tors should be placed on the RPAV node because this can disturb
the control loop.
V
CC
PHOTODIODE
ADN2873
R
1kΩ
MICROCONVERTER
ADC
INPUT
PAVSET
RPAV
07493-031
Figure 31. Single Measurement of IMPD at RPAV in Voltage Setpoint Mode
Method 2: Measuring IMPD Across a Sense Resistor
The second method has the advantage of providing a valid IMPD
reading at all times but has the disadvantage of requiring a
differential measurement across a sense resistor directly in
series with the IMPD. As shown in Figure 32, a small resistor, Rx,
is placed in series with the IMPD. If the laser used in the design
has a pinout where the monitor photodiode cathode and the
lasers anode are not connected, a sense resistor, Rx, can be placed
in series with the photodiode cathode and VCC, as shown in
Figure 33. When choosing the value of the resistor, the user must
take into account the expected IMPD value in normal operation.
The resistor must be large enough to make a significant signal
for the buffered ADC to read, but small enough not to cause a
significant voltage reduction across the photodiode. The voltage
across the sense resistor should not exceed 250 mV when the
laser is in normal operation. It is recommended that a 10 pF
capacitor be placed in parallel with the sense resistor.
V
CC
LDPHOTODIODE
MICROCONVERTER
A
DC DIFFERENTIAL
INPUT
200Ω
Rx 10pF
PAVSET
ADN2873
0
7493-032
Figure 32. Differential Measurement of IMPD Across a Sense Resistor
V
CC
V
CC
LD
PHOTODIODE
MICROCONVERTER
ADC
INPUT
200Ω
Rx
PAVSET
ADN2873
0
7493-033
Figure 33. Single Measurement of IMPD Across a Sense Resistor
Resistor Setpoint
In resistor setpoint calibration, the current through the resistor
from PAVSET to GND is the IMPD current. The recommended
method for measuring the IMPD current is to place a small resis-
tor in series with the PAVSET resistor (or potentiometer) and
measure the voltage across this resistor, as shown in Figure 34. The
IMPD current is then equal to this voltage divided by the value of
resistor used. In resistor setpoint calibration, PAVSET is held to
1.2 V nominal; it is recommended that the sense resistor be
selected so that the voltage across the sense resistor does not
exceed 250 mV.
ADN2873
Rev. 0 | Page 16 of 20
V
CC
PHOTODIODE
ADN2873
PAVSET
R
MICROCONVERTER
ADC
INPUT
07493-034
Figure 34. Recommended Method of IMPD Measurement Across a
Sense Resistor in Resistor Setting Mode
LOOP BANDWIDTH SELECTION
To ensure that the ADN2873 control loop has sufficient
bandwidth, the average power loop capacitor (PAVCAP) is
calculated using the slope efficiency of the laser (watts/amps)
and the average power required.
For resistor setpoint control,
AV
P
LI
PAVCAP ××= −6
102.3 (Farad)
For voltage setpoint control,
AV
P
LI
PAVCAP ××= −6
1028.1 (Farad)
where:
LI is the typical slope efficiency at 25°C of a batch of lasers that
PAV is the average power required (mW).
are used in a design (mW/mA).
LI can be calculated as
MOD
I
P0P1
LI −
= (mW/mA)
where:
P1 is the optical power (mW) at the one level.
P0 is the optical power (mW) at the zero level.
The capacitor value equation is used to obtain a centered value
for the particular type of laser that is used in a design and an
average power setting. The laser LI can vary by a factor of 7
between different physical lasers of the same type and across
temperatures without the need to recalculate the PAVCAP value.
This capacitor is placed between the PAVCAP pin and ground.
It is important that the capacitor is a low leakage, multilayer
ceramic type with an insulation resistance greater than 100 GΩ
or a time constant of 1000 sec, whichever is less. Pick a standard
off-the-shelf capacitor value such that the actual capacitance is
within ±30% of the calculated value after the capacitor’s own
tolerance is taken into account.
POWER CONSUMPTION
The ADN2873 die temperature must be kept below 125°C. The
LFCSP has an exposed paddle, which should be connected so
that it is at the same potential as the ADN2873 GND pins.
Power consumption can be calculated as
ICC = ICC min + 0.3 IMOD
P = VCC × ICC + (IBIAS × VBIAS_PIN) + IMOD (VMODP_PIN + VMODN_PIN)/2
TDIE = TAMBIENT + θJA × P
Thus, the maximum combination of IBIAS + IMOD must be
calculated, where:
ICC min = 32 mA, the typical value of ICC provided in Table 1
with IBIAS = IMOD = 0.
TDIE is the die temperature.
VBIAS_PIN is the voltage at the IBIAS pin.
VMODP_PIN is the voltage at the IMODP pin.
VMODN_PIN is the voltage at the IMODN pin.
TAMBIENT is the ambient temperature.
AUTOMATIC LASER SHUTDOWN (TX_DISABLE)
ALS (TX_DISABLE) is an input that is used to shut down the
optical output of the transmitter. The ALS pin is pulled up
internally with a 6 kΩ resistor and conforms to SFP MSA
specifications. When ALS is logic high or when open, both the
bias and modulation currents are turned off. If an alarm has
been triggered and the bias and modulation currents are turned
off, ALS can be brought high and then low to clear the alarm.
BIAS AND MODULATION MONITOR CURRENTS
IBMON and IMMON are current-controlled current sources
that mirror a ratio of the bias and modulation current. The
monitor bias current, IBMON, and the monitor modulation
current, IMMON, should both be connected to ground through
a resistor to provide a voltage proportional to the bias current
and modulation current, respectively. When using a micro-
controller, the voltage developed across these resistors can be
connected to two of the ADC channels, making a digital
representation of the bias and modulation current available.
IBIAS PIN
The ADN2873 IBIAS pin has one on-chip, 800 pull-up resistor.
The current sink from this resistor is VIBIAS dependent.
8.0
IBIASCC
UP
VV
I
−
= (mA)
where VIBIAS is the voltage measured at the IBIAS pin after setup
of one laser bias current, IBIAS.
Usually, when set up, a maximum laser bias current of 100 mA
results in a VIBIAS to about 1.2 V. In a worst-case scenario, VCC =
3.6 V, VIBIAS = 1.2 V, and IUP (the current bypass through the 800
resistor) ≤ 3 mA.
This on-chip resistor damps out the low frequency oscillation
observed from some inexpensive lasers. If the on-chip resistance
does not provide enough damping, one external RZ (see Figure 35)
may be necessary.
ADN2873
Rev. 0 | Page 17 of 20
DATA INPUTS
Data inputs should be ac-coupled (10 nF capacitors are recom-
mended) and are terminated via a 100 Ω internal resistor between
the DATAP and DATAN pins. A high impedance circuit sets the
common-mode voltage and is designed to allow maximum
input voltage headroom over temperature. It is necessary to use
ac-coupling to eliminate the need for matching the common-mode
voltages of the data source and the ADN2873 data input pins.
LASER DIODE INTERFACING
Figure 35 shows the recommended circuit for interfacing the
ADN2873 to most TO-can or coax lasers. Uncooled DFB and
FP lasers typically have impedances of 5 Ω to 7 Ω and have axial
leads. The circuit shown works over the full range of data rates
from 155 Mbps to 3.3 Gbps, including multirate operation (without
changes to PAVCAP and ERCAP values); see Figure 23, Figure 24,
and Figure 25 for multirate performance examples. Coax lasers
have special characteristics that make them difficult to interface to.
They tend to have higher inductance and their impedance is not
well controlled. The circuit in Figure 35 operates by deliberately
misterminating the transmission line at the laser side while provid-
ing a very high quality matching network at the driver side.
The impedance of the driver side matching network is very flat
in the designed frequency range and enables multirate operation.
A series damping resistor should not be used.
L
BLM18HG601SN1D
C
100nF
R
P
24Ω
ADN2873
IBIAS
IMODP
V
CC
L (0.5nH)
R
24Ω
C
2.2pF
Tx LINE
30Ω
Tx LINE
30Ω
V
CC
V
CC
R
Z
07493-035
Figure 35. Recommended Interface for ADN2873 AC Coupling
The 30 Ω transmission line used is a compromise between the
drive current required and the total power consumed. Other
transmission line values can be used, with some modification of
the component values. In Figure 35, the R and C snubber values
24 Ω and 2.2 pF, respectively, represent a starting point and must
be tuned for the particular model of laser being used. RP, the
pull-up resistor, is in series with a very small (0.5 nH) inductor.
In some cases, an inductor is not required or can be accommo-
dated with deliberate parasitic inductance, such as a thin trace
or a via placed on the PC board.
Care should be taken to mount the laser as close as possible to
the PC board, minimizing the exposed lead length between the
laser can and the edge of the board. The axial lead of a coax
laser is very inductive (approximately 1 nH per mm). Long
exposed leads result in slower edge rates and reduced eye margin.
Recommended component layouts and Gerber files are available
by contacting sales at Analog Devices. Note that the circuit in
Figure 35 can supply up to 56 mA of modulation current to the
laser, sufficient for most lasers available today. Higher currents
can be accommodated by changing transmission lines and back-
match values; contact sales for recommendations. This interface
circuit is not recommended for butterfly-style lasers or other lasers
with 25 Ω characteristic impedance. Instead, a 25 Ω transmission
line and inductive (instead of resistive) pull-up is recommended.
The ADN2873 single-ended application shown in Figure 35 is
recommended for use up to 2.7 Gbps. From 2.7 Gbps to 4.25 Gbps,
a differential drive is recommended when driving VCSELs or lasers
that have slow fall times. Differential drive can be implemented by
adding a few extra components. A possible implementation is
shown in Figure 36. The bias and modulation currents that are
programmed into the ADN2873 need to be larger than the bias
and modulation current required at the laser due to the laser ac
coupling interface and because some modulation current flows
in the pull-up resistors, R1 and R2.
In Figure 35 and Figure 36, Resistor RZ is required to achieve
optimum eye quality. The recommended RZ value is approximately
500 Ω ~ 800 Ω.
The interface circuit needs a special modification to support
HDTV pathological test patterns. Contact sales at Analog Devices
for HDTV support.
L3 = 4.7nH
L4 = BLM18HG601SN1D
V
CC
L6 = BLM18HG601SN1D
SNUBBER SETTINGS: 40Ω AND 1.5pF, NOT OPTIMIZED, OPTIMIZATION SHOULD
CONSIDER THE PARASITIC OF THE INTERFACE CIRCUITRY.
V
CC
R1 = 15Ω
IBIAS
IMODN
IMODP
ADN2873
C1 = C2 = 100nF
20Ω TRANSMISSION LINES
R2 = 15Ω
R3 C3
SNUBBER LIGHT
TO-CAN/VCSEL
L1 = 0.5nH
L2 = 0.5nH
V
CC
R
Z
07493-036
Figure 36. Recommended Differential Drive Circuit
ADN2873
Rev. 0 | Page 18 of 20
ALARMS
The ADN2873 has a latched, active high monitoring alarm
(FAIL). The FAIL alarm output is open drain in conformance
with SFP MSA specification requirements.
The ADN2873 has a three-fold alarm system that covers
• Use of a bias current that is higher than expected, likely as
a result of laser aging
• Out-of-bounds average voltage at the monitor photodiode
(MPD) input, indicating an excessive amount of laser
power or a broken loop
• Undervoltage in the IBIAS node (laser diode cathode) that
would increase the laser power
The bias current alarm trip point is set by selecting the value
of resistor on the IBMON pin to GND. The alarm is triggered
when the voltage on the IBMON pin goes above 1.2 V. FAIL is
activated when the single-point alarms in Table 5 occur. The
circuit in Figure 37 can be used to indicate that FAIL has been
activated while allowing the bias and modulation currents to
remain on. The VBE of the transistor clamps the FAIL voltage to
below 1.3 V, disabling the automatic shutdown of bias and modula-
tion currents. If an alarm has triggered and FAIL is activated,
ALS can be brought high and then low to clear the alarm.
ADN2873
FAIL
R1
10kΩ
R2
330Ω
Q1
NPN
V
CC
LED
D1
07493-037
Figure 37. FAIL Indication Circuit
Table 5. ADN2873 Single-Point Alarms
Alarm Type Mnemonic Overvoltage or Short to VCC Condition Undervoltage or Short to GND Condition
Bias Current IBMON Alarm if >1.2 V typical (±10% tolerance) Ignore
MPD Current PAVSET Alarm if >2.0 V Alarm if <0. 4V
Crucial
Nodes
ERREF (the ERRREF designed is tied
to VCC in resistor setting mode)
Alarm if shorted to VCC (the alarm is
valid for voltage setting mode only)
Ignore
IBIAS Ignore Alarm if shorted to GND
Table 6. ADN2873 Response to Various Single-Point Faults in AC-Coupled Configuration (as shown in Figure 35 and Figure 36)
Pin Short to VCC Short to GND Open
PAVSET Fault state occurs Fault state occurs Fault state occurs
PAVREF Voltage mode: fault state occurs Fault state occurs Fault state occurs
Resistor mode: tied to VCC Circuit designed to tie to VCC in resistor
setting mode, so no open case
RPAV Voltage mode: fault state occurs Fault state occurs Voltage mode: fault state occurs
Resistor mode: tied to VCC Resistor mode: does not increase
average power
PAVCAP Fault state occurs Fault state occurs Fault state occurs
DATAP Does not increase laser average power Does not increase laser average power Does not increase laser average power
DATAN Does not increase laser average power Does not increase laser average power Does not increase laser average power
ALS Output currents shut off Normal currents Output currents shut off
ERSET Does not increase laser average power Does not increase laser average power Does not increase laser average power
IMMON Does not affect laser power Does not increase laser average power Does not increase laser average power
ERREF Voltage mode: fault state occurs Voltage mode: does not increase average
power
Does not increase laser average power
Resistor mode: tied to VCC Resistor mode: fault state occurs
IBMON Fault state occurs Does not increase laser average power Does not increase laser average power
FAIL Fault state occurs Does not increase laser average power Does not increase laser average power
IMODP Does not increase laser average power Does not increase laser average power Does not increase laser average power
IMODN Does not increase laser average power Does not increase laser average power Does not increase laser power
IBIAS Fault state occurs Fault state occurs Fault state occurs
ADN2873
Rev. 0 | Page 19 of 20
OUTLINE DIMENSIONS
*COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-2
EXCEPT FOR EXPOSED PAD DIMENSION
1
24
6
7
13
19
18
12
*2.45
2.30 SQ
2.15
0.60 MAX
0.50
0.40
0.30
0.30
0.23
0.18
2.50 REF
0.50
BSC
12° MAX
0.80 MAX
0.65 TYP
0.05 MAX
0.02 NOM
1.00
0.85
0.80
SEATING
PLANE
PIN 1
INDICATOR TOP
VIEW 3.75
BSC SQ
4.00
BSC SQ PIN 1
INDICATOR
0.60 MAX
COPLANARITY
0.08
0.20 REF
0.23 MIN
EXPOSED
PA D
(BOTTOMVIEW)
Figure 38. 24-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
4 mm × 4 mm Body, Very Thin Quad
(CP-24-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model Temperature Range Package Description Package Option
ADN2873ACPZ1 −40°C to +85°C 24-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-24-2
ADN2873ACPZ-RL1 −40°C to +85°C 24-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-24-2
ADN2873ACPZ-RL71 −40°C to +85°C 24-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-24-2
1 Z = RoHS Compliant Part.
ADN2873
Rev. 0 | Page 20 of 20
NOTES
©2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07493-0-6/08(0)
