1 Mbit / 2 Mbit (x8) Many-Time Programmable Flash SST27VF010 / SST27VF020 SST27VF010 / 0205.0V-Read 1Mb / 2Mb (x8) MTP flash memories EOL Data Sheet FEATURES: * Fast Byte-Program Operation - Byte-Program Time: 15 s (typical) - Chip Program Time: 2 seconds (typical) for SST27VF010 4 seconds (typical) for SST27VF020 * Electrical Erase Using Programmer - Does not require UV source - Chip-Erase Time: 100 ms (typical) * JEDEC Standard Byte-wide EPROM Pinouts * Packages Available - 32-lead PLCC - 32-lead TSOP (8mm x 14mm) - 32-pin PDIP * Organized as 128K x8 / 256K x8 * 2.7-3.6V Read Operation * Superior Reliability - Endurance: At least 1000 Cycles - Greater than 100 years Data Retention * Low Power Consumption - Active Current: 20 mA (typical) - Standby Current: 2 A (typical) * Fast Read Access Time - 70 ns (PLCC or TSOP) - 90 ns (PDIP) PRODUCT DESCRIPTION The SST27VF010/020 are 128K x8 / 256K x8 CMOS, Many-Time Programmable (MTP) low cost flash, manufactured with SST's proprietary, high-performance SuperFlash technology. The split-gate cell design and thick-oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. These MTP devices can be electrically erased and programmed at least 1000 times using an external programmer with a 12V power supply. They have to be erased prior to programming. These devices conform to JEDEC standard pinouts for byte-wide memories. Device Operation Featuring high performance Byte-Program, the SST27VF010/020 provide a Byte-Program time of 15 s. Designed, manufactured, and tested for a wide spectrum of applications, these devices are offered with an endurance of at least 1000 cycles. Data retention is rated at greater than 100 years. Read The SST27VF010/020 are suited for applications that require infrequent writes and low power nonvolatile storage. These devices will improve flexibility, efficiency, and performance while matching the low cost in nonvolatile applications that currently use UV-EPROMs, OTPs, and mask ROMs. To meet surface mount and conventional through hole requirements, the SST27VF010/020 are offered in 32-pin PDIP, 32-lead PLCC, and 32-lead TSOP packages. See Figures 1, 2, and 3 for pin assignments. (c)2009 Silicon Storage Technology, Inc. S71251-01-EOL 2/09 1 The SST27VF010/020 are a low cost flash solution that can be used to replace existing UV-EPROM, OTP, and mask ROM sockets. These devices are functionally (read and program) and pin compatible with industry standard EPROM products. In addition to EPROM functionality, these devices also support electrical Erase operation via an external programmer. They do not require a UV source to erase, and therefore the packages do not have a window. The Read operation of the SST27VF010/020 is controlled by CE# and OE#. Both CE# and OE# have to be low for the system to obtain data from the outputs. Once the address is stable, the address access time is equal to the delay from CE# to output (TCE). Data is available at the output after a delay of TOE from the falling edge of OE#, assuming that CE# pin has been low and the addresses have been stable for at least TCE-TOE. When the CE# pin is high, the chip is deselected and a typical standby current of 2 A is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either CE# or OE# is high. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. MTP is a trademark of Silicon Storage Technology, Inc. These specifications are subject to change without notice. http://store.iiic.cc/ 1 Mbit / 2 Mbit Many-Time Programmable Flash SST27VF010 / SST27VF020 EOL Data Sheet Byte-Program Operation pins are "don't care". The falling edge of CE# (PGM# for SST27VF010/020) will start the Chip-Erase operation. Once the chip has been erased, all bytes must be verified for FFH. Refer to Figure 9 for the flowchart. The SST27VF010/020 are programmed by using an external programmer. The programming mode for SST27VF010/020 is activated by asserting 11.4-12.0V on VPP pin, VDD = 2.7-3.6V, VIL on CE# pin, and VIH on OE# pin. These devices are programmed byte-by-byte with the desired data at the desired address using a single pulse (PGM# pin low for SST27VF010/020) of 15 s. Using the MTP programming algorithm, the Byte-Programming process continues byte-by-byte until the entire chip has been programmed. Product Identification Mode The Product Identification mode identifies the devices as the SST27VF010 or SST27VF020 and manufacturer as SST. This mode may be accessed by the hardware method. To activate this mode for SST27VF010/020, the programming equipment must force VH (11.4-12.6V) on address A9 with VPP pin at VDD (2.7-3.6V) or VSS. Two identifier bytes may then be sequenced from the device outputs by toggling address line A0. For details, see Table 3 for hardware operation. Chip-Erase Operation The only way to change a data from a "0" to "1" is by electrical erase that changes every bit in the device to "1". Unlike traditional EPROMs, which use UV light to do the ChipErase, the SST27VF010/020 uses an electrical Chip-Erase operation. This saves a significant amount of time (about 30 minutes for each Erase operation). The entire chip can be erased in a single pulse of 100 ms (PGM# pin for SST27VF010/020). In order to activate the Erase mode for SST27VF010/020, the 11.4-12.6V is applied to the A9 pin, 11.4-12.0V is applied to the VPP pin, VDD = 2.7-3.6V, VIL on CE# pin, and VIH on OE# pin. All other address and data TABLE 1: PRODUCT IDENTIFICATION Manufacturer's ID Address Data 0000H BFH Device ID SST27VF010 0001H A9H SST27VF020 0001H AAH T1.0 1251 FUNCTIONAL BLOCK DIAGRAM OF THE SST27VF010/020 X-Decoder AMS - A0 SuperFlash Memory Address Buffer Y-Decoder CE# OE# A9 I/O Buffers Control Logic VPP DQ7 - DQ0 PGM# AMS = A17 for SST27VF020, A16 for SST27VF010 1251 B1.0 (c)2009 Silicon Storage Technology, Inc. S71251-01-EOL 2 http://store.iiic.cc/ 2/09 1 Mbit / 2 Mbit Many-Time Programmable Flash SST27VF010 / SST27VF020 A12 A15 A16 VPP VDD PGM# A17 A12 A15 A16 VPP VDD PGM# NC SST27VF010 SST27VF020 EOL Data Sheet 4 3 2 1 32 31 30 29 SST27VF010/020 SST27VF010/020 A7 5 A6 28 A13 A5 7 27 A8 A4 8 26 A9 A3 9 25 A11 A2 10 24 OE# A1 11 23 A10 A0 12 22 CE# DQ0 13 21 14 15 16 17 18 19 20 DQ7 32-lead PLCC Top View DQ6 DQ5 DQ4 DQ3 VSS DQ2 1251 32-plcc P1.0 DQ1 SST27VF010/020 A14 6 FIGURE 1: PIN ASSIGNMENTS FOR 32-LEAD PLCC SST27VF020 SST27VF010 A11 A9 A8 A13 A14 A17 PGM# VDD VPP A16 A15 A12 A7 A6 A5 A4 A11 A9 A8 A13 A14 NC PGM# VDD VPP A16 A15 A12 A7 A6 A5 A4 SST27VF010/020 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Standard Pinout Top View Die Up 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3 1251 32-tsop P2.0 FIGURE 2: PIN ASSIGNMENTS FOR 32-LEAD TSOP (8MM X 14MM) (c)2009 Silicon Storage Technology, Inc. S71251-01-EOL 3 http://store.iiic.cc/ 2/09 1 Mbit / 2 Mbit Many-Time Programmable Flash SST27VF010 / SST27VF020 EOL Data Sheet SST27SV010/020 VPP A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS SST27VF010 SST27VF020 1 2 3 4 5 32-pin 6 PDIP 7 8 Top View 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VDD PGM# NC A14 A13 A8 A9 A11 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VDD PGM# A17 A14 A13 A8 A9 A11 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 1251 32-pdip P3.0 FIGURE 3: PIN ASSIGNMENTS FOR 32-PIN PDIP (c)2009 Silicon Storage Technology, Inc. S71251-01-EOL 4 http://store.iiic.cc/ 2/09 1 Mbit / 2 Mbit Many-Time Programmable Flash SST27VF010 / SST27VF020 EOL Data Sheet TABLE 2: PIN DESCRIPTION Symbol Pin Name Functions AMS1-A0 Address Inputs To provide memory addresses DQ7-DQ0 Data Input/output To output data during Read cycles and receive input data during Program cycles The outputs are in tri-state when OE# or CE# is high. CE# Chip Enable To activate the device when CE# is low OE# Output Enable To gate the data output buffers during Read operation VPP Power Supply for Program or Erase High voltage pin during Chip-Erase and programming operation 11.4-12.0V VDD Power Supply To provide 3.0V supply (2.7-3.6V) VSS Ground NC No Connection Unconnected pins. T2.0 1251 1. AMS = Most significant address AMS = A16 for SST27VF010 and A17 for SST27VF020 TABLE 3: OPERATION MODES SELECTION Mode CE# OE# PGM# A9 VPP DQ Address Read VIL VIL X1 AIN VDD or VSS DOUT AIN Output Disable VIL VIH X X Program VIL VIH VIL AIN VDD or VSS High Z AIN VPPH DIN AIN Standby VIH X X X VDD or VSS High Z X Chip-Erase VIL VIH VIL VH VPPH High Z X Program/Erase Inhibit VIH X X X VPPH High Z X Product Identification VIL VIL X VH VDD or VSS Manufacturer's ID (BFH) Device ID2 AMS3 - A1=VIL, A0=VIL AMS3 - A1=VIL, A0=VIH T3.0 1251 1. X can be VIL or VIH, but no other value. 2. Device ID = A9H for SST27VF010 and AAH for SST27VF020 3. AMS = Most significant address AMS = A16 for SST27VF010 and A17 for SST27VF020 Note: VPPH = 11.4-12.0V, VH = 11.4-12.6V (c)2009 Silicon Storage Technology, Inc. S71251-01-EOL 5 http://store.iiic.cc/ 2/09 1 Mbit / 2 Mbit Many-Time Programmable Flash SST27VF010 / SST27VF020 EOL Data Sheet Absolute Maximum Stress Ratings (Applied conditions greater than those listed under "Absolute Maximum Stress Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55C to +125C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to +150C D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0V to VDD+2.0V Voltage on A9 and VPP Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 13.2V Package Power Dissipation Capability (Ta = 25C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W Through Hold Lead Soldering Temperature (10 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300C Surface Mount Lead Soldering Temperature (3 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240C Output Short Circuit Current1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA 1. Outputs shorted for no more than one second. No more than one output shorted at a time. OPERATING RANGE Range Commercial AC CONDITIONS OF TEST Ambient Temp VDD VPP 0C to +70C 2.7-3.6V 11.4-12.0V Input Rise/Fall Time . . . . . . . . . . . 5 ns Output Load . . . . . . . . . . . . . . . . . CL = 30 pF See Figures 7 and 8 (c)2009 Silicon Storage Technology, Inc. S71251-01-EOL 6 http://store.iiic.cc/ 2/09 1 Mbit / 2 Mbit Many-Time Programmable Flash SST27VF010 / SST27VF020 EOL Data Sheet TABLE 4: READ MODE DC OPERATING CHARACTERISTICS VDD = 2.7-3.6V, VPP=VDD OR VSS (Ta = 0C to +70C (Commercial)) Limits Symbol Parameter IDD VDD Read Current IPPR VPP Read Current Min Max Units Test Conditions Address input=VILT/VIHT at f=1/TRC Min VDD=VDD Max 15 mA CE#=OE#=VIL, all I/Os open Address input=VILT/VIHT at f=1/TRC Min VDD=VDD Max, VPP=VDD 100 A CE#=OE#=VIL, all I/Os open ISB Standby VDD Current 15 A CE#=VDD-0.3, VDD=VDD Max ILI Input Leakage Current 1 A VIN=GND to VDD, VDD=VDD Max ILO Output Leakage Current 10 A VOUT=GND to VDD, VDD=VDD Max VIL Input Low Voltage 0.8 V VDD=VDD Min VIH Input High Voltage 0.7VDD V VDD=VDD Max VIHC Input High Voltage (CMOS) VDD-0.3 V VDD=VDD Max V IOL=100 A, VDD=VDD Min V IOH=-100 A, VDD=VDD Min A CE#=OE#=VIL, A9=VH Max VOL Output Low Voltage VOH Output High Voltage IH Supervoltage Current for A9 0.2 VDD-0.3 200 T4.0 1251 TABLE 5: PROGRAM/ERASE DC OPERATING CHARACTERISTICS VDD = 2.7-3.6V, VPP = VPPH (Ta=25C5C) Limits Symbol Parameter Min Max Units Test Conditions IDD VDD Erase or Program Current 20 mA CE#=PGM#=VIL, OE#=VIH, VPP=11.4-12.0V, VDD=VDD Max IPP VPP Erase or Program Current 3 mA CE#=PGM#=VIL, OE#=VIH, VPP=11.4-12.0V, VDD=VDD Max ILI Input Leakage Current 1 A VIN =GND to VDD, VDD=VDD Max ILO Output Leakage Current 10 A VOUT =GND to VDD, VDD=VDD Max VH Supervoltage for A9 IH Supervoltage Current for A9 VPPH High Voltage for VPP Pin 11.4 12.6 V CE#=OE#=VIL, 200 A CE#=OE#=VIL, A9=VH Max 11.4 12.0 V T5.0 1251 (c)2009 Silicon Storage Technology, Inc. S71251-01-EOL 7 http://store.iiic.cc/ 2/09 1 Mbit / 2 Mbit Many-Time Programmable Flash SST27VF010 / SST27VF020 EOL Data Sheet TABLE 6: RECOMMENDED SYSTEM POWER-UP TIMINGS Symbol Parameter Minimum Units TPU-READ1 Power-up to Read Operation 100 s Power-up to Write Operation 100 s TPU-WRITE 1 T6.0 1251 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 7: CAPACITANCE (Ta = 25C, f=1 Mhz, other pins open) Parameter Description Test Condition Maximum CI/O1 I/O Pin Capacitance VI/O = 0V 12 pF Input Capacitance VIN = 0V 6 pF CIN 1 T7.0 1251 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 8: RELIABILITY CHARACTERISTICS Symbol NEND 1 Parameter Minimum Specification Units Test Method Endurance 1000 Cycles JEDEC Standard A117 TDR1 Data Retention 100 Years JEDEC Standard A103 ILTH1 Latch Up 100 mA JEDEC Standard 78 T8.0 1251 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. (c)2009 Silicon Storage Technology, Inc. S71251-01-EOL 8 http://store.iiic.cc/ 2/09 1 Mbit / 2 Mbit Many-Time Programmable Flash SST27VF010 / SST27VF020 EOL Data Sheet AC CHARACTERISTICS TABLE 9: READ CYCLE TIMING PARAMETERS VDD = 2.7-3.6V (Ta = 0C to +70C (Commercial)) SST27VF010-70 SST27VF020-70 Min Max SST27VF010-90 SST27VF020-90 Symbol Parameter TRC Read Cycle Time TCE Chip Enable Access Time 70 90 ns TAA Address Access Time 70 90 ns TOE Output Enable Access Time 35 45 ns TCLZ1 TOLZ1 TCHZ1 TOHZ1 TOH1 CE# Low to Active Output 0 0 ns OE# Low to Active Output 0 0 ns 70 Min Max Units 90 ns CE# High to High-Z Output 25 30 ns OE# High to High-Z Output 25 30 ns Output Hold from Address Change 0 0 ns T9.0 1251 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 10: PROGRAM/ERASE CYCLE TIMING PARAMETERS (Ta = 25C5C) Symbol TCES TCEH TAS TAH TPRT TVPS TVPH TPW TEW TDS TDH TVR TART TA9S TA9H Parameter CE# Setup Time CE# Hold Time Address Setup Time Address Hold Time VPP Pulse Rise Time VPP Setup Time VPP Hold Time PGM# Program Pulse Width PGM# Erase Pulse Width Data Setup Time Data Hold Time A9 Recovery Time for Erase A9 Rise Time to 12V during Erase A9 Setup Time during Erase A9 Hold Time during Erase Min 1 1 1 1 50 1 1 15 100 1 1 1 50 1 1 Max 25 200 Units s s s s ns s s s ms s s s ns s s T10.0 1251 (c)2009 Silicon Storage Technology, Inc. S71251-01-EOL 9 http://store.iiic.cc/ 2/09 1 Mbit / 2 Mbit Many-Time Programmable Flash SST27VF010 / SST27VF020 FULL or HALF PAGE (bottom) EOL Data Sheet FIGURE TITLE (BOTTOM): ____________________________________________________________ FIGURE 4: READ CYCLE TIMING DIAGRAM ADDRESS (EXCEPT A9) TCEH CE# OE# VIH DQ7-0 VPPH VPP VDD VSS VPPH A9 TVPH TPRT TVPS TVR TA9S VIH VIL TART TEW TA9H PGM# TCES 1251 F05.0 FIGURE 5: CHIP-ERASE TIMING DIAGRAM (c)2009 Silicon Storage Technology, Inc. S71251-01-EOL 10 http://store.iiic.cc/ 2/09 1 Mbit / 2 Mbit Many-Time Programmable Flash SST27VF010 / SST27VF020 EOL Data Sheet ADDRESS ADDRESS VALID TAS TAH CE# TCEH OE# VIH TDS DQ7-0 HIGH-Z TDH DATA VALID VDD VPP VPPH VSS TPRT TVPS TPW TVPH PGM# TCES 1251 F06.0 FIGURE 6: BYTE-PROGRAM TIMING DIAGRAM (c)2009 Silicon Storage Technology, Inc. S71251-01-EOL 11 http://store.iiic.cc/ 2/09 1 Mbit / 2 Mbit Many-Time Programmable Flash SST27VF010 / SST27VF020 EOL Data Sheet VIHT INPUT VIT REFERENCE POINTS VOT OUTPUT VILT 1251 F07.0 AC test inputs are driven at VIHT (0.9 VDD) for a logic "1" and VILT (0.1 VDD) for a logic "0". Measurement reference points for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input rise and fall times (10% 90%) are <5 ns. Note: VIT - VINPUTTest VOT - VOUTPUT Test VIHT - VINPUT HIGH Test VILT - VINPUT LOW Test FIGURE 7: AC INPUT/OUTPUT REFERENCE WAVEFORMS VDD TO TESTER RL HIGH TO DUT CL RL LOW 1251 F08.0 FIGURE 8: A TEST LOAD EXAMPLE (c)2009 Silicon Storage Technology, Inc. S71251-01-EOL 12 http://store.iiic.cc/ 2/09 1 Mbit / 2 Mbit Many-Time Programmable Flash SST27VF010 / SST27VF020 EOL Data Sheet Start A9 = VH, VPP = VPPH CE# = VIL, OE# = VIH Erase 100ms pulse (PGM# = VIL) PGM# = VIH A9 = VIL or VIH Wait A9 Recovery Time Read Device Compare all bytes to FFH No Yes Device Passed Device Failed 1251 F09.0 FIGURE 9: CHIP-ERASE ALGORITHM (c)2009 Silicon Storage Technology, Inc. S71251-01-EOL 13 http://store.iiic.cc/ 2/09 1 Mbit / 2 Mbit Many-Time Programmable Flash SST27VF010 / SST27VF020 EOL Data Sheet Start Erase* VPP = VPPH Address = First Location CE# = VIL, OE# = VIH Program 15 s pulse (PGM# = VIL) Increment Address Last Address? No Yes Read Device Compare all bytes to original data No Yes Device Passed Device Failed 1251 F10.0 * See Figure 9 FIGURE 10: BYTE-PROGRAM ALGORITHM (c)2009 Silicon Storage Technology, Inc. S71251-01-EOL 14 http://store.iiic.cc/ 2/09 1 Mbit / 2 Mbit Many-Time Programmable Flash SST27VF010 / SST27VF020 EOL Data Sheet PRODUCT ORDERING INFORMATION Device SST27VFxxx Speed - XXX Suffix1 - XX Suffix2 - XX X Environmental Attribute E = non-Pb Package Modifier H = 32 pins or leads Package Type N = PLCC P = PDIP W = TSOP (type 1, die up, 8mm x 14mm) Temperature Range C = Commercial = 0C to +70C Minimum Endurance 3 = 1,000 cycles Read Access Speed 70 = 70 ns 90 = 90 ns Device Density - x8 Organization 020 = 2 Mbit 010 = 1 Mbit Voltage Range V = 2.7-3.6V Product Series 27 = Many-Time Programmable Flash Valid combinations for SST27VF010 SST27VF010-70-3C-NH SST27VF010-70-3C-WH SST27VF010-90-3C-PH SST27VF010-70-3C-NHE SST27VF010-70-3C-WHE SST27VF010-90-3C-PHE Valid combinations for SST27VF020 SST27VF020-70-3C-NH SST27VF020-70-3C-NHE SST27VF020-70-3C-WH SST27VF020-70-3C-WHE SST27VF020-90-3C-PH SST27VF020-90-3C-PHE Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations. (c)2009 Silicon Storage Technology, Inc. S71251-01-EOL 15 http://store.iiic.cc/ 2/09 1 Mbit / 2 Mbit Many-Time Programmable Flash SST27VF010 / SST27VF020 EOL Data Sheet PACKAGING DIAGRAMS TOP VIEW Optional Pin #1 Identifier .048 .042 SIDE VIEW .495 .485 .453 .447 2 1 32 .112 .106 .020 R. MAX. .029 x 30 .023 .040 R. .030 .042 .048 .595 .553 .585 .547 BOTTOM VIEW .021 .013 .400 .530 BSC .490 .032 .026 .050 BSC .015 Min. .095 .075 .050 BSC .140 .125 .032 .026 Note: 1. Complies with JEDEC publication 95 MS-016 AE dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in inches (max/min). 3. Dimensions do not include mold flash. Maximum allowable mold flash is .008 inches. 4. Coplanarity: 4 mils. 32-plcc-NH-3 32-LEAD PLASTIC LEAD CHIP CARRIER (PLCC) SST PACKAGE CODE: NH (c)2009 Silicon Storage Technology, Inc. S71251-01-EOL 16 http://store.iiic.cc/ 2/09 1 Mbit / 2 Mbit Many-Time Programmable Flash SST27VF010 / SST27VF020 EOL Data Sheet 1.05 0.95 Pin # 1 Identifier 0.50 BSC 8.10 7.90 0.27 0.17 0.15 0.05 12.50 12.30 DETAIL 1.20 max. 0.70 0.50 14.20 13.80 0- 5 0.70 0.50 Note: 1. Complies with JEDEC publication 95 MO-142 BA dimensions, although some dimensions may be more stringent. 1mm 2. All linear dimensions are in millimeters (max/min). 3. Coplanarity: 0.1 mm 4. Maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads. 32-tsop-WH-7 32-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) 8MM X 14MM SST PACKAGE CODE: WH (c)2009 Silicon Storage Technology, Inc. S71251-01-EOL 17 http://store.iiic.cc/ 2/09 1 Mbit / 2 Mbit Many-Time Programmable Flash SST27VF010 / SST27VF020 EOL Data Sheet 32 CL Pin #1 Identifier 1 1.655 1.645 .075 .065 7 4 PLCS. Base Plane Seating Plane .625 .600 .550 .530 .200 .170 .050 .015 .080 .070 .065 .045 .022 .016 .100 BSC .150 .120 0 15 .012 .008 .600 BSC Note: 1. Complies with JEDEC publication 95 MO-015 AP dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in inches (max/min). 3. Dimensions do not include mold flash. Maximum allowable mold flash is .010 inches. 32-pdip-PH-3 32-PIN PLASTIC DUAL IN-LINE PINS (PDIP) SST PACKAGE CODE: PH Revision History Number Description Date 00 * Initial Release Dec 2003 01 * End of life all valid combinations in this data sheet Feb 2009 Silicon Storage Technology, Inc. * 1171 Sonora Court * Sunnyvale, CA 94086 * Telephone 408-735-9110 * Fax 408-735-9036 www.SuperFlash.com or www.sst.com (c)2009 Silicon Storage Technology, Inc. S71251-01-EOL 18 http://store.iiic.cc/ 2/09