ICS843011CGT - Integrated Circuit Systems, Inc.

843011CG www.icst.com/products/hiperclocks.html REV. A JANUARY 25, 2006

Integrated

Circuit

Systems, Inc.

ICS843011C

FEMTOCLOCKS™ C RYSTAL-TO-

3.3V LVPECL CLOCK GENERATOR

PRELIMINARY

GENERAL DESCRIPTION

The ICS843011C is a Fibre Channel Clock

Generator and a member of the HiPerClocksTM

family of high performance devices from ICS.

The ICS843011C uses a 26.5625MHz crystal to

synthesize 106.25MHz or a 25MHz crystal to

synthesize 100MHz. The ICS843011C has excellent <1ps

phase jitter performance, over the 637kHz – 10MHz

integration range. The ICS843011C is packaged in a small

8-pin TSSOP, making it ideal for use in systems with limit-

ed board space.

FEATURES

•One differential 3.3V LVPECL output

•Crystal oscillator interface designed for 26.5625MHz

18pF parallel resonant crystal

•Output frequency: 106.25MHz or 100MHz

•VCO range: 560MHz - 680MHz

•RMS phase jitter @ 100MHz, using a 25MHz crystal

(637kHz - 10MHz): 0.29ps (typical)

•3.3V operating supply

•-40°C to 85°C ambient operating temperature

•Available in both standard and lead-free RoHS compliant

packages

HiPerClockS™

ICS

FREQUENCY TABLE

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5265.6252.601

52001

ICS843011C

8-Lead TSSOP

4.40mm x 3.0mm x 0.925mm package body

G Package

Top View

VCCA

VEE

XTAL_OUT

XTAL_IN

VCC

OSC Phase

Detector

VCO

637.5MHz w/

26.5625MHz Ref.

M = ÷24 (fixed)

÷6

BLOCK DIAGRAM PIN ASSIGNMENT

XTAL_IN

XTAL_OUT

The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on

initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications

without notice.

843011CG www.icst.com/products/hiperclocks.html REV. A JANUARY 25, 2006

Integrated

Circuit

Systems, Inc.

ICS843011C

FEMTOCLOCKS™ C RYSTAL-TO-

3.3V LVPECL CLOCK GENERATOR

PRELIMINARY

TABLE 2. PIN CHARACTERISTICS

TABLE 1. PIN DESCRIPTIONS

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843011CG www.icst.com/products/hiperclocks.html REV. A JANUARY 25, 2006

Integrated

Circuit

Systems, Inc.

ICS843011C

FEMTOCLOCKS™ C RYSTAL-TO-

3.3V LVPECL CLOCK GENERATOR

PRELIMINARY

TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.3V±5%, TA = -40°C TO 85°C

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ACC

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ACC

tnerruCylppuSgolanAInidedulcni

01Am

tnerruCylppuSrewoP 86Am

TABLE 3B. LVPECL DC CHARACTERISTICS, VCC = 3.3V±5%, TA = -40°C TO 85°C

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0.2-V

7.1-V

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TABLE 5. AC CHARACTERISTICS, VCC = 3.3V±5%, TA = -40°C TO 85°C

TABLE 4. CRYSTAL CHARACTERISTICS

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ABSOLUTE MAXIMUM RATINGS

Supply Voltage, V

CC 4.6V

Inputs, VI-0.5V to VCC + 0.5V

Outputs, IO

Continuous Current 50mA

Surge Current 100mA

Package Thermal Impedance, θJA 101.7°C/W (0 mps)

Storage Temperature, T

STG -65°C to 150°C

NOTE: Stresses beyond those listed under Absolute

Maximum Ratings may cause permanent damage to the

device. These ratings are stress specifications only. Functional

operation of product at these conditions or any conditions be-

yond those listed in the DC Characteristics or AC Character-

istics is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect product reliability.

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zHM01-zHk736:egnaRnoitargetnI 92.0sp

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843011CG www.icst.com/products/hiperclocks.html REV. A JANUARY 25, 2006

Integrated

Circuit

Systems, Inc.

ICS843011C

FEMTOCLOCKS™ C RYSTAL-TO-

3.3V LVPECL CLOCK GENERATOR

PRELIMINARY

PARAMETER MEASUREMENT INFORMATION

OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD OUTPUT RISE/FALL TIME

3.3V OUTPUT LOAD AC TEST CIRCUIT

SCOPE

nQx

LVPECL

-1.3V ± 0.165V

Clock

Outputs 20%

80% 80%

20%

SWING

PERIOD

odc = x 100%

VEE

VCC

RMS PHASE JITTER

Phase Noise Mas

Offset Frequency

Phase Noise Plot

RMS Jitter = Area Under the Masked Phase Noise Plot

Noise Power

843011CG www.icst.com/products/hiperclocks.html REV. A JANUARY 25, 2006

Integrated

Circuit

Systems, Inc.

ICS843011C

FEMTOCLOCKS™ C RYSTAL-TO-

3.3V LVPECL CLOCK GENERATOR

PRELIMINARY

APPLICATION INFORMATION

Figure 2. CRYSTAL INPUt INTERFACE

CRYSTAL INPUT INTERFACE

The ICS843011C has been characterized with 18pF parallel

resonant crystals. The capacitor values, C1 and C2, shown in

Figure 2 below were determined using a 26.5625MHz, 18pF

parallel resonant crystal and were chosen to minimize the

ppm error. The optimum C1 and C2 values can be slightly

adjusted for different board layouts.

As in any high speed analog circuitry, the power supply pins

are vulnerable to random noise. The ICS843011C provides

separate power supplies to isolate any high switching

noise from the outputs to the internal PLL. VCC and VCCA

should be individually connected to the power supply

plane through vias, and bypass capacitors should be

used for each pin. To achieve optimum jitter performance,

power supply isolation is required. Figure 1 illustrates how

a 10Ω resistor along with a 10μF and a .01μF bypass

capacitor should be connected to each VCCA pin.

POWER SUPPLY FILTERING T ECHNIQUES

FIGURE 1. POWER SUPPLY FILTERING

10Ω

VCCA

10μF

.01μF

3.3V

.01μF

VCC

33p

18pF Parallel Crystal

22p

XTAL_OUT

XTAL_IN

843011CG www.icst.com/products/hiperclocks.html REV. A JANUARY 25, 2006

Integrated

Circuit

Systems, Inc.

ICS843011C

FEMTOCLOCKS™ C RYSTAL-TO-

3.3V LVPECL CLOCK GENERATOR

PRELIMINARY

APPLICATION SCHEMATIC

Figure 3A shows a schematic example of the ICS843011C.

An example of LVEPCL termination is shown in this sche-

matic. Additional LVPECL termination approaches are shown

in the LVPECL Termination Application Note. In this example,

an 18 pF parallel resonant 26.5625MHz crystal is used for

generating 106.25MHz output frequency. The C1 = 27pF and

C2 = 33pF are recommended for frequency accuracy. For

different board layout, the C1 and C2 values may be slightly

adjusted for optimizing frequency accuracy.

FIGURE 3A. ICS843011C SCHEMATIC EXAMPLE

FIGURE 3B. ICS843011 PC BOARD LAYOUT EXAMPLE

PC BOARD LAYOUT EXAMPLE

Figure 3B shows an example of ICS843011C P.C. board lay-

out. The crystal X1 footprint shown in this example allows

installation of either surface mount HC49S or through-hole

HC49 package. The footprints of other components in this

example are listed in the Table 6. There should be at least one

decoupling capacitor per power pin. The decoupling capaci-

tors should be located as close as possible to the power pins.

The layout assumes that the board has clean analog power

ground plane.

TABLE 6. FOOTPRINT T ABLE

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2C,1C2040

3C5080

5C,4C3060

2R3060

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.elpmaxetuoyalsihtninwohssezis

Zo = 50 Ohm

0.1u

33pF

XTAL_IN

18pF

VCCA

133

Zo = 50 Ohm

0.1u

Zo = 50 Ohm

82.5

Optional

Y-Termination

XTAL_OUT

26.5625MHz

Zo = 50 Ohm

VCC

27pF

843011C

VCCA

VEE

XT AL _ O U T

XT AL _ I N

VCC

82.5

10uF

VCC

133

843011CG www.icst.com/products/hiperclocks.html REV. A JANUARY 25, 2006

Integrated

Circuit

Systems, Inc.

ICS843011C

FEMTOCLOCKS™ C RYSTAL-TO-

3.3V LVPECL CLOCK GENERATOR

PRELIMINARY

POWER CONSIDERATIONS

This section provides information on power dissipation and junction temperature for the ICS843011C.

Equations and example calculations are also provided.

1. P ower Dissipation.

The total power dissipation for the ICS843011C is the sum of the core power plus the power dissipated in the load(s).

The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.

NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.

•Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 68mA = 235.6mW

•Power (outputs)MAX = 30mW/Loaded Output pair

Total Power_MAX (3.465V, with all outputs switching) = 235.6mW + 30mW = 265.6mW

2. Junction Temperature.

Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the

device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.

The equation for Tj is as follows: Tj = θJA * Pd_total + TA

Tj = Junction Temperature

θJA = Junction-to-Ambient Thermal Resistance

Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)

TA = Ambient Temperature

In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA

must be used. Assuming a

moderate air flow of 1 meter per second and a multi-layer board, the appropriate value is 90.5°C/W per Table 7 below.

Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:

85°C + 0.266W * 90.5°C/W = 109.1°C. This is well below the limit of 125°C.

This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,

and the type of board (single layer or multi-layer).

TABLE 7. THERMAL RESISTANCE θθ

θθ

θJA FOR 8-PIN TSSOP, FORCED CONVECTION

θθ

θJA by Velocity (Meters per Second)

0 1 2.5

Multi-Layer PCB, JEDEC Standard Test Boards 101.7°C/W 90.5°C/W 89.8°C/W

843011CG www.icst.com/products/hiperclocks.html REV. A JANUARY 25, 2006

Integrated

Circuit

Systems, Inc.

ICS843011C

FEMTOCLOCKS™ C RYSTAL-TO-

3.3V LVPECL CLOCK GENERATOR

PRELIMINARY

3. Calculations and Equations.

The purpose of this section is to derive the power dissipated into the load.

LVPECL output driver circuit and termination are shown in Figure 4.

To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination

voltage of V

- 2V.

• For logic high, VOUT = VOH_MAX = VCC_MAX – 0.9V

(VCCO_MAX - VOH_MAX

) = 0.9V

• For logic low, VOUT = VOL_MAX = VCC_MAX

– 1.7V

(VCCO_MAX - VOL_MAX

) = 1.7V

Pd_H is power dissipation when the output drives high.

Pd_L is the power dissipation when the output drives low.

Pd_H = [(VOH_MAX

– (VCC_MAX

- 2V))/R

] * (VCC_MAX

- VOH_MAX) = [(2V - (V

CC_MAX - VOH_MAX

))/R

] * (VCC_MAX

- VOH_MAX) =

[(2V - 0.9V)/50Ω] * 0.9V = 19.8mW

Pd_L = [(VOL_MAX

– (VCC_MAX

- 2V))/R

] * (VCC_MAX

- VOL_MAX) = [(2V - (V

CC_MAX - VOL_MAX

))/R

] * (VCC_MAX

- VOL_MAX) =

[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW

Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW

FIGURE 4. LVPECL DRIVER CIRCUIT AND T ERMINATION

VOUT

VCC

VCC - 2V

843011CG www.icst.com/products/hiperclocks.html REV. A JANUARY 25, 2006

Integrated

Circuit

Systems, Inc.

ICS843011C

FEMTOCLOCKS™ C RYSTAL-TO-

3.3V LVPECL CLOCK GENERATOR

PRELIMINARY

RELIABILITY INFORMATION

TRANSISTOR COUNT

The transistor count for ICS843011C is: 2436

TABLE 8. θJAVS. AIR FLOW TABLE FOR 8 LEAD TSSOP

θθ

θJA by Velocity (Meters per Second)

0 1 2.5

Multi-Layer PCB, JEDEC Standard Test Boards 101.7°C/W 90.5°C/W 89.8°C/W

843011CG www.icst.com/products/hiperclocks.html REV. A JANUARY 25, 2006

Integrated

Circuit

Systems, Inc.

ICS843011C

FEMTOCLOCKS™ C RYSTAL-TO-

3.3V LVPECL CLOCK GENERATOR

PRELIMINARY

PACKAGE OUTLINE - G SUFFIX FOR 8 LEAD TSSOP

TABLE 9. PACKAGE DIMENSIONS

Reference Document: JEDEC Publication 95, MO-153

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2A08.050.1

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ECISAB04.6

1E03.405.4

eCISAB56.0

L54

.057.0

α°0°8

aaa--01.0

843011CG www.icst.com/products/hiperclocks.html REV. A JANUARY 25, 2006

Integrated

Circuit

Systems, Inc.

ICS843011C

FEMTOCLOCKS™ C RYSTAL-TO-

3.3V LVPECL CLOCK GENERATOR

PRELIMINARY

TABLE 10. ORDERING INFORMATION

While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use

or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use

in normal commercial and industrial applications. Any other applications such as those requiring ehigh reliability or other extraordinary environmental requirements are not

recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product

for use in life support devices or critical medical instruments.

The aforementioned trademarks, HiPerClockS and FemtoClocks are trademarks of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.

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