Ultralow Power, Low Distortion, Fully Differential ADC Drivers ADA4940-1/ADA4940-2 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAMS 13 -VS 14 -VS 16 -VS -FB 1 12 DISABLE +IN 2 11 -OUT -IN 3 10 +OUT 9 19 -OUT1 21 -VS1 20 DISABLE1 24 +IN1 23 -FB1 22 -VS1 Figure 1. ADA4940-1 18 +OUT1 17 VOCM1 16 -VS2 -IN1 1 +FB1 2 +VS1 3 ADA4940-2 +VS1 4 15 -VS2 NOTES 1. CONNECT THE EXPOSED PAD TO -VS OR GROUND. 07429-202 +OUT2 12 +VS2 10 13 -OUT2 VOCM2 11 +IN2 6 -IN2 7 14 DISABLE2 +FB2 8 +VS2 9 -FB2 5 GENERAL DESCRIPTION With the ADA4940-1/ADA4940-2, differential gain configurations are easily realized with a simple external feedback network of four resistors determining the closed-loop gain of the amplifier. The ADA4940-1/ADA4940-2 are fabricated using Analog Devices, Inc., SiGe complementary bipolar process, enabling them to achieve very low levels of distortion with an input voltage noise of only 3.9 nV/Hz. The low dc offset and excellent dynamic performance of the ADA4940-1/ADA4940-2 make them well suited for a variety of data acquisition and signal processing applications. 08452-001 NOTES 1. CONNECT THE EXPOSED PAD TO -VS OR GROUND. Low power PulSAR(R)/SAR ADC drivers Single-ended-to-differential conversion Differential buffers Line drivers Medical imaging Industrial process controls Portable electronics The ADA4940-1/ADA4940-2 are low noise, low distortion fully differential amplifiers with very low power consumption. They are an ideal choice for driving low power, high resolution, high performance SAR and - analog-to-digital converters (ADCs) with resolutions up to 16 bits from dc to 1 MHz on only 1.25 mA of quiescent current. The adjustable level of the output commonmode voltage allows the ADA4940-1/ADA4940-2 to match the input common-mode voltage of multiple ADCs. The internal common-mode feedback loop provides exceptional output balance, as well as suppression of even-order harmonic distortion products. VOCM +VS 8 +VS 7 +VS 6 +VS 5 +FB 4 APPLICATIONS Rev. E 15 -VS ADA4940-1 Small signal bandwidth: 260 MHz Ultralow power 1.25mA Extremely low harmonic distortion -122 dB THD at 50 kHz -96 dB THD at 1 MHz Low input voltage noise: 3.9 nV/Hz 0.35 mV maximum offset voltage Balanced outputs Settling time to 0.1%: 34 ns Rail-to-rail output: -VS + 0.1 V to +VS - 0.1 V Adjustable output common-mode voltage Flexible power supplies: 3 V to 7 V (LFCSP) Disable pin to reduce power consumption ADA4940-1 is available in LFCSP and SOIC packages Figure 2. ADA4940-2 The ADA4940-1 is available in a 3 mm x 3 mm, 16-lead LFCSP and an 8-lead SOIC. The ADA4940-2 is available in a 4 mm x 4 mm, 24-lead LFCSP. The pinouts are optimized to facilitate printed circuit board (PCB) layout and minimize distortion. The ADA4940-1/ADA4940-2 are specified to operate over the -40C to +125C temperature range. Table 1. Similar Products to ADA4940-1/ADA4940-2 Product AD8137 ADA4932-1 ADA4941-1 ISUPPLY (mA) 3 9 2.2 Bandwidth (MHz) 110 560 31 Slew Rate (V/s) 450 2800 22 Noise (nV/Hz) 8.25 3.6 5.1 Table 2. Complementary Products to ADA4940-1/ADA4940-2 Product AD7982 AD7984 AD7621 AD7623 Power (mW) 7.0 10.5 65 45 Throughput (MSPS) 1 1.333 3 1.333 Resolution (Bits) 18 18 16 16 SNR (dB) 98 96.5 88 88 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 (c)2011-2018 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADA4940-1/ADA4940-2 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Applications Information .............................................................. 23 Applications ....................................................................................... 1 Analyzing an Application Circuit ............................................ 23 General Description ......................................................................... 1 Setting the Closed-Loop Gain .................................................. 23 Functional Block Diagrams ............................................................. 1 Estimating the Output Noise Voltage ...................................... 23 Revision History ............................................................................... 3 Impact of Mismatches in the Feedback Networks ................. 24 Specifications..................................................................................... 4 Calculating the Input Impedance of an Application Circuit 24 VS = 5 V.......................................................................................... 4 Input Common-Mode Voltage Range ..................................... 25 VS = 3 V.......................................................................................... 6 Input and Output Capacitive AC Coupling ............................ 26 Absolute Maximum Ratings ............................................................ 8 Setting the Output Common-Mode Voltage .......................... 26 Thermal Resistance ...................................................................... 8 DISABLE Pin .............................................................................. 26 Maximum Power Dissipation ..................................................... 8 Driving a Capacitive Load......................................................... 26 ESD Caution .................................................................................. 8 Driving a High Precision ADC ................................................ 27 Pin Configurations and Function Descriptions ........................... 9 Layout, Grounding, and Bypassing .............................................. 28 Typical Performance Characteristics ........................................... 11 ADA4940-1 LFCSP Example .................................................... 28 Test Circuits ..................................................................................... 20 Outline Dimensions ....................................................................... 29 Terminology .................................................................................... 21 Ordering Guide .......................................................................... 30 Definition of Terms .................................................................... 21 Theory of Operation ...................................................................... 22 Rev. E | Page 2 of 30 Data Sheet ADA4940-1/ADA4940-2 REVISION HISTORY 4/2018--Rev. D to Rev. E Changes to Figure 2........................................................................... 1 Changes to Figure 6.........................................................................10 Updated Outline Dimensions ........................................................29 5/2016--Rev. C to Rev. D Changes to Figure 1........................................................................... 1 Deleted Figure 2................................................................................. 1 Added Figure 2; Renumbered Sequentially ................................... 1 Updated Outline Dimensions ........................................................29 Changes to Ordering Guide ...........................................................30 9/2013--Rev. B to Rev. C Updated Outline Dimensions ........................................................30 Changes to Ordering Guide ...........................................................31 3/2012--Rev. A to Rev. B Reorganized Layout ........................................................... Universal Added ADA4940-1 8-Lead SOIC Package ..................... Universal Changes to Features Section, Table 1, and Figure 1; Replaced Figure 2 ............................................................................................... 1 Changed VS = 2 V(or +5 V) Section to VS = +5 V Section ....... 3 Changes to VS = +5 V Section and Table 3 .................................... 3 Changes to Table 4 and Table 5 ....................................................... 4 Changes to VS = 3 V Section and Table 6 ....................................... 5 Changes to Table 7 and Table 8 ....................................................... 6 Added Figure 5 and Table 12, Renumbered Sequentially ............ 9 Changes to Figure 7, Figure 8, and Figure 9 ................................10 Added Figure 15 and Figure 18; Changes to Figure 13, Figure 14, and Figure 16 .................................................................11 Changes to Figure 19 and Figure 20 .............................................12 Changes to Figure 25, Figure 26, and Figure 27; Added Figure 28, Figure 29, and Figure 30 ..............................................13 Changes to Figure 31, Figure 32, Figure 33, Figure 34, Figure 35, and Figure 36 ...................................................................................14 Changes to Figure 37, Figure38, Figure 39, and Figure 41 ........ 15 Changes to Figure 49, Figure 50, and Figure 51 .......................... 17 Added Figure 55 and Figure 57 ..................................................... 18 Changes to Differential VOS, Differential CMRR, and VOCM CMRR Section ................................................................................. 20 Changes to Calculating the Input Impedance of an Application Circuit Section ................................................................................. 23 Changes to Figure 71 ...................................................................... 25 Changes to Driving a High Precision ADC Section and Figure 73 ........................................................................................... 26 Changed ADA4940-1 Example Section to ADA4940-1 LFCSP Example Section .............................................................................. 27 Changes to Ordering Guide ........................................................... 29 12/2011--Rev. 0 to Rev. A Changes to Features Section, General Description Section, and Table 1 ................................................................................................. 1 Replaced Figure 1 and Figure 2 ....................................................... 1 Changes to VS = 2.5 V (or +5 V) Section and Table 3 ............... 3 Changes to Table 6 ............................................................................ 5 Replaced Figure 7, Figure 8, Figure 9, and Figure 10 ................... 9 Replaced Figure 14, Figure 15, and Figure 17 ............................. 10 Replaced Figure 24 and Figure 27 ................................................. 12 Changes to Figure 37 ...................................................................... 14 Replaced Figure 43 and Figure 46 ................................................. 15 Replaced Figure 53 .......................................................................... 18 Changes to Estimating the Output Noise Voltage Section, Table 14, Table 15, and Calculating the Input Impedance of an Application Circuit Section ................................................................................. 21 Changes to Input Common-Mode Voltage Range Section ....... 22 Changes to Driving a High Precision ADC Section and Figure 65 ........................................................................................... 24 10/2011--Revision 0: Initial Version Rev. E | Page 3 of 30 ADA4940-1/ADA4940-2 Data Sheet SPECIFICATIONS VS = 5 V VOCM = midsupply, RF = RG = 1 k, RL, dm = 1 k, TA = 25C, LFCSP package, unless otherwise noted. TMIN to TMAX = -40C to +125C. (See Figure 61 for the definition of terms.) +DIN or -DIN to VOUT, dm Performance Table 3. Parameter DYNAMIC PERFORMANCE -3 dB Small Signal Bandwidth -3 dB Large Signal Bandwidth Bandwidth for 0.1 dB Flatness Slew Rate Settling Time to 0.1% Overdrive Recovery Time NOISE/HARMONIC PERFORMANCE HD2/HD3 IMD3 Input Voltage Noise Input Current Noise Crosstalk INPUT CHARACTERISTICS Input Offset Voltage Input Offset Voltage Drift Input Bias Current Input Bias Current Drift Input Offset Current Input Common-Mode Voltage Range Input Resistance Input Capacitance Common-Mode Rejection Ratio (CMRR) Open-Loop Gain OUTPUT CHARACTERISTICS Output Voltage Swing Linear Output Current Output Balance Error Test Conditions/Comments Min Typ Max Unit VOUT, dm = 0.1 V p-p, G = 1 VOUT, dm = 0.1 V p-p, G = 2 VOUT, dm = 0.1 V p-p, G = 5 VOUT, dm = 2 V p-p, G = 1 VOUT, dm = 2 V p-p, G = 2 VOUT, dm = 2 V p-p, G = 5 VOUT, dm = 2 V p-p, G = 1 and G = 2 VOUT, dm = 2 V step VOUT, dm = 2 V step G = 2, VIN, dm = 6 V p-p, triangle wave 260 220 75 25 22 19 14.5 95 34 86 MHz MHz MHz MHz MHz MHz MHz V/s ns ns VOUT, dm = 2 V p-p, fC = 10 kHz VOUT, dm = 2 V p-p, fC = 50 kHz VOUT, dm = 2 V p-p, fC = 50 kHz, G = 2 VOUT, dm = 2 V p-p, fC = 1 MHz VOUT, dm = 2 V p-p, fC = 1 MHz, G = 2 VOUT, dm = 2 V p-p, f1 = 1.9 MHz, f2 = 2.1 MHz f = 100 kHz f = 100 kHz VOUT, dm = 2 V p-p, fC = 1 MHz -125/-118 -123/-126 -124/-117 -102/-96 -100/-92 -99 3.9 0.81 -110 dBc dBc dBc dBc dBc dBc nV/Hz pA/Hz dB VIP = VIN = VOCM = 0 V TMIN to TMAX -0.35 -1.6 TMIN to TMAX -500 Differential Common mode VOS, dm/VIN, cm, VIN, cm = 1 V dc 86 91 Each single-ended output -VS + 0.1 to +VS - 0.1 f = 1 MHz, RL, dm = 22 , SFDR = -60 dBc f = 1 MHz, VOUT, cm/VOUT, dm Rev. E | Page 4 of 30 0.06 1.2 -1.1 -4.5 50 -VS - 0.2 to +VS - 1.2 33 50 1 119 99 -VS + 0.07 to +VS - 0.07 46 -65 +0.35 +500 mV V/C A nA/C nA V k M pF dB dB V -60 mA peak dB Data Sheet ADA4940-1/ADA4940-2 VOCM to VOUT, cm Performance Table 4. Parameter VOCM DYNAMIC PERFORMANCE -3 dB Small Signal Bandwidth -3 dB Large Signal Bandwidth Slew Rate Input Voltage Noise Gain VOCM CHARACTERISTICS Input Common-Mode Voltage Range Input Resistance Offset Voltage Input Offset Voltage Drift Input Bias Current CMRR Test Conditions/Comments VOUT, cm = 0.1 V p-p VOUT, cm = 1 V p-p VOUT, cm = 1 V p-p f = 100 kHz VOUT, cm/VOCM, VOCM = 1 V Min Typ 0.99 36 29 52 83 1 VOS, dm/VOCM, VOCM = 1 V -7 86 -VS + 0.8 to +VS - 0.7 250 1 20 +4 100 Test Conditions/Comments Min Typ LFCSP SOIC Enabled TMIN to TMAX Disabled VOS, dm/VS, VS = 1 V p-p VOS, dm/VS, VS = 1 V p-p 3 3 1.05 VOS, cm = VOUT, cm - VOCM; VIP = VIN = VOCM = 0 V TMIN to TMAX -6 Max Unit 1.01 MHz MHz V/s nV/Hz V/V V k mV V/C A dB +6 Max Unit 7 6 1.38 V V mA A/C A dB dB +7 General Performance Table 5. Parameter POWER SUPPLY Operating Range Quiescent Current per Amplifier Quiescent Current Drift +PSRR -PSRR DISABLE (DISABLE PIN) DISABLE Input Voltage Turn-Off Time Turn-On Time DISABLE Pin Bias Current per Amplifier Enabled Disabled 80 80 Disabled Enabled 1.25 4.25 13.5 90 96 28.5 (-VS + 1) (-VS + 1.8) 10 0.6 DISABLE = +2.5 V DISABLE = -2.5 V OPERATING TEMPERATURE RANGE -10 -40 Rev. E | Page 5 of 30 2 -5 V V s s 5 A A +125 C ADA4940-1/ADA4940-2 Data Sheet VS = 3 V VOCM = midsupply, RF = RG = 1 k, RL, dm = 1 k, TA = 25C, LFCSP package, unless otherwise noted. TMIN to TMAX = -40C to +125C. (See Figure 61 for the definition of terms.) +DIN or -DIN to VOUT, dm Performance Table 6. Parameter DYNAMIC PERFORMANCE -3 dB Small Signal Bandwidth -3 dB Large Signal Bandwidth Bandwidth for 0.1 dB Flatness Slew Rate Settling Time to 0.1% Overdrive Recovery Time NOISE/HARMONIC PERFORMANCE HD2/HD3 IMD3 Input Voltage Noise Input Current Noise Crosstalk INPUT CHARACTERISTICS Input Offset Voltage Input Offset Voltage Drift Input Bias Current Input Bias Current Drift Input Offset Current Input Common-Mode Voltage Range Input Resistance Input Capacitance Common-Mode Rejection Ratio (CMRR) Open-Loop Gain OUTPUT CHARACTERISTICS Output Voltage Swing Linear Output Current Output Balance Error Test Conditions/Comments Min Typ Max Unit VOUT, dm = 0.1 V p-p VOUT, dm = 0.1 V p-p, G = 2 VOUT, dm = 0.1 V p-p, G = 5 VOUT, dm = 2 V p-p VOUT, dm = 2 V p-p, G = 2 VOUT, dm = 2 V p-p, G = 5 VOUT, dm = 0.1 V p-p VOUT, dm = 2 V step VOUT, dm = 2 V step G = 2, VIN, dm = 3.6 V p-p, triangle wave 240 200 70 24 20 17 14 90 37 85 MHz MHz MHz MHz MHz MHz MHz V/s ns ns VOUT, dm = 2 V p-p, fC = 50 kHz (HD2/HD3) VOUT, dm = 2 V p-p, fC = 1 MHz (HD2/HD3) VOUT, dm = 2 V p-p, f1 = 1.9 MHz, f2 = 2.1 MHz f = 100 kHz f = 100 kHz VOUT, dm = 2 V p-p, fC = 1 MHz -115/-121 -104/-96 -98 3.9 0.84 -110 dBc dBc dBc nV/Hz pA/Hz dB VIP = VIN = VOCM = 1.5 V TMIN to TMAX -0.4 -1.6 TMIN to TMAX -500 Differential Common mode VOS, dm/VIN, cm, VIN, cm = 0.25 V dc 86 91 Each single-ended output -VS + 0.08 to +VS - 0.08 f = 1 MHz, RL, dm = 26 , SFDR = -60 dBc f = 1 MHz, VOUT, cm/VOUT, dm Rev. E | Page 6 of 30 0.06 1.2 -1.1 -4.5 50 -VS - 0.2 to +VS - 1.2 33 50 1 114 99 -VS + 0.04 to +VS - 0.04 38 -65 +0.4 +500 mV V/C A nA/C nA V k M pF dB dB V -60 mA peak dB Data Sheet ADA4940-1/ADA4940-2 VOCM to VOUT, cm Performance Table 7. Parameter VOCM DYNAMIC PERFORMANCE -3 dB Small Signal Bandwidth -3 dB Large Signal Bandwidth Slew Rate Input Voltage Noise Gain VOCM CHARACTERISTICS Input Common-Mode Voltage Range Input Resistance Offset Voltage Input Offset Voltage Drift Input Bias Current CMRR Test Conditions/Comments VOUT, cm = 0.1 V p-p VOUT, cm = 1 V p-p VOUT, cm = 1 V p-p f = 100 kHz VOUT, cm/VOCM, VOCM = 0.25 V Min Typ 0.99 36 26 48 92 1 VOS,dm/VOCM, VOCM = 0.25 V -5 80 -VS + 0.8 to +VS - 0.7 250 1 20 +1 100 Test Conditions/Comments Min Typ LFCSP SOIC Enabled TMIN to TMAX Disabled VOS, dm/VS, VS = 0.25 V p-p VOS, dm/VS, VS = 0.25 V p-p 3 3 1 VOS, cm = VOUT, cm - VOCM; VIP = VIN = VOCM = 1.5 V TMIN to TMAX -7 Max Unit 1.01 MHz MHz V/s nV/Hz V/V V k mV V/C A dB +7 Max Unit 7 6 1.33 V V mA A/C A dB dB +5 General Performance Table 8. Parameter POWER SUPPLY Operating Range Quiescent Current per Amplifier +PSRR -PSRR DISABLE (DISABLE PIN) DISABLE Input Voltage Turn-Off Time Turn-On Time DISABLE Pin Bias Current per Amplifier Enabled Disabled 80 80 1.18 4.25 7 90 96 Disabled Enabled (-VS + 1) (-VS + 1.8) 16 0.6 DISABLE = +3 V DISABLE = 0 V 0.3 -3 -6 OPERATING TEMPERATURE RANGE -40 Rev. E | Page 7 of 30 22 V V s s 1 A A +125 C ADA4940-1/ADA4940-2 Data Sheet ABSOLUTE MAXIMUM RATINGS Table 9. Parameter Supply Voltage VOCM Differential Input Voltage Operating Temperature Range Storage Temperature Range Lead Temperature (Soldering, 10 sec) Junction Temperature ESD Field Induced Charged Device Model (FICDM) Human Body Model (HBM) Rating 8V VS 1.2 V -40C to +125C -65C to +150C 300C 150C 1250 V 2000 V Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. The power dissipated in the package (PD) is the sum of the quiescent power dissipation and the power dissipated in the package due to the load drive for all outputs. The quiescent power dissipation is the voltage between the supply pins (VS) times the quiescent current (IS). The load current consists of the differential and common-mode currents flowing to the load, as well as currents flowing through the external feedback networks and internal common-mode feedback loop. The internal resistor tap used in the common-mode feedback loop places a negligible differential load on the output. Consider rms voltages and currents when dealing with ac signals. Airflow reduces JA. In addition, more metal directly in contact with the package leads from metal traces, through holes, ground, and power planes reduces the JA. Figure 3 shows the maximum safe power dissipation in the package vs. the ambient temperature for the 8-lead SOIC (JA = 158C/W, single) the 16-lead LFCSP (JA = 91.3C/W, single) and 24-lead LFCSP (JA = 65.1C/W, dual) packages on a JEDEC standard 4-layer board. JA values are approximations. 3.5 Table 10. Package Type 8-Lead SOIC (Single)/4-Layer Board 16-Lead LFCSP (Single)/4-Layer Board 24-Lead LFCSP (Dual)/4-Layer Board JA 158 91.3 65.1 Unit C/W C/W C/W MAXIMUM POWER DISSIPATION The maximum safe power dissipation in the ADA4940-1/ ADA4940-2 packages is limited by the associated rise in junction temperature (TJ) on the die. At approximately 150C, which is the glass transition temperature, the plastic changes its properties. Even temporarily exceeding this temperature limit can change the stresses that the package exerts on the die, permanently shifting the parametric performance of the ADA4940-1/ADA4940-2. Exceeding a junction temperature of 150C for an extended period can result in changes in the silicon devices, potentially causing failure. 3.0 ADA4940-2 (LFCSP) 2.5 ADA4940-1 (LFCSP) 2.0 1.5 1.0 ADA4940-1 (SOIC) 0.5 0 -40 -20 0 20 40 60 80 AMBIENT TEMPERATURE (C) 100 120 08452-004 JA is specified for the worst-case conditions, that is, JA is specified for the device soldered on a circuit board in still air. MAXIMUM POWER DISSIPATION (W) THERMAL RESISTANCE Figure 3. Maximum Safe Power Dissipation vs. Ambient Temperature ESD CAUTION Rev. E | Page 8 of 30 Data Sheet ADA4940-1/ADA4940-2 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 13 -VS 14 -VS 16 -VS 15 -VS ADA4940-1 -FB 1 12 DISABLE +IN 2 11 -OUT -IN 3 10 +OUT 9 VOCM +VS 8 +VS 7 +VS 6 +VS 5 +FB 4 08452-101 PIN 1 INDICATOR NOTES 1. CONNECT THE EXPOSED PAD TO -VS OR GROUND. Figure 4. ADA4940-1 Pin Configuration (16-Lead LFCSP) Table 11. ADA4940-1 Pin Function Descriptions (16-Lead LFCSP) Mnemonic -FB +IN -IN +FB +VS VOCM +OUT -OUT DISABLE -VS Exposed pad (EPAD) Description Negative Output for Feedback Component Connection. Positive Input Summing Node. Negative Input Summing Node. Positive Output for Feedback Component Connection. Positive Supply Voltage. Output Common-Mode Voltage. Positive Output for Load Connection. Negative Output for Load Connection. Disable Pin. Negative Supply Voltage. Connect the exposed pad to -VS or ground. -IN 1 8 VOCM 2 7 DISABLE +VS 3 6 -VS 5 -OUT +OUT 4 ADA4940-1 +IN 08452-003 Pin No. 1 2 3 4 5 to 8 9 10 11 12 13 to 16 Figure 5. ADA4940-1 Pin Configuration (8-Lead SOIC) Table 12. ADA4940-1 Pin Function Descriptions (8-Lead SOIC) Pin No. 1 2 3 4 5 6 7 8 Mnemonic -IN VOCM +VS +OUT -OUT -VS DISABLE +IN Description Negative Input Summing Node Output Common-Mode Voltage Positive Supply Voltage Positive Output for Load Connection Negative Output for Load Connection Negative Supply Voltage Disable Pin Positive Input Summing Node Rev. E | Page 9 of 30 19 -OUT1 21 -VS1 20 DISABLE1 Data Sheet 24 +IN1 23 -FB1 22 -VS1 ADA4940-1/ADA4940-2 18 +OUT1 17 VOCM1 -IN1 1 +FB1 2 +VS1 3 16 -VS2 15 -VS2 ADA4940-2 +VS1 4 -FB2 5 14 DISABLE2 +IN2 6 NOTES 1. CONNECT THE EXPOSED PAD TO -VS OR GROUND. 08452-102 +OUT2 12 +VS2 10 VOCM2 11 -IN2 7 +FB2 8 +VS2 9 13 -OUT2 Figure 6. ADA4940-2 Pin Configuration (24-Lead LFCSP) Table 13. ADA4940-2 Pin Function Descriptions (24-Lead LFCSP) Pin No. 1 2 3, 4 5 6 7 8 9, 10 11 12 13 14 15, 16 17 18 19 20 21, 22 23 24 Mnemonic -IN1 +FB1 +VS1 -FB2 +IN2 -IN2 +FB2 +VS2 VOCM2 +OUT2 -OUT2 DISABLE2 -VS2 VOCM1 +OUT1 -OUT1 DISABLE1 -VS1 -FB1 +IN1 Exposed pad (EPAD) Description Negative Input Summing Node 1. Positive Output Feedback Pin 1. Positive Supply Voltage 1. Negative Output Feedback Pin 2. Positive Input Summing Node 2. Negative Input Summing Node 2. Positive Output Feedback Pin 2. Positive Supply Voltage 2. Output Common-Mode Voltage 2. Positive Output 2. Negative Output 2. Disable Pin 2. Negative Supply Voltage 2. Output Common-Mode Voltage 1. Positive Output 1. Negative Output 1. Disable Pin 1. Negative Supply Voltage 1. Negative Output Feedback Pin 1. Positive Input Summing Node 1. Connect the exposed pad to -VS or ground. Rev. E | Page 10 of 30 Data Sheet ADA4940-1/ADA4940-2 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25C, VS = 2.5 V, G = 1, RF = RG = 1 k, RT = 52.3 (when used), RL = 1 k, unless otherwise noted. See Figure 59 and Figure 60 for the test circuits. 3 3 G = 1, RL = 1k 2 1 1 0 0 NORMALIZED GAIN (dB) -1 G = 1, RL = 200 -2 -3 G = 2, RL = 1k -4 -5 G = 2, RL = 200 -6 -2 -3 -4 G = 2, RL = 200 -5 -6 G = 1, RL = 200 VOUT = 2V p-p 1 10 1000 100 FREQUENCY (MHz) Figure 7. Small Signal Frequency Response for Various Gains and Loads (LFCSP) 3 -9 0.1 08452-006 -9 0.1 G = 1, RL = 1k -8 VOUT, dm = 0.1V p-p 10 100 1000 FREQUENCY (MHz) Figure 10. Large Signal Frequency Response for Various Gains and Loads 3 VS = 3.5V 2 2 1 1 0 1 08452-009 -8 VS = 3.5V 0 VS = 2.5V -1 VS = 1.5V -3 -4 -3 -5 -6 -6 -7 -7 -8 -8 100 10 1000 FREQUENCY (MHz) VS = 1.5V -4 -5 VOUT, dm = 0.1V p-p -9 1 0.1 VS = 2.5V -2 VOUT = 2V p-p -9 0.1 1 10 100 1000 FREQUENCY (MHz) Figure 8. Small Signal Frequency Response for Various Supplies (LFCSP) 08452-010 GAIN (dB) -1 -2 08452-007 GAIN (dB) -1 -7 -7 Figure 11. Large Signal Frequency Response for Various Supplies 3 3 2 2 -40C 1 1 0 0 -1 -1 GAIN (dB) +25C -2 -3 +125C -4 +125C -4 -5 -6 -7 -7 -8 VOUT, dm = 0.1V p-p -9 1 +25C -3 -6 -8 -40C -2 -5 10 100 FREQUENCY (MHz) 1000 Figure 9. Small Signal Frequency Response for Various Temperatures (LFCSP) VOUT, dm = 2V p-p -9 08452-008 GAIN (dB) G = 2, RL = 1k 1 10 100 FREQUENCY (MHz) 1000 08452-011 NORMALIZED GAIN (dB) 2 Figure 12. Large Signal Frequency Response for Various Temperatures Rev. E | Page 11 of 30 ADA4940-1/ADA4940-2 Data Sheet 4 3 SOIC-1 3 2 1 1 0 -1 LFCSP-2: CH2 -1 -2 GAIN (dB) LFCSP-2:CH1 -3 -4 -7 -7 -8 10 100 1000 08452-012 1 1 100 1000 Figure 16. Large Signal Frequency Response for Various Packages 3 3 2 VOCM = -1V VOCM = 0V VOCM = +1V 2 VOCM = 0V 1 1 0 0 VOCM = -1V VOCM = +1V -3 -4 -2 -3 -4 -5 -5 -6 -6 -7 -7 -8 VOUT, dm = 0.1V p-p 10 100 1000 FREQUENCY (MHz) 08452-013 1 3 1 10 4 3 2 2 1 1 0 SOIC: RL = 1k SOIC: RL = 200 0 -2 GAIN (dB) VOCM = -1V VOCM = +1V -3 -4 -1 -2 -3 -6 -7 -7 -8 V OUT, dm = 0.1V p-p -9 0.1 1 -8 V OUT, dm = 0.1V p-p -9 0.1 1 100 1000 Figure 15. Small Signal Frequency Response for Various VOCM (SOIC) 08452-205 -5 -6 10 LFCSP: RL = 1k LFCSP: RL = 200 -4 -5 FREQUENCY (MHz) 1000 Figure 17. Large Signal Frequency Response at Various VOCM Levels VOCM = 0V -1 100 FREQUENCY (MHz) Figure 14. Small Signal Frequency Response at Various VOCM Levels (LFCSP) 4 VOUT, dm = 2V p-p -9 0.1 08452-016 -2 -1 GAIN (dB) -1 -9 0.1 10 FREQUENCY (MHz) Figure 13. Small Signal Frequency Response for Various Packages -8 VOUT = 2V p-p -9 08452-015 VOUT, dm = 0.1V p-p FREQUENCY (MHz) GAIN (dB) -4 -6 -6 GAIN (dB) -3 -5 -5 -9 0.1 -2 10 FREQUENCY (MHz) 100 1000 08452-203 GAIN (dB) 0 -8 LFCSP-1 LFCSP-2: CH1 LFCSP-2: CH2 SOIC-1 2 LFCSP-1 Figure 18. Small Signal Frequency Response for Various Packages and Loads Rev. E | Page 12 of 30 Data Sheet ADA4940-1/ADA4940-2 4 4 CCOM1 = CCOM2 = 2pF 3 2 2 1 1 0 CCOM1 = CCOM2 = 1pF -2 CCOM1 = CCOM2 = 0.5pF -3 CCOM1 = CCOM2 = 0pF GAIN (dB) -1 -4 -2 -3 -4 -5 -6 -6 -7 -7 10 100 1000 FREQUENCY (MHz) Figure 19. Small Signal Frequency Response for Various Capacitive Loads (LFCSP) 1 0.15 0.15 NORMALIZED GAIN (dB) 0.25 0.20 0 -0.05 G = 2, RL = 200 -0.10 G = 2, RL = 1k -0.20 0 -0.05 G = 2, RL = 200 -0.10 G = 1, RL = 1k -0.20 1 G = 1, RL = 1k 0.05 G = 1, RL = 200 VOUT, dm = 0.1V p-p -0.25 0.1 0.10 -0.15 G = 2, RL = 1k G = 1, RL = 200 VOUT, dm = 2V p-p 10 100 1000 FREQUENCY (MHz) -0.25 0.1 08452-018 -0.15 1000 Figure 22. Large Signal Frequency Response for Various Capacitive Loads 0.25 0.05 100 FREQUENCY (MHz) 0.20 0.10 10 08452-017 -8 CDIFF = 0pF VOUT = 2V p-p -9 1 10 100 1000 FREQUENCY (MHz) Figure 20. 0.1 dB Flatness Small Signal Frequency Response for Various Gains and Loads (LFCSP) 08452-021 -8 CDIFF = 0pF VOUT = 0.1V p-p -9 1 Figure 23. 0.1 dB Flatness Large Signal Frequency Response for Various Gains and Loads 3 3 2 2 1 1 0 0 -1 GAIN (dB) -2 VS = 1.5V -3 -4 -2 -3 -5 -6 -6 -7 -7 -8 VOUT, dm = 0.1V p-p 10 100 FREQUENCY (MHz) 1000 Figure 21. VOCM Small Signal Frequency Response for Various Supplies VOUT, dm = 1V p-p -9 08452-019 -9 1 VS = 1.5V -4 -5 -8 VS = 2.5V -1 VS = 2.5V 1 10 100 FREQUENCY (MHz) 1000 08452-022 NORMALIZED GAIN (dB) -1 -5 08452-014 GAIN (dB) 0 GAIN (dB) CCOM1 = CCOM2 = 0pF CCOM1 = CCOM2 = 0.5pF CCOM1 = CCOM2 = 1pF CCOM1 = CCOM2 = 2pF 3 Figure 24. VOCM Large Signal Frequency Response for Various Supplies Rev. E | Page 13 of 30 ADA4940-1/ADA4940-2 Data Sheet -20 -20 VOUT, dm = 2V p-p VOUT, dm = 2V p-p -30 -30 -60 HD3, G = 2 -70 HD3, G = 1 -80 HD2, G = 2 -90 HD2, G = 1 -100 -110 -50 -60 -70 -80 HD2, G = 2 -90 HD2, G = 1 -100 -110 -120 -130 0.01 -130 0.01 1 0.1 10 -20 VOUT, dm = 2V p-p VOUT, dm = 2V p-p -30 HARMONIC DISTORTION (dBc) -40 -50 -60 HD3, RL = 200 -70 HD3, RL = 1k -80 -90 -100 HD2, RL = 1k HD2, RL = 200 -110 -120 -40 -50 -70 -80 Figure 26. Harmonic Distortion vs. Frequency for Various Loads (LFCSP) HD2, RL = 1k -100 -110 -20 VOUT, dm = 2V p-p -40 -50 -60 -70 -80 HD2, VS = 3.5V HD3, VS = 1.5V HD2, VS = 1.5V HD3, VS = 3.5V HD2, VS = 2.5V FREQUENCY (MHz) 08452-024 HD3, VS = 2.5V 10 -60 -70 -80 -90 -100 -110 HD2, 2.5V HD2, 1.5V -120 HD3, 1.5V -130 0.01 -120 1 -50 HD3, 2.5V 0.1 1 FREQUENCY (MHz) Figure 27. Harmonic Distortion vs. Frequency for Various Supplies (LFCSP) 10 08452-202 HARMONIC DISTORTION (dBc) -40 0.1 10 Figure 29. Harmonic Distortion vs. Frequency for Various Loads (SOIC) -30 -130 0.01 1 0.1 FREQUENCY (MHz) VOUT, dm = 2V p-p -90 HD3, RL = 1k -130 0.01 -30 -110 HD2, RL = 200 -90 08452-201 10 08452-020 1 0.1 FREQUENCY (MHz) -100 HD3, RL = 200 -60 -120 -130 0.01 -20 10 Figure 28. Harmonic Distortion vs. Frequency vs. Gain (SOIC) -20 -30 1 0.1 FREQUENCY (MHz) Figure 25. Harmonic Distortion vs. Frequency for Various Gains (LFCSP) HARMONIC DISTORTION (dBc) HD3, G = 1 -120 FREQUENCY (MHz) HARMONIC DISTORTION (dBc) -40 08452-200 HARMONIC DISTORTION (dBc) -50 08452-023 HARMONIC DISTORTION (dBc) HD3, G = 2 -40 Figure 30. Harmonic Distortion vs. Frequency for Various Supplies (SOIC) Rev. E | Page 14 of 30 Data Sheet ADA4940-1/ADA4940-2 -20 VOUT, dm = 2V p-p HARMONIC DISTORTION (dBc) -50 -60 -70 SOIC: RL = 200 -90 SOIC: RL = 1k -100 -110 -120 -60 VS = +3V, 0V HD3 -70 VS = +3V, 0V HD2 -80 VS = 3.5V HD2 VS = 2.5V HD2 -90 -100 VS = 3.5V HD3 -110 VS = 2.5V HD3 -130 LFCSP: RL = 200 1 0.1 -50 -120 LFCSP: RL = 1k 10 FREQUENCY (MHz) Figure 31. Spurious-Free Dynamic Range vs. Frequency at RL = 200 and RL = 1 k -140 1 0 2 3 5 4 6 7 8 9 10 VOUT, dm (V p-p) Figure 34. Harmonic Distortion vs. VOUT, dm for Various Supplies, f = 1 MHz (LFCSP) -20 -20 VOUT, dm = 2V p-p HARMONIC DISTORTION (dBc) -40 -50 -60 -70 HD3 AT 1MHz HD2 AT 1MHz -90 -100 -110 -120 -50 -60 -70 -80 HD2 AT 1MHz -90 HD3 AT 1MHz -100 -110 HD2 AT 100kHz -120 -130 HD2 AT 100kHz -2.0 -1.5 -1.0 -0.5 0 -130 HD3 AT 100kHz 0.5 1.0 1.5 2.0 2.5 VOCM (V) -140 08452-025 -140 HD3 AT 100kHz Figure 32. Harmonic Distortion vs. VOCM for 100 kHz and 1 MHz, 2.5 V Supplies (LFCSP) 0 -40 HD2 AT VOUT, dm = 8V p-p -40 -50 HD3 AT VOUT, dm = 4V p-p HARMONIC DISTORTION (dBc) -30 HD2 AT VOUT, dm = 4V p-p -70 HD2 AT VOUT, dm = 2V p-p -90 HD3 AT VOUT, dm = 2V p-p -110 2.5 3.0 VOUT, dm = 2V p-p -50 -60 -70 -80 HD3, RF = RG = 499 -90 -100 HD2, RF = RG = 499 HD3, RF = RG = 1k -110 -120 -120 HD2, RF = RG = 1k -130 0.1 1 FREQUENCY (MHz) 10 -140 0.01 08452-026 -130 0.01 2.0 -20 HD3 AT VOUT, dm = 8V p-p -100 1.5 Figure 35. Harmonic Distortion vs. VOCM for 100 kHz and 1 MHz, 3 V Supply (LFCSP) -30 -80 1.0 VOCM (V) -20 -60 0.5 08452-028 -80 -150 -2.5 +VS = +3V, -VS = 0V VOUT, dm = 2V p-p -30 -40 HARMONIC DISTORTION (dBc) VS = 1.5V HD3 08452-027 -80 -130 0.01 HARMONIC DISTORTION (dBc) VS = 1.5V HD2 -40 -40 -30 f = 1MHz -30 Figure 33. Harmonic Distortion vs. Frequency for Various VOUT, dm (LFCSP) 0.1 1 FREQUENCY (MHz) 10 08452-029 -30 08452-030 SPURIOUS-FREE DYNAMIC RANGE (dBc) -20 Figure 36. Harmonic Distortion vs. Frequency for Various RF and RG (LFCSP) Rev. E | Page 15 of 30 ADA4940-1/ADA4940-2 Data Sheet 10 -60 VOUT, dm = 2V p-p (ENVELOPE) 0 VOUT, dm = 2V p-p -70 -20 -80 -30 CROSSTALK (dB) NORMALIZED SPECTRUM (dBc) -10 -40 -50 -60 -70 -80 CHANNEL 1 TO CHANNEL 2 -90 -100 -110 -90 CHANNEL 2 TO CHANNEL 1 -100 -120 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 FREQUENCY (MHz) 2.5 -130 0.1 08452-033 Figure 40. Crosstalk vs. Frequency, ADA4940-2 130 120 120 110 100 110 LFCSP 90 100 90 80 SOIC -PSRR 80 PSRR (dB) 70 60 +PSRR 70 50 60 20 0.1 1 10 100 FREQUENCY (MHz) 08452-100 30 40 0.1 10 1 100 FREQUENCY (MHz) Figure 38. CMRR vs. Frequency Figure 41. PSRR vs. Frequency -10 100 VOUT, dm = 2V p-p -20 GAIN (dB) -30 -40 -50 -60 -70 0 90 -15 80 -30 70 -45 60 -60 50 -75 40 -90 30 -105 20 -120 10 -135 0 -150 -10 -165 -20 -180 1 10 FREQUENCY (MHz) 100 08452-032 -30 -80 0.1 08452-034 40 50 Figure 39. Output Balance vs. Frequency -40 10k -195 100k 1M 10M 100M FREQUENCY (Hz) Figure 42. Open-Loop Gain and Phase vs. Frequency Rev. E | Page 16 of 30 PHASE (Degrees) CMRR (dB) 100 FREQUENCY (MHz) Figure 37. 2 MHz Intermodulation Distortion (LFCSP) OUTPUT BALANCE (dB) 10 1 -210 1G 08452-035 -120 1.5 08452-039 -110 Data Sheet ADA4940-1/ADA4940-2 2.0 8 0.5 G = +2 0.4 1.6 6 VOUT, dm 1.2 0.3 INPUT VOLTAGE (V) 0.8 2 2 x VIN 0 -2 0.2 OUTPUT 0.4 0.1 %ERROR 0 ERROR (%) OUTPUT VOLTAGE (V) 4 0 -0.4 -0.1 -0.8 -0.2 -1.2 -0.3 -4 -1.6 100 200 300 400 500 600 700 800 900 1000 -2.0 TIME (ns) 10 0 20 60 -0.5 80 70 100 10 1k 10k 100k 1M 10M FREQUENCY (Hz) 1 0.1 0.01 0.1 0 2.50 1.25 -0.25 2.25 -0.50 2.00 +2.5V R2 -2.5V -FB DISABLE -OUT +IN DISABLE 0.25 -1.25 VOCM 0 0.1F VICM -1.00 -1.50 +OUT -IN -0.25 -1.75 +FB R1 -0.50 R2 -2.5V -2.00 +OUT, VICM = 1V 80 90 08452-038 70 -1.00 -2.5V 0.75 -1.75 -OUT, VICM = 1V 0.50 -0.25 60 R2 -1.50 -2.75 100 50 R1 -1.25 -1.25 TIME (s) -0.75 -IN 1.00 0 40 -0.50 +OUT 1.25 -2.50 30 0.1F VICM 1.50 -1.00 20 DISABLE -OUT +FB 0.25 10 -0.25 -FB DISABLE +IN VOCM -2.25 -0.75 0V +2.5V R2 -2.5V 1.75 OUTPUT VOLTAGE (V) R1 0.50 -0.75 0V 0 R1 DISABLE PIN VOLTAGE (V) 0.75 100 Figure 47. Closed-Loop Output Impedance Magnitude vs. Frequency, G = 1 1.50 -OUT, VICM = 1V 10 FREQUENCY (MHz) Figure 44. Voltage Noise Spectral Density, Referred to Input 1.00 1 Figure 45. DISABLE Pin Turn-Off Time -2.00 +OUT, VICM = 1V -2.25 -2.50 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 TIME (s) Figure 48. DISABLE Pin Turn-On Time Rev. E | Page 17 of 30 DISABLE PIN VOLTAGE (V) 100 08452-037 1 10 10 08452-040 OUTPUT IMPEDANCE () INPUT VOLTAGE NOISE (nV/Hz) 50 Figure 46. 0.1% Settling Time 100 OUTPUT VOLTAGE (V) 40 TIME (ns) Figure 43. Output Overdrive Recovery, G = 2 0 30 1.8 -2.75 2.0 08452-057 0 08452-041 -8 -0.4 VOUT, dm = 2V p-p 08452-065 -6 ADA4940-1/ADA4940-2 Data Sheet 1.5 100 G = 1, RL = 200 G = 2, RL = 200 40 1.0 OUTPUT VOLTAGE (V) G = 2, RL = 1k 20 G = 1, RL = 1k 0 -20 -40 -60 -0.5 G G G G RL = RL = RL = RL = 1k 200 1k 200 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 TIME (ns) -1.5 08452-042 0 = 1, = 1, = 2, = 2, VOUT, dm = 2V p-p VOUT, dm = 0.1V p-p -100 Figure 49. Small Signal Transient Response for Various Gains and Loads (LFCSP) 0 20 40 60 80 100 120 140 160 180 200 220 240 260 280 300 TIME (ns) Figure 52. Large Signal Transient Response for Various Gains and Loads 100 1.5 80 VS = 3.5V VS = 1.5V VS = 1.5V 1.0 OUTPUT VOLTAGE (V) 60 OUTPUT VOLTAGE (mV) 0 -1.0 -80 40 VS = 2.5V 20 0 -20 -40 -60 VS = 2.5V 0.5 0 -0.5 -1.0 -80 VS = 3.5V VOUT, dm = 0.1V 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 TIME (ns) -1.5 08452-043 -100 0.5 VOUT, dm = 2V p-p 0 20 40 60 80 100 120 140 160 180 200 220 240 260 280 300 TIME (ns) Figure 50. Small Signal Transient Response for Various Supplies (LFCSP) 08452-046 OUTPUT VOLTAGE (mV) 60 08452-045 80 Figure 53. Large Signal Transient Response for Various Supplies 100 1.5 80 1.0 OUTPUT VOLTAGE (V) 40 20 0 CCOM1 = CCOM2 = 0pF CCOM1 = CCOM2 = 0.5pF CCOM1 = CCOM2 = 1pF CCOM1 = CCOM2 = 2pF -20 -40 -60 0.5 0 CCOM1 = CCOM2 = 0pF CCOM1 = CCOM2 = 0.5pF CCOM1 = CCOM2 = 1pF CCOM1 = CCOM2 = 2pF -0.5 -1.0 CDIFF = 0pF VOUT, dm = 0.1V p-p CDIFF = 0pF VOUT, dm = 2V p-p -100 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 TIME (ns) -1.5 08452-044 -80 Figure 51. Small Signal Transient Response for Various Capacitive Loads (LFCSP) 0 20 40 60 80 100 120 140 160 180 200 220 240 260 280 300 TIME (ns) 08452-047 OUTPUT VOLTAGE (mV) 60 Figure 54. Large Signal Transient Response for Various Capacitive Loads Rev. E | Page 18 of 30 Data Sheet ADA4940-1/ADA4940-2 100 80 LFCSP-1 LFCSP-2: CH1 LFCSP-2: CH2 SOIC-1 80 60 OUTPUT VOLTAGE (mV) 60 40 20 0 -20 -40 -60 40 20 0 -20 -40 -60 -80 -80 VOUT, dm = 0.1V p-p VOUT, dm = 0.1V p-p 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 TIME (ns) -100 08452-204 -100 Figure 55. Small Signal Transient Response for Various Packages, CL = 0 pF 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 TIME (ns) 08452-206 OUTPUT VOLTAGE (mV) 100 LFCSP-1 LFCSP-2: CH1 LFCSP-2: CH2 SOIC-1 Figure 57. Small Signal Transient Response for Various Packages, CL = 2 pF 100 1.00 80 0.75 VS = 2.5V VS = 2.5V OUTPUT VOLTAGE (V) 0.50 40 VS = 1.5V 20 0 -20 -40 VS = 1.5V 0.25 0 -0.25 -0.50 -60 -0.75 VOUT, dm = 0.1V p-p VOUT, dm = 1V p-p -100 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 TIME (ns) Figure 56. VOCM Small Signal Transient Response -1.00 0 20 40 60 80 100 120 140 160 180 200 220 240 260 280 300 TIME (ns) Figure 58. VOCM Large Signal Transient Response Rev. E | Page 19 of 30 08452-053 -80 08452-048 OUTPUT VOLTAGE (mV) 60 ADA4940-1/ADA4940-2 Data Sheet TEST CIRCUITS 1k NETWORK ANALYZER OUTPUT 475 1k 50 52.3 VIN NETWORK ANALYZER INPUT +2.5V ADA4940-1/ ADA4940-2 VOCM 1k 50 54.9 54.9 50 475 08452-067 25.5 -2.5V 1k Figure 59. Equivalent Basic Test Circuit 1k DC-COUPLED GENERATOR VIN 1k LOW-PASS FILTER 52.3 VOCM 1k 100 475 ADA4940-1/ ADA4940-2 54.9 2:1 50 DUAL FILTER HP LP CT 475 54.9 25.5 -2.5V 1k Figure 60. Test Circuit for Distortion Measurements Rev. E | Page 20 of 30 08452-056 50 +2.5V Data Sheet ADA4940-1/ADA4940-2 TERMINOLOGY Common-Mode Offset Voltage DEFINITION OF TERMS The common-mode offset voltage is defined as the difference between the voltage applied to the VOCM terminal and the common mode of the output voltage. -FB RF +IN -OUT ADA4940-1/ ADA4940-2 +VOCM -DIN RG RF -IN VOS, cm = VOUT, cm - VOCM - RL, dm VOUT, dm +OUT +FB Differential VOS, Differential CMRR, and VOCM CMRR + The differential mode and common-mode voltages each have their own error sources. The differential offset (VOS, dm) is the voltage error between the +IN and -IN terminals of the amplifier. Differential CMRR reflects the change of VOS, dm in response to changes to the common-mode voltage at the input terminals +DIN and -DIN. 08452-090 +DIN RG Figure 61. Circuit Definitions Differential Voltage Differential voltage refers to the difference between two node voltages. For example, the differential output voltage (or equivalently, output differential mode voltage) is defined as VOUT, dm = (V+OUT - V-OUT) CMRR DIFF VOCM CMRR reflects the change of VOS, dm in response to changes to the common-mode voltage at the output terminals. where V+OUT and V-OUT refer to the voltages at the +OUT and -OUT terminals with respect to a common reference. CMRRVOCM Similarly, the differential input voltage is defined as VIN, dm = (+DIN - (-DIN)) Common-Mode Voltage (CMV) CMV refers to the average of two node voltages. The output common-mode voltage is defined as VOUT, cm = (V+OUT + V-OUT)/2 V IN, cm VOS, dm VOCM VOS, dm Balance Balance is a measure of how well the differential signals are matched in amplitude; the differential signals are exactly 180 apart in phase. By this definition, the output balance is the magnitude of the output common-mode voltage divided by the magnitude of the output differential mode voltage. Similarly, the input common-mode voltage is defined as Output Balance Error VIN, cm = (+DIN + (-DIN))/2 Rev. E | Page 21 of 30 VOUT , cm VOUT , dm ADA4940-1/ADA4940-2 Data Sheet THEORY OF OPERATION The ADA4940-1/ADA4940-2 are high speed, low power differential amplifiers fabricated on Analog Devices advanced dielectrically isolated SiGe bipolar process. They provide two closely balanced differential outputs in response to either differential or single-ended input signals. An external feedback network that is similar to a voltage feedback operational amplifier sets the differential gain. The output common-mode voltage is independent of the input common-mode voltage and is set by an external voltage at the VOCM terminal. The PNP input stage allows input common-mode voltages between the negative supply and 1.2 V below the positive supply. A rail-torail output stage supplies a wide output voltage range. The DISABLE pin can reduce the supply current of the amplifier to 13.5 A. Figure 62 shows the ADA4940-1/ADA4940-2 architecture. The differential feedback loop consists of the differential transconductance GDIFF working through the GO output buffers and the RF/RG feedback networks. The common-mode feedback loop is set up with a voltage divider across the two differential outputs to create an output voltage midpoint and a commonmode transconductance, GCM. +DIN RG RF CC GO The differential feedback loop forces the voltages at +IN and -IN to equal each other. This fact sets the following relationships: V + DIN = - -OUT RG RF V - DIN = - +OUT RF RG Subtracting the previous equations gives the relationship that shows RF and RG setting the differential gain. (V+OUT - V-OUT) = (+DIN - (-DIN)) x The common-mode feedback loop drives the output commonmode voltage that is sampled at the midpoint of the output voltage divider to equal the voltage at VOCM. This results in the following relationships: -OUT GCM -IN VOCM VREF GO RG +OUT CC RF 08452-058 -DIN V+OUT = VOCM + VOUT, dm V-OUT = VOCM - VOUT, dm 2 2 Note that the differential amplifier's summing junction input voltages, +IN and -IN, are set by both the output voltages and the input voltages. +IN GDIFF RF RG Figure 62. ADA4940-1/ADA4940-2 Architectural Block Rev. E | Page 22 of 30 RF V+ IN = + DIN RF + RG RG + V-OUT R + R G F RF V- IN = - DIN RF + RG RG + V+OUT R +R G F Data Sheet ADA4940-1/ADA4940-2 APPLICATIONS INFORMATION VnRG1 ANALYZING AN APPLICATION CIRCUIT The ADA4940-1/ADA4940-2 use open-loop gain and negative feedback to force their differential and common-mode output voltages in such a way as to minimize the differential and commonmode error voltages. The differential error voltage is defined as the voltage between the differential inputs labeled +IN and -IN (see Figure 61). For most purposes, this voltage is zero. Similarly, the difference between the actual output common-mode voltage and the voltage applied to VOCM is also zero. Starting from these two assumptions, any application circuit can be analyzed. Determine the differential mode gain of the circuit in Figure 61 by using the following equation: VIN , dm = VnRF1 RF1 inIN+ + inIN- VnIN ADA4940-1/ ADA4940-2 VnOD VnRG2 RG2 RF2 VnCM VnRF2 08452-050 VOCM Figure 63. ADA4940-1/ADA4940-2 Noise Model SETTING THE CLOSED-LOOP GAIN VOUT , dm RG1 RF RG As with conventional op amp, the output noise voltage densities can be estimated by multiplying the input-referred terms at +IN and -IN by the appropriate output factor, where: GN = This assumes that the input resistors (RG) and feedback resistors (RF) on each side are equal. ESTIMATING THE OUTPUT NOISE VOLTAGE Estimate the differential output noise of the ADA4940-1/ ADA4940-2 by using the noise model in Figure 63. The inputreferred noise voltage density, vnIN, is modeled as a differential input, and the noise currents, inIN- and inIN+, appear between each input and ground. The noise currents are assumed equal and produce a voltage across the parallel combination of the gain and feedback resistances. vnCM is the noise voltage density at the VOCM pin. Each of the four resistors contributes (4kTRx)1/2. Table 14 summarizes the input noise sources, the multiplication factors, and the output-referred noise density terms. For more noise calculation information, go to the Analog Devices Differential Amplifier Calculator (DiffAmpCalcTM), click ADIDiffAmpCalculator.zip, and follow the on-screen prompts. 1 = 2 (1 + 2 ) is the circuit noise gain. RG1 RG2 and 2 = are the feedback factors. RF2 + RG2 RF1 + RG1 When RF1/RG1 = RF2/RG2, then 1 = 2 = , and the noise gain becomes GN = 1 R =1+ F RG Note that the output noise from VOCM goes to zero in this case. The total differential output noise density, vnOD, is the root-sumsquare of the individual output noise terms. vnOD = 8 2 vnOi i =1 Table 14. Output Noise Voltage Density Calculations Input Noise Contribution Differential Input Inverting Input Noninverting Input VOCM Input Gain Resistor RG1 Gain Resistor RG2 Feedback Resistor RF1 Feedback Resistor RF2 Input Noise Term vnIN inIN- inIN+ vnCM vnRG1 vnRG2 vnRF1 vnRF2 Input Noise Voltage Density vnIN inIN- x (RG2||RF2) inIN+ x (RG1||RF1) vnCM (4kTRG1)1/2 (4kTRG2)1/2 (4kTRF1)1/2 (4kTRF2)1/2 Rev. E | Page 23 of 30 Output Multiplication Factor GN GN GN GN (1 - 2) GN (1 - 2) GN (1 - 1) 1 1 Output-Referred Noise Voltage Density Term vnO1 = GN (vnIN) vnO2 = GN [inIN- x (RG2||RF2)] vnO3 = GN [inIN+ x (RG1||RF1)] vnO4 = GN (1 - 2)(vnCM) vnO5 = GN (1 - 2)(4kTRG1)1/2 vnO6 = GN (1 - 1)(4kTRG2)1/2 vnO7 = (4kTRF1)1/2 vnO8 = (4kTRF2)1/2 ADA4940-1/ADA4940-2 Data Sheet Table 15 and Table 16 list several common gain settings, recommended resistor values, input impedances, and output noise density for both balanced and unbalanced input configurations. Table 15. Differential Ground-Referenced Input, DC-Coupled, RL = 1 k (See Figure 64) Nominal Gain (dB) 0 6 10 14 RF () 1000 1000 1000 1000 RG () 1000 500 318 196 RIN, dm () 2000 1000 636 392 Differential Output Noise Density (nV/Hz) 11.3 15.4 20.0 27.7 RTI (nV/Hz) 11.3 7.7 6.8 5.5 Table 16. Single-Ended Ground-Referenced Input, DC-Coupled, RS = 50 , RL = 1 k (See Figure 65) Nominal Gain (dB) 0 6 10 14 RG () 1000 500 318 196 RT () 52.3 53.6 54.9 59.0 RIN, se () 1333 750 512 337 RG1 () 1 1025 526 344 223 Differential Output Noise Density (nV/Hz) 11.2 15.0 19.0 25.3 RTI (nV/Hz) 11.2 7.5 6.3 5 RG1 = RG + (RS||RT) IMPACT OF MISMATCHES IN THE FEEDBACK NETWORKS For an unbalanced, single-ended input signal (see Figure 65), the input impedance is Even if the external feedback networks (RF/RG) are mismatched, the internal common-mode feedback loop still forces the outputs to remain balanced. The amplitudes of the signals at each output remain equal and 180 out of phase. The input-to-output, differential mode gain varies proportionately to the feedback mismatch, but the output balance is unaffected. RIN , se RF +VS +DIN RG +IN VOCM -DIN RG ADA4940-1/ ADA4940-2 VOUT, dm -IN 08452-051 As well as causing a noise contribution from VOCM, ratio-matching errors in the external resistors result in a degradation of the ability of the circuit to reject input common-mode signals, much the same as for a four resistors difference amplifier made from a conventional op amp. In addition, if the dc levels of the input and output commonmode voltages are different, matching errors result in a small differential mode, output offset voltage. When G = 1, with a ground-referenced input signal and the output common-mode level set to 2.5 V, an output offset of as much as 25 mV (1% of the difference in common-mode levels) can result if 1% tolerance resistors are used. Resistors of 1% tolerance result in a worstcase input CMRR of about 40 dB, a worst-case differential mode output offset of 25 mV due to the 2.5 V level-shift, and no significant degradation in output balance error. RG = RF 1 - 2 x (R + R ) G F RF Figure 64. ADA4940-1/ADA4940-2 Configured for Balanced (Differential) Inputs RF +VS RG RS +IN VOCM RT RG RS RT ADA4940-1/ ADA4940-2 VOUT, dm -IN RF CALCULATING THE INPUT IMPEDANCE OF AN APPLICATION CIRCUIT 08452-052 1 RF () 1000 1000 1000 1000 Figure 65. ADA4940-1/ADA4940-2 Configured for Unbalanced (Single-Ended) Input The effective input impedance of a circuit depends on whether the amplifier is being driven by a single-ended or differential signal source. For balanced differential input signals, as shown in Figure 64, the input impedance (RIN, dm) between the inputs (+DIN and -DIN) is simply RIN, dm = 2 x RG. The input impedance of the circuit is effectively higher than it would be for a conventional op amp connected as an inverter because a fraction of the differential output voltage appears at the inputs as a common-mode signal, partially bootstrapping the voltage across the input resistor RG1. Rev. E | Page 24 of 30 ADA4940-1/ADA4940-2 Terminating a Single-Ended Input RS This section describes how to properly terminate a single-ended input to the ADA4940-1/ADA4940-2 with a gain of 1, RF = 1 k and RG = 1 k. An example using an input source with a terminated output voltage of 1 V p-p and source resistance of 50 illustrates the three steps that must be followed. Because the terminated output voltage of the source is 1 V p-p, the open-circuit output voltage of the source is 2 V p-p. The source shown in Figure 66 indicates this open-circuit voltage. VS 2V p-p RF +VS RG 1k 1k +VS ADA4940-1 ADA4940-2 VOCM RL VOUT, dm VTH 1.02V p-p RG RTH RG 25.5 1k VOCM 1k RTS 25.5 08452-059 -VS 1k -VS 1k The input impedance is calculated by Figure 69. Thevenin Equivalent and Matched Gain Resistors Figure 69 presents a tractable circuit with matched feedback loops that can be easily evaluated. R 1000 G = 1.33 k = RIN , se = 1000 RF - 1 1 - + x 2 ( 1000 1000 ) 2 x ( R + R ) F G It is useful to point out two effects that occur with a terminated input. The first is that the value of RG is increased in both loops, lowering the overall closed-loop gain. The second is that VTH is a little larger than 1 V p-p, as it would be if RT = 50 . These two effects have opposite impacts on the output voltage, and for large resistor values in the feedback loops (~1 k), the effects essentially cancel each other out. For small RF and RG, or high gains, however, the diminished closed-loop gain is not cancelled completely by the increased VTH. This can be seen by evaluating Figure 69. To match the 50 source resistance, calculate the termination resistor, RT, using RT||1.33 k = 50 . The closest standard 1% value for RT is 52.3 . RF 1k +VS RIN, se 50 VS 2V p-p RS RG 50 1k RT 52.3 VOCM ADA4940-1 ADA4940-2 RL The desired differential output in this example is 1 V p-p because the terminated input signal was 1 V p-p and the closed-loop gain = 1. The actual differential output voltage, however, is equal to (1.02 V p-p)(1000/1025.5) = 0.996 V p-p. This is within the tolerance of the resistors, so no change to the feedback resistor, RF, is required. VOUT, dm RG 1k 08452-060 -VS RF 1k Figure 67. Adding Termination Resistor RT 3. 1k RF Figure 66. Calculating Single-Ended Input Impedance, RIN 2. RL VOUT, dm RG RF 1. ADA4940-1 ADA4940-2 08452-062 RS 50 VTH 1.02V p-p 25.5 Figure 68. Calculating the Thevenin Equivalent 1k RIN, se 1.33k RTH RT 52.3 RTS = RTH = RS||RT = 25.5 . Note that VTH is greater than 1 V p-p, which was obtained with RT = 50 . The modified circuit with the Thevenin equivalent (closest 1% value used for RTH) of the terminated source and RTS in the lower feedback loop is shown in Figure 69. RF VS 2V p-p 50 08452-061 Data Sheet Figure 67 shows that the effective RG in the upper feedback loop is now greater than the RG in the lower loop due to the addition of the termination resistors. To compensate for the imbalance of the gain resistors, add a correction resistor (RTS) in series with RG in the lower loop. RTS is the Thevenin equivalent of the source resistance, RS, and the termination resistance, RT, and is equal to RS||RT. INPUT COMMON-MODE VOLTAGE RANGE The ADA4940-1/ADA4940-2 input common-mode range is shifted down by approximately 1 VBE, in contrast to other ADC drivers with centered input ranges, such as the ADA4939-1/ ADA4939-2. The downward-shifted input common-mode range is especially suited to dc-coupled, single-ended-to-differential, and single-supply applications. For 2.5 V or +5 V supply operation, the input common-mode range at the summing nodes of the amplifier is specified as -2.7 V to +1.3 V or -0.2 V to 3.8 V, and is specified as -0.2 V to +1.8 V with a +3 V supply. Rev. E | Page 25 of 30 ADA4940-1/ADA4940-2 Data Sheet INPUT AND OUTPUT CAPACITIVE AC COUPLING AMPLIFIER BIAS CURRENT DISABLE 08452-063 Although the ADA4940-1/ADA4940-2 is best suited to dccoupled applications, it is nonetheless possible to use it in accoupled circuits. Input ac coupling capacitors can be inserted between the source and RG. This ac coupling blocks the flow of the dc common-mode feedback current and causes the ADA4940-1/ADA4940-2 dc input common-mode voltage to equal the dc output common-mode voltage. These ac coupling capacitors must be placed in both loops to keep the feedback factors matched. Output ac coupling capacitors can be placed in series between each output and its respective load. +VS -VS Figure 70. DISABLE Pin Circuit SETTING THE OUTPUT COMMON-MODE VOLTAGE DRIVING A CAPACITIVE LOAD The VOCM pin of the ADA4940-1/ADA4940-2 is internally biased at a voltage approximately equal to the midsupply point, [(+VS) + (-VS)]/2. Relying on this internal bias results in an output common-mode voltage that is within approximately 100 mV of the expected value. A purely capacitive load reacts with the bond wire and pin inductance of the ADA4940-1/ADA4940-2, resulting in high frequency ringing in the transient response and loss of phase margin. One way to minimize this effect is to place a resistor in series with each output to buffer the load capacitance. The resistor and load capacitance form a first-order, low-pass filter; therefore, the resistor value must be as small as possible. In some cases, the ADCs require small series resistors to be added on their inputs. DISABLE PIN The ADA4940-1/ADA4940-2 feature a DISABLE pin that can be used to minimize the quiescent current consumed when the device is not being used. DISABLE is asserted by applying a low logic level to the DISABLE pin. The threshold between high and low logic levels is nominally 1.4 V above the negative supply rail. See Table 5 and Table 8 for the threshold limits. 120 VIN R3 +2.5V R4 -FB 100 The DISABLE pin features an internal pull-up network that enables the amplifier for normal operation. The ADA4940-1/ ADA4940-2 DISABLE pin can be left floating (that is, no external connection is required) and does not require an external pull-up resistor to ensure normal on operation (see Figure 70). When the ADA4940-1/ADA4940-2 is disabled, the output is high impedance. Note that the outputs are tied to the inputs through the feedback resistors and to the source using the gain resistors. In addition, there are back-to-back diodes on the input pins that limit the differential voltage to 1.2 V. Rev. E | Page 26 of 30 -OUT +IN RS CL VOCM 0.1F 80 CL +OUT -IN RS +FB R2 R1 -2.5V 60 40 20 0 5 10 100 1000 LOAD CAPACITANCE (pF) Figure 71. Capacitive Load vs. Series Resistance (LFCSP) 08452-064 It is also possible to connect the VOCM input to a common-mode level (CML) output of an ADC. However, care must be taken to ensure that the output has sufficient drive capability. The input impedance of the VOCM pin is approximately 250 k. Figure 71 illustrates the capacitive load vs. the series resistance required to maintain a minimum 45 of phase margin. SERIES RESISTANCE () In cases where more accurate control of the output common-mode level is required, it is recommended that an external source, or resistor divider (10 k or greater resistors), be used. The output common-mode offset listed in the Specifications section assumes that the VOCM input is driven by a low impedance voltage source. Data Sheet ADA4940-1/ADA4940-2 The total system power in Figure 73 is under 35 mW. A large portion of that power is the current coming from supplies to the output, which is set at 2.5 V, going back to the input through the feedback and gain resistors. To reduce that power to 25 mW, increase the value of the feedback and gain resistor from 1 k to 2 k and set the value of the resistors R5 and R6 to 3 k. The ADR435 is used to regulate the +6 V supply to +5 V, which ends up powering the ADC and setting the reference voltage for the VOCM pin. Figure 72 shows the FFT of a 20 kHz differential input tone sampled at 1 MSPS. The second and third harmonics are down at -118 dBc and -122 dBc. 0 -20 -40 -60 -80 -100 -120 -140 In this example, the signal generator has a 10 V p-p symmetric, ground-referenced bipolar output. The VOCM input is bypassed for noise reduction and set externally with 1% resistors to 2.5 V to maximize the output dynamic range. With an output common- -160 0 20k 40k 60k FREQUENCY (Hz) ADR435 +5V R3 10F +6V R4 -FB +2.5V +IN -OUT R5 VOCM 33 2.7nF ADA4940-1 IN+ REF VDD AD7982 2.7nF 0.1F +OUT 33 IN- GND -IN SERIAL INTERFACE +FB -DIN R1 R2 -1V Figure 73. ADA4940-1 (LFCSP) Driving the AD7982 ADC Rev. E | Page 27 of 30 08452-066 R6 100k Figure 72. Distortion Measurement of a 20 kHz Input Tone (See CN-0237) +6V +DIN 80k 08452-069 The ADA4940-1/ADA4940-2 are ideally suited for broadband dc-coupled applications. The circuit in Figure 73 shows a frontend connection for an ADA4940-1 driving an AD7982, which is an 18-bit, 1 MSPS successive approximation, analog-to-digital converter (ADC) that operates from a single power supply, 3 V to 5 V. It contains a low power, high speed, 18-bit sampling ADC and a versatile serial interface port. The reference voltage, REF, is applied externally and can be set independent of the supply voltage. As shown in Figure 73, the ADA4940-1 is dccoupled on the input and the output, which eliminates the need for a transformer to drive the ADC. The amplifier performs a single-ended-to-differential conversion if needed and level shifts the input signal to match the input common mode of the ADC. The ADA4940-1 is configured with a dual 7 V supply (+6 V and -1 V) and a gain that is set by the ratio of the feedback resistor to the gain resistor. In addition, the circuit can be used in a single-ended-input-to-differential output or differential-input-to-differential output configuration. If needed, a termination resistor in parallel with the source input can be used. Whether the input is a single-ended input or differential, the input impedance of the amplifier can be calculated as shown in the Terminating a Single-Ended Input section. If R1 = R2 = R3 = R4 = 1 k, the single-ended input impedance is approximately 1.33 k, which, in parallel with a 52.3 termination resistor, provides a 50 termination for the source. An additional 25.5 (1025.5 total) at the inverting input balances the parallel impedance of the 50 source and the termination resistor driving the noninverting input. However, if a differential source input is used, the differential input impedance is 2 k. In this case, two 52.3 termination resistors are used to terminate the inputs. mode voltage of 2.5 V, each ADA4940-1 output swings between 0 V and 5 V, opposite in phase, providing a gain of 1 and a 10 V p-p differential signal to the ADC input. The differential RC section between the ADA4940-1 output and the ADC provides single-pole, low-pass filtering with a corner frequency of 1.79 MHz and extra buffering for the current spikes that are output from the ADC input when its sample-and-hold (SHA) capacitors are discharged. AMPLITUDE (dB) DRIVING A HIGH PRECISION ADC ADA4940-1/ADA4940-2 Data Sheet LAYOUT, GROUNDING, AND BYPASSING As a high speed device, the ADA4940-1/ADA4940-2 are sensitive to the PCB environment in which they operate. Realizing their superior performance requires attention to the details of high speed PCB design. Bypass the power supply pins as close to the device as possible and directly to a nearby ground plane. Use high frequency ceramic chip capacitors. Use two parallel bypass capacitors (1000 pF and 0.1 F) for each supply. Place the 1000 pF capacitor closer to the device. Further away, provide low frequency bypassing using 10 F tantalum capacitors from each supply to ground. ADA4940-1 LFCSP EXAMPLE The first requirement is a solid ground plane that covers as much of the board area around the ADA4940-1 as possible. However, clear the area near the feedback resistors (RF), gain resistors (RG), and the input summing nodes (Pin 2 and Pin 3) of all ground and power planes (see Figure 74). Clearing the ground and power planes minimizes any stray capacitance at these nodes and prevents peaking of the response of the amplifier at high frequencies. Ensure that signal routing is short and direct to avoid parasitic effects. Wherever complementary signals exist, provide a symmetrical layout to maximize balanced performance. When routing differential signals over a long distance, ensure that PCB traces are close together, and twist any differential wiring such that loop area is minimized. Doing this reduces radiated energy and makes the circuit less susceptible to interference. 1.30 The thermal resistance, JA, is specified for the device, including the exposed pad, soldered to a high thermal conductivity 4-layer circuit board, as described in EIA/JESD 51-7. 0.80 08452-087 1.30 0.80 08452-086 Figure 75. Recommended PCB Thermal Attach Pad Dimensions (mm) Figure 74. Ground and Power Plane Voiding in Vicinity of RF and RG 1.30 TOP METAL GROUND PLANE 0.30 PLATED VIA HOLE 08452-088 POWER PLANE BOTTOM METAL Figure 76. Cross-Section of 4-Layer PCB Showing Thermal Via Connection to Buried Ground Plane (Dimensions in mm) Rev. E | Page 28 of 30 Data Sheet ADA4940-1/ADA4940-2 OUTLINE DIMENSIONS PIN 1 INDICATOR 3.10 3.00 SQ 2.90 DETAIL A (JEDEC 95) 0.30 0.23 0.18 13 0.50 BSC 16 12 1 PIN 1 INDIC ATOR AREA OPTIONS (SEE DETAIL A) 1.45 1.30 SQ 1.15 EXPOSED PAD 4 9 0.50 0.40 0.30 SIDE VIEW 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE PKG-004337 BOTTOM VIEW FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WEED-6 Figure 77. 16-Lead Lead Frame Chip Scale Package [LFCSP] 3 mm x 3 mm Body and 0.75 mm Package Height (CP-16-21) Dimensions shown in millimeters 5.00 (0.1968) 4.80 (0.1890) 8 4.00 (0.1574) 3.80 (0.1497) 1 5 4 1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040) COPLANARITY 0.10 SEATING PLANE 6.20 (0.2441) 5.80 (0.2284) 1.75 (0.0688) 1.35 (0.0532) 0.51 (0.0201) 0.31 (0.0122) 0.50 (0.0196) 0.25 (0.0099) 45 8 0 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) COMPLIANT TO JEDEC STANDARDS MS-012-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 78. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) Rev. E | Page 29 of 30 012407-A 0.80 0.75 0.70 0.20 MIN 5 8 10-11-2017-B TOP VIEW ADA4940-1/ADA4940-2 Data Sheet PIN 1 INDICATOR DETAIL A (JEDEC 95) 0.30 0.25 0.18 0.50 BSC PIN 1 INDIC ATOR AREA OPTIONS (SEE DETAIL A) 24 19 18 1 EXPOSED PAD 2.65 2.50 SQ 2.45 13 TOP VIEW 0.80 0.75 0.70 SIDE VIEW SEATING PLANE 0.50 0.40 0.30 6 12 7 BOTTOM VIEW 3.16 MIN 0.05 MAX 0.02 NOM COPLANARITY 0.08 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 0.20 REF PKG-004462 0.20 MIN COMPLIANT TO JEDEC STANDARDS MO-220-WGGD. 10-19-2017-B 4.10 4.00 SQ 3.90 Figure 79. 24-Lead Lead Frame Chip Scale Package [LFCSP] 4 mm x 4 mm Body and 0.75 mm Package Height (CP-24-7) Dimensions shown in millimeters ORDERING GUIDE Model 1 ADA4940-1ACPZ-R2 ADA4940-1ACPZ-RL ADA4940-1ACPZ-R7 ADA4940-1ARZ ADA4940-1ARZ-RL ADA4940-1ARZ-R7 ADA4940-2ACPZ-R2 ADA4940-2ACPZ-RL ADA4940-2ACPZ-R7 1 Temperature Range -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C Package Description 16-Lead LFCSP 16-Lead LFCSP 16-Lead LFCSP 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 24-Lead LFCSP 24-Lead LFCSP 24-Lead LFCSP Package Option CP-16-21 CP-16-21 CP-16-21 R-8 R-8 R-8 CP-24-7 CP-24-7 CP-24-7 Z = RoHS Compliant Part. (c)2011-2018 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08452-0-4/18(E) Rev. E | Page 30 of 30 Ordering Quantity 250 5,000 1,500 98 2,500 1,000 250 5,000 1,500 Marking Code H29 H29 H29 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Analog Devices Inc.: ADA4940-1ACP-EBZ ADA4940-1AR-EBZ