October 2002
Copyright © Alliance Semiconductor. All rights reserved.
®
AS7C1026Q
AS7C31026Q
5V/3.3V 64K X 16 CMOS SRAM
10/29/02, v. 0.9.0 Alliance Semiconductor P. 1 of 10
Features
• AS7C1026Q (5V version)
• AS7C31026Q (3 .3V version)
• Industrial and commercial versions
• Organization: 65,536 words × 16 bits
• Center power and ground pins for low noise
•High speed
- 12/15/20 ns address access time
- 6, 7, 8 ns output enable access time
• Low power consumption: ACTIVE
- 1.32W (AS7C1026Q) / max @ 12 ns
- 666mW (AS7C31026Q) / max @ 12 ns
• Low power consumption: STANDBY
- 55 mW (AS7C1026Q) / max CMOS I/O
- 36 mW (AS7C31026Q) / max CMOS I/O
• Latest 6T 0.25 u CMOS technology
• Easy memory expansion with CE, OE inputs
• TTL-compatible, three-state I/O
• JEDEC standard packaging
- 44-pin 400 mil SOJ
- 44-pin TSOP 2
- 48-ball 7 × 11 mm BGA
• ESD protection ≥ 2000 volts
• Latch-up current ≥ 200 mA
Logic block diagram
64K × 16
Array
OE
CE
WE Column decoder
Row decoder
A0
A1
A2
A3
A4
A5
A7
VCC
GND
A8
A9
A10
A11
A12
A13
A14
A15
Control circuit
I/O0–I/O7
I/O8–I/O15
UB
LB
I/O
buffer
A6
Pin and ball arrangement
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
I/O13
I/O12
GND
VCC
I/O11
I/O10
I/O9
I/O8
NC
A8
A9
A10
A11
NC
A0
CE
I/O0
I/O1
I/O2
I/O3
VCC
GND
I/O4
I/O5
I/O6
I/O7
WE
A15
A14
A13
44-Pin SOJ (400 mil), TSOP 2
21
22
A12
NC
UB
LB
I/O15
I/O14
2
A3 3
A2 4
A1
1
A4
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
43
42
41
44 A6
A7
OE
A5
AS7C1026Q
AS7C31026Q
Selection guide -12 -15 -20 Unit
Maximum address access time 12 15 20 ns
Maximum output enable access time 678ns
Maximum operating current AS7C1026Q 235 230 220 mA
AS7C31026Q 180 175 170 mA
Maximum CMOS standby current AS7C1026Q 10 10 10 mA
AS7C31026Q 5 5 5 mA
0000048 - BGA Ball-Grid-Array Package
123456
ALBOE A0A1A2NC
BI/O8UB A3 A4 CE I/O0
CI/O9
I/O10
A5 A6 I/O1 I/O2
DV
SS
I/O11
NC A7 I/O3 VDD
EV
DD
I/O12
NC NC I/O4 VSS
FI/O14
I/O13
A14 A15 I/O5 I/O6
G I/O15 NC A12 A13 WE I/O7
H NC A8 A9 A10 A11 NC
®
AS7C1026Q
AS7C31026Q
10/29/02, v. 0.9.0 Alliance Semiconductor P. 2 of 10
Functional description
The AS7C1026Q and AS7C31026Q are high-performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) devices organized as
65,536 words × 16 bits. They are designed for memory applications where fast data access, low power, and simple interfacing are desired.
Equal address access and cycle times (tAA, tRC, tWC) of 12/15/20 ns with output enable access times (tOE) of 6, 7, 8 ns are ideal for high-
performance applications.
When CE is high the devices enter standby mode. The AS7C1026Q is guaranteed not to exceed 55 mW power consumption in CMOS standby
mode.
A write cycle is accomplished by asserting write enable (WE) and chip enable (CE). Data on the input pins I/O0–I/O15 is written on the rising
edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been
disabled with output enable (OE) or write enable (WE).
A read cycle is accomplished b y asserting output ena b le (OE) and chip enable (CE), with write enable (WE) high. the chips drive I/O pins with
the data word referenced by the input address. When either chip enable or output enable is inactive, or write enable is active, output drivers
stay in high-impedance mode.
The devices provide multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be written and
read. LB controls the lower bits, I/O0–I/O7, and UB controls the higher bits, I/O8–I/O15.
All chip inputs and outputs are TTL-compatible, and operat ion is from a single 5V supply (AS7C1026Q) or 3.3V supply (AS7C31026Q). the
device is packaged in common industry standard packages. Chip scale BGA packaging, easy to use in manufacturing, provides the smallest
possible footprint. This 48-ball JEDEC-registered package has a ball pitch of 0.75 mm and external dimensions of 7 mm × 11 mm.
Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to abso-
lute maximum rating conditions for extended periods may affect reliability.
Key: H = High, L = Low, X = don’t care.
Absolute maximum ratings
Parameter Symbol Min Max Unit
Voltage on VCC relative to GND AS7C1026Q Vt1 –0.50 +7.0 V
AS7C31026Q Vt1 –0.50 +5.0 V
Voltage on an y pin relative to GND Both Vt2 –0.50 VCC +0.50 V
P ower dissipation Both PD–1.0W
Storage temperature (plastic) Both Tstg –65 +150 °C
Ambient temperature with VCC applied Both Tbias –55 +125 °C
DC current into outputs (low) Both IOUT –20mA
Truth table
CE WE OE LB UB I/O0–I/O7 I/O8–I/O15 Mode
H X X X X High Z High Z Standby (ISB), ISBI)
LHLLHD
OUT High Z Read I/O0–I/O7 (ICC)
LHLHLHigh ZD
OUT Read I/O8–I/O15 (ICC)
LHLLLD
OUT DOUT Read I/O0–I/O15 (ICC)
LLXLLD
IN DIN Write I/O0–I/O15 (ICC)
LLXLHD
IN High Z Write I/O 0–I/O7 (ICC)
LLXHLHigh ZD
IN Write I/O8–I/O15 (ICC)
L
LH
XH
XX
HX
HHigh Z High Z Output disable (ICC)
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AS7C31026Q
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Recommended operating conditions
Parameter Device Symbol Min Nominal Max Unit
Supply voltage AS7C1026Q VCC 4.5 5.0 5.5 V
AS7C31026Q VCC 3.0 3.3 3.6 V
Input voltage AS7C1026Q VIH 2.2 – VCC + 0.5 V
AS7C31026Q VIH 2.0 – VCC + 0.5 V
Both VIL1
1 VIL min. = –3.0V for pulse width less than tRC/2.
–0.5 – 0.8 V
Ambient operating temperature commercial TA0– 70 oC
industrial TA–40 – 85 oC
DC operating characteristics (over the operating range)
Parameter Sym Test conditions Device
-12 -15 -20
UnitMin Max Min Max Min Max
Input leakage
current | ILI | VCC = Max
VIN = GND to VCC Both –1–1–1µA
Output leakage
current | ILO | VCC = Max
CE = VIH,
VOUT = GND to VCC Both –1–1–1µA
Operating pow er
supply current ICC VCC = Max, CE ≤ VIL
outputs open,
f = fMax = 1/tRC
AS7C1026Q – 235 – 230 – 220 mA
AS7C31026Q – 180 – 170 – 160 mA
Standby
power supply
current
ISB VCC = Max, CE ≤ VIL,
outputs open,
f = fMax = 1/tRC
AS7C1026Q – 25 – 20 – 20 mA
AS7C31026Q – 25 – 20 – 20
ISB1 VCC = Max, CE ≥ VCC–0.2V,
VIN ≤ GND + 0.2V or
VIN ≥ VCC–0.2V, f = 0
AS7C1026Q – 10 – 10 – 10 mA
AS7C31026Q – 5 – 5 – 5
Output
voltage VOL IOL = 8 mA, VCC = Min Both –0.4–0.4–0.4V
VOH IOH = –4 mA, VCC = Min 2.4 – 2.4 – 2.4 – V
Capacitance (f = 1MHz, Ta = 25 °C, VCC = NOMINAL)2
Parameter Symbol Signals Test conditions Max Unit
Input capacitance CIN A, CE, WE, OE, LB, UB VIN = 0V 5 pF
I/O capacitance CI/O I/O VIN = VOUT = 0V 7 pF
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AS7C31026Q
10/29/02, v. 0.9.0 Alliance Semiconductor P. 4 of 10
Key to switching waveforms
Read waveform 1 (address controlled)
Read cycle (over the operating range)
Parameter Symbol
-12 -15 -20
Unit NotesMin Max Min Max Min Max
Read cycle time tRC 12 – 15 – 20 – ns
Address access time tAA –12–15–20ns 3
Chip enable (CE) access time tACE –12–15–20ns 3
Output enable (OE) access time tOE –6–7–8ns
Output hold from addr ess change tOH 3–3–3–ns5
CE Low to output in low Z tCLZ 0–0–0–ns4, 5
CE High to output in high Z tCHZ – 3 – 4 – 5 ns 4, 5
OE Low to output in low Z tOLZ 0–0–0–ns4, 5
Byte select access time tBA –6–7–8ns
Byte select Lo w to low Z tBLZ 0–0–0–ns4, 5
Byte select High to high Z tBHZ – 6 – 6 – 8 ns 4, 5
OE High to output in high Z tOHZ – 3 – 4 – 5 ns 4, 5
P ower up time tPU 0–0–0–ns4, 5
P ower down time tPD – 12 – 15 – 20 ns 4, 5
Undefined output/don’t careF alling inputRising input
t
OH
t
AA
t
RC
t
OH
Data
OUT
Address
Data validPrevious data valid
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AS7C31026Q
10/29/02, v. 0.9.0 Alliance Semiconductor P. 5 of 10
Read waveform 2 (OE, CE, UB, LB controlled)
Write cycle (over th e operating range)
Parameter Symbol
-12 -15 -20
Unit NotesMin Max Min Max Min Max
Writ e cycle time tWC 12 – 15 – 20 – ns
Chip enable (CE) to write end tCW 10 – 12 – 12 – ns
Address setup to write end tAW 9 – 10 – 12 – ns
Address setup time tAS 0–0–0–ns
Write pulse width tWP 8–9–12–ns
Write recovery time tWR 0–0–0–ns
Address hold from end of write tAH 0–0–0–ns
Data valid to write end tDW 6–8–10–ns
Data hold time tDH 0–0–0–ns5
Write enable to output in high Z tWZ – 6 – 6 – 8 ns 4, 5
Output activ e from write end tOW 1 – 1 – 2 – ns 4, 5
Byte select low to end of write tBW 10 – 12 – 12 – ns
Data valid
t
RC
t
AA
t
BLZ
t
BA
t
OE
t
OLZ
t
OH
t
OHZ
t
HZ
t
BHZ
t
ACE
t
LZ
Address
OE
CE
LB, UB
Data
IN
AS7C1026Q
AS7C31026Q
®
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Write waveform 1 (WE controlled)
Write waveform 2 (CE controlled)
Address
CE
LB, UB
WE
Data
IN
Data
OUT
t
WC
t
CW
t
BW
t
AW
t
AS
t
WP
t
DW
t
DH
t
OW
t
WZ
t
WR
Data undefined high Z
Data valid
t
AH
Address
CE
LB, UB
WE
Data
IN
t
WC
t
CW
t
BW
t
WP
t
DW
t
DH
t
OW
t
WZ
t
WR
Data
OUT
Data undefined
high Z high Z
t
AS
t
AW
Data valid
t
CLZ
t
AH
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AS7C1026Q
AS7C31026Q
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Data retention characteristics (over the operating range)
Data retention waveform
AC test conditions
Notes
1During V
CC power-up, a pull-up resistor to VCC on CE is required to meet ISB specification.
2 This parameter is sampled, but not 100% tested.
3 For test conditions, see AC Test Conditions, Figures A, B, and C.
4 These parameters are specified with CL = 5pF, as in Figures B or C. Transition is measured ± 500 mV from steady-state voltage.
5 This parameter is guaranteed, but not tested.
6WE
is High for read cycle.
7CE
and OE are Low for read cycle.
8 Address valid prior to or coincident with CE transition Low.
9 A ll read cycle timings are referenced from the last valid address to the first transitioning address.
10 CE or WE must be High during address transitions. Either CE or WE asserting high terminates a write cycle.
11 All write cycle timings are referenced from the last valid address to the first transitioning address.
12 Not applicable.
13 C=30pF, except all high Z and low Z parameters where C=5pF.
Parameter Symbol Test conditions Min Max Unit
VCC for da ta retention VDR VCC = 2.0 V
CS ≥ VCC – 0.2V
VIN ≥ VCC – 0.2V or
VIN ≤ 0.2V
2.0 V - V
Data reten tion current ICCDR – 1000 µA
Chip deselect to data retention ti me tCDR 0–ns
Operation recovery time tRtRC –ns
V
CC
CE
t
R
t
CDR
Data retention mode
4.5 V 4.5 V
V
DR
≥
2.0V
V
IH
V
IH
V
DR
255
Ω
C(14)
320
Ω
GND
+3.3V
Figure C: 3.3V Output load
168
Ω
Thevenin Equivalent:
D
OUT
+1.728V (5V and 3.3V)
255
Ω
C(14)
480
Ω
GND
+5V
Figure B: 5V Output load
10%
90%
10%
90%
GND
+3.0V
Figure A: Input pulse
2 ns
D
OUT
D
OUT
– Output load: see Figure B or Figure C.
– Input pulse level: GND to 3.0V. See Figure A.
– Input rise and fall times: 2 ns. See Figur e A.
– Input and output timing ref erence levels: 1.5V.
AS7C1026Q
AS7C31026Q
®
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Package dimensions
44-pin TSOP 2
Min
(mm) Max
(mm)
A1.2
A1 0.05
A2 0.95 1.05
b0.30 0.45
c0.127 (typical)
D18.28 18.54
E10.03 10.29
He 11.56 11.96
e0.80 (typical)
l0.40 0.60
D
He
1234567891011121314
4443 4241 40 39 38 37 36 35 3433 32 31
15 16
30 29
1718 19 20
28 27 26 25
c
l
A1
A2
e
44-pin TSOP 2
0–5
°
21
24
22
23
E
A
b
Seating
Plane
44-pin SOJ
44-pin SOJ
400 mil
Min (in) Max (in)
A0.128 0.148
A10.025 –
A20.105 1.115
B0.026 0.032
b0.015 0.020
c0.007 0.013
D1.120 1.130
E0.370 NOM
E10.395 0.405
E20.435 0.445
e0.050 NOM
e
Pin 1
A1
b
B
AA2
E2
E1
E2
D
c
®
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AS7C31026Q
10/29/02, v. 0.9.0 Alliance Semiconductor P. 9 of 10
Notes
1 Bump counts: 48 (8 row x 6 column).
2 Pitch: (x,y) = 0.75 mm x 0.75 mm (typ).
3 Units: millimeters.
4 All tolerance are ± 0.050 unless otherwise specified.
5 Typ: typical.
6 Y is coplanarity: 0.08 (max).
Minimum Typical Maximum
A–0.75–
B6.90 7.00 7.10
B1 –3.75–
C10.90 11.00 11.10
C1 –5.25–
D0.30 0.35 0.40
E– – 1.20
E1 –0.68–
E2 0.22 0.25 0.27
Y– – 0.08
48-ball BGA
Bottom Vie w
Side Vie w
Top View
Detail View
A
Y
Die
0.3/Typ
E2
E
Die
D
E1
E2
E
Ball #A1 Ball #A1 index
123456
A
C
D
E
F
G
H
B
A
A
B1
C1 SRAM Die C
Elastomer
B
®
AS7C1026Q
AS7C31026Q
© C o py rig h t A llia nc e S emico n du cto r C o rp o ratio n . A ll rig h ts re serv ed . O u r th r ee- po in t log o , ou r n ame a nd In te lliw att a re trad emar ks o r re gi stere d trad emar ks of A llian ce . A ll o the r b ra nd an d
p
ro du c t na m es m a y b e th e tr ad emar ks o f th eir resp e ctiv e co mpa nie s. A llia nc e r eser v es th e ri gh t to mak e c h an ge s to this d o cu m e nt a n d its p ro d u cts at a n y time w ith o u t n otic e. A llian c e as su me s no
responsibility for any errors that m ay appear in this docum ent. The data contain ed herein represents Alliance’s b est data and/or estim ates at the tim e of issuan ce. A lliance reserv es the right to
ch an g e o r co rr ect th is d ata at an y tim e , w ith o ut n ot ice. If th e p ro du c t de scr ibe d h er ein is u nd er de ve lop men t, sig n ifica nt c ha ng es to th ese sp ecif icat ion s ar e p o ssible . T h e in fo rmatio n in th is
p
ro du c t da ta sh ee t is inte n de d to be g en era l de scr iptiv e in f ormat ion fo r p ote nt ial cu sto mers a n d u ser s, an d is no t in ten de d to o perate as, or provide, any guarantee or warrantee to any user or
cu stome r. A llia nc e d o es n ot a ssu m e an y re sp on sib ility or liab ility a risin g ou t of the ap p licat ion or use of an y pro d uc t de scr ibe d h er ein , an d disc laims a ny ex p ress o r im p lied w a rran tie s re lated to
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against all claim s arising from such use.
10/29/02, v. 0.9.0 Alliance Semiconductor P. 10 of 10
Ordering codes
P a ckage \ Access time Volt/Temp 12 ns 15 ns 20 ns
Plastic SOJ, 400 mil 5V commercial AS7C1026Q-12JC AS7C1026Q-15JC AS7C1026Q-20JC
5V industrial AS7C1026Q-12JI AS7C1026Q-15JI AS7C1026Q-20JI
3.3V commercial AS7C31026Q-12JC AS7C31026Q-15JC AS7C31026Q-20JC
TSOP 2, 10.2 x 18.4 mm 5V commercial AS7C1026Q-12TC AS7C1026Q-15TC AS7C1026Q-20TC
3.3V commercial AS7C31026Q-12TC AS7C31026Q-15TC AS7C31026Q-20TC
3.3V industrial AS7C31026Q-12TI AS7C31026Q-15TI AS7C31026Q-20TI
BGA, 7 x 11 mm 5V commercial AS7C1026Q-12BC AS7C1026Q-15BC AS7C1026Q-20BC
3.3V commercial AS7C31026Q-12BC AS7C31026Q-15BC AS7C31026Q-20BC
3.3V industrial AS7C31026Q-12BI AS7C31026Q-15BI AS7C31026Q-20BI
Part numbering system
AS7C X1026Q –XX X C
SRAM
prefix
Voltage:
Blank=5V CMOS
3=3.3V CMOS
Device
number Access
time
Package:
J=SOJ 400 mil
T=TSOP 2, 10.2 x 18.4 mm
B=BGA, 7 x 11 mm
Temperature range:
C= Commercial: 0° C to 70° C
I= Industrial: -40° C to 85° C
