October 2002 AS7C1026Q AS7C31026Q (R) 5V/3.3V 64K X 16 CMOS SRAM Features * AS7C1026Q (5V version) * AS7C31026Q (3.3V version) * Industrial and commercial versions * Organization: 65,536 words x 16 bits * Center power and ground pins for low noise * High speed - 12/15/20 ns address access time - 6, 7, 8 ns output enable access time * Low power consumption: ACTIVE * Low power consumption: STANDBY - 55 mW (AS7C1026Q) / max CMOS I/O - 36 mW (AS7C31026Q) / max CMOS I/O * Latest 6T 0.25u CMOS technology * Easy memory expansion with CE, OE inputs * TTL-compatible, three-state I/O * JEDEC standard packaging - 44-pin 400 mil SOJ - 44-pin TSOP 2 - 48-ball 7 x 11 mm BGA - 1.32W (AS7C1026Q) / max @ 12 ns - 666mW (AS7C31026Q) / max @ 12 ns * ESD protection 2000 volts * Latch-up current 200 mA Pin and ball arrangement Logic block diagram 44-Pin SOJ (400 mil), TSOP 2 A0 A3 A4 A5 A6 VCC 64K x 16 Array GND A7 I/O buffer Control circuit UB OE LB CE A15 A14 A13 A12 A11 A8 A9 Column decoder WE A10 I/O0-I/O7 I/O8-I/O15 0000048 - BGA Ball-Grid-Array Package A4 A3 A2 A1 A0 CE I/O0 I/O1 I/O2 I/O3 VCC GND I/O4 I/O5 I/O6 I/O7 WE A15 A14 A13 A12 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 AS7C1026Q AS7C31026Q A2 Row decoder A1 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE UB LB I/O15 I/O14 I/O13 I/O12 GND VCC I/O11 I/O10 I/O9 I/O8 NC A8 A9 A10 A11 NC A B C D E F G H 1 LB I/O8 I/O9 VSS VDD I/O14 I/O15 NC 2 OE UB I/O10 I/O11 I/O12 I/O13 NC A8 3 A0 A3 A5 NC NC A14 A12 A9 4 A1 A4 A6 A7 NC A15 A13 A10 5 A2 CE I/O1 I/O3 I/O4 I/O5 WE A11 6 NC I/O0 I/O2 VDD VSS I/O6 I/O7 NC Selection guide -12 -15 -20 Unit Maximum address access time 12 15 20 ns Maximum output enable access time 6 7 8 ns AS7C1026Q 235 230 220 mA AS7C31026Q 180 175 170 mA AS7C1026Q 10 10 10 mA AS7C31026Q 5 5 5 mA Maximum operating current Maximum CMOS standby current 10/29/02, v. 0.9.0 Alliance Semiconductor P. 1 of 10 Copyright (c) Alliance Semiconductor. All rights reserved. AS7C1026Q AS7C31026Q (R) Functional description The AS7C1026Q and AS7C31026Q are high-performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) devices organized as 65,536 words x 16 bits. They are designed for memory applications where fast data access, low power, and simple interfacing are desired. Equal address access and cycle times (tAA, tRC, tWC) of 12/15/20 ns with output enable access times (tOE) of 6, 7, 8 ns are ideal for highperformance applications. When CE is high the devices enter standby mode. The AS7C1026Q is guaranteed not to exceed 55 mW power consumption in CMOS standby mode. A write cycle is accomplished by asserting write enable (WE) and chip enable (CE). Data on the input pins I/O0-I/O15 is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE). A read cycle is accomplished by asserting output enable (OE) and chip enable (CE), with write enable (WE) high. the chips drive I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or write enable is active, output drivers stay in high-impedance mode. The devices provide multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be written and read. LB controls the lower bits, I/O0-I/O7, and UB controls the higher bits, I/O8-I/O15. All chip inputs and outputs are TTL-compatible, and operation is from a single 5V supply (AS7C1026Q) or 3.3V supply (AS7C31026Q). the device is packaged in common industry standard packages. Chip scale BGA packaging, easy to use in manufacturing, provides the smallest possible footprint. This 48-ball JEDEC-registered package has a ball pitch of 0.75 mm and external dimensions of 7 mm x 11 mm. Absolute maximum ratings Parameter Symbol Min Max Unit AS7C1026Q Vt1 -0.50 +7.0 V AS7C31026Q Vt1 -0.50 +5.0 V Voltage on any pin relative to GND Both Vt2 -0.50 VCC +0.50 V Power dissipation Both PD - 1.0 W Storage temperature (plastic) Both Tstg -65 +150 C Ambient temperature with VCC applied Both Tbias -55 +125 C DC current into outputs (low) Both IOUT - 20 mA Voltage on VCC relative to GND Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Truth table CE WE OE LB UB I/O0-I/O7 I/O8-I/O15 Mode H X X X X High Z High Z Standby (ISB), ISBI) L H L L H DOUT High Z Read I/O0-I/O7 (ICC) L H L H L High Z DOUT Read I/O8-I/O15 (ICC) L H L L L DOUT DOUT Read I/O0-I/O15 (ICC) L L X L L DIN DIN Write I/O0-I/O15 (ICC) L L X L H DIN High Z Write I/O0-I/O7 (ICC) L L X H L High Z DIN Write I/O8-I/O15 (ICC) L L H X H X X H X H High Z High Z Output disable (ICC) Key: H = High, L = Low, X = don't care. 10/29/02, v. 0.9.0 Alliance Semiconductor P. 2 of 10 AS7C1026Q AS7C31026Q (R) Recommended operating conditions Parameter Supply voltage Input voltage Device Symbol Min Nominal Max Unit AS7C1026Q VCC 4.5 5.0 5.5 V AS7C31026Q VCC 3.0 3.3 3.6 V AS7C1026Q VIH 2.2 - VCC + 0.5 V AS7C31026Q VIH 2.0 - VCC + 0.5 V -0.5 - 0.8 V 70 o C 85 o C Both Ambient operating temperature commercial industrial VIL 1 TA 0 - -40 TA - 1 VIL min. = -3.0V for pulse width less than tRC/2. DC operating characteristics (over the operating range) -12 Parameter -15 -20 Sym Test conditions Device Min Max Min Max Min Max Unit Input leakage current | ILI | VCC = Max VIN = GND to VCC Both - 1 - 1 - 1 A Output leakage current | ILO | VCC = Max CE = VIH, VOUT = GND to VCC Both - 1 - 1 - 1 A VCC = Max, CE VIL outputs open, f = fMax = 1/tRC AS7C1026Q - 235 - 230 - 220 mA ICC AS7C31026Q - 180 - 170 - 160 mA VCC = Max, CE VIL, outputs open, f = fMax = 1/tRC AS7C1026Q - 25 - 20 - 20 ISB AS7C31026Q - 25 - 20 - 20 VCC = Max, CE VCC-0.2V, VIN GND + 0.2V or VIN VCC-0.2V, f = 0 AS7C1026Q - 10 - 10 - 10 ISB1 AS7C31026Q - 5 - 5 - 5 - 0.4 - 0.4 - 0.4 V 2.4 - 2.4 - 2.4 - V Operating power supply current Standby power supply current Output voltage VOL IOL = 8 mA, VCC = Min VOH IOH = -4 mA, VCC = Min Both mA mA Capacitance (f = 1MHz, Ta = 25 C, VCC = NOMINAL)2 Parameter Symbol Signals Test conditions Max Unit Input capacitance CIN A, CE, WE, OE, LB, UB VIN = 0V 5 pF I/O capacitance CI/O I/O VIN = VOUT = 0V 7 pF 10/29/02, v. 0.9.0 Alliance Semiconductor P. 3 of 10 AS7C1026Q AS7C31026Q (R) Read cycle (over the operating range) -12 Parameter -15 -20 Symbol Min Max Min Max Min Max Unit Notes Read cycle time tRC 12 - 15 - 20 - ns Address access time tAA - 12 - 15 - 20 ns 3 Chip enable (CE) access time tACE - 12 - 15 - 20 ns 3 Output enable (OE) access time tOE - 6 - 7 - 8 ns Output hold from address change tOH 3 - 3 - 3 - ns 5 CE Low to output in low Z tCLZ 0 - 0 - 0 - ns 4, 5 CE High to output in high Z tCHZ - 3 - 4 - 5 ns 4, 5 OE Low to output in low Z tOLZ 0 - 0 - 0 - ns 4, 5 Byte select access time tBA - 6 - 7 - 8 ns Byte select Low to low Z tBLZ 0 - 0 - 0 - ns 4, 5 Byte select High to high Z tBHZ - 6 - 6 - 8 ns 4, 5 OE High to output in high Z tOHZ - 3 - 4 - 5 ns 4, 5 Power up time tPU 0 - 0 - 0 - ns 4, 5 Power down time tPD - 12 - 15 - 20 ns 4, 5 Key to switching waveforms Rising input Falling input Undefined output/don't care Read waveform 1 (address controlled) tRC Address DataOUT 10/29/02, v. 0.9.0 tOH Previous data valid tAA tOH Data valid Alliance Semiconductor P. 4 of 10 AS7C1026Q AS7C31026Q (R) Read waveform 2 (OE, CE, UB, LB controlled) tRC Address tAA OE tOE tOLZ tOH CE tLZ tOHZ tACE tHZ LB, UB tBA tBLZ tBHZ DataIN Data valid Write cycle (over the operating range) -12 Parameter -15 -20 Symbol Min Max Min Max Min Max Unit Write cycle time tWC 12 - 15 - 20 - ns Chip enable (CE) to write end tCW 10 - 12 - 12 - ns Address setup to write end tAW 9 - 10 - 12 - ns Address setup time tAS 0 - 0 - 0 - ns Write pulse width tWP 8 - 9 - 12 - ns Write recovery time tWR 0 - 0 - 0 - ns Address hold from end of write tAH 0 - 0 - 0 - ns Data valid to write end tDW 6 - 8 - 10 - ns Data hold time tDH 0 - 0 - 0 - ns 5 Write enable to output in high Z tWZ - 6 - 6 - 8 ns 4, 5 Output active from write end tOW 1 - 1 - 2 - ns 4, 5 Byte select low to end of write tBW 10 - 12 - 12 - ns 10/29/02, v. 0.9.0 Alliance Semiconductor Notes P. 5 of 10 AS7C1026Q AS7C31026Q (R) Write waveform 1 (WE controlled) tWC tAH Address tWR tCW CE tBW LB, UB tAW tAS tWP WE tDW DataIN tDH Data valid tWZ DataOUT tOW Data undefined high Z Write waveform 2 (CE controlled) tWC tAH Address tAS CE tWR tCW tAW tBW LB, UB tWP WE tDH tDW Data valid DataIN tCLZ DataOUT 10/29/02, v. 0.9.0 high Z tWZ Data undefined Alliance Semiconductor tOW high Z P. 6 of 10 AS7C1026Q AS7C31026Q (R) Data retention characteristics (over the operating range) Parameter Symbol VCC for data retention VDR Data retention current ICCDR Chip deselect to data retention time tCDR Operation recovery time Test conditions VCC = 2.0 V CS VCC - 0.2V VIN VCC - 0.2V or VIN 0.2V tR Min Max Unit 2.0 V - V - 1000 A 0 - ns tRC - ns Data retention waveform Data retention mode VCC VDR 2.0V 4.5 V 4.5 V tCDR tR VDR VIH CE VIH AC test conditions - - - - Output load: see Figure B or Figure C. Input pulse level: GND to 3.0V. See Figure A. Input rise and fall times: 2 ns. See Figure A. Input and output timing reference levels: 1.5V. Thevenin Equivalent: 168 DOUT +1.728V (5V and 3.3V) +3.3V +5V 320 480 +3.0V GND DOUT DOUT 90% 10% 90% 2 ns Figure A: Input pulse 10% 255 C(14) GND Figure B: 5V Output load 255 C(14) GND Figure C: 3.3V Output load Notes 1 2 3 4 5 6 7 8 9 10 11 12 13 During VCC power-up, a pull-up resistor to VCC on CE is required to meet ISB specification. This parameter is sampled, but not 100% tested. For test conditions, see AC Test Conditions, Figures A, B, and C. These parameters are specified with CL = 5pF, as in Figures B or C. Transition is measured 500 mV from steady-state voltage. This parameter is guaranteed, but not tested. WE is High for read cycle. CE and OE are Low for read cycle. Address valid prior to or coincident with CE transition Low. All read cycle timings are referenced from the last valid address to the first transitioning address. CE or WE must be High during address transitions. Either CE or WE asserting high terminates a write cycle. All write cycle timings are referenced from the last valid address to the first transitioning address. Not applicable. C=30pF, except all high Z and low Z parameters where C=5pF. 10/29/02, v. 0.9.0 Alliance Semiconductor P. 7 of 10 AS7C1026Q AS7C31026Q (R) Package dimensions c 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 44-pin TSOP 2 Min (mm) A E He 44-pin TSOP 2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 D l A2 A 0-5 A1 e b Max (mm) 1.2 A1 0.05 A2 0.95 1.05 b 0.30 0.45 c 0.127 (typical) D 18.28 18.54 E 10.03 10.29 He 11.56 11.96 e l 0.80 (typical) 0.40 0.60 44-pin SOJ 400 mil D e Min (in) Max (in) 44-pin SOJ E1 E2 Pin 1 c B A2 A A1 b Seating Plane E2 A 0.128 0.148 A1 0.025 - A2 0.105 1.115 B 0.026 0.032 b 0.015 0.020 c 0.007 0.013 D 1.120 1.130 E E1 0.395 0.405 E2 0.435 0.445 e 10/29/02, v. 0.9.0 Alliance Semiconductor 0.370 NOM 0.050 NOM P. 8 of 10 AS7C1026Q AS7C31026Q (R) 48-ball BGA Bottom View 6 5 4 3 Top View 2 1 Ball #A1 index Ball #A1 A B C D SRAM Die C1 C E F A G H Elastomer A B B1 Detail View Side View A E2 D E E2 Y E Die Die E1 0.3/Typ Minimum Typical Maximum A - 0.75 - B 6.90 7.00 7.10 B1 - 3.75 - C 10.90 11.00 11.10 C1 - 5.25 - D 0.30 0.35 0.40 E - - 1.20 E1 - 0.68 - E2 0.22 0.25 0.27 Y - - 0.08 10/29/02, v. 0.9.0 Notes 1 Bump counts: 48 (8 row x 6 column). 2 Pitch: (x,y) = 0.75 mm x 0.75 mm (typ). 3 Units: millimeters. 4 All tolerance are 0.050 unless otherwise specified. 5 Typ: typical. 6 Y is coplanarity: 0.08 (max). Alliance Semiconductor P. 9 of 10 AS7C1026Q AS7C31026Q (R) Ordering codes Package \ Access time Plastic SOJ, 400 mil TSOP 2, 10.2 x 18.4 mm BGA, 7 x 11 mm Volt/Temp 12 ns 15 ns 20 ns 5V commercial AS7C1026Q-12JC AS7C1026Q-15JC AS7C1026Q-20JC 5V industrial AS7C1026Q-12JI AS7C1026Q-15JI AS7C1026Q-20JI 3.3V commercial AS7C31026Q-12JC AS7C31026Q-15JC AS7C31026Q-20JC 5V commercial AS7C1026Q-12TC AS7C1026Q-15TC AS7C1026Q-20TC 3.3V commercial AS7C31026Q-12TC AS7C31026Q-15TC AS7C31026Q-20TC 3.3V industrial AS7C31026Q-12TI AS7C31026Q-15TI AS7C31026Q-20TI 5V commercial AS7C1026Q-12BC AS7C1026Q-15BC AS7C1026Q-20BC 3.3V commercial AS7C31026Q-12BC AS7C31026Q-15BC AS7C31026Q-20BC 3.3V industrial AS7C31026Q-12BI AS7C31026Q-15BI AS7C31026Q-20BI Part numbering system AS7C X Voltage: SRAM Blank=5V CMOS prefix 3=3.3V CMOS 10/29/02, v. 0.9.0 1026Q Device number -XX X Package: Access J=SOJ 400 mil time T=TSOP 2, 10.2 x 18.4 mm B=BGA, 7 x 11 mm Alliance Semiconductor C Temperature range: C= Commercial: 0 C to 70 C I= Industrial: -40 C to 85 C P. 10 of 10 (c) Copyright A lliance Sem iconductor Corporation. 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