Semiconductor Components Industries, LLC, 2010
November, 2010 -- Rev. 11
1Publication Order Number:
MC33260/D
MC33260
GreenLinetCompact
Power Factor Controller:
Innovative Circuit for
Cost Effective Solutions
The MC33260 is a controller for Power Factor Correction
preconverters meeting international standard requirements in
electronic ballast and off--line power conversion applications.
Designed to drive a free frequency discontinuous mode, it can also be
synchronized and in any case, it features very effective protections that
ensure a safe and reliable operation.
This circuit is also optimized to offer extremely compact and cost
effective PFC solutions. While it requires a minimum number of
external components, the MC33260 can control the follower boost
operation that is an innovative mode allowing a drastic size reduction
of both the inductor and the power switch. Ultimately, the solution
system cost is significantly lowered.
Also able to function in a traditional way (constant output voltage
regulation level), any intermediary solutions can be easily
implemented. This flexibility makes it ideal to optimally cope with a
wide range of applications.
General Features
Standard Constant Output Voltage or “Follower Boost” Mode
Switch Mode Operation: Voltage Mode
Latching PWM for Cycle--by--Cycle On--Time Control
Constant On--Time Operation That Saves the Use of an Extra Multiplier
Totem Pole Output Gate Drive
Undervoltage Lockout with Hysteresis
Low Startup and Operating Current
Improved Regulation Block Dynamic Behavior
Synchronization Capability
Internally Trimmed Reference Current Source
These are Pb--Free Devices
Safety Features
Overvoltage Protection: Output Overvoltage Detection
Undervoltage Protection: Protection Against Open Loop
Effective Zero Current Detection
Accurate and Adjustable Maximum On--Time Limitation
Overcurrent Protection
ESD Protection on Each Pin
Figure 1. Typical Application
8
Filtering
Capacitor L1
CT
M1
D1
D1...D4
VCC
C1
+
Sync
Vcontrol
ROCP
Rcs
Ro
7
6
5
1
2
3
4
LOAD
(SMPS, Lamp
Ballast,...)
MC33260
DIP--8 CONFIGURATION SHOWN
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MC33260P
PIN CONNECTIONS
18
7
6
5
2
3
4
Feedback Input
Vcontrol
Oscillator
Capacitor (CT)
VCC
Current Sense
Input
Synchronization
Input
Gnd
Gate Drive
PDIP--8
P SUFFIX
CASE 626
1
8
SO--8
D SUFFIX
CASE 751
1
8
MARKING
DIAGRAMS
33260
ALYW
G
1
8
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
GorG= Pb--Free Package
18
7
6
5
2
3
4
Feedback Input
Vcontrol
Oscillator
Capacitor (CT)
VCC
Current Sense
Input
Synchronization
Input
Gnd Gate Drive
MC33260D
See detailed ordering and shipping information in the package
dimensions section on page 20 of this data sheet.
ORDERING INFORMATION
MC33260P
AWL
YYWWG
MC33260
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Figure 2. Block Diagram
15 pF
11 V
Current
Mirror
Current Mirror
Io
IoIoIref
11 V
300 k
Vreg
r
r
r
--
+
CT
FB
Vo
Vcontrol
REGULATOR
Enable
11 V/8.5 V
Synchro
Arrangement
11 V
R
R
RQ
Q
S
PWM
Latch
ThStdwn
--
+
11 V
LEB
--
+
Output_Ctrl
--
+
--
+
-- 6 0 m V
Iuvp
OVP
UVP
IovpH/IovpL
Ics (205 mA)
Synchro
VCC
Drive
Gnd
Output_Ctrl
MC33260
Current
Sense
Vref
Iref
01
01
PWM Comparator
Output_Ctrl
Io
1.5 V
97%Iref Iref
Vref
Io
IOSC -- c h = Iref
2xI
OxI
O
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MAXIMUM RATINGS
Rating
Pin #
PDIP--8
Pin #
SO--8 Symbol Value Unit
Gate Drive Current*
Source
Sink
7 5
IO(Source)
IO(Sink)
--500
500
mA
VCC Maximum Voltage 8 6 (Vcc)max 16 V
Input Voltage Vin --0.3to+10 V
Power Dissipation and Thermal Characteristics
P Suffix, PDIP Package
Maximum Power Dissipation @ TA=85C
Thermal Resistance Junction--to--Air
PD
RθJA
600
100
mW
C/W
Operating Junction Temperature TJ150 C
Operating Ambient Temperature TA--40 to +105 C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
ELECTRICAL CHARACTERISTICS (VCC =13V,T
J=25C for typical values, TJ=--40to105C for min/max values
unless otherwise noted.)
Characteristic
Pin #
PDIP--8
Pin #
SO--8 Symbol Min Typ Max Unit
GATE DRIVE SECTION
Gate Drive Resistor
Source Resistor @ IDrive = 100 mA
Sink Resistor @ IDrive = 100 mA
7 5
ROL
ROH
10
5
20
10
35
25
Ω
Gate Drive Voltage Rise Time (From 3.0 V Up to 9.0 V)
(Note 1)
7 5 tr-- 50 -- ns
Output Voltage Falling Time (From 9.0 V Down to 3.0 V)
(Note 1)
7 5 tf-- 50 -- ns
OSCILLATOR SECTION
Maximum Oscillator Swing 3 1 ΔVT1.4 1.5 1.6 V
Charge Current @ IFB = 100 mA3 1 Icharge 87.5 100 112.5 mA
Charge Current @ IFB = 200 mA3 1 Icharge 350 400 450 mA
Ratio Multiplier Gain Over Maximum Swing
@I
FB = 100 mA
3 1 Kosc 5600 6400 7200 1/(V.A)
Ratio Multiplier Gain Over Maximum Swing
@I
FB = 200 mA
3 1 Kosc 5600 6400 7200 1/(V.A)
Average Internal Oscillator Pin Capacitance Over
Oscillator Maximum Swing (CTVoltage Varying From
0Upto1.5V)(Note2)
3 1 Cint 10 15 20 pF
Discharge Time (CT=1.0nF) 3 1 Tdisch -- 0.5 1.0 ms
REGULATION SECTION
Regulation High Current Reference 1 7 IregH 192 200 208 mA
Ratio (Regulation Low Current Reference) / IregH 1 7 IregL /I
regH 0.965 0.97 0.98 --
Vcontrol Impedance 1 7 ZVcontrol -- 300 -- kΩ
NOTE: IFB is the current that is drawn by the Feedback Input Pin.
1. 1.0 nF being connected between the Pin 7 and ground for PDIP--8, between Pin 5 and ground for SO--8.
2. Guaranteed by design.
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ELECTRICAL CHARACTERISTICS (VCC =13V,T
J=25C for typical values, TJ=--40to105C for min/max values
unless otherwise noted.)
Characteristic
Pin #
PDIP--8
Pin #
SO--8 Symbol Min Typ Max Unit
REGULATION SECTION (continued)
Feedback Pin Clamp Voltage @ IFB = 100 mA17VFB--100 1.5 2.1 2.5 V
Feedback Pin Clamp Voltage @ IFB = 200 mA17VFB--200 2.0 2.6 3.0 V
CURRENT SENSE SECTION
Zero Current Detection Comparator Threshold 4 2 VZCD--th -- 9 0 -- 6 0 -- 3 0 mV
Negative Clamp Level (ICS--pin =--1.0mA) 4 2 Cl--neg -- -- 0 . 7 -- V
Bias Current @ Vcs = VZCD--th 4 2 Ib--cs -- 0 . 2 -- -- mA
Propagation Delay (Vcs > VZCD--th)toGateDriveHigh 7 5 TZCD -- 500 -- ns
Current Sense Pin Internal Current Source 4 2 IOCP 192 205 218 mA
Leading Edge Blanking Duration LEB -- 400 -- ns
OverCurrent Protection Propagation Delay
(Vcs < VZCD--th to Gate Drive Low)
7 5 TOCP 100 160 240 ns
SYNCHRONIZATION SECTION
Synchronization Threshold
PDIP--8
SO--8
5
--
--
3
Vsync--th
Vsync--th
0.8
0.8
1.0
1.0
1.2
1.4
V
V
Negative Clamp Level (Isync =--1.0mA) 5 3 Cl--neg -- -- 0 . 7 -- V
Minimum Off--Time 7 5 Toff 1.5 2.1 2.7 ms
Minimum Required Synchronization Pulse Duration 5 3 Tsync -- -- 0.5 ms
OVERVOLTAGE PROTECTION SECTION
OverVoltage Protection High Current Threshold
and IregH Difference
1 7 IOVPH-- I regH 8.0 13 18 mA
OverVoltage Protection Low Current Threshold
and IregH Difference
1 7 IOVPL-- I regH 0-- -- --
Ratio (IOVPH/IOVPL) 1 7 IOVPH /I
OVPL 1.02 -- -- --
Propagation Delay (IFB > 110% Iref to Gate Drive Low) 7 5 TOVP -- 500 -- ns
UNDERVOLTAGE PROTECTION SECTION
Ratio (UnderVoltage Protection Current
Threshold) / IregH
1 7 IUVP/IregH 12 14 16 %
Propagation Delay (IFB < 12% Iref to Gate Drive Low) 7 5 TUVP -- 500 -- ns
THERMAL SHUTDOWN SECTION
Thermal Shutdown Threshold 7 5 Tstdwn —150 -- C
Hysteresis 7 5 ΔTstdwn -- 30 -- C
VCC UNDERVOLTAGE LOCKOUT SECTION
Startup Threshold 8 6 Vstup--th 9.7 11 12.3 V
Disable Voltage After Threshold Turn--On 8 6 Vdisable 7.4 8.5 9.6 V
TOTAL DEVICE
Power Supply Current
Startup (VCC =5VwithV
CC Increasing)
Operating @ IFB = 200 mA
8 6 ICC
--
--
0.1
4.0
0.25
8.0
mA
NOTE: Vcs is the Current Sense Pin Voltage and IFB is the Feedback Pin Current.
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Pin Numbers are Relevant to the PDIP--8 Version
0
3.5
20 40 60 80 100 120 140 160 180 200 220 240
0
0.5
1.0
1.5
2.0
2.5
3.0
JUNCTION TEMPERATURE (C)
Ipin1: FEEDBACK CURRENT (mA)
Ipin1: FEEDBACK CURRENT (mA)
Figure 3. Regulation Block Output versus
Feedback Current
Ipin1: FEEDBACK CURRENT (mA)
Figure 4. Regulation Block Output versus
Feedback Current
Figure 5. Maximum Oscillator Swing versus
Temperature
Figure 6. Feedback Input Voltage versus
Feedback Current
Figure 7. Oscillator Charge Current versus
Feedback Current
Figure 8. Oscillator Charge Current versus
Temperature
MAXIMUM OSCILLATOR SWING (V)I , OSCILLATOR CHARGE CURRENT ( A)
osc--ch V : REGULATION BLOCK OUTPUT (V)
control
FEEDBACK INPUT VOLTAGE (V) V : REGULATION BLOCK OUTPUT (V)
control
JUNCTION TEMPERATURE (C)
Ipin1: FEEDBACK CURRENT (mA)
0
1.6
-- 4 0 C
25C
105C
20 40 60 80 100 120 140 160 180 200 220 240
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
185
1.6
190 195 200 205 210
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
1.340
--40 --20 0 20 40 60 80 100
1.335
1.330
1.325
1.320
1.315
1.310
1.305
1.300
0
500
20 40 60 80 100 120 140 160 180 200 220 240
0
50
100
150
200
250
300
350
400
450
-- 4 0
410
-- 2 0 0 20 40 60 80 100
405
400
395
390
385
Ipin1 = 200 mA
-- 4 0 C
25C
105C
-- 4 0 C
25C
105C
-- 4 0 C
25C
105C
m
I , OSCILLATOR CHARGE CURRENT ( A)
osc--ch m
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Pin Numbers are Relevant to the PDIP--8 Version
-- 4 0
0.150
-- 4 0
207
30
120
50
75
-- 4 0
104
ON--TIME ( s)
OSCILLATOR CHARGE CURRENT ( A)
Figure 9. Oscillator Charge Current versus
Temperature
Figure 10. On--Time versus Feedback Current
Figure 11. On--Time versus Feedback Current Figure 12. Internal Current Sources versus
Temperature
Figure 13. (IovpH/Iref), (IovpL/Iref), (IregL/Iref)
versus Temperature
Figure 14. Undervoltage Ratio versus
Temperature
Ipin1: FEEDBACK CURRENT (mA)
Ipin1: FEEDBACK CURRENT (mA)
TJ, JUNCTION TEMPERATURE (C)
TJ, JUNCTION TEMPERATURE (C)
TJ, JUNCTION TEMPERATURE (C)
--20 0 20 40 60 80 100
103
102
101
100
99
98
97
50 70 90 110 130 150 170 190 210
100
80
60
40
20
0
60 70 80 90 100
65
55
45
35
25
15 --20 0 20 40 60 80 100
197
198
199
200
201
202
203
204
205
206
--20 0 20 40 60 80 100
0.140
0.130
0.132
0.134
0.136
0.138
0.142
0.144
0.146
0.148
Ipin1 = 100 mA-- 4 0 C
25C
105C
1 nF Connected to Pin 3
ON--TIME ( s)
-- 4 0 C
25C
105C
1 nF Connected to Pin 3
IOCP
IregH
REGULATION AND CS CURRENT SOURCE ( A)
UNDERVOLTAGE RATIO (I uvp/I )
ref
-- 4 0
1.07
TJ, JUNCTION TEMPERATURE (C)
--20 0 20 40 60 80 100
0.96
0.97
0.98
0.99
1.00
1.01
1.02
1.03
1.04
1.05
1.06
(IovpH /Iref ), (I ovpL /Iref ), (I regL/Iref )
(IovpH/Iref)
(IovpL/Iref)
(IregL/Iref)
MC33260
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Pin Numbers are Relevant to the PDIP--8 Version
Ch1
1
0
4.5
0
20
-- 4 0
--54.8
VCC: SUPPLY VOLTAGE (V)
Vcontrol: PIN 2 VOLTAGE (V)
Figure 15. Current Sense Threshold versus
Temperature
Figure 16. Circuit Consumption versus
Supply Voltage
Figure 17. Oscillator Pin Internal Capacitance Figure 18. Gate Drive Cross Conduction
Figure 19. Gate Drive Cross Conduction Figure 20. Gate Drive Cross Conduction
TJ, JUNCTION TEMPERATURE (C)
--20 0 20 40 60 80 100
-- 5 5
--55.2
--55.4
--55.6
--55.8
-- 5 6
--56.2
--56.4
--56.6
2 4 6 8 10 12 14 16
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
, CIRCUIT CONSUMPTION (mA)ICC
0.2 0.4 0.6 0.8 1.0 1.2 1.4
15
10
5
0
OSCILLATOR PIN INTERNAL CAPACITANCE (pF) CURRENT SENSE THRESHOLD (mV)
-- 4 0 C
25C
105C
-- 4 0 C
25C
105C
10.0 V Ch2
2
10.0 mVΩM1.00ms Ch1 600 mV
Ch1
1
10.0 V Ch2
2
10.0 mVΩM1.00ms Ch1 600 mV Ch1
1
10.0 V Ch2
2
10.0 mVΩM1.00ms Ch1 600 mV
Vgate
Icross--cond (50 mA/div)
25C
VCC =12V
Cgate =1nF
Vgate
Icross--cond (50 mA/div)
105C
VCC =12V
Cgate =1nF
Vgate
Icross--cond (50 mA/div)
-- 4 0 C
VCC =12V
Cgate =1nF
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PIN FUNCTION DESCRIPTION
Pin #
PDIP--8
Pin #
SO--8 Function Description
1 7 Feedback Input This pin is designed to receive a current that is proportional to the preconverter output
voltage. This information is used for both the regulation and the overvoltage and
undervoltage protections. The current drawn by this pin is internally squared to be used
as oscillator capacitor charge current.
2 8 Vcontrol This pin makes available the regulation block output. The capacitor connected between
this pin and ground, adjusts the control bandwidth. It is typically set below 20 Hz to
obtain a nondistorted input current.
3 1 Oscillator Capacitor
(CT)
The circuit uses an on--time control mode. This on--time is controlled by comparing the
CTvoltage to the Vcontrol voltage. CTis charged by the squared feedback current.
4 2 Zero Current
Detection Input
This pin is designed to receive a negative voltage signal proportional to the current
flowing through the inductor. This information is generally built using a sense resistor.
The Zero Current Detection prevents any restart as long as the Pin 4 voltage is below
(--60 mV). This pin is also used to perform the peak current limitation. The overcurrent
threshold is programmed by the resistor connected between the pin and the external
current sense resistor.
5 3 Synchronization
Input
This pin is designed to receive a synchronization signal. For instance, it enables to
synchronize the PFC preconverter to the associated SMPS. If not used, this pin must
be grounded.
6 4 Ground This pin must be connected to the preregulator ground.
7 5 Gate Drive The gate drive current capability is suited to drive an IGBT or a power MOSFET.
8 6 VCC This pin is the positive supply of the IC. The circuit turns on when VCC becomes higher
than 11 V, the operating range after startup being 8.5 V up to 16 V.
Figure 21. Application Schematic
18
7
6
5
2
3
4
L1
Filtering
Capacitor
Sync
M1
C1
D1
+
Vcontrol
VCC Load
(SMPS, Lamp
Ballast,...)
Ro
CT
ROCP
Rcs
D1...D4
MC33260
DIP--8 CONFIGURATION SHOWN
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FUNCTIONAL DESCRIPTION
Pin Numbers are Relevant to the PDIP--8 Version
INTRODUCTION
The need of meeting the requirements of legislation on
line current harmonic content, results in an increasing
demand for cost effective solutions to comply with the
Power Factor regulations. This data sheet describes a
monolithic controller specially designed for this purpose.
Most off--line appliances use a bridge rectifier associated
to a huge bulk capacitor to derive raw dc voltage from the
utility ac line.
Figure 22. Typical Circuit Without PFC
Load
ConverterRectifiers
Bulk
Storage
Capacitor
+
AC
Line
This technique results in a high harmonic content and in
poor power factor ratios. In effect, the simple rectification
technique draws power from the mains when the
instantaneous ac voltage exceeds the capacitor voltage. This
occurs near the line voltage peak and results in a high charge
current spike. Consequently, a poor power factor (in the
range of 0.5 -- 0.7) is generated, resulting in an apparent input
power that is much higher than the real power.
Figure 23. Line Waveforms Without PFC
Line Sag
Rectified DC
AC Line Voltage
AC Line Current
0
0
Vpk
Active solutions are the most popular way to meet the
legislation requirements. They consist of inserting a PFC
pre--regulator between the rectifier bridge and the bulk
capacitor. This interface is, in fact, a step--up SMPS that
outputs a constant voltage while drawing a sinusoidal
current from the line.
Figure 24. PFC Preconverter
ConverterRectifiers
+
AC
Line
Load
Bulk Storage
Capacitor
High Frequency
Bypass Capacitor
PFC Preconverter
MC33260
The MC33260 was developed to control an active solution
with the goal of increasing its robustness while lowering its
global cost.
OPERATION DESCRIPTION
The MC33260 is optimized to just as well drive a free
running as a synchronized discontinuous voltage mode.
It also features valuable protections (overvoltage and
undervoltage protection, overcurrent limitation, ...) that
make the PFC preregulator very safe and reliable while
requiring very few external components. In particular, it is
able to safely face any uncontrolled direct charges of the
output capacitor from the mains which occur when the
output voltage is lower than the input voltage (startup,
overload, ...).
In addition to the low count of elements, the circuit can
control an innovative mode named “Follower Boost” that
permits to significantly reduce the size of the preconverter
inductor and power MOSFET. With this technique, the
output regulation level is not forced to a constant value, but
can vary according to the a.c. line amplitude and to the
power. The gap between the output voltage and the ac line
is then lowered, what allows the preconverter inductor and
power MOSFET size reduction. Finally, this method brings
a significant cost reduction.
A description of the functional blocks is given below.
REGULATION SECTION
Connecting a resistor between the output voltage to be
regulated and the Pin 1, a feedback current is obtained.
Typically, this current is built by connecting a resistor
between the output voltage and the Pin 1. Its value is then
given by the following equation:
Ipin1 =
Vo−Vpin1
Ro
where:
Rois the feedback resistor,
Vois the output voltage,
Vpin1 is the Pin 1 clamp value.
The feedback current is compared to the reference current
so that the regulation block outputs a signal following the
characteristic depicted in Figure 25. According to the power
and the input voltage, the output voltage regulation level
varies between two values (Vo)regL and (Vo)regH
corresponding to the IregL and IregH levels.
Figure 25. Regulation Characteristic
1.5 V
Regulation Block Output
Io
IregL
(97%Iref)
IregH
(Iref)
The feedback resistor must be chosen so that the feedback
current should equal the internal current source IregH when
the output voltage exceeds the chosen upper regulation
voltage [(Vo)regH].
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Pin Numbers are Relevant to the PDIP--8 Version
Ro=
VoregH −Vpin1
IregH
Consequently:
In practice, Vpin1 is small compared to (Vo)regH and this
equation can be simplified as follows (IregH being also
replaced by its typical value 200 mA
Ro≈5×VoregH (kΩ)
The regulation block output is connected to the Pin 2
through a 300 kΩresistor. The Pin 2 voltage (Vcontrol)is
compared to the oscillator sawtooth for PWM control.
An external capacitor must be connected between Pin 2
and ground, for external loop compensation. The bandwidth
is typically set below 20 Hz so that the regulation block
output should be relatively constant over a given ac line
cycle. This integration that results in a constant on--time over
the ac line period, prevents the mains frequency output
ripple from distorting the ac line current.
OSCILLATOR SECTION
The oscillator consists of three phases:
Charge Phase: The oscillator capacitor voltage grows
up linearly from its bottom value (ground) until it
exceeds Vcontrol (regulation block output voltage). At
that moment, the PWM latch output gets low and the
oscillator discharge sequence is set.
Discharge Phase: The oscillator capacitor is abruptly
discharged down to its valley value (0 V).
Waiting Phase: At the end of the discharge sequence,
the oscillator voltage is maintained in a low state until
the PWM latch is set again.
Figure 26. Oscillator
Icharge =2¢Io¢Io/I
ref
01
CT
3
15 pF
01
Output_Ctrl
The oscillator charge current is dependenton the feedback
current (Io). In effect
Icharge =2×
I2
o
Iref
where:
Icharge is the oscillator charge current,
Iois the feedback current (drawn by Pin 1),
Iref is the internal reference current (200 mA
So, the oscillator charge current is linked to the output
voltage level as follows:
Icharge =
2×Vo−Vpin12
R2
o×Iref
where:
Vois the output voltage,
Rois the feedback resistor,
Vpin1 is the Pin 1 clamp voltage.
In practice, Vpin1 that is in the range of 2.5 V, is very small
compared to Vo. The equation can then be simplified by
neglecting Vpin1:
Icharge ≈
2×V2
o
R2
o×Iref
It must be noticed that the oscillator terminal (Pin 3) has
an internal capacitance (Cint) that varies versus the Pin 3
voltage. Over the oscillator swing, its average value
typically equals 15 pF (min 10 pF, max 20 pF).
The total oscillator capacitor is then the sum of the internal
and external capacitors.
Cpin3 =CT+Cint
PWM LATCH SECTION
The MC33260 operates in voltage mode: the regulation
block output (Vcontrol -- Pin 2 voltage) is compared to the
oscillator sawtooth so that the gate drive signal (Pin 7) is
high until the oscillator ramp exceeds Vcontrol.
The on--time is then given by the following equation:
ton =
Cpin3 ×Vcontrol
Ich
where:
ton is the on--time,
Cpin3 is the total oscillator capacitor (sum of the
internal and external capacitor),
Icharge is the oscillator charge current (Pin 3 current),
Vcontrol is the Pin 2 voltage (regulation block output).
Consequently, replacing Icharge by the expression given in
the Oscillator Section:
ton =
R2
o×Iref ×Cpin3 ×Vcontrol
2×V2
o
One can notice that the on--time depends on Vo
(preconverter output voltage) and that the on--time is
maximum when Vcontrol is maximum (1.5 V typically).
At a given Vo, the maximum on--time is then expressed by
the following equation:
tonmax =
Cpin3 ×R2
o×Iref ×Vcontrolmax
2×V2
o
This equation can be simplified replacing
2
[(Vcontrol)max *I
ref]by Kosc
Refer to Electrical Characteristics, Oscillator Section.
Then:
tonmax =
Cpin3 ×R2
o
Kosc ×V2
o
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Pin Numbers are Relevant to the PDIP--8 Version
This equation shows that the maximum on--time is inversely
proportional to the squared output voltage. This property is
used for follower boost operation (refer to Follower Boost
section).
CURRENT SENSE BLOCK
The inductor current is converted into a voltage by
inserting a ground referenced resistor (Rcs) in series with the
input diodes bridge (and the input filtering capacitor).
Therefore a negative voltage proportional to the inductor
current is built:
Vcs =-- Rcs ×IL
where:
ILis the inductor current,
Rcs is the current sense resistor,
Vcs is the measured Rcs voltage.
Figure 27. Current Sensing
VOCP
-- 6 0 m V
Zero Current Detection
Power Switch DriveInductor CurrentRcs VoltagePin 4 Voltage
Time
VOCP =R
OCP ¢IOCP
An overcurrent is detected if Vpin4 crosses the threshold (--60 mV)
duringthePowerSwitchonstate
ThenegativesignalV
cs is applied to the current sense
through a resistor ROCP
. The pin is internally protected by a
negative clamp (--0.7 V) that prevents substrate injection.
As long as the Pin 4 voltage is lower than (--60 mV), the
Current Sense comparator resets the PWM latch to force the
gate drive signal low state. In that condition, the power
MOSFET cannot be on.
During the on--time, the Pin 4 information is used for the
overcurrent limitation while it serves the zero current
detection during the off time.
Zero Current Detection
The Zero Current Detection function guarantees that the
MOSFET cannot turn on as long as the inductor current
hasn’t reached zero (discontinuous mode).
The Pin 4 voltage is simply compared to the (--60 mV)
threshold so that as long as Vcs is lower than this threshold,
the circuit gate drive signal is kept in low state.
Consequently, no power MOSFET turn on is possible until
the inductor current is measured as smaller than (60 mV/Rcs)
that is, the inductor current nearly equals zero.
Figure 28. Current Sense Block
1 0
Iocp (205 mA)
Output_Ctrl
LEB
--
+
-- 6 0 m V PWM
Latch
R
S
QOutput_Ctrl
R
4
To Output Buffer
(Output_Ctrl Low <=> Gate Drive in Low State)
ROCP
VOCP
Rcs
D1...D4
Overcurrent Protection
During the power switch conduction (i.e. when the Gate
Drive Pin voltage is high), a current source is applied to the
Pin 4. A voltage drop VOCP is then generated across the
resistor ROCP that is connected between the sense resistor
and the Current Sense Pin (refer to Figure 28). So, instead
of Vcs,thesum(V
cs +V
OCP) is compared to (--60 mV) and
the maximum permissible current is the solution of the
following equation:
-- Rcs ×Ipkmax+VOCP =-- 6 0 m V
where:
Ipkmax is maximum allowed current,
Rcs is the sensing resistor.
The overcurrent threshold is then:
Ipkmax =ROCP ×IOCP+60 ×10-- 3
Rcs
where:
ROCP is the resistor connected between the pin and the
sensing resistor (Rcs),
IOCP is the current supplied by the Current Sense Pin
when the gate drive signal is high (power switch
conduction phase). IOCP equals 205 mA typically.
Practically, the VOCP offset is high compared to 60 mV
and the precedent equation can be simplified. The maximum
current is then given by the following equation:
Ipkmax ≈
ROCP(kΩ)
Rcs(Ω)×0.205 (A)
Consequently, the ROCP resistor can program the OCP level
whatever the Rcs value is. This gives a high freedom in the
choice of Rcs. In particular, the inrush resistor can be utilized.
MC33260
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12
Pin Numbers are Relevant to the PDIP--8 Version
Figure 29. PWM Latch
PWM
Latch
R
S
Q
Q
Synchronization
Arrangement
--
+
OVP, UVP
&
--
+
PWM Latch
Comparator
Vcontrol (Vpin2 -- Regulation Output)
Output
Buffer 7
ZCD & OCP
Current Sense
Comparator
-- 6 0 m V
Oscillator Sawtooth
Output_Ctrl
Th--Stdwn VCC
5
A LEB (Leading Edge Blanking) has been implemented.
This circuitry disconnects the Current Sense comparator
from Pin 4 and disables it during the 400 first ns of the power
switch conduction. This prevents the block from reacting on
the current spikes that generally occur at power switch turn
on. Consequently, proper operation does not require any
filtering capacitor on Pin 4.
PROTECTIONS
OCP (Overcurrent Protection)
Refer to Current Sense Block.
OVP (Overvoltage Protection)
The feedback current (Io) is compared to a threshold
current (IovpH). If it exceeds this value, the gate drive signal
is maintained low until this current gets lower than a second
level (IovpL).
Figure 30. Internal Current Thresholds
Gate
Drive
Enable
Vcontrol
Io
Iuvp IregL IovpH
IovpL
IregH
So, the OVP upper threshold is:
VovpH =Vpin1 +Ro×IovpH
where:
Rois the feedback resistor that is connected between
Pin 1 and the output voltage,
IovpH is the internal upper OVP current threshold,
Vpin1 is the Pin 1 clamp voltage.
Practically, Vpin1 that is in the range of 2.5 V, can be
neglected. The equation can then be simplified:
VovpH =Ro(MΩ)×IovpH(mA)(
V)
On the other hand, the OVP low threshold is:
VovpL =Vpin1 +Ro×IovpL
where IovpL is the internal low OVP current threshold.
Consequently, Vpin1 being neglected:
VovpL =Ro(MΩ)×IovpL(mA)(
V)
The OVP hysteresis prevents erratic behavior.
IovpL is guaranteed to be higher than IregH (refer to
parameters specification). This ensures that the OVP
function doesn’t interfere with the regulation one.
UVP (Undervoltage Protection)
This function detects when the feedback current is lower
than 14% of Iref. In this case, the PWM latch is reset and the
power switch is kept off.
This protection is useful to:
Protect the preregulator from working in too low
mains conditions.
To detect the feedback current absence (in case of a
nonproper connection for instance).
The UVP threshold is:
Vuvp ≈Vpin1 +Ro(MΩ)×Iuvp(mA)(V)
Practically (Vpin1 being neglected),
Vuvp =Ro(MΩ)×Iuvp(mA)(
V)
Maximum On--Time Limitation
As explained in PWM Latch, the maximum on--time is
accurately controlled.
Pin Protection
All the pins are ESD protected.
MC33260
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13
Pin Numbers are Relevant to the PDIP--8 Version
In particular, a 11 V Zener diode is internally connected
between the terminal and ground on the following pins:
Feedback, Vcontrol, Oscillator, Current Sense, and
Synchronization.
Figure 31. Synchronization Arrangement
S2
R2
Q2
S1
R2
Q1
&
2ms
Rsync
--
+
Sync
5
1V
UVLO
1V
Output_Ctrl
PWM
Latch
Set
Q1 High <=>
Synchronization Mode
SYNCHRONIZATION BLOCK
The MC33260 features two modes of operation:
Free Running Discontinuous Mode: The power switch
is turned on as soon as there is no current left in the
inductor (Zero Current Detection). This mode is
simply obtained by grounding the synchronization
terminal (Pin 5).
Synchronization Mode: This mode is set as soon as a
signal crossing the 1.0 V threshold, is applied to the
Pin 5. In this case, operation in free running can only
be recovered after a new circuit startup. In this mode,
the power switch cannot turn on before the two
following conditions are fulfilled.
-- Still, the zero current must have been detected.
-- The precedent turn on must have been followed by (at
least) one synchronization raising edge crossing the
1.0 V threshold.
In other words, the synchronization acts to prolong the
power switch off time.
Consequently, a proper synchronized operation requires
that the current cycle (on--time + inductor demagnetization)
is shorter than the synchronization period. Practically, the
inductor must be chosen accordingly. Otherwise, the system
will keep working in free running discontinuous mode.
Figure 36 illustrates this behavior.
It must be noticed that whatever the mode is, a 2.0 ms
minimum off--time is forced. This delay limits the switching
frequency in light load conditions.
OUTPUT SECTION
The output stage contains a totem pole optimized to
minimize the cross conduction current during high speed
operation. The gate drive is kept in a sinking mode whenever
the Undervoltage Lockout is active. The rise and fall times
have been controlled to typically equal 50 ns while loaded
by 1.0 nF.
REFERENCE SECTION
An internal reference current source (Iref) is trimmed to be
4% accurate over the temperature range (the typical value
is 200 mA). Iref is the reference used for the regulation
(IregH =I
ref).
UNDERVOLTAGE LOCKOUT SECTION
An Undervoltage Lockout comparator has been
implemented to guarantee that the integrated circuit is
operating only if its supply voltage (VCC) is high enough to
enable a proper working. The UVLO comparator monitors
the Pin 8 voltage and when it exceeds 11 V, the device gets
active. To prevent erratic operation as the threshold is
crossed, 2.5 V of hysteresis is provided.
The circuit off state consumption is very low: in the range
of 100 mA@V
CC = 5.0 V. This consumption varies versus
VCC as the circuit presents a resistive load in this mode.
THERMAL SHUTDOWN
An internal thermal circuitry is provided to disable the
circuit gate drive and then to prevent it from oscillating, if
the junction temperature exceeds 150C typically.
The output stage is again enabled when the temperature
drops below 120C typically (30C hysteresis).
MC33260
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14
Pin Numbers are Relevant to the PDIP--8 Version
FOLLOWER BOOST
Traditional PFC preconverters provide the load with a fixed
and regulated voltage that generally equals 230 V or 400 V
according to the mains type (U.S., European, or universal).
In the “Follower Boost” operation, the preconverter
output regulation level is not fixed but varies linearly versus
the ac line amplitude at a given input power.
Figure 32. Follower Boost Characteristics
Traditional Output
Vo(Follower Boost)
Load
Vac
This technique aims at reducing the gap between the
output and the input voltages to minimize the boost
efficiency degradation.
Follower Boost Benefits
The boost presents two phases:
The on--time during which the power switch is on. The
inductor current grows up linearly according to a slope
(Vin/Lp), where Vin is the instantaneous input voltage
and Lpthe inductor value.
The off--time during which the power switch is off.
The inductor current decreases linearly according the
slope (Vo-- V in)/Lp,whereV
ois the output voltage.
This sequence that terminates when the current equals
zero, has a duration that is inversely proportional to the
gap between the output and input voltages.
Consequently, the off--time duration becomes longer
in follower boost.
Consequently, for a given peak inductor current, the
longer the off time, the smaller power switch duty cycle and
then its conduction dissipation. This is the first benefit of this
technique: the MOSFET on--time losses are reduced.
The increase of the off time duration also results in a
switching frequency diminution (for a given inductor
value). Given that in practise, the boost inductor is selected
big enough to limit the switching frequency down to an
acceptable level, one can immediately see the second benefit
of the follower boost: it allows the use of smaller, lighter and
cheaper inductors compared to traditional systems.
Finally, this technique utilization brings a drastic system
cost reduction by lowering the size and then the cost of both
the inductor and the power switch.
the power switch is on the power switch is off
IL
time
Ipk
Vout
traditional preconverter
follower boost preconverter
Vin
Vin
Vin
Vin
IL IL
Figure 33. Off--Time Duration Increase
Follower Boost Implementation
In the MC33260, the on--time is differently controlled
according to the feedback current level. Two areas can be
defined:
When the feedback current is higher than IregL (refer
to regulation section), the regulation block output
(Vcontrol) is modulated to force the output voltage to a
desired value.
On the other hand, when the feedback current is lower
than IregL, the regulation block output and therefore,
the on--time are maximum. As explained in PWM
Latch Section, the on--time is then inversely
proportional to the output voltage square. The
Follower Boost is active in these conditions in which
the on--time is simply limited by the output voltage
level. Note: In this equation, the Feedback Pin voltage
(Vpin1) is neglected compared to the output voltage
(refer to the PWM Latch Section).
ton =tonmax =
Cpin3 ×R2
o
Kosc ×V2
o
where:
Cpin3 is the total oscillator capacitor (sum of the
internal and external capacitors -- Cint +C
T),
Kosc is the ratio (oscillator swing over oscillator gain),
Vois the output voltage,
Rois the feedback resistor.
MC33260
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15
Pin Numbers are Relevant to the PDIP--8 Version
On the other hand, the boost topology has its own rule that
dictates the on--time necessary to deliver the required power:
ton =
4×Lp×Pin
V2
pk
where:
Vpk is the peak ac line voltage,
Lpis the inductor value,
Pin is the input power.
Combining the two equations, one can obtain the
Follower Boost equation:
Vo=Ro
2×
Cpin3
Kosc ×Lp×Pin
×Vpk
Consequently, a linear dependency links the output
voltage to the ac line amplitude at a given input power.
Figure 34. Follower Boost Characteristics
The Regulation Block is Active
Output Voltage
Input Power
ton on--time
Vo
Pin
Output Voltage
Input Power
ton =k/V
o2
Vac
(Vac)max
(Vac)min
The behavior of the output voltage is depicted in
Figures 34 and 35. In particular, Figure 35 illustrates how
the output voltage converges to a stable equilibrium level.
First, at a given ac line voltage, the on--time is dictated by the
power demand. Then, the follower boost characteristic
makes correspond one output voltage level to this on--time.
Combining these two laws, it appears that the power level
forces the output voltage.
One can notice that the system is fully stable:
If an output voltage increase makes it move away from
its equilibrium value, the on--time will immediately
diminish according to the follower boost law. This will
result in a delivered power decrease. Consequently,
the supplied power being too low, the output voltage
will decrease back,
In the same way, if the output voltage decreases, more
power will be transferred and then the output voltage
will increase back.
Figure 35. Follower Boost Output Voltage
VacLL Vac VacHL
Vac
VoRegulation Block is Active Vo=V
pk
Pin
(Pin)min
(Pin)max
non usable area
Mode Selection
The operation mode is simply selected by adjusting the
oscillator capacitor value. As shown in Figure 35, the output
voltage first has an increasing linear characteristic versusthe
ac line magnitude and then is clamped down to the
regulation value. In the traditional mode, the linear area
must be rejected. This is achieved by dimensioning the
oscillator capacitor so that the boost can deliver the
maximum power while the output voltage equals its
regulation level and this, whatever the given input voltage.
Practically, that means that whatever the power and input
voltage conditions are, the follower boost would generate
output voltages values higher than the regulation level, if
there was no regulation block.
In other words, if (Vo)regL is the low output regulation
level:
VoregL ≤Ro
2×
CT+Cint
Kosc ×Lp×Pinmax
×Vpk
Consequently,
CT≥-- C int +
4×Kosc ×Lp×Pinmax ×Vo2
regL
R2
o×V2
pk
Using IregL (regulation block current reference), this
equation can be simplified as follows:
CT≥-- C int +
4×Kosc ×Lp×Pinmax ×I2
regL
V2
pk
In the Follower Boost case, the oscillator capacitor must
be chosen so that the wished characteristics are obtained.
Consequently, the simple choice of the oscillator
capacitor enables the mode selection.
MC33260
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16
Figure 36. Typical Waveforms
2ms
Synchronization
Signal
Zero Current
Detection
2ms
Delay
2ms 2 ms
2ms
Vcontrol
205 mA
Oscillator
Circuit
Output
Ics
Inductor
Current
3 41 2
case no. 1: the turn on is delayed by the Zero Current Detection
cases no. 2 and no. 3: the turn on is delayed by the synchronization signal
case no. 4: the turn on is delayed by the minimum off--time (2 ms)
MC33260
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MAIN DESIGN EQUATIONS (Note 3)
rms Input Current (Iac)
Iac =Po
η×Vac
(preconverter efficiency) is generally in the
range of 90 -- 95%.
Maximum Inductor Peak Current ((Ipk)max):
(Ipk)max=2×2
×(Po)max
η×V
acLL
(Ipk)max is the maximum inductor current.
Output Voltage Peak to Peak 100Hz (120Hz) Ripple ((ΔVo)pk--pk):
(ΔVo)pk–pk =Po
2π×fac ×Co×Vo
fac is the ac line frequency (50 or 60Hz).
Inductor Value (Lp):
Lp=
2×t×Vo
2
−VacLL ×VacLL 2
Vo×VacLL ×(Ipk)max
t is the maximum switching period.
(t = 40 ms) for universal mains operation and
(t = 20ms) for narrow range are generally
used.
Maximum Power MOSFET Conduction Losses ((pon)max):
(Pon )max≈1
3×(Rds)on ×(Ipk)max
2×1−
1.2 ×VacLL
Vo
(Rds)on is the MOSFET drain source on--time
resistor.
In Follower Boost, the ratio (VacLL/Vo)is
higher. The on--time MOSFET losses are then
reduced.
Maximum Average Diode Current (Id):
(Id)max=(P
o)max
(V
o)min
The Average Diode Current depends on the
power and on the output voltage.
Current Sense Resistor Losses (pRcs):
pRcs =1
6×(Rds)on ×(Ipk)2max
This formula indicates the required dissipation
capability for Rcs (current sense resistor).
Over Current Protection Resistor (ROCP):
ROCP ≈
Rcs ×(Ipk)max
0.205
(kΩ)
The overcurrent threshold is adjusted by ROCP
at a given Rcs.
Rcs can be a preconverter inrush resistor.
Oscillator External Capacitor Value (CT):
--Traditional Operation
CT≥−Cint +
2×Kosc ×Lp×(Pin )max×I2
regL
V2
ac
The Follower Boost characteristic is adjusted
by the CTchoice.
The Traditional Mode is also selected by CT
.
Cint is the oscillator pin internal capacitor.
-- Follower Boost:
Vo=Ro
2×
CT+Cint
Kosc ×Lp×Pin
×Vpk
Feedback Resistor (Ro):
Ro=
(Vo)reg −VFB
IregH ≈Vo
200
(MΩ)
The output voltage regulation level is adjusted
by Ro.
3. The preconverter design requires the following characteristics specification:
-- ( V o)reg: desired output voltage regulation level
-- ( ΔVo)pk--pk: admissible output peak to peak ripple voltage
-- P o: desired output power
-- V ac: ac rms operating line voltage
-- V acLL: minimum ac rms operating line voltage
-- V FB: Feedback Pin voltage
MC33260
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18
Figure 37. 80 W Wide Mains Power Factor Corrector
C2
47 mF
450 V
D5
+
80 W Load
(SMPS, Lamp
Ballast,...)
R1
1MΩ
0.25 W
EMI
Filter
15 kΩ/0.25 W
R2
1MΩ
0.25 W
MUR460E
1N4007
D1
D2
D4D3
R4
1Ω/2 W
R3
C1
330 nF
500 Vdc
Q1
MTP4N50E
L1 320 mH
90 to
270 Vac
22 Ω/0.25 W
R5
Feedback
Block
--
+
Iocp (205 mA)
--
+
PWM
Latch
Synchronization
Block
S
R
Q
Q
REGULATOR
Enable
Iref
Vref
11 V/8.5 V
Output
ThStdwn
--
+
C4
330 pF
Synchro
Gnd
Drive
VCC
PWM Comp
Iref
Io
Iref
Io
C3
680 nF 300 k Io
1.5 V
97%.Iref Iref
Vreg
Output
CT
Vcontrol
Io
Current
Sense
Block
Regulation
Block
Output
Buffer
Vprot
MC33260
-- 6 0 m V
Vreg
Oscillator
15 pF
Iosc–ch =2x|0x|0
Iref
LEB
0110
UVP, OVP
Vprot
Io
IovpL IovpH
Iuvp
(------)
L1: Coilcraft N2881 -- A (primary: 62 turns of # 22 AWG -- Secondary: 5 turns of # 22 AWG Core: Coilcraft PT2510, EE 25
L1: Gap: 0.072total for a primary inductance (Lp) of 320 mH)
Feedback
Input
POWER FACTOR CONTROLLER TEST DATA*
AC Line Input
DC Output
Current Harmonic Distortion (% Ifund)
Vrms
(V)
Pin
(W)
PF
(--)
Ifund
(mA) THD H2 H3 H5 H7 H9
Vo
(V)
ΔVo
(V)
Io
(mA)
Po
(W)
(%)
90 88.2 0.991 990 8.1 0.07 5.9 4.3 1.5 1.7 181 31.2 440 79.6 90.2
110 86.3 0.996 782 7.0 0.05 2.7 5.7 1.1 0.8 222 26.4 360 79.9 92.6
135 85.2 0.995 642 8.2 0.03 1.5 6.8 1.1 1.5 265 20.8 300 79.5 93.3
180 87.0 0.994 480 9.5 0.16 4.0 6.5 3.1 4.0 360 16.0 225 81.0 93.1
220 84.7 0.982 385 15 0.5 8.4 7.8 5.3 1.9 379 14.0 210 79.6 94.4
240 85.3 0.975 359 16.5 0.7 9.0 7.8 7.4 3.8 384 14.0 210 80.6 94.5
260 84.0 0.967 330 18.8 0.7 11.0 7.0 9.0 4.0 392 13.2 205 80.4 95.7
*Measurements performed using Voltech PM1200 ac power analysis.
MC33260
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19
Figure 38. Circuit Supply Voltage
18
7
6
5
2
3
4
MC33260
D1...D4
+
VCC
15 V Cpin8
+
r
Rstup
PDIP--8 CONFIGURATION SHOWN
MC33260 VCC SUPPLY VOLTAGE
In some applications, the arrangement shown in Figure 38
must be implemented to supply the circuit. A startup resistor
is connected between the rectified voltage (or one--half
wave) to charge the MC33260 VCC up to its startup
threshold (11 V typically). The MC33260 turns on and the
VCC capacitor (Cpin8) starts to be charged by the PFC
transformer auxiliary winding. A resistor, r (in the range of
22 Ω) and a 15 V Zener should be added to protect the circuit
from excessive voltages.
When the PFC preconverter is loaded by an SMPS, the
MC33260 should preferably be supplied by the SMPS itself.
In this configuration, the SMPS starts first and the PFC gets
active when the MC33260 VCC supplied by the power
supply, exceeds the device startup level. With this
configuration, the PFC preconverter doesn’t require any
auxiliary winding and finally a simple coil can be used.
PCB LAYOUT
The connections of the oscillator and Vcontrol capacitors
should be as short as possible.
Figure 39. Preconverter Loaded by a Flyback SMPS: MC33260 VCC Supply
18
7
6
5
2
3
4
MC33260
VCC
SMPS Driver
+
++
++
+
Preconverter Output
+
DIP--8 CONFIGURATION SHOWN
MC33260
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20
ORDERING INFORMATION
Device Package Shipping†
MC33260PG PDIP--8
(Pb--Free)
50 Units / Rail
MC33260DG SOIC--8
(Pb--Free)
98 Units / Rail
MC33260DR2G SOIC--8
(Pb--Free)
2500 Units / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
MC33260
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21
PACKAGE DIMENSIONS
8LEADPDIP
CASE 626--05
ISSUE M
14
58
F
NOTE 5
D
e
b
L
A1
A
E3
E
A
TOP VIEW
CSEATING
PLANE
0.010 CA
SIDE VIEW
END VIEW
END VIEW
NOTE 3
DIM MIN NOM MAX
INCHES
A-- -- -- -- -- -- -- -- 0 . 2 1 0
A1 0.015 -------- --------
b0.014 0.018 0.022
C0.008 0.010 0.014
D0.355 0.365 0.400
D1 0.005 -------- --------
e0.100 BSC
E0.300 0.310 0.325
L0.115 0.130 0.150
-- -- -- -- -- -- -- -- 5 . 3 3
0 . 3 8 -- -- -- -- -- -- -- --
0.35 0.46 0.56
0.20 0.25 0.36
9.02 9.27 10.02
0 . 1 3 -- -- -- -- -- -- -- --
2.54 BSC
7.62 7.87 8.26
2.92 3.30 3.81
MIN NOM MAX
MILLIMETERS
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
3. DIMENSION E IS MEASURED WITH THE LEADS RE-
STRAINED PARALLEL AT WIDTH E2.
4. DIMENSION E1 DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
E1 0.240 0.250 0.280 6.10 6.35 7.11
E2
E3 -- -- -- -- -- -- -- -- 0 . 4 3 0 -- -- -- -- -- -- -- -- 1 0 . 9 2
0.300 BSC 7.62 BSC
E1
D1
M
8X
e/2
E2
c
MC33260
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22
PACKAGE DIMENSIONS
SOIC--8
CASE 751--07
ISSUE AJ
SEATING
PLANE
1
4
58
N
J
X45
_
K
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751--01 THRU 751--06 ARE OBSOLETE. NEW
STANDARD IS 751--07.
A
BS
D
H
C
0.10 (0.004)
DIM
A
MIN MAX MIN MAX
INCHES
4.80 5.00 0.189 0.197
MILLIMETERS
B3.80 4.00 0.150 0.157
C1.35 1.75 0.053 0.069
D0.33 0.51 0.013 0.020
G1.27 BSC 0.050 BSC
H0.10 0.25 0.004 0.010
J0.19 0.25 0.007 0.010
K0.40 1.27 0.016 0.050
M0808
N0.25 0.50 0.010 0.020
S5.80 6.20 0.228 0.244
-- X --
-- Y --
G
M
Y
M
0.25 (0.010)
-- Z --
Y
M
0.25 (0.010) ZSXS
M
____
1.52
0.060
7.0
0.275
0.6
0.024
1.270
0.050
4.0
0.155
mm
inches
SCALE 6:1
*For additional information on our Pb--Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
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MC33260/D
GreenLine is a trademark of Motorola, Inc.
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