Enpirion® Power Datasheet
EP5352QI/EP5362QI/EP5382QI
500/600/800mA PowerSoC
Sy nchronous Buc k Regulat o r s
With Integrated Inductor
Voltage
Select
DAC
Switch
VREF
(+)
(-)
Error
Amp
V
SENSE
V
FB
V
OUT
VS0 VS1 VS2
Package Boundry
P-Drive
N-Drive
UVLO
Thermal Limit
Current Limit
Soft Start
Sawtooth
Generator
(+)
(-)PWM
Comp
V
IN
ENABLE
GND
Logic
Compensation
Network
Product Highlights
• Revolutionary integrated inductor
• Very small solution foot print*
• Fully RoHS compli ant; MS L 3 260°C reflow
• Only two low cost components required
• 5mm x 4mm x1.1mm QFN package
• W ide 2. 4V t o 5.5V input r ange
• 500, 600, 800 mA output current versi ons
• Less than 1 µA st andby cur r ent
• 4 MHz swi tchi ng frequency
• Fast transi ent response
• Very low ripple voltage; 5mVp-p typical
• 3 Pin VID Output Voltage select
• External divider option
• Dynamically adjustable output
• Desi gned for Low noi se/E MI
• Short circuit, UVLO, and thermal protection
Product Overview
The Ultra-Low-Profile EP53X2QI product family
is targeted to applications where board area and
profile are critical. EP53X2QI is a complete
power conversion solution requiring only two low
cost ceramic MLCC caps. Inductor, MOSFETS,
PWM, and compensation are integrated into a
tiny 5mm x 4mm x 1.1mm QFN package. The
EP53x2QI family is engineered to s im plify des ign
and to minimize layout constraints. High
switching frequency and internal type III
compensation provides superior transient
response. With a 1.1 mm profile, the EP53x2 is
perfec t for s pac e and height lim ited applic ations .
A 3 -pin VID output voltage select scheme
provides s even pre-programmed output voltages
along with an option for external resistor divider.
O utput voltage c an be pr ogram m ed on-the-fly to
provide fas t, dynam ic voltage s c aling.
Typical Application Circuit
V
IN
V
Sense
V
in
VS1
VS2
VS0
10µF
2.2uF
V
OUT
V
out
GND
ENABLE
V
FB
Voltage
Select
Figure 1. Typical ap pl ication circuit .
Applications
• Area constrained applications
• Mobile multimedia, smartphone & PDA
• Mobile and Cellular platforms
• VoIP and Video phones
• Pers onal Media Players
• FPGA, DSP, IO & Peripherals
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03132 October 11, 2013 Rev H
EP5382QI/EP5362QI/EP5352QI
Absolute Maximum Ratings
CAUTION: Absolute Maximum ratings are stress ratings only. Functional operation beyond recommended operating
conditions is not implied. Stress beyond absolute maximum ratings may cause permanent damage to the device.
Exposure t o absol ut e m axi m um rated condi ti ons for ex tended peri ods m ay affect devi c e rel i abi l i t y.
PARAMETER
SYMBOL
MIN
MAX
UNITS
I nput Supply Voltage
VIN
-0.3
7.0
V
Voltages on: ENABLE , VSENSE, VS0-VS2
-0.3
VIN + 0.3
V
Voltage on: VFB
-0.3
2.7
V
Storage T emperature Range
TSTG
-65
150
°C
Ref low T emp, 10 Sec, MSL3 JEDEC J -STD-020A
260
°C
ESD Rating (based on Human Body Model)
2000
V
Recommended Operating Conditions
PARAMETER
SYMBOL
MIN
MAX
UNITS
I nput Voltage Range
VIN
2.4
5.5
V
Output Voltage Range
VOUT
0.6
VIN-0.45
V
Operating Ambient T emperature
TA
-40
+85
°C
Operating Junction T emperature
TJ
-40
+125
°C
Thermal Characteristics
PARAMETER
SYMBOL
TYP
UNITS
T hermal Resistance: Junction to A mbient (0 LFM)
θJA
65
°C/W
T hermal Resistance: Junction to Cas e (0 LFM)
θJC
15
°C/W
T hermal Shutdown
TJ-TP
+150
°C
T hermal Shutdown Hysteresi s
15
°C
Electrical Characteristics
NOTE: TA = 25°C unless otherwise noted. Typica l values are at VI N = 3.6V.
EP5352QI, EP5362QI: CIN = 2.2µF, COUT=10uF.
EP5382QI: CIN = 4.7µF, COUT=10uF.
PARAMETER
SYMBOL
TES T CO NDIT IONS
MIN
TYP
MAX
UNITS
Operating I nput Voltage
VIN
2.4
5.5
V
Under Voltage Lockout
VUVLO
VIN going low to high
2.2
2.3
V
UVLO Hysteresis
0.145
V
VOUT I nitial Accuracy VOUT
2.4V ≤ V
IN
≤ 5.5V, I
LOAD
= 100mA;
TA = 25C
-2.0 +2.0 %
V
OUT
Variation for all
Causes VOUT
2.4V ≤ V
IN
≤ 5.5V, I
LOAD
= 0 –
800mA,
TA = -40°C to +85°C
-3.0 +3.0 %
Feedback Pin Volt age VFB
2.4V ≤ V
IN
≤ 5.5V, I
LOAD
= 100mA
VSO=VS1=VS2=1
0.591 0.603 0.615
V
Feedback Pin I nput Current
IFB
1
nA
Feedback Pin Voltage
VFB
2.4V ≤ VIN ≤ 5.5V, ILOAD = 0 -800mA,
0.585
0.603
0.621
V
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03132 October 11, 2013 Rev H
EP5382QI/EP5362QI/EP5352QI
PARAMETER
SYMBOL
TES T CO NDIT IONS
MIN
TYP
MAX
UNITS
T
A
= -40°C to +85°C
VSO=VS1=VS2=1
Dynamic Voltage Slew Rate
Vslew
3
V/mS
Continuous Output Curr ent
EP5352QI
IOUT EP5352QI 500 mA
Continuous Output Curr ent
EP5362QI
IOUT EP5362QI 600 mA
Continuous Output Curr ent
EP5382QI
IOUT EP5382QI 800 mA
Shut-Dow n Current
ISD
Enable = Low
0.75
µA
Quiescent Current
No switching
800
µA
PFET OCP T hreshold ILIM
2.4V ≤ V
IN
≤ 5.5V,
0.6V ≤ VOUT ≤ VIN – 0.6V
1.4 2 A
VS0-VS1 Voltage
Threshold
Pin = Low
Pin = High
0.0
1.4
0.4
VIN
V
VS0-VS2 Pin I nput Current
IVSX
1
nA
Enable Voltage T hreshold
Logic Low
Logic High
0.0
1.4
0.2
VIN
V
Enable Pin Input Current
IEN
VIN = 3.6V
2
µA
Operating Frequency
FOSC
4
MHz
PFET On Resistance
RDS(ON)
340
mΩ
NFET On Resistance
RDS(ON)
270
mΩ
I nternal Inductor DCR
.110
Ω
Soft-Start Operation
Soft-Start Slew Rate
VSS
VID pr ogramming mode
1.95
3
4.05
V/mS
VOUT Rise Time
TSS
VFB programming mode
1.56
2.4
3.24
mS
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03132 October 11, 2013 Rev H
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Pin Description
VIN (Pin 1,2): Input voltage pin. Supplies power
to the IC . VIN can range from 2.4V to 5.5V.
Input GND: (Pin 3): Input power ground.
Connect this pin to the ground terminal of the
input capacitor. Refer to Layout
Rec om m endations for further details .
Output GND: (Pin 4): Power ground. The
output filter capacitor should be connected to
this pin. Refer to Layout recommendations for
further detail.
VOUT (Pin 5,6,7): Regulated output voltage.
NC (Pin 8,9,10,11,12,13,14): These pins
should not be electrically connected to each
other or to any external signal, voltage, or
ground. One or more of these pins may be
c onnec ted internally.
VSENSE (Pin 15): Sense pin for output voltage
regulation. Connect VSENSE to the output
voltage rail as close to the terminal of the
output filter c apac itor as pos s ible.
VFB (Pin 16): Feed back pin for external divider
option. When using the external divider option
(VS0=VS1=VS2= high) connect this pin to the
center of the external divider. Set the divider
such that VFB = 0.603V .
VS0,VS1,VS2 (Pin 17,18,19): Output voltage
select. VS0=pin19, VS1=pin18, VS2=pin17.
Selects one of seven preset output voltages or
choose external divider by connecting pins to
logic high or low. Logic low is defined as VLOW
≤ 0.4V. Logic high is defined as VHIGH ≥ 1.4V .
Any level between these two values is
indeterminate. (refer to section on output
voltage select for more detail).
ENABLE (Pin 20): Output enable. Enable =
logic high, disable = logic low. Logic low is
defined as VLOW ≤ 0.2V. Logic high is defined
as VHIGH ≥ 1.4V. Any level between these two
values is indeterminate.
Thermal Pad. Thermal pad to remove heat
from package. Connect to surface ground pad
and PCB internal ground plane.
Figure 2. Pin descript ion , top v iew.
VOUT
NC
NC
NC
VOUT
VFB
VSENSE
NC
NC
NC
NC
VOUT
GND
GND
VIN
ENABLE
VS0
VS1
VS2
1
2
6
5
4
3
10
9
8
7
11
12
13
14
15
16
20
19
18
17
VIN
V
OUT
NC
NC
NC
V
OUT
V
FB
V
SENSE
NC
NC
NC
NC
V
OUT
GND
GND
V
IN
ENABLE
VS0
VS1
VS2
1
2
5
4
3
10
9
8
7
11
12
13
14
15
16
20
19
18
17
V
IN
Thermal
Pad
6
Figure 3. Pi n desc ript io n, bot t om view.
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03132 October 11, 2013 Rev H
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Functional Block Diagram
Voltage
Select
DAC
Switch
VREF
(+)
(-)
Error
Amp
V
SENSE
V
FB
V
OUT
VS0 VS1 VS2
Package Boundry
P-Drive
N-Drive
UVLO
Thermal Li mit
Current Lim i t
Soft Start
Sawtooth
Generator
(+)
(-)PWM
Comp
V
IN
ENABLE
GND
Logic
Compensation
Network
Fi gure 4. Functional bl ock di agram .
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03132 October 11, 2013 Rev H
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Typical Performance Characteristics
50
55
60
65
70
75
80
85
90
95
50 150 250 350 450 550
Efficiency vs Output C ur rent
V
OUT
= 3.3V
Load Cur rent (mA)
V
IN
= 5.0V
V
OUT
= 3.0V
V
OUT
= 2.7V
V
OUT
= 2.5V
V
OUT
= 1.8V
Efficiency -%
50
55
60
65
70
75
80
85
90
95
50 150 250 350 450 550
Efficiency vs Output C ur rent
V
OUT
= 3.3V
Load Cur rent (mA)
V
IN
= 5.0V
V
OUT
= 3.0V
V
OUT
= 2.7V
V
OUT
= 2.5V
V
OUT
= 1.8V
Efficiency -%
50
55
60
65
70
75
80
85
90
95
100
50 150 250 350 450 550
Efficiency vs Output Current
V
OUT
= 1.2V
Load Curre nt (m A)
V
IN
= 3.3V
V
OUT
= 3.0V
V
OUT
= 2.7V
V
OUT
= 2.5V
V
OUT
= 1.8V
Efficiency -%
50
55
60
65
70
75
80
85
90
95
100
50 150 250 350 450 550
Efficiency vs Output Current
V
OUT
= 1.2V
Load Curre nt (m A)
V
IN
= 3.3V
V
OUT
= 3.0V
V
OUT
= 2.7V
V
OUT
= 2.5V
V
OUT
= 1.8V
Efficiency -%
50
55
60
65
70
75
80
85
90
95
100
50 150 250 350 450 550
Efficiency vs Outp ut Current
V
OUT
= 3.3V
Load Cur rent (mA)
V
IN
= 3.6V
V
OUT
= 3.0V
V
OUT
= 2.7V
V
OUT
= 2.5V
V
OUT
= 1.8V
Efficiency -%
50
55
60
65
70
75
80
85
90
95
100
50 150 250 350 450 550
Efficiency vs Outp ut Current
V
OUT
= 3.3V
Load Cur rent (mA)
V
IN
= 3.6V
V
OUT
= 3.0V
V
OUT
= 2.7V
V
OUT
= 2.5V
V
OUT
= 1.8V
Efficiency -%
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Detailed Description
Functional Overview
The EP53x2QI family is a complete DCDC
converter solution requiring only two low cost
MLCC capacitors. MOSFET switches, PWM
controller, Gate-drive, compensation, and
inductor are integrated into the tiny 5mm x
4mm x 1.1mm package to provide the smallest
footprint possible while maintaining high
efficiency and high performance. The converter
uses voltage mode control to provide the
simplest implementation and high noise
immunity. The device operates at a 4 MHz
switching frequency. The high switching
frequency allows for a wide control loop
bandwidth providing excellent transient
performance. The 4 MHz switching frequency
enables the use of very small components
making possible this unprecedented level of
integration.
Altera Enpirion’s proprietary power MOSFET
technology provides very low switching loss at
frequencies of 4 MHz and higher, allowing for
the use of very small internal components, and
very wide control loop bandwidth. Unique
magnetic design allows for integration of the
inductor into the very low profile 1.1mm
package. Integration of the inductor virtually
eliminates the design/layout issues normally
associated with switch-mode DCDC
converters. All of this enables much easier
and faster integration into various applications
to meet demanding EMI requirements.
Output voltage is chosen from seven preset
values via a three pin VID voltage select
scheme. An external divider option enables
the selection of any voltage in the 0.6 to VIN -
Vdropout. This reduces the number of
components that must be qualified and
reduces inventory problems. The VID pins can
be toggled on the fly to implement glitch free
dynam ic voltage s c aling.
Protection features include under-voltage lock-
out (UVLO), over-current protection (OCP),
short circuit protection, and thermal overload
protection.
Integrated Inductor
Altera has introduced the world’s first product
family featuring integrated inductors. The
EP53x2QI family utilizes a low loss, planar
construction inductor. The use of an internal
inductor localizes the noises associated with
the output loop currents. The inherent shielding
7 www.altera.com/enpirion
03132 October 11, 2013 Rev H
EP5382QI/EP5362QI/EP5352QI
and compact construction of the integrated
inductor reduces the radiated noise that
couples into the traces of the circuit board.
Further, the package layout is optimized to
reduce the electrical path length for the AC
ripple currents that are a major source of
radiated emissions from DCDC converters.
The integrated inductor significantly reduces
parasitic effects that can harm loop stability,
and m akes layout very s im ple.
S o ft S ta rt
Internal soft start circuits limit in-rush current
when the device starts up from a power down
condition or when the “ENABLE” pin is
asserted “high”. Digital control circuitry limits
the VOUT ramp rate to levels that are safe for
the Power MOSFETS and the integrated
inductor.
The EP53x2QI have two soft start operating
modes. When VOUT is programmed using a
preset voltage in VID mode, the device has a
constant slew rate. When the EP53x2QI is
configured in external resistor divider mode,
the device has a constant VOUT ramp time.
Output voltage slew rate and ramp time is
given in the Elec tric al C harac teris tic s Table.
Excess bulk capacitance on the output of the
device can cause an over-current condition at
s tar tup.
When operating in VID mode, the maximum
total capacitance on the output, including the
output filter capacitor and bulk and decoupling
c apac itanc e, at the load, is given as :
COUT_TOTAL_MAX = COUT_Filter + COUT_BULK = 350uF
When the EP53x2QI output voltage is
programmed using and external resistor divider
the m axim um total c apac itanc e on the output is
given as:
COUT_TOTAL_MAX = 6.253x10-4/VOUT Farads
The above number and formula assume a no
load condition at startup.
Over Current/Short Circuit Protection
The current limit function is achieved by
sensing the current flowing through a sense P-
MOSFET which is compared to a reference
current. When this level is exceeded the P-
FET is turned off and the N-FET is turned on,
pulling VOUT low. This condition is maintained
for a per iod of 1m S and then a norm al s oft s tar t
is initiated. If the over current condition still
persists, this cycle will repeat in a “hiccup”
mode.
Under Vol t age Lock out
During initial power up an under voltage
lockout circuit will hold-off the switching
circuitry until the input voltage reaches a
sufficient level to insure proper operation. If
the voltage drops below the UVLO threshold
the lockout circuitry will again disable the
switching. Hysteresis is included to prevent
chattering between states.
Enable
The ENABLE pin provides a means to shut
down the converter or enable normal
operation. A logic low will disable the converter
and cause it to shut down. A logic high will
enable the converter into normal operation. In
shutdown mode, the device quiescent current
will be less than 1 uA. The ENABLE pin must
not be left floating.
Thermal Shutdown
When excessive power is dissipated in the
chip, the junction temperature rises. Once the
junction temperature exceeds the thermal
shutdown temperature the thermal shutdown
circuit turns off the converter output voltage
thus allowing the device to cool. When the
junction temperature decreases by 15C°, the
device will go through the normal startup
process.
Application Information
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03132 October 11, 2013 Rev H
EP5382QI/EP5362QI/EP5352QI
Output Vo ltage Select
To provide the highest degree of flexibility in
choosing output voltage, the EP53x2QI family
uses a 3 pin VID, or Voltage ID, output voltage
select arrangement. This allows the designer
to choose one of seven preset voltages, or to
use an external voltage divider. Internally, the
output of the VID multiplexer sets the value for
the voltage reference DAC, which in turn is
connected to the non-inverting input of the
error amplifier. This allows the use of a single
feedback divider with constant loop gain and
optimum compensation, independent of the
output voltage selected.
Table 1 shows the various VS0-VS2 pin logic
states and the associated output voltage
levels . A logic “ 1” indic ates a c onnec tion to VIN
or to a “high” logic voltage level. A logic “0”
indicates a connection to ground or to a “low”
logic voltage level. These pins can be either
hardwired to VIN or GND or alternatively can be
driven by standard logic levels. These pins
m us t not be left floating.
VS2
VS1
VS0
VOUT
0
0
0
3.3
0
0
1
2.5
0
1
0
2.8
0
1
1
1.2
1
0
0
3.0
1
0
1
1.8
1
1
0
2.7
1
1
1
External
External V oltag e Divider
As described above, the external voltage
divider option is chosen by connecting the
VS0, VS1, and VS2 pins to VIN or logic “high”.
The EP53x2QI uses a separate feedback pin,
VFB, when using the external divider. VSENSE
must be connected to VOUT as indicated in
Figure 5.
VIN
V
Sense
V
in
VS1
VS2
VS0
10µF
2.2uF
4.7uF
VOUT
V
out
GND
ENABLE
Ra
Rb
V
FB
F igure 5. Extern a l Divider.
The output voltage is selected by the following
formula:
( )
Rb
Ra
OUT
VV += 1603.0
Ra must be chosen as 200KΩ to m aintain loop
gain. Then R b is given as:
Ω
−
=603.0
102.1
5
OUT
b
Vx
R
Dynamically Adjustable Output
The EP53x2QI are designed to allow for
dynamic switching between the predefined VID
voltage levels The inter-voltage slew rate is
optimized to prevent excess undershoot or
overshoot as the output voltage levels
trans ition. The s lew rate is identic al to the s oft-
start slew rate of 3V/mS.
Dynamic transitioning between internal VID
s ettings and the exter nal divider is not allowed.
Power-Up/Down Sequencing
During power-up, ENABLE should not be
asserted before VIN. During power down, the
VIN should not be powered down before the
ENABLE. Tying PVIN and ENABLE together
Table 1. Vo ltage s elect settings .
9 www.altera.com/enpirion
03132 October 11, 2013 Rev H
EP5382QI/EP5362QI/EP5352QI
during power-up or power-down meets this
requirement.
Pre-Bias Start-up
The EP53x2QI does not support startup into a
pre-biased condition. Be sure the output
capacitors are not charged or the output of the
EP53x2QI is not pre-biased when the
EP53x2QI is first enabled.
Input and Output Capacitors
The input capacitance requirement is as
follows:
EP5352QI, EP5362QI = 2.2uF
EP5382QI = 4.7uF
Altera recommends that a low ESR MLCC
capacitor be used. The input capacitor must
use a X5R or X7R or equivalent dielectric
formulation. Y5V or equivalent dielectric
formulations lose capacitance with frequency,
bias, and with temperature, and are not
suitable for switch-mode DC-DC converter
input and output filter applic ations .
The output capacitance requirement is a
minimum of 10uF. The control loop is
designed to be stable with up to 60uF of total
output capacitance without requiring
modification of the control loop. Capacitance
above the 10uF minimum should be added if
the trans ient per form anc e is not s uffic ient us ing
the 10uF. Altera recommends a low ESR
MLCC type capacitor be used. The output
c apac itor m us t us e a X5R or X7R or equivalent
dielectric formulation. Y5V or equivalent
dielectric formulations lose capacitance with
frequency, bias, and temperature and are not
suitable for switch-mode DC-DC converter
input and output filter applic ations.
LAYOUT CONSIDERATIONS*
*Optimized PCB Layout f ile downloadable f rom http://www.altera.com/enpirion to assure f irst pass des ign succ ess.
Recommendation 1: Input and output filter capacitors should be placed as close to the EP53x2QI
package as possible to reduce EMI from input and output loop AC currents. This reduces the
phys ic al area of the Input and O utput AC c urrent loops .
Recommendation 2: DO NOT connect GND pins 3 and 4 together. Pin 3 should be used for the
Input capacitor local ground and pin 4 should be used for the output capacitor ground. The ground
pad for the input and output filter capacitors should be isolated ground islands and should be
c onnec ted to s ys tem ground as indic ated in rec om m endation 3 and rec om m endation 5.
Cin
Manufacturer Part # Value WVDC Case Size
Murata GRM219R61A475KE19D 4.7uF 10V 0805
GRM319R61A475KA01D 1206
GRM219R60J475KE01D 6.3V 0805
GRM31MR60J475KA01L 1206
Panasonic ECJ-2FB1A475K 10V 0805
ECJ-3YB1A475K 1206
ECJ-2FB0J475K 6.3V 0805
ECJ-3YB0J475K 1206
Taiyo Yuden LMK212BJ475KG-T 10V 0805
LMK316BJ475KD-T 1206
JMK212BJ475KD-T 6.3V 0805
Cin
Manufacturer Part # Value WVDC Case Size
Murata GRM21BR71A225KA01L 2.2uF 10V 0805
GRM31MR71A225KA01L 1206
GRM21BR70J225KA01L 6.3V 0805
Panasonic ECJ-2FB1A225K 10V 0805
ECJ-3YB1A225K 1206
ECJ-2YB0J225K 6.3V 0805
Taiyo Yuden LMK107BJ225KA-T 10V 0603
LMK212BJ225KG-T 0805
Cout
Manufacturer Part # Value WVDC Case Size
Murata GRM219R60J106KE19D 10uF 6.3V 0805
GRM319R60J106KE01D 1206
Panasonic ECJ-2FB0J106K 6.3V 0805
ECJ-3YB0J106K 1206
Taiyo Yuden JMK212BJ106KD-T 6.3V 0805
JMK316BJ106KF-T 1206
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03132 October 11, 2013 Rev H
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Recommendation 3: Multiple small vias (0.25mm after copper plating) should be used to connect
ground terminals of the Input capacitor and the output capacitor to the system ground plane. This
provides a low inductance path for the high-frequency AC currents, thereby reducing ripple and
s uppres s ing EMI (s ee Fig. 5, Fig. 6, and Fig. 7) .
Recommendation 4: The large thermal pad underneath the component must be connected to the
system ground plane through as many thermal vias as possible. The vias should use 0.33mm drill
s iz e w ith m inim um one ounc e c opper plating ( 0.035m m plating thic knes s ). This pr ovides the path for
heat dis s ipation from the c onverter .
Recommendation 5: The system ground plane referred to in recommendations 3 and 4 should be
the first layer immediately below the surface layer (PCB layer 2). This ground plane should be
continuous and un-interrupted below the converter and the input and output capacitors that carry
large AC currents. If it is not possible to make PCB layer 2 a continuous ground plane, an
uninterrupted ground “island” should be created on PCB layer 2 immediately underneath the
EP53x2QI and its input and output capacitors. The vias that connect the input and output capacitor
grounds , and the therm al pad to the gr ound is land, s hould c ontinue through to the PC B GND layer as
well.
Recommendation 6: As with any switch-mode DC/DC converter, do not run sensitive signal or
c ontr ol lines underneath the c onverter pac kage.
Figure 6 shows an example schematic for the EP53x2QI using the internal voltage select. In this
example, the device is set to a V OUT of 1.2V (VS2= 0, VS1= 1, VS 0=1).
VOUT
NC
NC
NC
VOUT
VFB
VSENSE
NC
NC
NC
NC
VOUT
GND
GND
VIN
ENABLE
VS0
VS1
VS2
1
2
6
5
4
3
10
9
8
7
11
12
13
14
15
16
20
19
18
17
VIN
AGND
4.7uF/2.2uF 10µF
VIN VOUT
(see layout recommendation 3)
Fi gure 6. Ex am ple a ppl i ca tion, Vout=1.2V.
Figure 7 shows an example schematic using an external voltage divider. VS0=VS1=VS2= “1”. The
resistor values are chosen to give an output voltage of 2.6V .
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03132 October 11, 2013 Rev H
EP5382QI/EP5362QI/EP5352QI
V
OUT
NC
NC
NC
V
OUT
V
FB
V
SENSE
NC
NC
NC
NC
V
OUT
GND
GND
V
IN
ENABLE
VS0
VS1
VS2
1
2
6
5
4
3
10
9
8
7
11
12
13
14
15
16
20
19
18
17
V
IN
AGND
4.7uF 10µF
V
IN
V
OUT
Ra=200K
Rb=60K
(see layout recommendation 3)
Fi gure 7. S che m ati c show i ng the use of e xte rna l di vider opti on, V out = 2.6V.
Figur e 8 s how s tw o exam ple boar d layouts . Note the placem ent of the input and output c apac itors .
They are plac ed c los e to the devic e to m inim iz e the phys ic al area of the AC c urrent loops . Note the
plac em ent of the vias per rec om m endation 3.
Figure 8. E xam pl e lay o ut showi ng PCB t op lay er, as wel l as dem onst rati n g use of v ias from in put, outpu t filter
capacitor lo c al grounds, and the rm al pad, t o PCB sy stem ground .
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03132 October 11, 2013 Rev H
EP5382QI/EP5362QI/EP5352QI
Ordering Information
Part Num ber
Te m p Ra nge
Package
EP5352QI -40°C to +85°C 20-pi n QF N T&R
EP5362QI -40°C to +85°C 20-pi n QF N T&R
EP5382QI
-40°C to +85°C
20-pin QFN T&R
EVB-EP5352QI EP5352QI Eval uat i on Board
EVB-EP5362QI
EP5362QI E val uati on B oard
EVB-EP5382QI EP5382QI E val uat i on Board
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Design Considerations for Lead-Frame Based Modules
Exp osed Metal on Bottom Of P ackage
Altera has developed a break-through in pac kage tec hnology that utiliz es the lead fram e as part of
the elec tric al c irc uit. The lead fram e offers m any advantages in therm al perfor m anc e, in reduc ed
elec tr ic al lead res is tanc e, and in overall foot pr int. How ever, it does require som e s pec ial
considerations.
As par t of the pac kage as s em bly proc es s , lead fram e c ons truc tion r equires that for m ec hanic al
s upport, s om e of the lead-fr am e m etal be expos ed at the point w here w ire-bond or internal passives
are attached. This res ults in s everal s m all pads being expos ed on the bottom of the pac kage.
O nly the lar ge therm al pad and the per im eter pads ar e to be m ec hanic ally or elec tric ally c onnec ted to
the PC board. The PCB top layer under the EP53x2QI should be clear of any metal except for the
large thermal pad. The “grayed-out” area in Figure 9 represents the area that should be clear of any
m etal ( trac es , vias , or planes ), on the top layer of the P CB .
NOTE: Clearanc e betw een the various expos ed m etal pads , the therm al gr ound pad, and the
perim eter pins , m eets or exc eeds JED EC r equirem ents for lead fr am e pac kage c ons truc tion ( JED EC
MO-220, Is s ue J, D ate May 2005) . The s eparation betw een the large ther m al pad and the neares t
adjacent metal pad or pin is a minimum of 0.20mm, including tolerances. This is shown in Figure 10.
Figure 9. E xp osed m et al and mec hanica l dim ensions of the package . The g ray area repr esents the bottom metal
no-connect area. This area should be clear of an y traces , plan es , or vias , on the top layer of the PCB.
Ther m al Pad.
Connec t to
Ground plane
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Contact Information
Altera Corporation
101 Innovation Drive
San Jos e, C A 95134
Phone: 408-544-7000
www.altera.com
© 2013 Altera Corporation—Confidential. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, HARDCOPY, MAX, MEGACORE, NIOS,
QU AR TU S and STR ATIX w or ds and logos ar e tr ademar ks of Alter a C or por atio n and r egister ed in the U.S. Patent and Trademark Office and in other
countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at
www.altera.com/com mon/legal.html. Altera warrants perform ance of i ts semi conductor products to current speci fi cati ons i n accordance wi th Altera's
standar d w ar r anty , but r eser ves the r ight to make changes to any pr oduct s and ser vices at any time without not ice. Alter a assumes no responsi bi lity or
liabil i ty ar ising out of the appl ication or use of any i nform ation, product, or service descri bed herein except as expressl y agreed to i n writi ng by Al tera.
Alter a customer s ar e advised to obt ain the latest v er sion of dev ice specifi cat io ns befor e r elyi ng on any publ ished info r matio n and before placing orders
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18 www.altera.com/enpirion
03132 October 11, 2013 Rev H
