1/13
XC61H Series
Voltage Detector with Delay Circuit Built-In
VIN
RESETB
VSS
3
1
2
R pull
RESETB
INPUT
VIN
VSS
Not necessary with CMOS output products
μP
XC61HN series
■GENERAL DESCRIPTION
The XC61H series is a highly accurate, low power consumption CMOS voltage detector with a delay circuit. Detect voltage is
accurate with minimal temperature drift. Output configurations are available in both CMOS and N-channel open drain.
Since the full delay circuit is built-in, an external delay-time capacitor is not necessary so that high density mounting is possible.
■APPLICATIONS
●Microprocessor reset circuitry
●System battery life and charge voltage monitors
●Memory battery back-up circuits
●Power-on reset circuits
●Power failure detection
●Delay circuitry
■TYPICAL PERFORMANCE
CHARACTERISTICS
■FEATURES
Detect Voltage Accuracy : ± 2%
Low Power Consumption
: 1.0μA(TYP.)[ VIN=2.0V ]
Detect Voltage Range
:
1.6V ~ 6.0V (0.1V increments)
Operating Voltage Ran ge
: 0.7V ~ 10.0V
Detect Vo ltage Temperature Characteristics
: ±100ppm/℃(TYP.)
Built-In Release Delay time : 1ms (MIN.)
50ms (MIN.)
80ms (MIN.)
Output Configuration :
N-ch
open drain or CMOS
Package :
SOT-23
Environmentally Friendly : EU RoHS Compliant, Pb Free
■TYPICAL APPLICATION CIRCUITS
Ambient Temperature: Ta (℃)
●Release Delay Time (tDR) vs. Ambient Temperature
ETR0212-003a
Release Delay Time: tDR(ms)
ＸＣ６１ＨＣ３０１２
Rpull is not necessary with CMOS output products
2/14
XC61H Series
（TOP VIEW）
DESIGNATOR ITEM SYMBOL DESCRIPTION
C CMOS output
① Output Configuration N N-ch open drain output
②③ Detect Voltage (VDF) 16 ~ 60 e.g. 2.5V → ②2 , ③5
1 50ms ~ 200ms
4 80ms ~ 400ms
④ Release Delay Time
5 1ms ~ 50ms
⑤ Detect Accuracy 2 ± 2.0%(*2)
⑥⑦-⑧(*1) Package
(Oder Unit) MR-G SOT-23 (3000/Reel)
PIN NUMBER
SOT-23 PIN NAME FUNCTION
1 VSS Ground
2 RESETB Output
3 VIN Supply Voltage Input
■PIN CONFIGURATION
■PRODUCT CLASSIFICATION
●Ordering Information
XC61H ①②③④⑤⑥⑦-⑧(*1)
■BLOCK DIAGRAMS
(1)CMOS output
■PIN ASSIGNMENT
(2)N-ch open drain output
(*1) The ”-G” suffix indicates that the products are Halogen and Antimony free as well as being fully RoHS compliant.
(*2) No parts are available with an accuracy of ± 1%
3/13
XC61H
Series
PARAMETER SYMBOL RATINGS UNITS
Input Voltage VIN 12.0 V
Output Current IOUT 50 mA
CMOS
V
SS
-0.3 ~V
IN
+0.3
Output Voltage
N-ch open drain RESTB VSS -0.3 ~ 12 V
Power Dissipation
SOT-23 Pd 250 mW
Operating Temperature Range Topr -30～+80 ℃
Storage Temperature Range Tstg -40～+125 ℃
PARAMETER
SYMBOL
CONDITIONS MIN. TYP. MAX.
UNITS
CIRCUIT
Detect Voltage VDF
V
DF(T)
x 0.98
V
DF(T)
V
DF(T)
x 1.02 V ①
Hysteresis Width VHYS VDF
x 0.02
VDF
x 0.05
VDF
x 0.08 V ①
V
IN = 1.5V - 0.9 2.6
V
IN = 2.0V - 1.0 3.0
V
IN = 3.0V - 1.3 3.4
VIN = 4.0V - 1.6 3.8
Supply Current (*1) ISS
VIN = 5.0V - 2.0 4.2
μA ②
Operating Voltage VIN VDF=1.6V～6.0V 0.7 - 10.0 V ①
V
IN = 1.0V 1.0 2.2 -
V
IN = 2.0V 3.0 7.7 -
N-ch, VDS = 0.5V VIN = 3.0V 5.0 10.1 -
V
IN = 4.0V 6.0 11.5 -
V
IN = 5.0V 7.0 13.0 -
③
Output Current IOUT
P-ch, VDS=2.1V
(CMOS Output)
VIN = 8.0V -10.0 -2.0
mA
④
CMOS Output - 0.01 -
Leakage
Current
Nch Open Drain
ILEAK V
IN=10.0V, VOUT=10.0V
- 0.01 0.1
μA ③
Detect Voltage
Temperature Characteristics
Δ
V
DF
Δ
Topr
･
V
DF
- ±100 -
ppm/℃-
50 - 200
80 - 400
Release Delay Time
(VDR → RESEB inversion)
tDR VIN changes from 0.6V to 10V
1 - 50
ms ⑤
Ta= 25℃
VDF (T) is nominal detect voltage value
Release Voltage: VDR = VDF + VHYS
(*1) The supply current during power-start until output being stable (during release operation) is 2μA greater with comparison to the period
after the completion of release operation because of the shoot-through current in delay current.
■
A
BSOLUTE MAXIMUM RATINGS
Ta = 2 5℃
■ELECTRICAL CHARACTERISTICS
4/14
XC61H Series
■OPERATIONAL EXPLANATION
●CMOS output
① An input voltage VIN starts higher than the release voltage VDR. Then, VIN voltage will gradually fall. When VIN voltage is
higher than detect voltage VDF, output voltage RESETB is equal to the VIN voltage.
*Note that high impedance exists at RESETB with the N-channel open drain configuration. If the RESETB pin is pulled
up, RESETB will be equal to the pull up voltage.
② When VIN falls below VDF, RESETB will be equal to ground voltage VSS level (detect state).
* Note that this also applies to N-channel open drain configurations.
③ When VIN falls to a level below that of the minimum operating voltage VMIN, output will become unstable.
*When the output pin is generally pulled up with N-channel open drain configurations, output will be equal to pull up
voltage.
④ When VIN rises above the VSS level (excepting levels lower than minimum operating voltage), RESETB will be equal to
VSS until VIN reaches the VDR level.
⑤ Although VIN will rise to a level higher than VDR, RESETB maintains ground voltage level via the delay circuit.
⑥ After taking a release delay time, VIN voltage will be output at the RESETB pin.
*High impedance exists with the N-channel open drain configuration and that voltage will be dependent on pull up.
●Timing Chart
Notes:
1. The difference between VDR and VDF represents the hysteresis width.
2. Release delay time (tDR) represents the time it takes until when VIN voltage appears at RESETB pin once the input
voltage has exceeded the VDR level.
Release Delay Time (tDR)
Output Voltage (RESETB)
5/13
XC61H
Series
■NOTES ON USE
1. Please use this IC within the stated maximum ratings. The IC is liable to malfunction should the ratings be exceeded.
2. When a resistor is connected between the VIN pin and the input with CMOS output configurations, irregular oscillation
may occur as a result of voltage drops at RIN if load current (IOUT) exists. It is therefore recommend that no resistor be
added. (refer to Figure 1 below)
3. When a resistor is connected between the VIN pin and the input with CMOS output configurations, irrespective of N-ch
output configurations, oscillation may occur as a result of shoot-through current at the time of voltage release even if
load current (IOUT) does not exist. (refer to Figure 1 below)
4. By connecting a resistor between the VIN pin and the input, detect and release voltages will rise as a result of the IC's
supply current flowing through the VIN pin.
5. If a resistor (RIN) must be used, then please use with as small a level of input impedance as possible in order to control
the occurrences of oscillation as described above.
Further, please ensure that RIN is less than 10kΩ and that CIN is more than 0.1μF (Figure 1). In such cases, detect
and release voltages will rise due to voltage drops at RIN brought about by the IC's supply current.
6. Depending on circuit's operation, release delay time of this IC can be widely changed due to upper limits or lower limits
of operational ambient temperature.
●Irregular Oscillations
(1) Irregular oscillation as a result of output current with the CMOS output configuration:
When the voltage applied at IN rises, release operations commence and the detector's output voltage increases.
Load current (IOUT) will flow through RL. Because a voltage drop (RIN x IOUT) is produced at the RIN resistor, located
between the input (IN) and the VIN pin, the load current will flow via the IC's VIN pin. The voltage drop will also lead to
a fall in the voltage level at the VIN pin. When the VIN pin voltage level falls below the detect voltage level, detect
operations will commence. Following detect operations, load current flow will cease and since voltage drop at RIN will
disappear, the voltage level at the VIN pin will rise and release operations will begin over again.
Irregular oscillation may occur with this "release - detect - release" repetition.
Further, this condition will also appear via means of a similar mechanism during detect operations.
(2) Irregular oscillation as a result of shoot-through current:
Since the XC61H series are CMOS ICS, shoot-through current will flow when the IC's internal circuit switching
operates (during release and detect operations). Consequently, irregular oscillation is liable to occur during release
voltage operations as a result of output current which is influenced by this shoot-through current (Figure 3).
Since hysteresis exists during detect operations, irregular oscillation is unlikely to occur.
図 1．入力抵抗を入れた時の回路例
Fi
g
ure 1 Use of in
p
ut resistor RIN
XC61HN Series XC61HC Series
6/14
XC61H Series
ＲＩＮ
ＲＩＮ
×ＩOUT VIN RESETB
VSS
ＸＣ６１HＣシリーズ
電圧降下
ＩOUT
ＲL
ＸＣ６１HNシリーズ
ＲＩＮ
ＲＩＮ×Ｉ SS *
ＩSS*
（貫通電流を含む）
ＸＣ６１HＣシリーズ
電圧降下 VIN RESETB
VSS
■NOTES ON USE
●Irregular Oscillations (Continued)
図 2．出力電流による発振
図 3．貫通電流による発振
XC61HC Series
Voltage drop
Figure 2 Irregular Oscillation by output current
XC61HC Series
XC61HN Series
Voltage drop
(Includes shoot-through current)
Figure 3 Irregular Oscillation by shoot-through current
7/13
XC61H
Series
測定回路１ 測定回路２
測定回路３ 測定回路４
測定回路５
V
V
VIN
VIN
VSS
*R220kΩ
RESETB
A
VIN
VIN
VSS
RESETB
A
VIN
VIN
VSS VDS
RESETB A
VIN
VIN
VSS
VDS
RESETB
VIN
VSS
220kΩ
measurement of
waveform
*R
RESETB
■TEST CIRCUITS
*R is not necessary with CMOS output products.
●Circuit ① ●Circuit ②
●Circuit ③ ●Circuit ④
●Circuit
⑤
8/14
XC61H Series
■TYPICAL PERFORMANCE CHARACTERISTICS
検出電圧,解除電圧 VDF,VDR (V)
出力電圧 VOUT (V)
出力電圧 VOUT (V)
XC61HN1612
XC61HN1612
XC61HN1612
XC61HN1612
XC61HN2512
XC61HN2512
X
C61HN2512
XC61HN2512
X
C61HN1612
XC61HN3512
XC61HN3512
XC61HN3512
R-pull:100kΩ
Ta=- 3 0 ℃
25℃
80℃
R-pull:100kΩ
Ta=- 3 0 ℃
25℃
80℃
R-pull:100kΩ
Ta=- 3 0 ℃
25℃
80℃
Detect, Release Voltage: VDF,VDR (V)
Detect, Release Voltage: VDF,VDR (V)
Detect, Release Voltage: VDF,VDR (V)
(3) Detect Voltage, Release Voltage vs. Input Voltage
9/13
XC61H
Series
■TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
Release Delay Time: tDR (ms)
Release Delay Time: tDR (ms)
Release Delay Time: tDR (ms)
XC61HN1612
XC61HC2712
XC61HN2512
XC61HN2512
X
C61HN3512 XC61HN3512
XC61HN
3
512
XC61HC
4412
XC61HC
3012
X
C61HC3042 XC61HC3052
（7）Ambient Temperature vs. Release Delay Time (tDR)
10/14
XC61H Series
■TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
（8）Input Voltage vs. Release Delay Time (tDR)
Release Delay Time: tDR (ms)
XC61HC2712
11/13
XC61H
Series
■PACKAGING INFORMATION
●SOT-23
12/14
XC61H Series
MARK PRODUCTS SERIES
8 XC61H*******-G
MARK VOLTAGE
(V) MARK VOLTAGE
(V)
A 1. X P 1. X
B 2. X R 2. X
C 3. X S 3. X
D 4. X T 4. X
E 5. X U 5. X
F 6. X V 6. X
MARK
DELAY TIME
50ms～200ms
DELAY TIME
80ms～400ms
DELAY TIME
1ms～50ms
DETECT
VOLTAGE
(V) （XC61H***1***-G） （XC61H***4***-G） （XC61H***5***-G）
X.0 0 A N
X.1 1 B P
X.2 2 C R
X.3 3 D S
X.4 4 E T
X.5 5 F U
X.6 6 H V
X.7 7 K X
X.8 8 L Y
X.9 9 M Z
■MARKING RULE
●SOT-23
③ represents decimal number of detect voltage and delay time.
④ represents production lot number
0 to 9, A to Z or inverted characters of 0 to 9, A to Z repeated.
(G, I, J, O, Q,W excluded)
*No character inversion used.
① represents product series
② standard：represents output configuration and integer number of detect voltage
CMOS out
ut
XC61HC series
N-channel o
p
en drain
(
XC61HN series
)
13/13
XC61H
Series
1. The products and product specifications contained herein are subject to change without
notice to improve performance characteristics. Consult us, or our representatives
before use, to confirm that the information in this datasheet is up to date.
2. We assume no responsibility for any infringement of patents, patent rights, or other
rights arising from the use of any information and circuitry in this datasheet.
3. Please ensure suitable shipping controls (including fail-safe designs and aging
protection) are in force for equipment employing products listed in this datasheet.
4. The products in this datasheet are not developed, designed, or approved for use with
such equipment whose failure of malfunction can be reasonably expected to directly
endanger the life of, or cause significant injury to, the user.
(e.g. Atomic energy; aerospace; transport; combustion and associated safety
equipment thereof.)
5. Please use the products listed in this datasheet within the specified ranges.
Should you wish to use the products under conditions exceeding the specifications,
please consult us or our representatives.
6. We assume no responsibility for damage or loss due to abnormal use.
7. All rights reserved. No part of this datasheet may be copied or reproduced without the
prior permission of TOREX SEMICONDUCTOR LTD.