FUJITSU SEMICONDUCTOR DATA SHEET DS07-13702-1E 16-bit Proprietary Microcontroller CMOS F2MC-16LX MB90520 Series MB90522/523/F523/V520 DESCRIPTION The MB90520 series is a general-purpose 16-bit microcontroller developed and designed by Fujitsu for process control applications in consumer products that require high-speed real-time processing. The instruction set of F2MC-16LX CPU core inherits AT architecture of F2MC*1 family with additional instruction sets for high-level languages, extended addressing mode, enhanced multiplication/division instructions, and enhanced bit manipulation instructions. The microcontroller has a 32-bit accumulator for processing long word data. The MB90520 series has peripheral resources of 8/10-bit A/D converter, a 8-bit D/A converter, UART (SCI), extended I/O serial interfaces 0 and 1, 8/16-bit up/down counter/timers 0 and 1, 8/16-bit PPG timers 0 and 1, I/O timer (16-bit free-run timers 1 and 2, input captures 0 and 1 (ICU), output compares 0 and 1 (OCU)), LCD controller/driver. *1: F2MC stands for FUJITSU Flexible Microcontroller. PACKAGE 120-pin Plastic LQFP 120-pin Plastic QFP (FPT-120P-M05) (FPT-120P-M13) MB90520 Series FEATURES * Clock Embedded PLL clock multiplication circuit Operating clock (PLL clock) can be selected from divided-by-2 of oscillation or one to four times the oscillation (at oscillation of 4 MHz, 3 MHz to 16 MHz). The system can be operated by an oscillation sub-clock (rated at 32.768 kHz). Minimum instruction execution time: 62.5 ns (at oscillation of 4 MHz, four times the PLL clock, operation at VCC of 5.0 V) * Maximum memory space 16 Mbytes * Instruction set optimized for controller applications Ri65data types (bit, byte, word, long word) Rich addressing mode (23 types) Enhanced signed multiplication/division instruction and RETI instruction functions Enhanced precision calculation realized by the 32-bit accumulator * Instruction set designed for high level language (C) and multi-task operations Adoption of system stack pointer Enhanced pointer indirect instructions Barrel shift instructions * Program patch function (for two address pointers) * Enhanced execution speed 4-byte instruction queue * Enhanced interrupt function 8 levels, 34 factors * Automatic data transmission function independent of CPU operation Extended intelligent I/O service function (EI2OS): Up to 16 channels * Embedded ROM size and types Mask ROM: 64 kbytes/128 kbytes Flash ROM: 256 kbytes Embedded RAM size: 4 kbytes/10 kbytes (mass-produced products) 4 kbytes (flash memory) 6 kbytes (evaluation chip) * Low-power consumption (stand-by) mode Sleep mode (mode in which CPU operating clock is stopped) Stop mode (mode in which oscillation is stopped) CPU intermittent operation mode Hardware stand-by mode Clock mode (mode in which other than sub-oscillation and timebase timer are stopped) * Process CMOS technology * I/O port General-purpose I/O ports (CMOS): 53 ports General-purpose I/O ports (via pull-up resistors): 24 ports General-purpose I/O ports (open-drain): 8 ports Total: 85 ports (Continued) 2 MB90520 Series (Continued) * Timer Timebase timer/watchdog timer: 1 channel 8/16-bit PPG timers 0, 1: 8-bit x 2 channels or 16-bit x 1 channel 16-bit re-load timers 0, 1: 2 channels * 16-bit I/O timer 16-bit free-run timers 1, 2: 2 channels Input captures 0, 1 (ICU): Generates an interrupt request by latching a 16-bit free-run timer counter value upon detection of an edge input to the pin. Output compares 0, 1 (OCU): Generates an interrupt request and reverse the output level upon detection of a match between the 16-bit free-run timer counter value and the compare setting value. 8/16-bit up/down counter/timers 0, 1: 1 channel (8-bit x 2 channels) * Extended I/O serial interfaces 0, 1: 1 channel * UART (SCI) With full-duplex double buffer Clock asynchronized or clock synchronized transmission can be selectively used. * DTP/external interrupt circuit (8 channels) A module for starting extended intelligent I/O service (EI2OS) and generating an external interrupt triggered by an external input. * Wake-up interrupt Receives external interrupt requests and generates an interrupt request upon an "L" level input. * Delayed interrupt generation module Generates an interrupt request for switching tasks. * 8/10-bit A/D converter (8 channels) 8/10-bit resolution can be selectively used. Starting by an external trigger input. Conversion time: 16.0 s or slower * 8-bit D/A converter (based on the R-2R system) 8-bit resolution: 2 channels (independent) Setup time: 12.5 s * Clock timer: 1 channel * LCD controller/driver A common driver and a segment driver that can directly drive the LCD (liquid crystal display) panel * Clock output function Note: Do not set external bus mode for the MB90520 series because it cannot be operated in this mode. 3 MB90520 Series PRODUCT LINEUP Part number MB90522 MB90523 MB90F523 MB90V520 Mass-produced product (flash ROM product) Evaluation product Item Mass-produced products (mask ROM products) Classification ROM size 64 kbytes 128 kbytes RAM size None 6 kbytes The number of instructions: 340 Instruction bit length: 8 bits, 16 bits Instruction length: 1 byte to 7 bytes Data bit length: 1 bit, 8 bits, 16 bits CPU functions Minimum execution time: 62.5 ns (at machine clock of 16 MHz) Minimum execution time: 100 ns (at machine clock of 10 MHz) Minimum execution time: 62.5 ns (at machine clock of 16 MHz) Interrupt processing time: 1.5 s (at machine clock of 16 MHz, minimum value) General-purpose I/O ports (CMOS output): 53 General-purpose I/O ports (via pull-up resistor): 24 General-purpose I/O ports (N-ch open-drain output): 8 Total: 85 Ports Clock synchronized transmission (62.5 kbps to 1 Mbps) Clock asynchronized transmission (1202 bps to 9615 bps) Transmission can be performed by bi-directional serial transmission or by master/slave connection. UART (SCI) 8/10-bit A/D converter Conversion precision: 8/10-bit can be selectively used. Number of inputs: 8 One-shot conversion mode (converts selected channel only once) Scan conversion mode (converts two or more successive channels and can program up to 8 channels.) Continuous conversion mode (converts selected channel continuously) Stop conversion mode (converts selected channel and stop operation repeatedly) 8/16-bit PPG timers 0, 1 Number of channels: 1 (8-bit x 2 channels) PPG operation of 8-bit or 16-bit A pulse wave of given intervals and given duty ratios can be output. Pulse interval: 62.5 ns to 1 s (at oscillation of 4 MHz, machine clock of 16 MHz) 8/16-bit up/down counter/ timers 0, 1 Number of channels: 1 (8-bit x 2 channels) Event input: 6 channels 8-bit up/down counter/timer used: 2 channels 8-bit re-load/compare function supported: 1 channel 16-bit I/O timer 16-bit freerun timers 1, 2 Number of channels: 2 Overflow interrupts (Continued) 4 MB90520 Series (Continued) Part number MB90522 MB90523 MB90F523 MB90V520 Item 16-bit I/O timer Output compares 0, 1 (OCU) Number of channels: 8 Pin input factor: A match signal of compare register Input captures 0, 1 (ICU) Number of channels: 2 Rewriting a register value upon a pin input (rising, falling, or both edges) DTP/external interrupt circuit Wake-up intrrupt Number of inputs: 8 Started by a rising edge, a falling edge, an "H" level input, or an "L" level input. External interrupt circuit or extended intelligent I/O service (EI2OS) can be used. Number of inputs: 8 Started by an "L" level input. Delayed interrupt generation module An interrupt generation module for switching tasks Used in real-time operating systems. Extended I/O serial interfaces 0, 1 Clock synchronized transmission (3125 bps to 1 Mbps) LSB first/MSB first Timebase timer 8-bit D/A converter LCD controller/driver Watchdog timer Low-power consumption (stand-by) mode 18-bit counter Interrupt interval: 1.024 ms, 4.096 ms, 16.384 ms, 131.072 ms (at oscillation of 4 MHz) 8-bit resolution Number of channels: 2 channels Based on the R-2R system Number of common output pins: 4 Number of segment output pins: 32 Number of power supply pins for LCD drive: 4 RAM for LCD indication: 16 bytes Booster for LCD drive: Internal Split resistor for LCD drive: Internal Reset generation interval: 3.58 ms, 14.33 ms, 57.23 ms, 458.75 ms (at oscillation of 4 MHz, minimum value) Sleep/stop/CPU intermittent operation/clock timer/hardware stand-by Process Power supply voltage for operation* CMOS 3.0 V to 5.5 V 4.0 V to 5.5 V 3.0 V to 5.5 V * : Varies with conditions such as the operating frequency. (See section " Electrical Characteristics.") Assurance for the MB90V520 is given only for operation with a tool at a power voltage of 3.0 V to 5.5 V, an operating temperature of 0 to 55 degrees centigrade, and an operating frequency of 1 MHz to 16 MHz. 5 MB90520 Series PACKAGE AND CORRESPONDING PRODUCTS Package MB90522 MB90523 MB90F523 FPT-120P-M05 FPT-120P-M13 : Available x : Not available Note: For more information about each package, see section " Package Dimensions." DIFFERENCES AMONG PRODUCTS Memory Size In evaluation with an evaluation chips, note the difference between the evaluation chip and the chip actually used. The following items must be taken into consideration. * The MB90V520 does not have an internal ROM, however, operations equivalent to chips with an internal ROM can be evaluated by using a dedicated development tool, enabling selection of ROM size by settings of the development tool. * In the MB90V520, images from FF4000H to FFFFFFH are mapped to bank 00, and FE0000H to FF3FFFH to mapped to bank FE and FF only. (This setting can be changed by configuring the deveolpment tool.) * In the MB90522, images from FF4000H to FFFFFFH are mapped to bank 00, and FF0000H to FF3FFFH to bank FF only. * In the MB90523/F523, images from FF4000H to FFFFFFH are mapped to bank 00, and FE0000H to FF3FFFH to bank FE and bank FF. 6 MB90520 Series PIN ASSIGNMENT 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 P30 VSS P27/ADTG P26/ZIN0/INT7 P25/BIN0 P24/AIN0 P23/IC11 P22/IC10 P21/IC01 P20/IC00 P17/WI7 P16/WI6 P15/WI5 P14/WI4 P13/WI3 P12/WI2 P11/WI1 P10/WI0 P07 P06/INT6 P05/INT5 P04/INT4 P03/INT3 P02/INT2 P01/INT1 P00/INT0 VCC X1 X0 VSS (Top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 RST MD0 MD1 MD2 HST V3 V2 V1 V0 P97/SEG31 P96/SEG30 P95/SEG29 P94/SEG28 P93/SEG27 P92/SEG26 P91/SEG25 X0A X1A P90/SEG24 P87/SEG23 P86/SEG22 P85/SEG21 P84/SEG20 P83/SEG19 P82/SEG18 P81/SEG17 P80/SEG16 VSS P77/COM3 P76/COM2 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 PA6/SEG14 PA7/SEG15 VSS C P50/SIN2/AIN1 P51/SOT2/BIN1 P52/SCK2/ZIN1 DVCC DVSS P53/DA0 P54/DA1 AVCC AVRH AVRL AVSS P60/AN0 P61/AN1 P62/AN2 P63/AN3 P64/AN4 P65/AN5 P66/AN6 P67/AN7 VCC P70/TI0/OUT4 P71/TO0/OUT5 P72/TI1/OUT6 P73/TO1/OUT7 P74/COM0 P75/COM1 P31/CKOT P32/OUT0 P33/OUT1 P34/OUT2 P35/OUT3 P36/PG00 P37/PG01 VCC P40/PG10 P41/PG11 P42/SIN0 P43/SOT0 P44/SCK0 P45/SIN1 P46/SOT1 P47/SCK1 SEG00 SEG01 SEG02 SEG03 SEG04 SEG05 SEG06 SEG07 PA0/SEG08 PA1/SEG09 PA2/SEG10 PA3/SEG11 PA4/SEG12 PA5/SEG13 (FPT-120P-M05) (FPT-120P-M13) 7 MB90520 Series PIN DESCRIPTION Pin no. Pin name LQFP-120*1 QFP-120*2 Circuit type 92, 93 X0, X1 A This is a high-speed crystal oscillator pin. 74, 73 X0A, X1A B This is a low-speed crystal oscillator pin. MD0 to MD2 C This is an input pin for selecting operation modes. Connect directly to VCC or VSS. 90 RST C This is external reset request signal. 86 HST C This is a hardware stand-by input pin. P00 to P06 D This is a general-purpose I/O port. This function can be set by the port 0 input pull-up resistor setup register (RDR0) for input. For output, however, this function is invalid. 89 to 87 95 to 101 INT0 to INT6 102 103 to 110 This is a request input pin of the DTP/external interrupt circuit ch.0 to ch.6. P07 D This is a general-purpose I/O port. This function can be set by the port 0 input pull-up resistor setup register (RDR0) for input. For output, however, this function is invalid. P10 to 17 D This is a general-purpose I/O port. This function can be set by the port 1 input pull-up resistor setup register (RDR1) for input. For output, however, this function is invalid. WI0 to WI7 111, 112, 113, 114 P20, P21, P22, P23 This is an I/O pin for wake-up interrupts. E 115 P24 E AIN0 116 P25 BIN0 *1: FPT-120P-M05 *2: FPT-120P-M13 This is a general-purpose I/O port. This is a trigger input pin for input capture (ICU) 0 and 1. Since this input is used as required for input capture 0 and 1 (ICU) ch.0, ch.01, ch.10 and ch.11 input operation, output by other functions must be suspended except for intentional operation. IC00, IC01, IC10, IC11 8 Function This is a general-purpose I/O port. This port can be used as count clock A input for 8/16-bit up/down counter/timer 0. E This is a general-purpose I/O port. This port can be used as count clock B input for 8/16-bit up/down counter/timer 0. (Continued) MB90520 Series Pin no. Pin name LQFP-120*1 QFP-120*2 117 118 P26 Circuit type F Function This is a general-purpose I/O port. ZIN0 This port can be used as count clock Z input for 8/16-bit up/down counter/timer 0. INT7 This is a request input pin of the DTP/external interrupt circuit ch.7. P27 F This is a general-purpose I/O port. This is external trigger input pin of the 8/10-bit A/D converter. Since this input is used as required for 8/10-bit A/D converter input operation, output by other functions must be suspended except for intentional operation. ADTG 120 P30 E This is a general-purpose I/O port. 1 P31 E This is a general-purpose I/O port. CKOT 2 P32 This is a clock monitor function output pin. This function is vaild when clock monitor output is enabled. E OUT0 3 P33 This is an event output pins for output compare 0 (OCU) ch.0. This function is valid when output for each channel is enabled. E OUT1 4 P34 P35 E P36 PG00 *1: FPT-120P-M05 *2: FPT-120P-M13 This is a general-purpose I/O port. This function becomes vaild when waveform output from the OUT2 is disabled. This is an event output pins for output compare 0 (OCU) ch.2. This function is valid when output for each channel is enabled. E OUT3 6 This is a general-purpose I/O port. This function becomes vaild when waveform output from the OUT1 is disabled. This is an event output pins for output compare 0 (OCU) ch.1. This function is valid when output for each channel is enabled. OUT2 5 This is a general-purpose I/O port. This function becomes vaild when waveform output from the OUT0 is disabled. This is a general-purpose I/O port. This function becomes vaild when waveform output from the OUT3 is disabled. This is an event output pins for output compare 0 (OCU) ch.3. This function is valid when output for each channel is enabled. E This is a general-purpose I/O port. This function becomes vaild when waveform output from the PG00 is disabled. This is an output pin of 8/16-bit PPG timer 0. This function becomes valid when waveform output from PG00 is enabled. (Continued) 9 MB90520 Series Pin no. Pin name LQFP-120*1 QFP-120*2 7 P37 Circuit type Function E This is a general-purpose I/O port. This function becomes vaild when waveform output from the PG01 is disabled. PG01 9, 10 P40, P41 This is an output pin of 8/16-bit PPG timer 0. This function becomes valid when waveform output from PG01 is enabled. D PG10, PG11 11 P42 This is an output pin of 8/16-bit PPG timer 1. This function becomes valid when waveform outputs from PG10 and PG11 are enabled. D SIN0 12 P43 P44 D P45 SIN1 *1: FPT-120P-M05 *2: FPT-120P-M13 10 This is a general-purpose I/O port. This function can be set by the pull-up resistor setup register (RDR4) for input. For output, however, this function is invalid. This is a serial data output pin of UART (SCI). This function becomes valid when serial data output from UART (SCI) is enabled. D SCK0 14 This is a general-purpose I/O port. This function can be set by the pull-up resistor setup register (RDR4) for input. For output, however, this function is invalid. This is a serial data input pin of UART (SCI). Because this input is used as required when UART (SCI) is performing input operations, and it is necessary to stop outputs by other functions unless such outputs are made intentionally. When using other output functions as well, disable output during SIN operation. SOT2 13 This is a general-purpose I/O port. This function becomes vaild when waveform output from the PG10 and PG11 are disabled. This function can be set by the pull-up resistor setup register (RDR4) for input. For output, however, this function is invalid. This is a general-purpose I/O port. This function can be set by the pull-up resistor setup register (RDR4) for input. For output, however, this function is invalid. This is a serial clock I/O pin of UART (SCI). This function becomes valid when serial clock output from UART (SCI) is enabled. D This is a general-purpose I/O port. This function can be set by the port 4 input pull-up resistor setup register (RDR4) for input. For output, however, this function is invalid. This is a data input pin for extended I/O serial interface 0. Since this input is used as required for serial data input operation, output by other functions must be suspended except for intentional operation. When using other output functions as well, disable output during SIN operation. (Continued) MB90520 Series Pin no. Pin name LQFP-120*1 QFP-120*2 15 P46 Circuit type E SOT1 16 P47 36 37 40, 41 P50 D This is a general-purpose I/O port. This function can be set by the port 4 input pull-up resistor setup register (RDR4) for input. For output, however, this function is invalid. This is a serial clock I/O pin for extended I/O serial interface 0. This function becomes valid when serial clock output from SCK1 is enabled. D This is a general-purpose I/O port. SIN2 This is a data input pin for extended I/O serial interface 1. Since this input is used as required for serial data input operation, output by other functions must be suspended except for intentional operation. AIN1 This port can be used as count A input for 8/16-bit up/down counter/timer 1. P51 D This is a general-purpose I/O port. SOT2 This function becomes valid when serial data output from SOT2 is enabled. BIN1 This port can be used as count B input for 8/16-bit up/down counter/timer 1. P52 D This is a general-purpose I/O port. SCK2 This is a serial clock I/O pin for extended I/O serial interface 1. This function becomes valid when serial clock output from serial SCK2 is enabled. ZIN1 This port can be used as control clock Z input for 8/16-bit up/down counter/timer 1. P53, P54 I DA0, DA1 46 to 53 This is a general-purpose I/O port. This function can be set by the port 4 input pull-up resistor setup register (RDR4) for input. For output, however, this function is invalid. This is a data output pin for extended I/O serial interface 0. This function becomes valid when serial data output from SOT1 is enabled. SCK1 35 Function P60 to P67 AN0 to AN7 *1: FPT-120P-M05 *2: FPT-120P-M13 This is a general-purpose I/O port. These are analog signal output pins for 8-bit D/A converter ch.0 and ch.1. K This is a general-purpose I/O port. The input function become valid when the analog input enable register (ADER) is set to select a port. These are analog input pins of the 8/10-bit A/D converter. This function is valid when the analog input enable register (ADER) is enabled. (Continued) 11 MB90520 Series Pin no. Pin name LQFP-120*1 QFP-120*2 55, 57 56, 58 59 to 62 P70, P72 Circuit type E These are event input pins for 16-bit re-load timers 0 and 1. Since this input is used as required for 16-bit re-load timers 0 and 1 operation, output by other functions must be suspended except for intentional operation. OUT4, OUT6 These are event output pins for output compare 1 (OCU) ch.4 and ch.6. This function is valid when output for each channel is enabled. P71, P73 E These are output pins for 16-bit re-load timers 0 and 1. This function is valid with TO0 and TO1 output is enabled. OUT5, OUT7 These are event output pins for output compare 1 (OCU) ch.5 and ch.7. This function is valid when output for each channel is enabled. P74 to P77 L P80 to P87 P90, P91 to P97 This is a general-purpose I/O port. This function is valid with port output specified for the LCD controller/driver control register. These are common pins for the LCD controller/driver. This function is valid with common output specified for the LCD controller/driver control register. L This is a general-purpose I/O port. This function is valid with port output specified for the LCD controller/driver control register. These are segment outputs for the LCD controller/driver. This function is valid with common output specified for the LCD controller/driver control register. M This is a general-purpose I/O port. The maximum IOL can be 10mA. This function is valid with port output specified for the LCD controller/driver control register. These are ports for the LCD controller/driver. This function is valid with common output specified for the LCD controller/driver control register. SEG24, SEG25 to SEG31 17 to 24 SEG00 to SEG07 F These are pins dedicated to LCD segments 00 to 07 for the LCD controller/driver. 25 to 32 PA0 to PA7 L This is a general-purpose I/O port. This function is valid with port output specified for the LCD controller/driver control register. SEG08 to SEG15 *1: FPT-120P-M05 *2: FPT-120P-M13 12 This is a general-purpose I/O port. This function is valid with TO0 and TO1 output disabled. TO0, TO1 SEG16 to SEG23 72, 75 to 81 This is a general-purpose I/O port. TI0, TI1 COM to COM3 64 to 71 Function These are pins for LCD segments 08 to 15 for the LCD controller/ driver. Units of four ports or segments can be selected by the internal register in the LCD controller. (Continued) MB90520 Series (Continued) Pin no. LQFP-120*1 QFP-120*2 34 82 to 85 Circuit type Function C G This is a capacitance pin for power supply stabilization. Connect an external ceramic capacitor rated at about 0.1 F. This capacitor is not, however, required for the M90F523 (flash product). V0 to V3 N This is a pin for the reference power supply for the LCD controller/ driver. Pin name 8, 54, 94 VCC Power supply This is power supply (5.0 V) input pin to the digital circuit. 33, 63, 91 119 VSS Power supply This provides the GND level (0.0 V) input pin for the digital circuit. 42 AVCC H This is power supply to the analog circuit. Make sure to turn on/turn off this power supply with a voltage exceeding AVCC applied to VCC. 43 AVRH J This is a reference voltage input to the analog circuit. Make sure to turn on/turn off this power supply with a voltage exceeding AVRH applied to AVCC. 44 AVRL H This is a reference voltage input to the analog circuit. 45 AVSS H This is a GND level of the analog circuit. 38 DVCC H This is the Vref input pin for the D/A converter. The voltage to be applied must not exceed VCC. 39 DVSS H This is the GND level pin for the D/A converter. The potential must be the same as VSS. *1: FPT-120P-M05 *2: FPT-120P-M13 13 MB90520 Series I/O CIRCUIT TYPE Type Circuit Remarks A * High-speed oscillation feedback resistor approx. 1M X1 X0 Standby control signal B * Low-speed oscillation feedback resistor approx. 1M X1A X0A Standby control signal C * Hysteresis input rated at about 50 k R Hysteresis input D Selecting signal whether with a input pull-up resistor or without it * Hysteresis input can be set the input pullup resistor CMOS level output * Rated at about 50 k * Provided with a standby control function for input interruption R Hysteresis input IOL = 4 mA Standby control for input interruption (Continued) 14 MB90520 Series Type Circuit Remarks E * CMOS hysteresis input/output * CMOS level output * Provided with a standby control function for input interruption VCC R Hysteresis input IOL = 4 mA Standby control for input interruption F * Pins dedicated to segment output R G * C pin output (Pin for capacitor connection) N.C. pin for the MB90F523 H * Analog power input protector AVP I VCC R Hysteresis input * CMOS hysteresis input/output * Pin for analog output/CMOS output (During analog output, CMOS output is not produced.) (Analog output has priority over CMOS output: DAE = 1) * Provided with a standby control function for input interruption Standby control for input interruption IOL = 4 mA DAO (Continued) 15 MB90520 Series Type Circuit Remarks J * Input pin for ref+ power for the A/D converter Provided with a power protection ANE AVR ANE K * Hysteresis input/analog input * CMOS output * Provided with a standby control for input interruption R Hysteresis input Standby control for input interruption Analog input IOL = 4 mA L * Hysteresis input/output * Segment input * Standby control to cut off the input is available in segment input operation R Hysteresis input R SEG IOL = 4 mA M * Hysteresis input * N-ch open-drain output (High current for LCD drive) * Standby control to cut off the input is available in segment input operation R Hysteresis input IOL = 10 mA N * Reference power supply pin for the LCD controller R IOL = 10 mA 16 MB90520 Series HANDLING DEVICES 1. Make Sure that the Voltage not Exceed the Maximum Rating (to Avoid a Latch-up). In CMOS ICs, a latch-up phenomenon is caused when an voltage exceeding VCC or an voltage below VSS is applied to input or output pins or a voltage exceeding the rating is applied across VCC and VSS. When a latch-up is caused, the power supply current may be dramatically increased causing resultant thermal break-down of devices. To avoid the latch-up, make sure that the voltage not exceed the maximum rating. In turning on/turning off the analog power supply, make sure the analog power voltage (AVCC, AVRH, DVCC) and analog input voltages not exceed the digital voltage (VCC). And also make sure the voltage applied to the LCD power supply pin (V3 to V0) doesn't exceed the power supply voltage (VCC). 2. Connection of Unused Pins Leaving unused pins open may result in abnormal operations. Clamp the pin level by connecting it to a pull-up or a pull-down resistor. 3. Notes on Using External Clock In using the external clock, drive X0 pin only and leave X1 pin unconnected. * Using external clock X0 Open X1 MB90520 series 4. Power Supply Pins In products with multiple VCC or VSS pins, the pins of a same potential are internally connected in the device to avoid abnormal operations including latch-up. However, connect the pins external power and ground lines to lower the electro-magnetic emission level and abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total current rating. Make sure to connect VCC and VSS pins via lowest impedance to power lines. It is recommended to provide a bypass capacitor of around 0.1 F between VCC and VSS pin near the device. 5. Crystal Oscillator Circuit Noises around X0 or X1 pins may be possible causes of abnormal operations. Make sure to provide bypass capacitors via shortest distance from X0, X1 pins, crystal oscillator (or ceramic resonator) and ground lines, and make sure, to the utmost effort, that lines of oscillation circuit not cross the lines of other circuits. It is highly recommended to provide a printed circuit board art work surrounding X0 and X1 pins with an grand area for stabilizing the operation. 17 MB90520 Series 6. Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs Make sure to turn on the A/D converter power supply, D/A converter power supply (AVCC, AVRH, AVRL, DVCC, DVSS) and analog inputs (AN0 to AN7) after turning-on the digital power supply (VCC). Turn-off the digital power after turning off the A/D converter supply and analog inputs. In this case, make sure that AVRH and DVCC not exceed AVCC (turning on/off the analog and digital supplies simultaneously is acceptable). 7. Connection of Unused Pins of A/D Converter Connect unused pins of A/D converter and those of D/A converter to AVCC = DVCC = VCC, AVSS = AVRH = AVRL = VSS. 8. N.C. Pin The N.C. (internally connected) pin must be opened for use. 9. Notes on Energization To prevent the internal regulator circuit from malfunctioning, set the voltage rise time during energization at 50 or more s (0.2 V to 2.7 V). 10. Use of SEG/COM Pins for the LCD Controller/Driver as Ports In MB90520 series, pins SEG08 to SEG31, and COM0 to COM3 can also be used general-purpose ports. The electrical standard is such that pins SEG08 to SEG23, and COM0 to COM3 have the same ratings as the CMOS output port, while pins SEG24 to SEG31 have the same ratings as the open-drain type. 11. Initialization In the device, there are internal registers which is initialized only by a power-on reset. To initialize these registers turning on the power again. 12. Interrupt Recovery from the Standby State "H" level request must be an input request when using an external interrupt to recover from the standby state. In this case "L" level request may occur malfunction. 18 MB90520 Series BLOCK DIAGRAM Port 8*5, 9*5, A*5 24 F2MC-16LX CPU X0, X1 X0A, X1A RST HST Main clock Sub clock 4 7 7 Output 4 compare (OCU) 8/16-bit up/down counter/timer 0, 1 16-bit free-run timer 2 16-bit I/O timer 1 2 Input capture 0 (ICU) 16-bit free-run timer 1 P32/OUT0 P33/OUT1 P34/OUT2 P35/OUT3 P31/CKOT Output 4 compare 0 Input capture 1 (ICU) Intrnal data bus P20/IC00 P21/IC01 2 P30 P36/PG00 P37/PG01 Port 6*4 8 2 P40/PG10 P41/PG11 8/16-bit PPG timer 0, 1 P42/SIN0 P43/SOT0 P44/SCK0 UART (SCI) P45/SIN1 P46/SOT1 P47/SCK1 SIO ch.0 Interrupt controller Port 5*5 P50/SIN2/AIN1 P51/SOT2/BIN1 P52/SCK2/ZIN1 SIO ch.1 Port 1*2 Other pins MD0 to MD2, C, VCC, VSS 8 8 Wake-up interrupt P60/AN0 to P67/AN7 Port 2*4 Port 4*2 P10/WI0 to P17/WI7 8 AVCC AVSS AVRH AVRL P27/ADTG 8/10-bit A/D converter Port 3*4 2 P22/IC10 P23/IC11 Port 2*4 (OCU) Clock output P80/SEG16 to P87/SEG23 P90/SEG24 to P97/SEG31 PA0/SEG08 to PA7/SEG15 SEG00 to SEG07 V0 to V3 P74/COM0 to P77/COM3 P70/TI0/OUT4 P71/TO0/OUT5 P72/TI1/OUT6 P73/TO1/OUT7 16-bit I/O timer 2 Port 2*4 3 8 4 4 16-bit re-load timer 0 16-bit re-load timer 1 DTP/ external interrupt circuit P24/AIN0 P25/BIN0 P26/ZIN0/INT7 8 8 Port 7*4 Port 0*2 P07 P00/INT0 to P06/INT6 LCD controller/ driver Clock control block*1 (including timebase timer) 8 2 8-bit D/A converter x 2 ch. P53/DA0 P54/DA1 DVCC DVSS RAM ROM Notes: One 16-bit free-run timer 1 is supported although two free-run timers are seemingly supported. *1: The clock control circuit comprises a watchdog timer, a timebase timer, and a power consumption controller. *2: A register for setting a pull-up resistor is supported. *3: This is a high-current port for LCD drive. *4: A register for setting a pull-up resistor is supported. A signal in the CMOS level is input and output. *5: Also used for LCD output. With this port used as is, N-ch open-drain output develops. A register for setting a pull-up resistor. 19 MB90520 Series MEMORY MAP Single chip mode A mirroring function is supported. FFFFFFH ROM area Address #1 FE0000H 010000H ROM area (image of bank FF) Address #2 004000H 002000H Address #3 RAM Register 000100H 0000C0H 000000H Part number Peripheral Address #1* Address #2 * Address #3 * MB90522 FF0000H 004000H 001100H MB90523 FE0000H 004000H 001100H MB90F523 FE0000H 004000H 001100H : Internal access memory : Access prohibited *: Addresses #1, #2 and #3 are unique to the product type. Note: The ROM data of bank FF is reflected in the upper address of bank 00, realizing effective use of the C compiler small model. The lower 16-bit of bank FF and the lower 16-bit of bank 00 is assigned to the same address, enabling reference of the table on the ROM without stating "far". For example, if an attempt has been made to access 00C000H, the contents of the ROM at FFC000H are accessed actually. Since the ROM area of the FF bank exceeds 48k bytes, the whole area cannot be reflected in the image for the 00 bank. The ROM data at FF4000H to FFFFFFH looks, therefore, as if it were the image for 00400H to 00FFFFH. Thus, it is recommended that the ROM data table be stored in the area of FF4000H to FFFFFFH 20 MB90520 Series F2MC-16LX CPU PROGRAMMING MODEL * Dedicated registers AH AL : Accumlator (A) Dual 16-bit register used for storing results of calculation etc. The two 16-bit registers can be combined to be used as a 32-bit register. USP : User stack pointer (USP) The 16-bit pointer for containing a user stack address. SSP : System stack pointer (SSP) The 16-bit pointer for displaying the status of the system stack address. PS : Processor status (PS) The 16-bit register for displaying the system status. PC : Program counter (PC) The 16-bit register for displaying storing location of the current instruction code. DPR : Direct page register (DPR) The 8-bit register for specifying bit 8 through 15 of the operand address in the short direct addressing mode. PCB : Program bank register (PCB) The 8-bit register for displaying the program space. DTB : Data bank register (DTB) The 8-bit register for displaying the data space. USB : User stack bank register (USB) The 8-bit register for displaying the user stack space. SSB : System stack bank register (SSB) The 8-bit register for displaying the system stack space. ADB : Additional data bank register (ADB) The 8-bit register for displaying the additional data space. 8-bit 16-bit 32-bit 21 MB90520 Series * General-purpose registers Maximum of 32 banks R7 R6 RW7 R5 R4 RW6 R3 R2 RW5 R1 R0 RW4 RL3 RL2 RW3 RL1 RW2 RW1 RL0 RW0 000180H + (RP x 10H ) 16-bit * Processor status (PS) ILM RP CCR bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 PS ILM2 ILM1 ILM0 Initial value -- : Unused X : Indeterminate 22 0 0 0 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 B4 B3 B2 B1 B0 -- I S T N Z V C 0 0 0 0 0 -- 0 1 X X X X X MB90520 Series I/O MAP Address Abbreviated register name 000000H PDR0 000001H Read/ write Resource name Initial value Port 0 data register R/W Port 0 XXXXXXXX B PDR1 Port 1 data register R/W Port 1 XXXXXXXX B 000002H PDR2 Port 2 data register R/W Port 2 XXXXXXXX B 000003H PDR3 Port 3 data register R/W Port 3 XXXXXXXX B 000004H PDR4 Port 4 data register R/W Port 4 XXXXXXXX B 000005H PDR5 Port 5 data register R/W Port 5 - - -XXXXXB 000006H PDR6 Port 6 data register R/W Port 6 XXXXXXXX B 000007H PDR7 Port 7 data register R/W Port 7 XXXXXXXX B 000008H PDR8 Port 8 data register R/W Port 8 XXXXXXXX B 000009H PDR9 Port 9 data register R/W Port 9 XXXXXXXX B 00000AH PDRA Port A data register R/W Port A XXXXXXXX B 00000BH LCDCMR Port 7/COM pin selection register R/W Port 7, ----0000B 00000CH PDRC Port C data register R/W Port C XXXXXXXX B 16-bit I/O timer XXXXXXXX B OCP4 OCU compare register ch.4 R/W (output compare 1 (OCU) section) XXXXXXXX B Register name 00000CH 00000DH 00000EH LCD controller/driver (Disabled) 00000FH EIFR Wake-up interrupt flag register R/W Wake-up interrupt -------0B 000010H DDR0 Port 0 direction register R/W Port 0 00000000B 000011H DDR1 Port 1 direction register R/W Port 1 00000000B 000012H DDR2 Port 2 direction register R/W Port 2 00000000B 000013H DDR3 Port 3 direction register R/W Port 3 00000000B 000014H DDR4 Port 4 direction register R/W Port 4 00000000B 000015H DDR5 Port 5 direction register R/W Port 5 ---00000B 000016H DDR6 Port 6 direction register R/W Port 6 00000000B 000017H DDR7 Port 7 direction register R/W Port 7 00000000B 000018H DDR8 Port 8 direction register R/W Port 8 00000000B 000019H DDR9 Port 9 direction register R/W Port 9 00000000B 00001AH DDRA Port A direction register R/W Port A 00000000B 00001BH ADER Analog input enable register R/W Port 6, A/Dconverter 11111111B OCP5 OCU compare register ch.5 R/W 00001CH 00001DH 00001EH 00001FH 16-bit I/O timer XXXXXXXX B (output compare 1 (OCU) section) XXXXXXXX B Wake-up interrupt 00000000B (Disabled) EICR Wake-up interrupt enable register W (Continued) 23 MB90520 Series Address Abbreviated register name 000020H SMR Serial mode register R/W 000021H SCR Serial control register R/W 000022H SIDR/ SODR Serial input data register/ serial output data register R/W 000023H SSR Serial status register R/W 00001-00B 000024H SMCSL0 Serial mode control lower status register 0 R/W ----0000B 000025H SMCSH0 Serial mode control upper status register 0 R/W 000026H SDR0 Serial data register 0 R/W 000027H CDCR Communications prescaler control register R/W 000028H SMCSL1 Serial mode control lower status register 1 R/W 000029H SMCSH1 Serial mode control upper status register 1 R/W 00002AH SDR1 Serial data register 1 R/W 00002BH 00002CH 00002DH 00002EH 00002FH Read/ write Register name OCS45 OCS67 OCU control status register ch.45 R/W OCU control status register ch.67 R/W ENIR DTP/interrupt enable register R/W 000031H EIRR DTP/interrupt factor register R/W ELVR Request level setting register R/W OCP6 OCU compare register ch.6 R/W 000033H 000034H 000035H Initial value 00000000B UART (SCI) Extended I/O serial interface 0 00000100B XXXXXXXX B 00000010B XXXXXXXX B Communications prescaler control register 0---1111B ----0000B Extended I/O serial interface 1 00000010B XXXXXXXX B (Disabled) 000030H 000032H Resource name 0000--00B 16-bit I/O timer ----0000B (output compare 1 (OCU) section) 0000--00B ----0000B 00000000B DTP/external interrupt circuit XXXXXXXX B 00000000B 00000000B 16-bit I/O timer XXXXXXXX B (output compare 1 (OCU) section) XXXXXXXX B 000036H ADCS1 A/D control status register lower digits R/W 00000000B 000037H ADCS2 A/D control status register upper digits R/W 000038H ADCR1 A/D data register lower digits R 000039H ADCR2 A/D data register upper digits R/W 0 0 0 0 1 -XXB 00003AH DADR0 D/A converter data register ch.0 R/W XXXXXXXX B 00003BH DADR1 D/A converter data register ch.1 R/W 00003CH DACR0 D/A control register 0 R/W 00003DH DACR1 D/A control register 1 R/W 8/10-bit A/D converter 8/10-bit D/A converter 00000000B XXXXXXXX B XXXXXXXX B -------0B -------0B (Continued) 24 MB90520 Series Address Abbreviated register name 00003EH CLKR Register name Clock output enable register 00003FH Read/ write Resource name Initial value R/W Clock monitor function ----0000B (Disabled) 000040H PRLL0 PPG0 re-load register L R/W XXXXXXXX B 000041H PRLH0 PPG0 re-load register H R/W XXXXXXXX B 000042H PRLL1 PPG1 re-load register L R/W XXXXXXXX B 000043H PRLH1 PPG1 re-load register H R/W XXXXXXXX B 8/16-bit PPG timer 0, 1 000044H PPGC0 PPG0 operating mode control register R/W 000045H PPGC1 PPG1 operating mode control register R/W 0X000001B 000046H PPGOE0/ PPGOE1 PPG0 and 1 output control registers R/W 00000000B 000047H 000048H 000049H 00004AH 00004BH 00004CH 00004DH 00004EH 00004FH 000050H 000051H 000052H 000053H 000054H (Disabled) TMCSR0 Timer control status register ch.0 000057H 000058H 000059H 16-bit re-load timer 0 16-bit timer register ch.0/ 16-bit re-load register ch.0 R/W TMCSR1 Timer control status register ch.1 R/W TMR1/ TMRLR1 IPCP0 00000000B R/W TMR0/ TMRLR0 ICU data register ch.1 ICS01 ICU control status register XXXXXXXX B XXXXXXXX B R R ----0000B XXXXXXXX B 16-bit I/O timer IPCP1 XXXXXXXX B 00000000B R/W ICU data register ch.0 ----0000B XXXXXXXX B 16-bit re-load timer 1 16-bit timer register ch.1/ 16-bit re-load register ch.1 000055H 000056H 0-000--1B (input compare 0, 1 (ICU) section) R/W XXXXXXXX B XXXXXXXX B XXXXXXXX B 00000000B (Disabled) TCDT1 Free-run timer data register 1 R/W TCCS1 Free-run timer control status register 1 R/W 16-bit I/O timer (16-bit free-run timer 1 section) 00000000B 00000000B 00000000B (Disabled) (Continued) 25 MB90520 Series Address 00005AH 00005BH 00005CH 00005DH 00005EH 00005FH 000060H 000061H 000062H 000063H 000064H 000065H 000066H 000067H 000068H Abbreviated register name Read/ write Register name OCP0 OCU compare register ch.0 R/W OCP1 OCU compare register ch.1 R/W OCP2 OCU compare register ch.2 R/W OCP3 OCU compare register ch.3 R/W OCS01 OCU control status register ch.01 R/W OCS23 OCU control status register ch.23 R/W TCDT2 Free-run timer data register 2 R/W TCCS2 Free-run timer control status register 2 R/W 000069H Initial value XXXXXXXX B XXXXXXXX B XXXXXXXX B XXXXXXXX B XXXXXXXX B 16-bit I/O timer (output compare 0 (OCU) section) XXXXXXXX B XXXXXXXX B XXXXXXXX B 0000--00B ---00000B 0000--00B ---00000B 16-bit I/O timer (16-bit free-run timer 2 section) 00000000B 00000000B 00000000B (Disabled) 00006AH LCR0 00006BH LCR1 LCDC control registers 0 and 1 R/W R/W 00006CH 00006DH Resource name OCP7 OCU compare register ch.7 00006EH R/W LCD controller/ driver 00010000B 16-bit I/O timer (output compare 1 (OCU) section) XXXXXXXX B 00000000B XXXXXXXX B (Disabled) W ROM mirroring function selection module -------1B R/W LCD controller/ driver XXXXXXXX B 00006FH ROMM ROM mirroring function selection register 000070H to 00007FH VRAM RAM for LCD indication 000080H UDCR0 Up/down count register 0 R 000081H UDCR1 Up/down count register 1 R 000082H RCR0 Re-load compare register 0 W 000083H RCR1 Re-load compare register 1 W 000084H CSR0 Counter status register 0 00000000B 8/16-bit up/down counter/timer 0, 1 R/W 00000000B 00000000B 00000000B 00000000B (Reserved area)*3 000085H 000086H CCRL0 000087H CCRH0 000088H CSR1 Counter control register 0 R/W Counter status register 1 R/W 8/16-bit up/down counter/timer 0, 1 -0000000B 00000000B 00000000B (Continued) 26 MB90520 Series Address Abbreviated register name Resource name Initial value -0000000B (Reserved area)*3 000089H 00008AH Read/ write Register name CCRL1 Counter control register 1 R/W 8/16-bit up/down counter/timer 0, 1 -0000000B 00008BH CCRH1 00008CH RDR0 Port 0 input pull-up resistor setup register R/W Port 0 00000000B 00008DH RDR1 Port 1 input pull-up resistor setup register R/W Port 1 00000000B 00008EH RDR4 Port 4 input pull-up resistor setup register R/W Port 4 00000000B R/W Address match detection function 00000000B Delayed interrupt generation module -------0B 00008FH to 00009DH (Area used by the system)*3 PACSR Program address detection control status register 00009FH DIRR Delayed interrupt factor generation/ cancellation register R/W 0000A0H LPMCR Low-power consumption mode control register R/W! 0000A1H CKSCR Clock select register R/W 00009EH 0000A2H to 0000A7H 00011000B Low-power consumption (stand-by) mode 11111100B (Disabled) 0000A8H WDTC Watchdog timer control register R/W Watchdog timer XXXXXXXX B 0000A9H TBTC Timebase timer control register R/W Timebase timer 1--00100B 0000AAH WTC Clock timer control register R/W Clock timer 1X000000B Flash interface 1--00100B 0000ABH to 0000ADH 0000AEH 0000AFH (Disabled) FMCS Flash control register R/W (Disabled) (Continued) 27 MB90520 Series (Continued) Address Abbreviated register name 0000B0H ICR00 Interrupt control register 00 R/W 00000111B 0000B1H ICR01 Interrupt control register 01 R/W 00000111B 0000B2H ICR02 Interrupt control register 02 R/W 00000111B 0000B3H ICR03 Interrupt control register 03 R/W 00000111B 0000B4H ICR04 Interrupt control register 04 R/W 00000111B 0000B5H ICR05 Interrupt control register 05 R/W 00000111B 0000B6H ICR06 Interrupt control register 06 R/W 00000111B 0000B7H ICR07 Interrupt control register 07 R/W 0000B8H ICR08 Interrupt control register 08 R/W 0000B9H ICR09 Interrupt control register 09 R/W 00000111B 0000BAH ICR10 Interrupt control register 10 R/W 00000111B 0000BBH ICR11 Interrupt control register 11 R/W 00000111B 0000BCH ICR12 Interrupt control register 12 R/W 00000111B 0000BDH ICR13 Interrupt control register 13 R/W 00000111B 0000BEH ICR14 Interrupt control register 14 R/W 00000111B 0000BFH ICR15 Interrupt control register 15 R/W 00000111B 0000C0H to 0000FFH (External area)*1 000100H to 00####H (RAM area)*2 00####H to 001FEFH (Reserved area)*3 Resource name Interrupt controller Initial value 00000111B 00000111B Program address detection register 0 R/W XXXXXXXX B Program address detection register 1 R/W XXXXXXXX B 001FF2H Program address detection register 2 R/W 001FF3H Program address detection register 3 R/W Program address detection register 4 R/W XXXXXXXX B Program address detection register 5 R/W XXXXXXXX B 001FF0H 001FF1H 001FF4H 001FF5H PADR0 PADR1 001FF6H to 001FFFH Descriptions for read/write R/W: Readable and writable R: Read only W: Write only 28 Read/ write Register name (Reserved area)*3 Program patch processing XXXXXXXX B XXXXXXXX B MB90520 Series Descriptions for initial value 0 : The initial value of this bit is "0". 1 : The initial value of this bit is "1". X : The initial value of this bit is indeterminate. - : This bit is not used. The initial value is indeterminate. *1: This area is the only external access area having an address of 0000FFH or lower. An access operation to this area is handled as that to external I/O area. *2: For details of the RAM area, see the memory map. *3: The reserved area is basically disabled because it is used in the system. *4: Area used by the system is the area set by the resistor for evaluating tool. Notes: * For bits that is initialized by an reset operation, the initial value set by the reset operation is listed as an initial value. Note that the values are different from reading results. For LPMCR/CKSCR/WDTC, there are cases where initialization is performed or not performed, depending on the types of the reset. However initial value for resets that initializes the value are listed. * The addresses following 0000FFH are reserved. No external bus access signal is generated. * Boundary ####H between the RAM area and the reserved area varies with the product model. * Channels 0 to 3 of the OCU compare register use 16-bit free-run timer 2, while channels 4 to 7 of the OCU compare register use 16-bit free-run timer 1. 16-bit free-run timer 1 is also used by input captures (ICU) 0 and 1. 29 MB90520 Series INTERRUPT FACTORS, INTERRUPT VECTORS, INTERRUPT CONTROL REGISTER Interrupt vector Interrupt control register EI2OS support Number Address ICR Address Reset x # 08 FFFFDCH -- -- INT9 instruction x # 09 FFFFD8H -- -- Exception x # 10 FFFFD4H -- -- # 11 FFFFD0H ICR00 0000B0H # 12 FFFFCCH # 13 FFFFC8H ICR01 0000B1H # 14 FFFFC4H # 15 FFFFC0H ICR02 0000B2H # 16 FFFFBCH Extended I/O serial interface 1 # 17 FFFFB8H DTP2/DTP3 (external interrupt 2/ external interrupt 3) ICR03 0000B3H # 18 FFFFB4H # 19 FFFFB0H DTP4/DTP5 (external interrupt 4/ external interrupt 5) ICR04 0000B4H # 20 FFFFACH 8/16-bit up/down counter/timer 0 compare match # 21 FFFFA0H 8/16-bit up/down counter/timer 0 overflow/inversion ICR05 0000B5H # 22 FFFFA4H # 23 FFFFA0H DTP6/DTP7 (external interrupt 6/ external interrupt 7) ICR06 0000B6H # 24 FFFF9CH Output compare 1 (OCU) ch.4/ch.5 match # 25 FFFF98H ICR07 0000B7H # 26 FFFF94H # 27 FFFF90H ICR08 0000B8H # 28 FFFF8CH 8/16-bit up/down counter/timer 1 compare match # 29 FFFF88H 8/16-bit up/down counter/timer 1 overflow/inversion ICR09 0000B9H # 30 FFFF84 Input capture 0 (ICU) include # 31 FFFF80H ICR10 0000BAH Input capture 1 (ICU) include # 32 FFFF7CH ICR10 0000BAH Interrupt source 8/10-bit A/D converter Timebase timer x DTP0/DTP1 (external interrupt 0/ external interrupt 1) 16-bit free-run timer 1 overflow x Extended I/O serial interface 0 Wake-up interrupt 8/16-bit PPG timer 0 counter borrow 8/16-bit PPG timer 1 counter borrow Clock prescaler x x x x Output compare 1 (OCU) ch.6/ch.7 match 16-bit free-run timer 2 overflow x Priority High H Low (Continued) 30 MB90520 Series (Continued) Interrupt source EI2OS support Interrupt vector Number Address Output compare 0 (OCU) ch.0 match # 33 FFFF78H Output compare 0 (OCU) ch.1 match # 34 FFFF74H Output compare 0 (OCU) ch.2 match # 35 FFFF70H # 36 FFFF6CH UART (SCI) reception complete # 37 FFFF68H 16-bit re-load timer 0 # 38 FFFF64H UART (SCI) transmission complete # 39 FFFF60H 16-bit re-load timer 1 # 40 FFFF5CH Output compare 0 (OCU) ch.3 match x Reserved x # 41 FFFF58H Delayed interrupt generation module x # 42 FFFF54H Interrupt control register ICR Address Priority High ICR11 0000BBH ICR12 0000BCH ICR13 0000BDH ICR14 0000BEH ICR15 0000BFH Low : Can be used x : Can not be used : Can be used. With EI2OS stop function. 31 MB90520 Series PERIPHERALS 1. I/O Port (1) Input/Output Port Port 0 through 8, A are general-purpose I/O ports having a combined function as a resource input. The input output ports function as general-purpose I/O port only in the single-chip mode. * Operation as output port The pin is configured as an output port by setting the corresponding bit of the DDR register to "1". Writing data to PDR register when the port is configured as output, the data is retained in the output latch in the PDR and directly output to the pin. The value of the pin (the same value retained in the output latch of PDR) can be read out by reading the PDR register. Note: When a read-modify-write type instruction (e.g. bit set instruction) is performed to the port data register, the destination bit of the operation is set to the specified value, not affecting the bits configured by the DDR register for output, however, values of bits configured by the DDR register as inputs are changed because input values to the pins are written into the output latch. To avoid this situation, configure the pins by the DDR register as output after writing output data to the PDR register when configuring the bit used as input as outputs. * Operation as input port The pin is configured as an input by setting the corresponding bit of the DDR register to "0". When the pin is configured as an input, the output buffer is turned-off and the pin is put into a high-impedance status. When a data is written into the PDR register, the data is retained in the output latch of the PDR, but pin outputs are unaffected. Reading the PDR register reads out the pin level ("0" or "1"). 32 MB90520 Series (2) Register Configuration * Port 0 data register (PDR0) Address bit 15 . . . . . . . . . . . . bit 8 bit 7 (PDR1) 000000H bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Initial value XXXXXXXX B P07 P06 P05 P04 P03 P02 P01 P00 R/W R/W R/W R/W R/W R/W R/W R/W * Port 1 data register (PDR1) Address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 . . . . . . . . . . . . bit 0 P17 P16 P15 P14 P13 P12 P11 P10 R/W R/W R/W R/W R/W R/W R/W R/W 000001H Initial value XXXXXXXX B (PDR0) * Port 2 data register (PDR2) Address bit 15 . . . . . . . . . . . . bit 8 bit 7 (PDR3) 000002H bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Initial value XXXXXXXX B P27 P26 P25 P24 P23 P22 P21 P20 R/W R/W R/W R/W R/W R/W R/W R/W * Port 3 data register (PDR3) Address bit 15 000003H bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 . . . . . . . . . . . . bit 0 P37 P36 P35 P34 P33 P32 P31 P30 R/W R/W R/W R/W R/W R/W R/W R/W Initial value XXXXXXXX B (PDR2) * Port 4 data register (PDR4) Address bit 15 . . . . . . . . . . . . bit 8 bit 7 000004H (PDR5) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Initial value XXXXXXXX B P47 P46 P45 P44 P43 P42 P41 P40 R/W R/W R/W R/W R/W R/W R/W R/W * Port 5 data register (PDR5) Address bit 15 000005H bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 . . . . . . . . . . . . bit 0 -- -- -- P54 P53 P52 P51 P50 -- -- -- R/W R/W R/W R/W R/W Initial value - - - XXXXX B (PDR4) * Port 6 data register (PDR6) Address bit 15 . . . . . . . . . . . . bit 8 bit 7 (PDR7) 000006H bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Initial value XXXXXXXX B P67 P66 P65 P64 P63 P62 P61 P60 R/W R/W R/W R/W R/W R/W R/W R/W * Port 7 data register (PDR7) Address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 . . . . . . . . . . . . bit 0 P77 P76 P75 P74 P73 P72 P71 P70 R/W R/W R/W R/W R/W R/W R/W R/W 000007H Initial value XXXXXXXX B (PDR6) * Port 8 data register (PDR8) Address bit 15 . . . . . . . . . . . . bit 8 bit 7 (PDR9) 000008H bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Initial value XXXXXXXX B P87 P86 P85 P84 P83 P82 P81 P80 R/W R/W R/W R/W R/W R/W R/W R/W * Port 9 data register (PDR9) Address 000009H bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 . . . . . . . . . . . . bit 0 P97 P96 P95 P94 P93 P92 P91 P90 R/W R/W R/W R/W R/W R/W R/W R/W (PDR8) Initial value XXXXXXXX B (Continued) 33 MB90520 Series * Port A data register (PDRA) Address bit 15 . . . . . . . . . . . . bit 8 bit 7 00000AH (LCDCMR) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Initial value XXXXXXXX B PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 R/W R/W R/W R/W R/W R/W R/W R/W bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Initial value D07 D06 D05 D04 D03 D02 D01 D00 00000000 B R/W R/W R/W R/W R/W R/W R/W R/W * Port 0 direction register (DDR0) Address bit 15 . . . . . . . . . . . . bit 8 bit 7 (DDR1) 000010H * Port 1 direction register (DDR1) Address 000011H bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 . . . . . . . . . . . . bit 0 D17 D16 D15 D14 D13 D12 D11 D10 R/W R/W R/W R/W R/W R/W R/W R/W Initial value 00000000 B (DDR0) * Port 2 direction register (DDR2) Address bit 15 . . . . . . . . . . . . bit 8 bit 7 (DDR3) 000012H bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Initial value 00000000 B D27 D26 D25 D24 D23 D22 D21 D20 R/W R/W R/W R/W R/W R/W R/W R/W * Port 3 direction register (DDR3) Address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 . . . . . . . . . . . . bit 0 000013H D37 D36 D35 D34 D33 D32 D31 D30 R/W R/W R/W R/W R/W Initial value 00000000 B (DDR2) * Port 4 direction register (DDR4) Address bit 15 . . . . . . . . . . . . bit 8 bit 7 (DDR5) 000014H bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Initial value 00000000 B D47 D46 D45 D44 D43 D42 D41 D40 R/W R/W R/W R/W R/W R/W R/W R/W * Port 5 direction register (DDR5) Address 000015H bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 . . . . . . . . . . . . bit 0 -- -- -- D54 D53 D52 D51 D50 R/W R/W R/W R/W R/W R/W R/W R/W Initial value - - - 00000 B (DDR4) * Port 6 direction register (DDR6) Address bit 15 . . . . . . . . . . . . bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Initial value 000016H D67 D66 D65 D64 D63 D62 D61 D60 00000000 B R/W R/W R/W R/W R/W R/W R/W R/W (DDR7) * Port 7 direction register (DDR7) Address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 . . . . . . . . . . . . bit 0 000017H D77 D76 D75 D74 D73 D72 D71 D70 R/W R/W R/W R/W R/W R/W R/W R/W Initial value 00000000 B (DDR6) * Port 8 direction register (DDR8) Address bit 15 . . . . . . . . . . . . bit 8 bit 7 000018H (DDR9) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Initial value 00000000 B D87 D86 D85 D84 D83 D82 D81 D80 R/W R/W R/W R/W R/W R/W R/W R/W (Continued) 34 MB90520 Series (Continued) * Port 9 direction register (DDR9) Address bit 15 000019H bit 14 bit 13 bit 12 bit 11 bit 10 bit 8 bit 7 . . . . . . . . . . . . bit 0 bit 9 D97 D96 D95 D94 D93 D92 D91 D90 R/W R/W R/W R/W R/W R/W R/W R/W Initial value 00000000 B (DDR8) * Port A direction register (DDRA) Address bit 15 . . . . . . . . . . . . bit 8 bit 7 (ADER) 00001AH bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Initial value DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 00000000 B R/W R/W R/W R/W R/W R/W R/W R/W * Port 0 input pull-up resistor setup register (RDR0) Address bit 15 . . . . . . . . . . . . bit 8 bit 7 (RDR1) 00008CH bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Initial value RD07 RD06 RD05 RD04 RD03 RD02 RD01 RD00 00000000 B R/W R/W R/W R/W R/W R/W R/W R/W * Port 1 input pull-up resistor setup register (RDR1) Address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 . . . . . . . . . . . . bit 0 00008DH RD17 RD16 RD15 RD14 RD13 RD12 RD11 RD10 R/W R/W R/W R/W R/W R/W R/W R/W Initial value 00000000 B (RDR0) * Port 4 input pull-up resistor setup register (RDR4) Address bit 15 . . . . . . . . . . . . bit 8 bit 7 (Disabled) 00008EH bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Initial value RD47 RD46 RD45 RD44 RD43 RD42 RD41 RD40 00000000 B R/W R/W R/W R/W R/W R/W R/W R/W * Analog input enable register (ADER) bit 8 bit 7 . . . . . . . . . . . . bit 0 Address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 00001BH ADE7 ADE6 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0 R/W R/W R/W R/W R/W R/W R/W R/W bit 11 bit 10 bit 9 bit 8 bit 7 . . . . . . . . . . . . bit 0 (DDRA) Initial value 11111111 B * Port 7/COM pin selection register (LCDCMR) Address bit 15 00000BH -- -- -- -- -- -- -- -- bit 14 bit 13 bit 12 COM3 COM2 COM1 COM0 R/W R/W R/W (PDRA) Initial value - - - - 0000 B R/W R/W : Readable and writable -- : Unused X : Indeterminate 35 MB90520 Series (3) Block Diagram * Input/output port PDR (port data register) Internal data bus PDR read Output latch P-ch PDR write Pin DDR (port direction register) N-ch Direction latch DDR write Standby control (SPL=1) DDR read Standby control: Stop, timebase timer mode and SPL=1, or hardware standby mode * Input pull-up resistor setup register (RDR) To resource input PDR (port data register) Pull-up resistor About 5.0 k (5.0 V) PDR read Output latch P-ch P-ch PDR write Pin Internal data bus DDR (port direction register) DDR write Standby control (SPL=1) DDR read RDR (input pull-up resistor setup register) RDR latch RDR write RDR read Standby control: Stop, timebase timer mode and SPL=1 36 N-ch Direction latch MB90520 Series * Analog input enable register (ADER) ADER (analog input enable register) ADER read ADER latch To analog input ADER write Internal data bus PDR (port data register) RMW (read-modify-write type instruction) PDR read Output latch P-ch PDR write Pin DDR (port direction register) Direction latch N-ch DDR write DDR read Standby control (SPL=1) Standby control: Stop, timebase timer mode and SPL=1 37 MB90520 Series 2. Timebase Timer The timebase timer is a 18-bit free-run counter (timebase counter) for counting up in synchronization to the internal count clock (divided-by-2 of oscillation) with an interval timer function for selecting an interval time from four types of 212/HCLK, 214/HCLK, 216/HCLK, and 219/HCLK. The timebase timer also has a function for supplying operating clocks for the timer output for the oscillation stabilization time or the watchdog timer etc. (1) Register Configuration * Timebase timer control register (TBTC) Address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 0000A9H RESV -- -- TBIE TBOF TBR TBC1 TBC0 -- -- -- R/W R/W R/W R/W R/W bit 7 . . . . . . . . . . . .bit 0 Initial value (WDTC) 1 - - 00000 B R/W: Readable and writable -- : Unused RESV: Reserved bit (2) Block Diagram To watchdog timer To 8/16-bit PPG timer Timebase timer counter Divided-by-2 of HCLK x 21 x 22 x 23 ... ... x 28 x 29 x 210 x 211 x 212 x 213 x 214 x 215 x 216 x 217 x 218 OF OF OF OF To oscillation stabilization time selector of clock control block Power-on reset Start stop mode CKSCR : MCS = 10*1 Counter clear circuit Interval timer selector Set TBOF Clear TBOF Timebase timer control register (TBTC) RESV -- -- TBIE TBOF TBR Timebase timer interrupt signal #12*2 OF: Overflow HCLK: Oscillation clock *1: Switch machine clock from oscillation clock to PLL clock *2: Interrupt number 38 TBC1 TBC0 MB90520 Series 3. Watchdog Timer The watchdog timer is a 2-bit counter operating with an output of the timebase timer and resets the CPU when the counter is not cleared for a preset period of time. (1) Register Configuration * Watchdog timer control register (WDTC) Address bit 15 . . . . . . . . . . . . bit 8 bit 7 0000A8H (TBTC) bit 6 bit 5 bit 4 PONR STBR WRST ERST R R R bit 3 bit 2 bit 1 bit 0 SRST WTE WT1 WT0 R W W W R Initial value XXXXXXXX B R : Read only W : Write only X : Indeterminate (2) Block Diagram Watchdog timer control register (WDTC) PONR STBR WRST ERST SRST WTE WT1 WT0 2 Watchdog timer CLR and start Overflow Start sleep mode Start hold status Start stop mode Counter clear control circuit Count clock selector 2-bit counter CLR Watchdog timer reset generation circuit To internal reset generation circuit CLR 4 Clear (Timebase timer counter) Divided-by-2 of HCLK x 21 x 2 2 ... x 28 x 29 x 210 x 211 x 212 x 213 x 214 x 215 x 216 x 217 x 218 HCLK: Oscillation clock 39 MB90520 Series 4. 8/16-bit PPG Timer 0, 1 The 8/16-bit PPG timer is a 2-CH re-load timer module for outputting pulse having given frequencies/duty ratios. The two modules performs the following operation by combining functions. * 8-bit PPG output 2-CH independent operation mode This is a mode for operating independent 2-CH 8-bit PPG timer, in which PPG0 and PPG1 pins correspond to outputs from PPG0 and PPG1 respectively. * 16-bit PPG timer output operation mode In this mode, PPG0 and PPG1 are combined to be operated as a 1-CH 8/16-bit PPG timer 0 and 1 operating as a 16-bit timer. Because PPG0 and PPG1 outputs are reversed by an underflow from PPG1 outputting the same output pulses from PPG0 and PPG1 pins. * 8 + 8-bit PPG timer output operation mode In this mode, PPG0 is operated as an 8-bit communications pre-scaler, in which an underflow output of PPG0 is used as a clock source for PPG1. A toggle output of PPG0 and PPG output of PPG1 are output from PPG0 and PPG1 respectively. * PPG output operation A pulse wave with any period/duty ratio is output. The module can also be used as a D/A converter with an external add-on circuit. 40 MB90520 Series (1) Register Configuration * PPG0 operating mode control register (PPGC0) Address bit 15 . . . . . . . . . . . . bit 8 bit 7 (PPGC1) 000044H bit 6 bit 5 bit 4 bit 3 PEN0 -- PE00 PIE0 PUF0 R/W -- R/W R/W R/W bit 2 bit 1 bit 0 Initial value -- -- RESV 0 - 000 - - 1 B -- -- -- * PPG1 operating mode control register (PPGC1) Address bit 15 000045H bit 8 bit 7 . . . . . . . . . . . . bit 0 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 PEN1 -- PE10 PIE1 PUF1 MD1 MD0 RESV R/W -- R/W R/W R/W R/W R/W R/W Initial value 0X0 0 0 0 0 1 B (PPGC0) * PPG0 output control register (PPGOE0) Address bit 15 . . . . . . . . . . . . bit 8 bit 7 (Disabled) 000046H bit 6 PCS2 PCS1 R/W R/W bit 5 bit 4 PCS0 PCM2 PCM1 PCM0 R/W bit 3 bit 2 bit 1 bit 0 Initial value PE11 PE01 00000000 B R/W R/W R/W R/W R/W bit 3 bit 2 bit 1 bit 0 Initial value PE11 PE01 00000000 B R/W R/W * PPG1 output control register (PPGOE1) Address bit 15 . . . . . . . . . . . . bit 8 bit 7 (Disabled) 000046H bit 6 bit 5 bit 4 PCS2 PCS1 PCS0 PCM2 PCM1 PCM0 R/W R/W R/W R/W R/W R/W * PPG0 re-load register H (PRLH0) Address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 . . . . . . . . . . . . bit 0 R/W R/W R/W R/W R/W R/W R/W bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 . . . . . . . . . . . . bit 0 (PRLL0) 000041H R/W Initial value XXXXXXXX B * PPG1 re-load register H (PRLH1) Address bit 15 bit 14 bit 13 (PRLL1) 000043H R/W R/W R/W R/W R/W R/W R/W Initial value XXXXXXXX B R/W * PPG0 re-load register L (PRLL0) Address bit 15 . . . . . . . . . . . . bit 8 bit 7 000040H bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W R/W R/W R/W R/W R/W R/W R/W Address bit 15 . . . . . . . . . . . . bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W R/W R/W R/W R/W R/W R/W * PPG1 re-load register L (PRLL1) 000042H Initial value XXXXXXXX B (PRLH0) (PRLH1) Initial value XXXXXXXX B R/W R/W : Readable and writable -- : Unused X : Indeterminate RESV: Reserved bit 41 MB90520 Series (2) Block Diagram * Block diagram of 8/16-bit PPG timer 0 Data bus for "H" digits Data bus for "L" digits PPG0 re-load register PRLH0 PPG0 operating mode control register (PPGC0) PEN0 PRLL0 -- PE00 PIE0 PUF0 -- -- RESV R Temporary buffer (PRLBH0) S 2 Re-load selector L/H selector Select signal Mode control signal PPG1 underflow PPG0 underflow (to PPG1) Count value Re-load Interrupt request #19* Q Clear Pulse selector Down counter (PCNT0) Underflow CLK Reverse PPG0 output latch Pin P36/PG00 Timebase timer output (512/HCLK) Peripheral clock (16/) Peripheral clock (8/) Peripheral clock (4/) Peripheral clock (2/) Peripheral clock (1/) PPG output control circuit Count clock selector Pin P37/PG01 3 Select signal PCS2 PCS1 PCS0 PCM2 PCM1 PCM0 PE11 PE01 PPG0, 1 output control register (PPGOE) * : Interrupt number HCLK : Oscillation clock : Machine clock frequency 42 MB90520 Series * Block diagram of 8/16-bit PPG timer 1 Data bus for "H" digits Data bus for "L" digits PPG1 operating mode control register (PPGC1) PPG1 re-load register PRLL0 PRLH0 PEN1 -- Operating mode control signal PEI0 PIE1 PUF1 MD1 MD0 RESV 2 R Temporary buffer (PRLBH1) S Re-load selector (L/H selector) Interrupt request #23* Q Select signal Count value Re-load Down counter (PCNT1) Clear Underflow Reverse PPG1 output latch Pin P40/PG10 PPG1 underflow (to PPG0) PPG output control circuit MD0 CLK Pin PPG0 underflow P41/PG11 Timebase timer output (512/HCLK) Peripheral clock (16/) Peripheral clock (8/) Peripheral clock (4/) Peripheral clock (2/) Peripheral clock (1/) Count clock selector 3 Select signal PCS2 PCS1 PCS0 PCM2 PCM1 PCM0 PE11 PE01 PPG0, 1 Output control register (PPGOE) * : Interrupt number HCLK : Oscillation clock : Machine clock frequency 43 MB90520 Series 5. 16-bit Re-load Timer 0, 1 (With an Event Count Function) The 16-bit re-load timer has an internal clock mode for counting down in synchronization to three types of internal clocks and an event count mode for counting down detecting a given edge of the pulse input to the external bus pin, and either of the two functions can be selectively used. For this timer, an "underflow" is defined as the timing of transition from the counter value of "0000H" to "FFFFH". According to this definition, an underflow occurs after [re-load register setting value + 1] counts. In operaring the counter, the re-load mode for repeating counting operation after re-loading a counter value after an underflow or the one-shot mode for stopping the counting operation after an underflow can be selectively used. Because the timer can generate an interrupt upon an underflow, the timer conforms to the extended intelligent I/O service (EI2OS). The MB90520 series has 2 channels of 16-bit re-load timers. (1) Register Configuration * Timer control status register upper digits ch.0, ch.1 (TMCSR0, TMCSR1 : H) Address TMCSR0 : 000049H TMCSR1 : 00004DH bit 8 bit 7 . . . . . . . . . . . . bit 0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 -- -- -- -- CSL1 CSL0 MOD2 MOD1 -- -- -- -- R/W R/W bit 9 R/W Initial value - - - - 0000 B (TMCSR : L) R/W * Timer control status register lower digits ch.0, ch.1 (TMCSR0, TMCSR1 : L) bit 6 bit 5 Address bit 15 . . . . . . . . . . . . bit 8 bit 7 TMCSR0 : 000048H (TMCSR : H) MOD0 OUTE OUTL TMCSR1 : 00004CH R/W R/W R/W bit 4 bit 3 bit 2 bit 1 bit 0 Initial value RELD INTE UF CNTE TRG 00000000 B R/W R/W R/W R/W R/W * 16-bit timer register upper and lower digits ch.0, ch.1 (TMR0, TMR1) Address TMR0 : 00004AH 00004BH TMR1 : 00004EH 00004FH bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R R R R R R R R R R R R R R R R Initial value XXXXXXXX B XXXXXXXX B XXXXXXXX B XXXXXXXX B * 16-bit re-load register upper and lower digits ch.0, ch.1 (TMRL0, TMRL1) Address TMRL0 : 00004AH 00004BH TMRL1 : 00004EH 00004FH bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 W W W R/W : Readable and writable R : Read only W : Write only -- : Unused X : Indeterminate 44 W W W W W W W W W W W W W Initial value XXXXXXXX B XXXXXXXX B XXXXXXXX B XXXXXXXX B MB90520 Series (2) Block Diagram Internal data bus TMRLR0*1 <TMRLR1> 16-bit re-load register Re-load control circuit Re-load register TMR0*1 <TMR1> 16-bit timer register (down counter) UF CLK Count clock generation circuit Prescaler 3 Gate input Valid clock decision circuit Clear To UART*1 <To 8/10-bit A/D converter> CLK Internal clock Output control circuit Input control circuit Pin Wait signal Clock selecter External clock P70/TI0/OUT4*1 3 <P72/TI1/OUT6> 2 Output generation circuit Reverse -- -- EN P71/TO0/OUT5*1 <P73/TO1/OUT7> Select signal Function select -- Pin Operation control circuit -- CSL1 CSL0 MOD2MOD1MOD0 OUTE OUTL RELD INTE UF CNTE TRG Timer control status register (TMCSR0)*1 <TMCSR1> *1: The timer has ch.0 and ch.1, and listed in the parenthesis < > are for ch.1 *2: Interrupt number : Machine clock frequency Clear EI2CS Interrupt request signal #40*1, *2 <#38> 45 MB90520 Series 6. 16-bit I/O Timer The 16-bit I/O timer module consists of two 16-bit free-run timer, two input capture circuits (ICU), and eight output comparators (OCU). This module allows two independent waveforms to be output on the basis of the 16-bit free-run timer. Input pulse width and external clock periods can, therefore, be measured. * Block diagram Internal data bus Input capture 0, 1 (ICU) 46 16-bit Dedicated Dedicated Output compare 0, 1 free-run timer 1, 2 (OCU) bus bus MB90520 Series (1) 16-bit Free-run Timer 1, 2 The 16-bit free-run timer consists of a 16-bit up counter, a control register, and a communications prescaler register. The value output from the timer counter is used as basic timer (base timer) for input capture (ICU) and output compare (OCU). * A counter operation clock can be selected from four internal clocks (/4, /16, /32 and /64). * An interrupt can be generated by overflow of counter value or compare match with OCU compare register 0 and 4. (Compare match requires mode setup.) * The counter value can be initialized to "0000H" by a reset, software clear or compare match with OCU compare register 0 and 4. * Register configuration * Free-run timer data register 1, 2 (TCDT1, TCDT2) Address TCDT1 : 000056H 000057H TCDT2 : 000066H 000067H bit 15bit 14bit 13bit 12bit 11bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 T15 T14 T13 T12 T11 T10 T9 T8 T7 T6 T5 T4 T3 T2 T1 T0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial value 00000000 B 00000000 B 00000000 B 00000000 B * Free-run timer control status register 1, 2 (TCCS1, TCCS2) bit 15. . . . . . . . . . . . .bit 8 bit 7 Address TCCS1 : 000058H TCCS2 : 000068H (Disabled) bit 6 bit 5 bit 4 RESV IVF IVFE STOP MODE R/W R/W R/W R/W bit 3 R/W bit 2 bit 1 bit 0 Initial value CLR CLK1 CLK0 R/W R/W R/W 00000000 B 00000000 B R/W: Readable and writable RESV: Reserved bit * Block diagram Count value output to ICO and OCU Free-run timer data register (TCDT1)*1 <TCDT2> OF 16-bit counter STOP CLR Communications pre-scaler register OCU compare register 0 match signal 2 Internal data bus CLK Free-run timer control status register (TCCS1) *1 <TCCS2> RESV IVF IVFE STOP MODE CLR CLK1 CLK0 16-bit free-run timer interrupt request #14*1, *2 <#28> *1: The timer has ch.1 and ch.2, and listed in the parenthesis < > are for ch.2. *2: Interrupt number : Machine clock frequency OF : Overflow 47 MB90520 Series (2) Input Capture 0, 1 (ICU) The input capture (ICU) generates an interrupt request to the CPU simultaneously with a storing operation of current counter value of the 16-bit free-run timer to the ICU data register (IPCP) upon an input of a trigger edge to the external pin. There are two sets (two channels) of the input capture external pins and ICU data registers, enabling measurements of maximum of four events. * The input capture has two sets of external input pins (IN0, IN1) and ICU registers (IPCP), enabling measurements of maximum of four events. * A trigger edge direction can be selected from rising/falling/both edges. * The input capture can be set to generate an interrupt request at the storage timing of the counter value of the 16-bit free-run timer to the ICU data register (IPCP). * The input compare conforms to the extended intelligent I/O service (EI2OS). * The input capture ( ICU) function is suited for measurements of intervals (frequencies) and pulse-widths. * Register configuration * ICU data register ch.0 ch.1 (IPCP0, IPCP1) Address IPCP0 : 000051H IPCP1 : 000053H Address IPCP0 : 000050H IPCP1 : 000052H bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 . . . . . . . . . . . . . bit 0 Initial value CP15 CP14 CP13 CP12 CP11 CP10 CP09 CP08 XXXXXXXXB R R R R R R R R bit 15. . . . . . . . . . . . bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (IPCP0, IPCP1) CP07 CP06 CP05 CP04 CP03 CP02 CP01 CP00 R R R R R R R R (IPCP0, IPCP1) Initial value XXXXXXXXB Note: This register holds a 16-bit free-run timer value when the valid edge of the corresponding external pin input waveform is detected. (You can word-access this register, but you cannot program it.) * ICU cnotrol status register (ICS01) Address bit 15. . . . . . . . . . . . bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 000054H (Disabled) ICP1 ICP0 ICE1 ICE0 EG11 EG10 EG01 EG00 R/W R/W R/W R/W R/W R/W R/W R/W : Readable and writable R : Read only X : Unused 48 bit 0 R/W Initial value 00000000B MB90520 Series * Block diagram Internal data bus Latch signal P20/IC00 Pin Output latch ICU data register (IPCP) Edge detection circuit P21/IC01 Pin P22/IC10 Data latch signal IPCP0H Pin 16 2 Pin P23/IC11 IPCP0L IPCP1H IPCP1L 16 16-bit free-run timer 1, 2 2 ICU control status register (ICS01) ICP1 ICP0 ICE1 ICE0 EG11 EG10 EG01 EG00 Interrupt request #31* Interrupt request #32* * : Interrupt number 49 MB90520 Series (3) Output Compare 0, 1 (OCU) The output compare (OCU) is two sets of compare units consisting of a eight-channel OCU compare registers, a comparator and a control register. An interrupt request can be generated for each channel upon a match detection by performing time-division comparison between the OCU compare data register setting value and the counter value of the 16-bit free-run timer. The OUT pin can be used as a waveform output pin for reversing output upon a match detection or a generalpurpose output port for directly outputting the setting value of the CMOD bit. * Register Configuration * OCU control status register ch.1, ch.23, ch.45, ch.67 (OCS01, OCS23, OCS45, OCS67) Address ch.01 : OCS01 : 0000063H ch.23 : OCS23 : 0000065H ch.45 : OCS45 : 000002DH ch.67 : OCS67 : 000002FH Address ch.01 : OCS01 : 000062H ch.23 : OCS23 : 000064H ch.45 : OCS45 : 00002CH ch.67 : OCS67 : 00002EH bit 15 bit 14 bit 13 -- -- -- -- -- -- bit 12 bit 11 CMOD OTE1 R/W R/W bit 10 bit 9 OTE0 OTD1 R/W R/W bit 8 bit 7 . . . . . . . . . . . . . bit 0 OTD0 (OCS) Initial value - - - 00000 B R/W bit 15. . . . . . . . . . . . bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (OCS) ICP1 ICP0 ICE1 ICE0 -- -- CST1 CST0 R/W R/W R/W R/W -- -- R/W R/W Initial value 0000 - - 00 B * OCU control status register ch.0 to ch.7 (OCS0 to OCS7) Address ch.0 : OCP0 : 00005BH ch.1 : OCP1 : 00005DH ch.2 : OCP2 : 00005FH ch.3 : OCP3 : 000061H ch.4 : OCP0 : 00000DH ch.5 : OCP1 : 00001DH ch.6 : OCP2 : 000035H ch.7 : OCP3 : 00006DH Address ch.0 : OCP0 : 00005AH ch.1 : OCP1 : 00005CH ch.2 : OCP2 : 00005EH ch.3 : OCP3 : 000060H ch.4 : OCP0 : 00000CH ch.5 : OCP1 : 00001CH ch.6 : OCP2 : 000034H ch.7 : OCP3 : 00006CH bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 C15 C14 C13 C12 C11 C10 C09 C08 R/W R/W R/W R/W R/W R/W R/W R/W bit 7 (OCP) R/W : Readable and writable -- : Unused X : Indeterminate 50 bit 6 bit 5 bit 4 bit 3 Initial value XXXXXXXX B (OCP) bit 2 bit 1 bit 0 Initial value XXXXXXXX B C07 C06 C05 C04 C03 C02 C01 C00 R/W R/W R/W R/W R/W R/W R/W R/W MB90520 Series * Block diagram * Output compare 0 (OCU) #36* #35* Output compare interrupt request OCU control status register 23 (OCS23) -- -- CMOD OTE1 OTE0 OTD1 OTD0 ICP1 ICP0 ICE1 ICE0 -- -- CST1 CST0 -- 2 2 16-bit free-run timer 1 Compare control circuit 3 OCCP3 OCU compare register 3 Internal data bus Compare control circuit 2 P35/OUT3 Output control circuit 3 OCCP2 Pin OCU compare register 2 P34/OUT2 Output control circuit 2 Pin Compare control circuit 1 P33/OUT1 Output control circuit 1 OCCP1 OCU compare register 1 Pin P32/OUT0 Output control circuit 0 Compare control circuit 0 Pin OCCP0 OCU compare register 0 2 2 -- -- -- CMOD OTE1 OTE0 OTD1 OTD0 ICP1 ICP0 ICE1 ICE0 OCU control status register 01 (OCS01) -- -- CST1 CST0 #34* #33* Output compare interrupt request * : Interrupt number 51 MB90520 Series * Output compare 1 Output compare interrupt request #27* OCU control status register 67 (OCS67) -- -- -- CMOD OTE1 OTE0 OTD1 OTD0 ICP1 ICP0 ICE1 ICE0 -- -- CST1 CST0 2 2 16-bit free-run timer 2 Compare control circuit 7 OCCP3 Internal data bus OCU compare register 7 P73/TO1/OUT7 Compare control circuit 6 Output control circuit 7 OCCP2 OCU compare register 6 Pin P72/TI1/OUT6 Output control circuit 6 Pin Compare control circuit 5 P71/TO0/OUT5 OCCP1 Output control circuit 5 Pin OCU compare register 5 P70/TI0/OUT4 Output control circuit 4 Compare control circuit 4 Pin OCCP0 OCU compare register 4 2 2 -- -- -- CMOD OTE1 OTE0 OTD1 OTD0 ICP1 ICP0 ICE1 ICE0 -- -- CST1 CST0 OCU control status register 45 (OCS45) #25* Output compare interrupt request * : Interrupt number 52 MB90520 Series 7. 8/16-bit Up/Down Counter/Timer 0, 1 The 8/16-bit up/down counter/timer consists of six event input pins, two 8-bit up/down counters, two 8-bit re-load compare registers, and their controllers. (1) Register Configuration * Up/down count register 0 (UDCR0) Address bit 15 . . . . . . . . . . . . bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Initial value D07 D06 D05 D04 D03 D02 D01 D00 00000000 B R R R R R R R R 000080H (UDCR1) * Up/down count register 1 (UDCR1) Address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 . . . . . . . . . . . . . bit 0 Initial value 000081H D17 D16 D15 D14 D13 D12 D11 D10 (UDCR0) 00000000 B R R R R R R R R * Re-load compare register 0 (RCR0) Address bit 15 . . . . . . . . . . . . bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Initial value D07 D06 D05 D04 D03 D02 D01 D00 00000000 B W W W W W W W W (RCR1) 000082H * Re-load compare register 1 (RCR1) Address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 . . . . . . . . . . . . . bit 0 Initial value 000083H D17 D16 D15 D14 D13 D12 D11 D10 (RCR0) 00000000 B W W W W W W W W * Counter status register 0, 1 (CSR0, CSR1) Address CSR0 : 000084H CSR1 : 000088H bit 15 . . . . . . . . . . . . bit 8 bit 7 (Reserved area) bit 6 bit 5 bit 4 bit 3 CSTR CITE UDIE CMPF OVFF bit 2 bit 1 R/W R/W R/W R/W R/W R/W R R bit 4 bit 3 bit 2 bit 1 bit 0 UDFF UDF1 bit 0 Initial value UDF0 00000000 B * Counter control register 0, 1 (CCRL0, CCRL1) Address CSRL0 : 000086H CSRL1 : 00008AH bit 15 . . . . . . . . . . . . bit 8 bit 7 (CCRH0, CCRH1) -- -- bit 6 bit 5 CTUT UCRE RLDE UDCC CGSC CGE1 CGE0 R/W R/W R/W R/W R/W R/W Initial value - 0000000 B R/W * Counter control register 0 (CCRH0) Address bit 15 000087H bit 14 bit 13 bit 12 M16E CDCF CFIE CLKS CMS1 CMS0 CES1 CES0 R/W R/W R/W R/W R/W R/W R/W bit 11 bit 10 bit 9 bit 8 R/W bit 11 bit 10 bit 9 bit 8 bit 7 . . . . . . . . . . . . . bit 0 Initial value (CCRL0) 00000000 B bit 7 . . . . . . . . . . . . . bit 0 Initial value (CCRL1) - 0000000 B * Counter control register 1 (CCRH1) Address bit 15 bit 14 bit 13 bit 12 00008BH -- CDCF CFIE CLKS CMS1 CMS0 CES1 CES0 -- R/W R/W R/W R/W R/W R/W R/W R/W : Readable and writable R : Read only W : Write only -- : Unused 53 MB90520 Series (2) Block Diagram * Block diagram of 8/16-bit up/down counter/timer 0 Internal data bus RCR0 Re-load compare register 0 Re-load control circuit UDCR0 CARRY/ BORRW Up/down count register 0 (to channel 1) Counter control register 0 (CCRL0) Pin Counter clear circuit Edge/level detection circuit Prescaler P24/AIN0 Pin Underflow P26/ZIN0/INT7 CTUT UCRE RLDE UDCC CGSC CGE1 CGE0 Overflow -- Compare control circuit Count clock Counter status register 0 (CSR0) UP/down count clock selector CSTR CITE UDIE CMPF OVFF UDFF UDF1 UDF0 Pin P25/BIN0 Interrupt request #21* Interrupt request #22* M16E CDCF CFIE CLKS CMS1 CMS0 CES1 CES0 Counter control register 0 (CCRH0) * : Interrupt number : Machine clock frequency 54 M16E (to channel 1) MB90520 Series * Block diagram of 8/16-bit up/down counter/timer 1 Internal data bus RCR1 Re-load compare register 1 Re-load control circuit UDCR1 Up/down count register 1 Counter control register 1 (CCRH1) P52/SCK2/ZIN1 Counter clear circuit Edge/level Pin detection circuit CARRY/BORRW (from channel 0) Prescaler Pin Compare control circuit Count clock Counter status (CSR1) register 1 P50/SIN2/AIN1 Underflow CTUT UCRE RLDE UDCC CGSC CGE1 CGE0 Overflow -- UP/down count clock selector CSTR CITE UDIE CMPF OVFF UDFF UDF1 UDF0 Pin P51/SOT2/BIN1 M16E (from channel 1) Interrupt request #29* Interrupt request #30* -- CDCF CFIE CLKS CMS1 CMS0 CES1 CES0 Counter control register 1 (CCRH1) * : Interrupt number : Machine clock frequency 55 MB90520 Series 8. Extended I/O Serial Interface 0, 1 The extended I/O serial interface transfers data using a clock synchronization system having an 8-bit x 1 channel configuration. For data transfer, you can select LSB first/MSB first. (1) Register Configuration * Serial mode control upper status register 0, 1 (SMCSH0, SMCSH1) Address SMCSH0 : 000025H SMCSH1 : 000029H bit 15 bit 14 bit 13 SMD2 SMD1 SMD0 R/W R/W R/W bit 12 bit 11 SIE SIR R/W R/W bit 10 bit 9 bit 8 bit 7 . . . . . . . . . . . . . bit 0 Initial value (SMCSL) 00000010 B BUSY STOP STRT R R/W R/W * Serial mode control lower status register 0, 1 (SMCSL0, SMCSL1) bit 15 . . . . . . . . . . . . bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Initial value -- -- * Serial data register 0, 1 (SDR0, SDR1) -- -- -- -- -- -- MODE BDS SOE SCOE - - - - 0000 B R/W R/W R/W R/W bit 15 . . . . . . . . . . . . bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Initial value D7 D6 D5 D4 D3 D2 D1 D0 XXXXXXXX B R/W R/W R/W R/W R/W R/W R/W R/W Address SMCSL0 : 000024H SMCSL1 : 000028H Address SDR0 : 000026H SDR1 : 00002AH (SMCSH) (CDCR, disabled) R/W : Readable and writable R : Read only -- : Unused X : Indeterminate 56 MB90520 Series (2) Block Diagram Internal data bus (MSB first) D0 to D7 D7 to D0 (LSB first) Transfer direction selection Pin Read Write Serial data register (SDR) P45/SIN1 Pin Pin P50/SIN2/AIN1 P46/SOT1 Pin P51/SOT2/BIN1 Pin P47/SCK1 Control circuit Shift clock counter Pin P52/SCK2/ZIN1 Internal clock 2 1 3 0 SMD2 SMD1 SMD0 SIE Serial mode control status register (SMCS) SIR BUSY STOP STRT -- -- -- -- MODE BDS SOE SCOE Interrupt request #15 (SMCS0)* #17 (SMCS1)* *: Interrupt number 57 MB90520 Series 9. UART (SCI) UART (SCI) is general-purpose serial data communication interface for performing synchronous or asynchronous communication (start-stop synchronization system). * Data buffer: Full-duplex double buffer * Transfer mode: Clock synchronized (with start and stop bit) Clock asynchronized (start-stop synchronization system) * Baud rate: Embedded dedicated baud rate generator External clock input possible Internal clock (a clock supplied from 16-bit re-load timer can be used.) Internal machine clock Asynchronization 9615 bps/31250 bps/4808 bps/2404 bps/1202 bps For 6 MHz, 8 MHz, 10 MHz, CLK synchronization 1 Mbps/500 kbps/250 kbps/125 kbps/62.5 kbps 12 MHz and 16 MHz * Data length: 7 bit to 9 bit selective (without a parity bit) 6 bit to 8 bit selective (with a parity bit) * Signal format: NRZ (Non Return to Zero) system * Reception error detection: Framing error Overrun error Parity error (multi-processor mode is supported, enabling setup of any baud rate by an external clock.) * Interrupt request: Receive interrupt (receive complete, receive error detection) Receive interrupt (transmit complete) Transmit/receive conforms to extended intelligent I/O service (EI2OS) } 58 MB90520 Series (1) Register Configuration * Serial control register (SCR) Address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 . . . . . . . . . . . . . bit 0 000021H PEN P SBL CL A/D REC RXE TXE (SMR) R/W R/W R/W R/W R/W W R/W R/W Initial value 00000100 B * Serial mode register (SMR) Address bit 15. . . . . . . . . . . . bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 000020H (SCR) MD1 MD0 CS2 CS1 CS0 RESV SCKE SOE R/W R/W R/W R/W R/W R/W R/W R/W Initial value 00000000 B * Serial status register (SSR) Address bit 15 bit 14 bit 13 bit 12 000023H PE ORE FRE RDRF TRDE R R R R bit 11 R bit 10 bit 9 bit 8 bit 7 . . . . . . . . . . . . . bit 0 -- RIE TIE (SIDR/SODR) -- R/W R/W Initial value 00001 - 00 B * Serial input data register (SIDR) Address bit 15. . . . . . . . . . . . bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 000022H (SSR) D7 D6 D5 D4 D3 D2 D1 D0 R R R R R R R R Initial value XXXXXXXX B * Serial output data register (SODR) Address bit 15. . . . . . . . . . . . bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 000022H (SSR) D7 D6 D5 D4 D3 D2 D1 D0 W W W W W W W W Initial value XXXXXXXX B * Communications prescaler control register (CDCR) Address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 . . . . . . . . . . . . . bit 0 000027H MD -- -- -- DIV3 DIV2 DIV1 DIV0 (SDR0) -- -- R/W R/W R/W R/W R/W -- R/W : Readable and writable R : Read only W : Write only -- : Unused X : Indeterminate RESV : Reserved bit Initial value 0 - - - 1111 B 59 MB90520 Series (2) Block Diagram Control bus Dedicated baud rate generator 16-bit re-load timer 0 Receive interrupt signal #37* Transmit interrupt signal #39* Transmit clock Clock selector External clock Receive clock Receive control circuit Transmit control circuit Pin P42/SCK0 Start bit detection circuit Transmit start circuit Receive bit counter Transmit bit counter Receive parity counter Transmit parity counter Pin P43/SOT0 Shift register for transmission Shift register for reception Pin P42/SIN0 Reception complete SIDR0 Start transmission SODR0 Receive condition decision circuit To EI2OS reception error generation signal (to CPU) Internal data bus SMR0 register MD1 MD0 CS2 CS1 CS0 SCKE SOE * : Interrupt number 60 SCR0 register PEN P SBL CL A/D REC RXE TXE SSR0 register PE ORE FRE RDRF TDRE RIE TIE MB90520 Series 10. DTP/External Interrupt Circuit DTP (Data Transfer Peripheral), which is located between the peripheral circuit outside the device and the F2MC-16LX CPU, receives an interrupt request or DMA request generated by the external peripheral circuit* for transmission to the F2MC-16LX CPU. DTP is used to activate the intelligent I/O service or interrupt processing. As request levels, two types of "H" and "L" can be selected for the intelligent I/O service. Rising and falling edges as well as "H" and "L" can be selected for an external interrupt request. * : The external peripheral circuit is connected outside the MB90520 series device. (1) Register Configuration * DTP/interrupt factor register (EIRR) Address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 . . . . . . . . . . . . bit 0 ER7 ER6 ER5 ER4 ER3 ER2 ER1 ER0 R/W R/W R/W R/W R/W R/W R/W R/W 000031H (ENIR) Initial value XXXXXXXX B * DTP/interrupt enable register (ENIR) Address bit 15 . . . . . . . . . . . . bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 000030H EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0 R/W R/W R/W R/W R/W R/W R/W R/W Address bit 15 . . . . . . . . . . . . bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 LB3 LA3 LB2 LA2 LB1 LA1 LB0 LA0 R/W R/W R/W R/W R/W R/W R/W R/W (EIRR) Initial value 00000000 B * Request level setting register (ELVR) Low order address 000032H (ELVR upper) Address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 . . . . . . . . . . . . bit 0 LB7 LA7 LB6 LA6 LB5 LA5 LB4 LA4 R/W R/W R/W R/W R/W R/W R/W R/W High order address 000033H (ELVR lower) Initial value 00000000 B Initial value 00000000 B R/W : Readable and writable X : Indeterminate 61 62 Pin P00/INT0 Pin P01/INT1 Pin P02/INT2 Pin P03/INT3 *: Interrupt number Internal data bus Pin P04/INT4 P05/INT5 Pin P06/INT6 Pin P26/ZIN0/INT7 Level edge selector 6 Level edge selector 7 2 EN7 ER7 LB7 EN6 ER6 LA7 EN5 ER5 2 LB6 EN4 ER4 LA6 2 LA5 EN3 ER3 EN2 ER2 Level edge selector 4 EN1 ER1 LB4 Level edge selector 5 LB5 Request level setting register (ELVR) 2 LB3 2 LA3 LA2 Level edge selector 2 Level edge selector 3 LB2 2 LB1 EN0 DTP/interrupt enable register (ENIR) #13* #18* #20* #24* LB0 Level edge selector 0 Level edge selector 1 LA0 DTP/external intrrupt input detection circuit 2 LA1 ER0 DTP/interrupt factor register (EIRR) LA4 2 MB90520 Series (2) Block Diagram MB90520 Series 11. Wake-up Interrupt Wake-up intrrupts transmits interrupt request ("L" level) generated by peripheral equipment located between external periphera devices and the F2MC-16LX CPU to the CPU and invokes interrupt processing. The interrupt does not conform to the exterded intelligent I/O service (EI2OS). (1) Register Configuration * Wake-up interrupt flag register (EIFR) Address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 00000FH -- -- -- -- -- -- -- WIF -- -- -- -- -- -- -- R/W bit 8 bit 7 . . . . . . . . . . . . bit 0 Initial value - - - - - - -0B (Disabled) * Wake-up interrupt enable register (EICR) Address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 . . . . . . . . . . . . bit 0 00001FH EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0 W W W W W W W W Initial value 00000000 B (Disabled) R/W : Readable and writable W : Write only -- : Unused (2) Block Diagram Internal data bus Wake-up interrupt enable register (EICR) EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0 Wake-up interrupt flag register (EIFR) -- -- -- -- -- -- -- WIF Interrupt request detection circuit P10/WI0 Pin P11/WI1 Pin P12/WI2 Pin Wake-up interrupt request #16* P13/WI3 Pin P14/WI4 Pin P15/WI5 Pin P16/WI6 Pin P17/WI7 Pin *: Interrupt number 63 MB90520 Series 12. Delayed Interrupt Generation Module The delayed interrupt generation module generates interrupts for switching tasks for development on a realtime operating system (REALOS series). The module can be used to generate softwarewise generates hardware interrupt requests to the CPU and cancel the interrupts. This module does not conform to the extended intelligent I/O service (EI2OS). (1) Register Configuration * Delayed interrupt factor generation/cancellation register (DIRR) bit 8 bit 7 . . . . . . . . . . . . bit 0 Address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 00009FH -- -- -- -- -- -- -- R0 -- -- -- -- -- -- -- R/W (PACSR) Initial value - - - - - - -0B Note: Upon a reset, an interrupt is canceled. R/W : Readable and writable -- : Unused The DIRR is the register used to control delay interrupt request generation/cancellation. Programming this register with "1" generates a delay interrupt request. Programming this register with "0" cancels a delay interrupt request. Upon a reset, an interrupt is canceled. The reserved bit area can be programmed with either "0" or "1". For future extension, however, it is recommended that bit set and clear instructions be used to access this register. (2) Block Diagram Internal data bus -- -- -- -- -- Delayed interrupt factor generation/ cancellation register (DIRR) *: Interrupt number 64 -- -- R0 S factor R latch Interrupt request signal #42* MB90520 Series 13. 8/10-bit A/D Converter The 8/10-bit A/D converter has a function of converting analog voltage input to the analog input pins (input voltage) to digital values (A/D conversion) and has the following features. * Minimum conversion time: 16.3 s (at machine clock of 16 MHz, including sampling time) * Minimum sampling period: 4 s/8 s/16 s/256 s (at machine clock of 16 MHz) * Compare time: 99/176 machine cycles per channel. (99 machine cycles are used for a machine clock below 10 MHz.) * Conversion method: RC successive approximation method with a sample and hold circuit. * 8/10-bit resolution * Analog input pins: Selectable from eight channels by software Single conversion mode: Selects and converts one channel. Scan conversion mode: Converts two or more successive channels. Up to eight channels can be programmed. Continuous conversion mode: Repeatedly converts specified channels. Stop conversion mode: Stops conversion after completing a conversion for one channel and wait for the next activation (conversion can be started synchronously.) * Interrupt requests can be generated and the extended intelligent I/O service (EI2OS) can be started after the end of A/D conversion. Furthermore, A/D conversion result data can be transferred to the memory, enabling efficient continuous processing. * When interrupts are enabled, there is no loss of data even in continuous operations because the conversion data protection function is in effect. * Starting factors for conversion: Selected from software activation, and external trigger (falling edge). 65 MB90520 Series (1) Register Configuration * A/D control status register upper digits (ADCS2) bit 8 bit 7 . . . . . . . . . . . . bit 0 Address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 000037H BUSY INT INTE PAUS STS1 STS0 STRT RESV R/W R/W R/W R/W R/W R/W W (ADCS1) Initial value 00000000 B R/W * A/D control status register lower digits (ADCS1) Address bit 15 . . . . . . . . . . . . bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 000036H MD1 MD0 ANS2 ANS1 ANS0 ANE2 ANE1 ANE0 R/W R/W R/W R/W R/W R/W R/W R/W (ADCS2) Initial value 00000000 B * A/D data register upper digits (ADCR2) Address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 . . . . . . . . . . . . bit 0 000039H RESV ST1 ST0 CT1 XCT0 -- (D9) (D8) W W W W W -- R R (ADCR1) Initial value 0 0 0 0 1 - XX B * A/D data register lower digits (ADCR1) Address bit 15 . . . . . . . . . . . . bit 8 bit 7 000038H (ADCR2) R/W : Readable and writable R : Read only W : Write only -- : Unused X : Indeterminate RESV : Reserved bit 66 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 D7 D6 D5 D4 D3 D2 D1 D0 R R R R R R R R Initial value XXXXXXXX B MB90520 Series (2) Block Diagram A/D control status register (ADCS) BUSY INT Interrupt request #11* INTE PAUS STS1 STS0 STRT DA MD1 MD0 ANS2 ANS1 ANS0 ANE2 ANE1 ANE0 6 2 Clock selector Decoder Internal data bus P27/ADTG P73/TO1/OUT7 Comparator P67/AN7 P66/AN6 P65/AN5 P64/AN4 P63/AN3 P62/AN2 P61/AN1 P60/AN0 Sample hold circuit Control circuit Analog channel selector A/D data register SELB ST1 ST0 CT1 CT0 (ADCR) AVRH, AVRL AVCC AVSS -- (D9) (D8) D7 8-bit D/A converter D6 D5 D4 D3 D2 D1 D0 : Machine clock frequency TO : 16-bit PPG timer channel 1 output * : Interrupt number 67 MB90520 Series 14. 8-bit D/A Converter The 8-bit D/A converter, which is based on the R-2R system, supports 8-bit resolution mode. It contains two channels each of which can be controlled in terms of output by the D/A control register. (1) Register Configuration * D/A converter data register ch.0 (DADR0) Address bit 15 . . . . . . . . . . . . bit 8 bit 7 00003AH (DADR1) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 DA07 DA06 DA05 DA04 DA03 DA02 DA01 DA00 R/W R/W R/W R/W R/W R/W R/W R/W Initial value XXXXXXXX B * D/A converter data register ch.1 (DADR1) Address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 . . . . . . . . . . . . bit 0 00003BH DA17 DA16 DA15 DA14 DA13 DA12 DA11 DA10 R/W R/W R/W R/W R/W R/W R/W R/W (DADR0) Initial value XXXXXXXX B * D/A control register 0 (DACR0) Address bit 15 . . . . . . . . . . . . bit 8 bit 7 00003CH (DACR1) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 -- -- -- -- -- -- -- DAE0 -- -- -- -- -- -- -- R/W Initial value - - - - - - -0B * D/A control register 1 (DACR1) bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 00003DH -- -- -- -- -- -- -- DAE1 -- -- -- -- -- -- -- R/W R/W : Readable and writable -- : Unused X : Indeterminate 68 bit 8 bit 7 . . . . . . . . . . . . bit 0 Address (DACR0) Initial value - - - - - - -0B MB90520 Series * Block Diagram Internal data bus D/A converter data register ch.1 (DADR1) D/A converter data register ch.0 (DADR0) DA17 DA16 DA15 DA14 DA13 DA12 DA11 DA10 DA07 DA06 DA05 DA04 DA03 DA02 DA01 DA00 D/A converter 1 D/A converter 0 DVRH DVRL DA17 DA07 Pin 2R P54/DA1 R DA16 2R DA15 2R DA14 2R DA13 2R DA12 2R DA11 2R DA10 Pin 2R DA06 2R R DA05 R DA04 R DA03 R DA02 R DA01 R DA00 2R 2R 2R 2R 2R 2R 2R -- -- R R R R R 2R DVSS DVSS Standby control D/A control register 1 (DACR1) -- R 2R Standby control -- P53/DA0 R -- D/A control register 0 (DACR0) -- -- DAE1 -- -- -- -- -- -- -- DAE0 Internal data bus 69 MB90520 Series 15. Clock Timer The clock timer control register (WTC) controls operation of the clock timer, and time for an interval interrupt. (1) Register Configuration * Clock timer control register (WTC) . . . . . . . . . . . . bit 8 bit 7 Address bit 15 (Disabled) 0000AAH bit 6 bit 5 WDCS SCE WTIE WTOF R/W R R/W bit 4 bit 3 WTR R/W R bit 2 bit 1 bit 0 WTC2 WTC1 WTC0 R/W R/W Initial value 1X0 0 0 0 0 0 B R/W R/W : Readable and writable R : Read only X : Indeterminate (2) Block Diagram To watchdog timer Timer counter LCLK x 21 x 22 x 23 x 24 x 25 x 26 x 27 x 28 x 29 x 210 x 211 x 212 x 213 x 214 x 215 OF OF OF OF OF OF OF Power-on reset Shift to a hardware standby Counter clear circuit To sub-clock oscillation stabilization time controller Shift to stop mode Interval timer selector Clock timer interrupt request #22* WDCS SCE WTIE WTOF WTR WTC2 WTC1 WTC0 Clock timer control register (WTC) * : Interrupt number OF : Overflow LCLK : Oscillation sub-clock frequency 70 MB90520 Series 16.LCD Controller/Driver The LCD controller/driver, which contains a 16-byte display data memory, controls LCD indication using four common output pins and 32 segment output pins. It can select three types of duty output, and directly drive the LCD (liquid crystal display) panel. (1) Register Configuration * LCDC control register 0 (LCR0) Address bit 15 . . . . . . . . . . . . bit 8 bit 7 00006AH (LCR1) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 CSS LCEN VSEL BK MS1 MS0 FP1 FP0 R/W R/W R/W R/W R/W R/W R/W R/W Initial value 00010000 B * LCDC control register 1 (LCR1) Address bit 15 bit 14 00006BH RESV SEG5 bit 13 bit 12 bit 11 bit 10 SEG4 RESV SEG3 SEG2 SEG1 R/W R/W bit 9 bit 8 bit 7 . . . . . . . . . . . . bit 0 SEG0 (LCR10) R/W R/W bit 9 bit 8 bit 7 . . . . . . . . . . . . bit 0 Initial value 00000000 B * Port 7/COM pin selection register (LCDCMR) Address bit 15 bit 14 bit 13 bit 12 00000BH -- -- -- -- -- -- -- -- bit 11 bit 10 COM3 COM2 COM1 COM0 R/W R/W W (PDRA) Initial value - - - - 0000 B R/W R/W : Readable and writable -- : Unused X : Indeterminate RESV : Reserved bit 71 (2) Block Diagram LCDC control register 0 (LCR0) Timing controller 2 CSS LCEN VSEL BK MS1 MS0 FP1 FP0 Prescaler Split resistor Commen driver Segment driver HCLK LCLK 32 6 Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin SEG02 SEG01 SEG00 COM3 COM2 COM1 COM0 V3 V2 V1 V0 Pin Pin Pin P77/SEG31 P76/SEG30 P95/SEG29 ......... Indication RAM (16 bytes) RESV SEG5 SEG4 RESV SEG3 SEG2 SEG1 SEG0 LCDC control register 1 (LCR1) Controller section HCLK : Oscillation frequency LCLK : Oscillation sub-clock frequency ......... generator AC MB90520 Series 72 Internal data bus MB90520 Series 17. Communications Prescaler Register This register controls machine clock division. Output from the communications prescaler register is used for UART0 (SCI), UART1 (SCI), and extended I/O serial interface. The communications prescaler register is so designed that a constant baud rate may be acquired for various machine clocks. (1) Register Configuration * Communications prescaler control register (CDCR) Address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 . . . . . . . . . . . . bit 0 000027H MD -- -- -- DIV3 DIV2 DIV1 DIV0 R/W -- -- -- R/W R/W R/W R/W (SDR0) Initial value 0 - - - 1111 B R/W : Readable and writable -- : Unused 73 MB90520 Series 18. Address Match Detection Function When the address is equal to a value set in the address detection register, the instruction code loaded into the CPU is replaced forcibly with the INT9 instruction code (01H). As a result, when the CPU executes a set instruction, the INT9 instruction is executed. Processing by the INT#9 interrupt routine allows the program patching function to be implemented. Two address detection registers are supported. An interrupt enable bit and flag are prepared for each register. If the value set in the address detection register matches an address and if the interrupt enable bit is set at "1", the interrupt flag is set at "1" and the instruction code loaded into the CPU is replaced forcibly with the INT9 instruction code. The interrupt flag is cleared to "0" by writing 0 by an instruction. (1) Register Configuration * Program address detection register 0 to 2 (PADR0) Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W R/W R/W R/W R/W R/W R/W R/W bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W R/W R/W R/W R/W R/W R/W R/W bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W R/W R/W R/W R/W R/W R/W R/W PADR0 (Low order address) : 001FF0H Address PADR0 (Middle order address) : 001FF1H Address PADR0 (High order address) : 001FF2H Initial value XXXXXXXX B Initial value XXXXXXXX B Initial value XXXXXXXX B * Program address detection register 3 to 5 (PADR1) Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W R/W R/W R/W R/W R/W R/W R/W bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W R/W R/W R/W R/W R/W R/W R/W bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W R/W R/W R/W R/W R/W R/W R/W bit 3 bit 2 bit 1 bit 0 AD1D AD0E AD0D R/W R/W R/W PADR1 (Low order address) : 001FF3H Address PADR1 (Middle order address) : 001FF4H Address PADR1 (High order address) : 001FF5H Initial value XXXXXXXX B Initial value XXXXXXXX B Initial value XXXXXXXX B * Program address detection control status register (PACSR) Address bit 7 00009EH RESV -- R/W : Readable and writable -- : Unused X : Indeterminate RESV : Reserved bit 74 bit 6 bit 5 bit 4 RESV RESV RESV AD1E -- -- -- R/W Initial value 00000000 B MB90520 Series Address latch Internal data bus Address detection register Enable bit Compare (2) Block Diagram INT9 instruction F2MC-16LX CPU core Detect bit Reset Set 75 MB90520 Series 19. ROM Mirroring Function Selection Module The ROM mirroring function selection module can select what the FF bank allocated the ROM sees through the 00 bank according to register settings. (1) Register Configuration * ROM mirroring function selection register (ROMM) Address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 . . . . . . . . . . . . bit 0 00006FH -- -- -- -- -- -- -- MI -- -- -- -- -- -- -- W (Disabled) W : Write only -- : Unused Note: Do not access this register during operation at addresses 004000H to 00FFFFH. (2) Block Diagram Internal data bus ROM mirroring function selection register (ROMM) Address area Address FF bank 00 bank Data ROM 76 Initial value - - - - - - -1B MB90520 Series 20. Low-power Consumption (Stand-by) Mode The F2MC-16LX has the following CPU operating mode configured by selection of an operating clock and clock operation control. * Clock mode PLL clock mode : A mode in which the CPU and peripheral equipment are driven by PLL-multiplied oscillation clock (HCLK). Main clock mode: A mode in which the CPU and peripheral equipment are driven by divided-by-2 of the oscillation clock (HCLK). The PLL multiplication circuits stops in the mainclock mode. * CPU intermittent operation mode The CPU intermittent operation mode is a mode for reducing power consumption by operating the CPU intermittently while external bus and peripheral functions are operated at a high-speed. * Hardware stand-by mode The hardware standby mode is a mode for reducing power consumption by stopping clock supply to the CPU by the low-power consumption control circuit, stopping clock supplies to the CPU and peripheral functions (timebase timer mode), and stopping oscillation clock (stop mode, hardware standby mode). Of these modes, modes other than the PLL clock mode are power consumption modes. (1) Register Configuration * Clock select register (CKSCR) Address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 . . . . . . . . . . . . bit 0 0000A1H SCM MCM WS1 WS0 SCS MCS CS1 CS0 R R R/W R/W R/W R/W R/W R/W (LPMCR) Initial value 11111100 B * Low-power consumption mode control register (LPMCR) Address bit 15 . . . . . . . . . . . . bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0000A0H STP SLP SPL RST TMD CG1 CG0 SSR W W R/W W W R/W R/W R/W (CKSCR) Initial value 00011000 B R/W : Readable and writable R : Read only W : Write only 77 MB90520 Series (2) Block Diagram Standby control circuit Low-power consumption mode control register (LPMCR) STP SLP SPL RST TMD CG1 CG0 SSR Hardware standby CPU clock control circuit Peripheral clock control circuit S Q S R Reset Interrupt CPU intermittent operation cycle selector 2 Clock mode Sleep signal Stop signal Q R S Q S R CPU operation clock Peripheral function operation clock Machine clock Q R Clock selector Oscillation stabilization time selector 2 2 PLL multiplication circuit SCM MCM WS1 WS0 SCS MCS CS1 CS0 Clock select register (CKSCR) X0 X1 Pin Oscillation clock Pin Dividedby-2 Main Clock oscillator Dividedby-2048 Dividedby-4 Dividedby-4 Dividedby-8 clock Timebase timer To watchdog timer X0A Pin X1A Pin Oscillation sub-clock Sub-clock oscillator S : Set R : Reset Q : Output 78 Dividedby-1024 Dividedby-8 Clock timer Dividedby-2 Dividedby-2 MB90520 Series ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings (AVSS = VSS = 0.0 V) Parameter Symbol Value Unit Remarks Min. Max. VCC VSS - 0.3 VSS + 6.0 V AVCC VSS - 0.3 VSS + 6.0 V *1 AVRH, AVRL VSS - 0.3 VSS + 6.0 V *1 DVCC VSS - 0.3 VSS + 6.0 V *1 Input voltage VI VSS - 0.3 VCC + 6.0 V *2 Output voltage VO VSS - 0.3 VCC + 6.0 V *2 "L" level maximum output current IOL 15 mA *3 "L" level average output current IOLAV 4 mA *4 "L" level total maximum output current IOL 100 mA Power supply voltage "L" level total average output current IOLAV 50 mA *5 "H" level maximum output current IOH -15 mA *3 "H" level average output current IOHAV -4 mA *4 "H" level total maximum output current IOH -100 mA "H" level total average output current IOHAV -50 mA Power consumption PD 300 mW Operating temperature TA -40 +85 C Storage temperature Tstg -55 +150 C *1: *2: *3: *4: *5: *5 AVCC, AVRH, AVRL, and DVCC shall never exceed VCC. AVRL shall never exceed AVRH. VI and VO shall never exceed VCC + 0.3 V. The maximum output current is a peak value for a corresponding pin. Average output current is an average current value observed for a 100 ms period for a corresponding pin. Total average current is an average current value observed for a 100 ms period for all corresponding pins. Note: Average output current = operating currnet x operating efficiency WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. 79 MB90520 Series 2. Recommended Operating Conditions (AVSS = VSS = 0.0 V) Parameter Symbol Value Unit Remarks Min. Max. VCC 3.0 5.5 V Normal operation (MB90523) VCC 4.5 5.5 V Normal operation (MB90F523) Guaranteed frequency = 10 MHz at 4.0 V to 4.5V VCC 3.0 5.5 V Retains status at the time of operation stop Smoothing capacitor CS 0.1 1.0 F * Operating temperature TA -40 +85 C Power supply voltage * : Use a ceramic capacitor or a capacitor with equivalent frequency characteristics. The smoothing capacitor to be connected to the VCC pin must have a capacitance value higher than CS. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. * C pin diagram C CS 80 MB90520 Series 3. DC Characteristics Parameter Symbol Pin name (AVCC = VCC = 5.0 V 10%, AVSS = VSS = 0.0 V, TA = -40C to +85C) Value Condition Unit Remarks Min. Typ. Max. VIH CMOS input pin 0.7 VCC -- VCC + 0.3 V VIHS CMOS hysteresis input pin 0.8 VCC -- VCC + 0.3 V VIHM MD pin input -- VCC + 0.3 V VIL CMOS input pin -- 0.3 V CC V VILS CMOS hysteresis input pin VSS - 0.3 -- 0.2 VCC V VILM MD pin input VSS - 0.3 -- VSS + 0.3 V "H" level output voltage VOH Other than P90 and P97 VCC = 4.5 V IOH = -2.0 mA VCC - 0.5 -- -- V "L" level output voltage VOL All output pins VCC = 4.5 V IOL = 2.0 mA -- -- 0.4 V -- 0.1 5 A -5 -- 5 A "H" level input voltage "L" level input voltage VCC = 3.0 V to 5.5 V VCC - 0.3 (MB90523) VCC = 4.0 V to 5.5 V VSS - 0.3 (MB90F523) Open-drain output Ileak leakage current Output pin P90 to P97 Input leakage current IIL Other than P90 and P97 Pull-up resistance RUP P00 to P07, P10 to P17, P40 to P47, RST, MD0, MD1 -- 15 30 100 k Pull-down resistance RDOWN MD0 to MD2 -- 15 30 100 k -- VCC = 5.5 V VSS < VI < VCC (Continued) 81 MB90520 Series Parameter Symbol Power supply current* Pin name ICC VCC ICC VCC ICC VCC ICC VCC ICC VCC ICC VCC ICC VCC ICCS VCC ICCS VCC ICCL VCC ICCL VCC ICCLS VCC ICCLS VCC ICCT VCC ICCT VCC ICCH VCC I V ICCH VCC CCH Input CIN capacitance CC Other than AVCC, AVSS, VCC, VSS (AVCC = VCC = 5.0 V 10%, AVSS = VSS = 0.0 V, TA = -40C to +85C) Value Condition Unit Remarks Min. Typ. Max. -- 30 40 mA MB90523 -- 85 130 mA MB90F523 -- 35 45 mA MB90523 -- 90 140 mA MB90F523 -- 40 50 mA MB90523 -- 95 145 mA MB90F523 -- 95 140 mA MB90F523 -- 7 12 mA MB90523 -- 25 30 mA MB90F523 -- 0.1 1.0 mA MB90523 -- 4 7 mA MB90F523 -- 30 50 mA MB90523 -- 0.1 1 mA MB90F523 -- 15 30 A MB90523 -- 30 50 A MB90F523 -- 5 20 A MB90523 -- 0.1 10 A MB90F523 TA = +25C (max.) In stop mode -- -- 200 A MB90F523 -- -- 10 80 pF Internal operation at 16 MHz VCC at 5.0 V Normal operation Internal operation at 16 MHz VCC at 5.0 V A/D converter operation Internal operation at 16 MHz VCC at 5.0 V D/A converter operation When data written in flash mode is erased Internal operation at 16 MHz VCC at 5.0 V In sleep mode Internal operation at 8 kHz VCC at 5.0 V TA = +25C Subsystem operatin Internal operation at 8 kHz VCC at 5.0 V TA = +25C In subsleep mode Internal operation at 8 kHz VCC at 5.0 V TA = +25C In clock mode TA = +25C In stop mode (Continued) 82 MB90520 Series (Continued) Parameter Symbol LCD split resistor RLCD Pin name V0 to V1, V1 to V2, V2 to V3 Output impedance RVCOM for COM0 to COM3 COM0 to COM3 Output impedance RVSEG for SEG00 to SEG31 SEG00 to SEG31 LCDC leak ILCKC current V0 to V3, COM1 to COM3, SEG00 to SEG31 (AVCC = VCC = 5.0 V 10%, AVSS = VSS = 0.0 V, TA = -40C to +85C) Value Condition Unit Remarks Min. Typ. Max. -- 50 100 200 k -- -- 2.5 k -- -- 15 k -- -- 5 A V1 to V3 = 5.0 V -- * : The current value is preliminary value and may be subject to change for enhanced characteristics without previous notice.The power supply current is measured with an external clock. 83 MB90520 Series 4. AC Characteristics (1) Reset, Hardware Standby Input Timing Parameter (AVCC = VCC = 5.0 V 10%, AVSS = VSS = 0.0 V, TA = -40C to +85C) Value Symbol Pin name Condition Unit Remarks Min. Max. Reset input time tRSTL RST Hardware standby input time tHSTL HST -- 4 tCP* -- ns 4 tCP* -- ns * : For tCP (internal operating clock cycle time), refer to "(3) Clock Timings." tRSTL, tHSTL RST HST 0.2 VCC 0.2 VCC * Measurement conditions for AC ratings Pin CL CL is a load capacitance connected to a pin under test. Capacitors of CL = 30 pF must be connected to CLK and ALE pins, while CL of 80 pF must be connected to address data bus (AD15 to AD00), RD, and WR pins. 84 MB90520 Series (2) Specification for Power-on Reset Parameter Symbol Pin name Condition Power supply rising time tR VCC Power supply cut-off time tOFF VCC -- (AVSS = VSS = 0.0 V, TA = -40C to +85C) Value Unit Remarks Min. Max. 0.05 30 ms * Due to repeated 4 -- ms operations * : VCC must be kept lower than 0.2 V before power-on. Notes: * The above ratings are values for causing a power-on reset. * There are internal registers which can be initialized only by a power-on reset. Apply power according to this rating to ensure initialization of the registers. tR VCC 2.7 V 0.2 V 0.2 V 0.2 V tOFF Sudden changes in the power supply voltage may cause a power-on reset. To change the power supply voltage while the device is in operation, it is recommended to raise the voltage smoothly to suppress fluctuations as shown below. In this case, change the supply voltage with the PLL clock not used. If the voltage drop is 1 mV or fewer per second, however, you can use the PLL clock. VCC 0.2 V VSS It is recommended to keep the rising speed of the supply voltage at 50 mV/ms or slower. 85 MB90520 Series (3) Clock Timings (AVCC = VCC = 5.0 V 10%, AVSS = VSS = 0.0 V, TA = -40C to +85C) Value Symbol Pin name Condition Unit Remarks Parameter Min. Typ. Max. FC X0, X1 -- 3 -- 16 MHz 4.0 V to Clock frequency FC X0, X1 3 -- 10 MHz MB90F523 4.5 V X0A, X1A -- 32.768 -- kHz FCL -- HCYL t X0, X1 62.5 -- 333 ns 4.0 V to Clock cycle time tHCYL X0, X1 100 -- 333 ns MB90F523 4.5 V X0A, X1A -- 30.5 -- s tLCYL Recommened PWH, X0 10 -- -- ns duty ratio of PWL 30% to 70% Input clock pulse width PWLH, X0A -- 15.2 -- s PWLL tCR, External clock Input clock rising/falling time X0, X0A -- -- 5 ns tCF operation When the main -- 1.5 -- 16 MHz fCP clock is used 4.0 V to When the main Internal operating clock -- 1.5 -- 10 MHz fCP 4.5 V clock is used frequency Subclock -- -- 8.192 -- kHz fLCP operation When the main -- 62.5 -- 333 ns tCP clock is used 4.0 V to When the main Internal operating clock cycle -- 100 -- 333 ns tCP 4.5 V clock is used time Subclock -- -- 122.1 -- s tLCP operation Frequency fluctuation rate f -- -- -- 5 % * locked * : The frequency fluctuation rate is the maximum deviation rate of the preset center frequency when the multiplied PLL signal is locked. + + f = || x 100 (%) fO Center frequency fO - - The PLL frequency deviation changes periodically from the preset frequency "(about CLK x (1CYC to 50 CYC)", thus minimizing the chance of worst values to be repeated (errors are minimal and negligible for pulses with long intervals). 86 MB90520 Series * X0, X1 clock timing tHCYL 0.8 VCC 0.8 VCC 0.8 VCC 0.2 VCC X0 0.2 VCC PWH PWL tCF tCR * X0A, X1A clock timing tLCYL 0.8 VCC 0.8 VCC 0.8 VCC 0.2 VCC X0A 0.2 VCC PWLH PWLL tCF tCR * PLL operation guarantee range Relationship between internal operating clock frequency and power supply voltage Power supply voltage VCC (V) MB90F523 guarantee range 5.5 4.5 4.0 PLL operation guarantee range 3.3 MB90V520 guarantee range 3.0 MB90523 guarantee range 1 3 8 10 Internal clock fCP 12 16 (MHz) Relationship between oscillating frequency, internal operating clock frequency, and power supply voltage (MHz) Multiplied Multiplied Multiplied -by-3 -by-2 -by-4 Internal clock fCP 16 Multiplied -by-1 12 8 Not multiplied 4 3 2 1 2 3 4 6 8 12 16 (MHz) Oscillation clock FC 87 MB90520 Series The AC ratings are measured for the following measurement reference voltages. * Input signal waveform Hystheresis input pin Hystheresis input pin 0.8 VCC 2.4 VCC 0.2 VCC 0.8 VCC Pins other than hystheresis input/MD input 0.7 VCC 0.3 VCC 88 * Output signal waveform MB90520 Series (4) Recommended Resonator Manufactures * Sample application of ceramic resonator X0 X1 R * C1 C2 * Mask ROM product (MB90522, MB90523) Resonator manufacturer* Murata Mfg. Co., Ltd. TDK Corporation Frequency (MHz) C1 (pF) C2 (pF) R CSA2.00MG040 2.00 100 100 Not required CSA4.00MG040 4.00 100 100 Not required CSA8.00MTZ 8.00 30 30 Not required CSA16.00MXZ040 16.00 15 15 Not required CSA32.00MXZ040 32.00 5 5 Not required CCR3.52MC3 to CCR6.96MC3 3.52 to 6.96 Built-in Built-in Not required CCR7.0MC5 to CCR12.0MC5 7.00 to 12.00 Built-in Built-in Not required CCR20.0MSC6 to CCR32.0MSC6 20.00 to 32.00 Built-in Built-in Not required Resonator (Continued) 89 MB90520 Series (Continued) * Flash ROM product (MB90F523) Resonator Resonator manufacturer* CSA2.00MG040 CSA4.00MG040 Murata CSA8.00MTZ Mfg. Co., Ltd. CSA16.00MXZ040 CST32.00MXZ040 CCR3.52MC3 to CCR6.96MC3 TDK Corporation CCR7.0MC5 to CCR12.0MC5 CCR20.0MSC6 to CCR32.0MSC6 Frequency (MHz) 2.00 4.00 8.00 16.00 32.00 3.52 to 6.96 7.0 to 12.0 20.0 to 32.0 C1 (pF) C2 (pF) R 100 100 30 15 5 100 100 30 15 5 Not required Not required Not required Not required Not required Built-in Built-in Not required Built-in Built-in Not required Built-in Built-in Not required Inquiry:Murata Mfg. Co., Ltd.. * Murata Electronics North America, Inc.: TEL 1-404-436-1300 * Murata Europe Management GmbH: TEL 49-911-66870 * Murata Electronics Singapore (Pte.): TEL 65-758-4233 TDK Corporation * TDK Corporation of America Chicago Regional Office: TEL 1-708-803-6100 * TDK Electronics Europe GmbH Components Division: TEL 49-2102-9450 * TDK Singapore (PTE) Ltd.: TEL 65-273-5022 * TDK Hongkong Co., Ltd.: TEL 852-736-2238 * Korea Branch, TDK Corporation: TEL 82-2-554-6636 90 MB90520 Series (5) Clock Output Timing Parameter Cycle time CLK CLK (AVCC = VCC = 5.0 V 10%, AVSS = VSS = 0.0 V, TA = -40C to +85C) Value Pin Symbol name Condition Unit Remarks Min. Max. tCYC CLK VCC = 5.0 V 10% 62.5 -- ns VCC = 5.0 V 10% 100 -- ns MB90F523 tCYC CLK 4.0 V to 4.5 V CLK VCC = 5.0 V 10% 20 -- ns tCHCL VCC = 5.0 V 10% 32 -- ns MB90F523 tCHCL CLK 4.0 V to 4.5 V tCYC tCHCL 2.4 V CLK 2.4 V 0.8 V 91 MB90520 Series (6) Ready Input Timing Parameter RDY setup time RDY hold time (AVCC = VCC = 5.0 V 10%, AVSS = VSS = 0.0 V, TA = -40C to +85C) Value Symbol Pin name Condition Unit Remarks Min. Max. tRYHS RDY 45 -- ns -- RDY 0 -- ns tRYHH Note: Use the automatic ready function when the setup time for the rising edge of the RDY signal is not sufficient. 2.4 V 2.4 V CLK ALE RD/WR tRYHS RDY (wait inserted) 0.2 VCC RDY (wait not inserted) 0.8 VCC tRYHS 0.2 VCC 0.8 VCC tRYHH (7) Hold Timing Parameter Symbol (AVCC = VCC = 5.0 V 10%, AVSS = VSS = 0.0 V, TA = -40C to +85C) Value Pin name Condition Unit Remarks Min. Max. Pins in floating status tXHAL HAK time HAK HAK pin valid time HAK tHAHV -- 30 1 tCP* ns 1 tCP* 2 tCP* ns * : For tCP (internal operating clock cycle time), refer to "(3) Clock Timings." Note: More than 1 machine cycle is needed before HAK changes after HRQ pin is fetched. HAK 2.4 V 0.8 V tXHAL Pins 92 2.4 V 0.8 V tHAHV High impedance 2.4 V 0.8 V MB90520 Series (8) UART (SCI) Timing Parameter Serial clock cycle time SCK SOT delay time Valid SIN SCK SCK valid SIN hold time Serial clock "H" pulse width Serial clock "L" pulse width SCK SOT delay time (AVCC = VCC = 5.0 V 10%, AVSS = VSS = 0.0 V, TA = -40C to +85C) Value Symbol Pin name Condition Unit Remarks Min. Max. 8 tCP* tSCYC SCK0 to SCK4 -- ns SCK0 to SCK4, Internal shift clock - 80 80 ns tSLOV SOT0 to SOT4 mode SCK0 to SCK4, CL = 80 pF 100 -- ns tIVSH + 1 TTL for an SIN0 to SIN4 SCK0 to SCK4, output pin tSHIX 60 -- ns SIN0 to SIN4 tSHSL SCK0 to SCK4 4 tCP* -- ns tSLSH SCK0 to SCK4 External shift clock mode SCK0 to SCK4, CL = 80 pF SOT0 to SOT4 + 1 TTL for an SCK0 to SCK4, output pin SIN0 to SIN4 SCK0 to SCK4, SIN0 to SIN4 4 tCP* -- ns -- 150 ns 60 -- ns 60 -- ns tSLOV Valid SIN SCK tIVSH SCK valid SIN hold time tSHIX * : For tCP (internal operating clock cycle time), refer to "(3) Clock Timings." Notes: * These are AC ratings in the CLK synchronous mode. * CL is the load capacitor value connected to pins while testing. 93 MB90520 Series * Internal shift clock mode tSCYC SCK 2.4 V 0.8 V 0.8 V tSLOV 2.4 V SOT 0.2 V tIVSH SIN tSHIX 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC * External shift clock mode tSLSH SCK tSHSL 0.8 VCC 0.2 VCC 0.8 VCC 0.2 VCC tSLOV SOT 2.4 V 0.8 V tIVSH SIN 94 tSHIX 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC MB90520 Series (9) Timer Input Timing Parameter Input pulse width Symbol tTIWH, tTIWL (AVCC = VCC = 5.0 V 10%, AVSS = VSS = 0.0 V, TA = -40C to +85C) Value Pin name Condition Unit Remarks Min. Max. IN0, IN1 -- 4 tCP* -- ns * : For tCP (internal operating clock cycle time), refer to "(3) Clock Timings." 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC IN tTIWH tTIWL (10) Timer Output Timing Parameter CLK TOUT transition time (AVCC = VCC = 5.0 V 10%, AVSS = VSS = 0.0 V, TA = -40C to +85C) Value Symbol Pin name Condition Unit Remarks Min. Max. OUT0 to OUT3, tTO -- 30 -- ns PPG0, PPG1 2.4 V CLK tTO TOUT 2.4 V 0.8 V 95 MB90520 Series 5. A/D Converter Electrical Characteristics Parameter Resolution Total error Non-linear error Differential linearity error Zero transition voltage Full-scale transition voltage (AVCC = VCC = 5.0 V 10%, AVSS = VSS = 0.0 V, 3.0 V AVRH - AVRL, TA = -40C to +85C) Value Symbol Pin name Condition Unit Min. Typ. Max. -- -- -- 8/10 -- bit -- -- -- -- 5.0 LSB -- -- -- -- 2.5 LSB -- -- mV VFST AN0 to AN7 AVRH -6.5LSB mV Sampling period -- -- VCC = 5.0 V 10% at machine clock of 16 MHz VCC = 5.0 V 10% at machine clock of 16 MHz VAIN -- AVRH -- AVRL IA -- -- ns -- 64 tCP* -- ns -- -- 10 A AVRL -- AVRH V AVRL + 2.7 -- AVCC V 0 -- -- -- AVCC IAH AVCC IR AVRH IRH AVRH -- AN0 to AN7 5 AVRH -2.7 -- mA V Supply current when CPU stopped and 8/10-bit A/D converter not in operation (VCC = AVCC = AVRH = 5.0 V) -- Supply current when CPU stopped and 8/10-bit A/D converter not in operation (VCC = AVCC = AVRH = 5.0 V) -- -- 5 A -- 400 -- A -- -- 5 A -- -- -- 4 LSB * : For tCP (internal operating clock cycle time), refer to "(3) Clock Timings." 96 AVRH AVRH -1.5 LSB +1.5 LSB 176 tCP* AN0 to AN7 AN0 to AN7 IAIN Reference voltage Offset between channels LSB AVSS AVSS +0.5 LSB -3.5 LSB +4.5 LSB -- Reference voltage supply current 1.9 AN0 to AN7 -- Power supply current -- VOT Conversion time Analog port input current Analog input voltage -- -- MB90520 Series 6. A/D Converter Glossary Resolution: Analog changes that are identifiable with the A/D converter Linearity error: The deviation of the straight line connecting the zero transition point ("00 0000 0000" "00 0000 0001") with the full-scale transition point ("11 1111 1110" "11 1111 1111") from actual conversion characteristics Differential linearity error: The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value Total error: The total error is defined as a difference between the actual value and the theoretical value, which includes zero-transition error/full-scale transition error and linearity error. Total error 3FF 3FE 0.5 LSB' Actual conversion characteristics Digital output 3FD {1 LSB x (N - 1) + 0.5 LSB} 004 VNT (mesured value) 003 Actual conversion characteristics 002 Theoretical characteristics 001 0.5 LSB' AVRL 1 LSB' = (Theoretical value) AVRH - AVRL Analog input [V] 1024 VOT' (Theoretical value) = AVRL + 0.5 LSB' [V] AVRH Total error for digital output N = VNT - {1 LSB x (N - 1) + 0.5 LSB} [LSB] 1 LSB' VNT: Voltage at a transition of digital output from (N - 1) to N VFST' (Theoretical value) = AVRH - 1.5 LSB' [V] (Continued) 97 MB90520 Series (Continued) Linearity error Differential linearity error Theoretical characteristics 3FF Actual conversion characteristics 3FD Digital output N+1 {1 LSB x (N - 1) + VOT'} VFST (mesured value) VNT (mesured value) 004 Actual conversion characteristics 003 Actual conversion characteristics N Digital output 3FE N-1 V(N + 1)T (mesured value) N-2 VNT (mesured value) 002 Theoretical characteristics 001 Actual conversion characteristics VOT (mesured value) AVRL Analog input AVRH AVRL Analog input AVRH Linearity error of VNT - {1 LSB x (N - 1) + VOT} [LSB] digital output N = 1 LSB' Differential linearity error = of digital N 1 LSB = V(N + 1)T - VNT - 1 LSB [LSB] 1 LSB' VFST - VOT [V] 1022 VOT: Voltage at transition of digital output from "000H" to "001H" VFST: Voltage at transition of digital output from "3FEH" to "3FFH" 7. Notes on Using A/D Converter The impedance value of about 5 k or lower for the external circuit of analog input are recommended. When capacitors are connected to external pins, the capacitance of several thousand times the internal capacitor value is recommended to minimized the effect of voltage distribution between the external capacitor and internal capacitor. When the output impedance of the external circuit is too high, the sampling period for analog voltages may not be sufficient (sampling period = 4.00 s @machine clock of 16 MHz). * Block diagram of analog input circuit model Analog input RON C Comparator MB90523 RON: Approx. 1.5 k C: Approx. 3.0 pF MB90F523 RON: Approx. 3.0 k C: Approx. 65 pF Note: Listed values must be considered as standards. * Error The smaller the | AVRH - AVRL |, the greater the error would become relatively. 98 MB90520 Series 8. D/A Converter Electrical Characteristics Parameter (AVCC = VCC = DVCC = 5.0 V 10%, AVSS = VSS = DVSS = 0.0 V, TA = -40C to +85C) Value Unit Remarks Symbol Pin name Min. Typ. Max. Resolution -- -- -- 8 -- bit Differential linearity error -- -- -- -- 0.9 LSB Absolute accuracy -- -- -- -- 1.2 % Linearity error -- -- -- -- 1.5 LSB Conversion time -- -- -- 10 20 Analog reference voltage -- DVCC VSS + 3.0 -- AVCC V IDVR DVCC -- -- 300 A IDVRS DVCC -- -- 10 A In sleep mode -- 20 -- k Reference voltage supply current Analog output impedance -- -- s Load capacitance: 20 pF 99 MB90520 Series EXAMPLE CHARACTERISTICS (1) Power Supply Current (MB90523) ICCS - VCC ICC - VCC ICCS (mA) 10 ICC (mA) 35 TA = +25C TA = +25C 9 30 8 25 Fc = 16 MHz 20 Fc = 12.5 MHz Fc = 10 MHz 15 Fc = 8 MHz 10 Fc = 5 MHz Fc = 4 MHz Fc = 2 MHz 5 3.0 4.0 5.0 Fc = 16 MHz 7 6 Fc = 12.5 MHz 5 Fc = 10 MHz Fc = 8 MHz 4 Fc = 5 MHz Fc = 4 MHz 3 2 Fc = 2 MHz 1 3.0 6.0 VCC (V) 4.0 5.0 6.0 VCC (V) ICCS - TA ICC - TA ICC (mA) 35 ICCS (mA) 10 VCC = 5.0 V VCC = 5.0 V 9 30 8 25 Fc = 16 MHz 20 Fc = 12.5 MHz Fc = 10 MHz 15 Fc = 8 MHz 10 Fc = 5 MHz Fc = 4 MHz Fc = 2 MHz 5 -20 +10 +40 +70 Fc = 16 MHz 7 6 Fc = 12.5 MHz 5 Fc = 10 MHz 4 Fc = 8 MHz 3 Fc = 5 MHz Fc = 4 MHz Fc = 2 MHz 2 1 +100 -20 +10 +70 +40 TA (C) ICCL - VCC ICCLS - VCC ICCLS (mA) 70 ICCL (A) 160 TA = +25C TA = +25C 60 140 Fc = 8 kHz 120 +100 TA (C) 100 50 Fc = 8 kHz 40 80 30 60 20 40 10 20 3.0 100 4.0 5.0 6.0 VCC (V) 3.0 4.0 5.0 6.0 VCC (V) MB90520 Series ICCS - Fc ICC - Fc ICC (mA) 35 ICCS (mA) 10 TA = +25C VCC = 6.0 V VCC = 5.5 V VCC = 5.0 V VCC = 4.5 V VCC = 4.0 V VCC = 3.5 V 30 25 20 VCC = 3.0 V 15 VCC = 2.5 V TA = +25C 7 VCC = 6.0 V VCC = 5.5 V VCC = 5.0 V VCC = 4.5 V VCC = 4.0 V VCC = 3.5 V 6 VCC = 3.0 V 5 VCC = 2.5 V 9 8 4 3 10 2 5 1 4.0 6.0 12.0 8.0 4.0 16.0 Fc (MHz) ICCH (A) 10 TA = +25C 18 8.0 12.0 16.0 Fc (MHz) ICCH - VCC ICCT - VCC ICCT (A) 20 6.0 TA = +25C 9 16 8 14 Fc = 8 kHz 7 12 6 10 5 8 4 6 3 4 2 2 1 3.0 4.0 5.0 6.0 VCC (V) 3.0 ICCT - TA 4.0 5.0 6.0 VCC (V) ICCH - TA ICCT (A) 10 ICCL (A) 10 9 9 8 VCC = 6.0 V VCC = 5.5 V VCC = 5.0 V 7 6 VCC = 4.5 V VCC = 4.0 V VCC = 3.5 V VCC = 3.0 V VCC = 2.5 V 5 4 3 8 6 5 4 3 2 2 1 1 -20 +10 +40 +70 +100 TA (C) VCC = 6.0 V VCC = 5.5 V VCC = 5.0 V VCC = 4.5 V VCC = 4.0 V VCC = 3.5 V VCC = 3.0 V VCC = 2.5 V 7 -20 +10 +40 +70 +100 TA (C) 101 MB90520 Series ICCL - TA ICCLS - TA ICCL (A) 20 VCC = 6.0 V VCC = 5.5 V VCC = 5.0 V VCC = 4.5 V VCC = 4.0 V VCC = 3.5 V VCC = 3.0 V VCC = 2.5 V 18 16 14 12 10 ICCLS (A) 14 VCC = 6.0 V VCC = 5.5 V VCC = 5.0 V 12 10 VCC VCC VCC VCC VCC 8 6 8 6 = 4.5 V = 4.0 V = 3.5 V = 3.0 V = 2.5 V 4 4 2 2 -20 +10 +40 +100 +70 -20 +10 +40 +100 +70 TA (C) TA (C) (2) Power Supply Current (MB90F523) ICCS - VCC ICC - VCC ICC (mA) 140 ICCS (mA) 40 TA = +25C TA = +25C 35 120 Fc = 16 MHz 30 100 80 60 40 Fc = 12.5 MHz Fc = 10 MHz 25 Fc = 8 MHz 20 Fc = 5 MHz Fc = 4 MHz Fc = 2 MHz 15 20 Fc = 16 MHz Fc = 12.5 MHz Fc = 10 MHz Fc = 8 MHz Fc = 5 MHz Fc = 4 MHz Fc = 2 MHz 10 5 3.0 4.0 5.0 3.0 6.0 VCC (V) ICC - TA ICC (mA) 120 4.0 5.0 6.0 VCC (V) ICCS - TA ICCS (mA) 40 VCC = 5.0 V VCC = 5.0 V 35 100 80 60 Fc = 16 MHz 30 Fc = 12.5 MHz 25 Fc = 10 MHz 20 Fc = 16 MHz Fc = 8 MHz 40 Fc = 5 MHz Fc = 4 MHz Fc = 2 MHz 20 -20 +10 +40 +70 +100 TA (C) 102 15 Fc = 12.5 MHz Fc = 10 MHz 10 Fc = 8 MHz 5 Fc = 5 MHz Fc = 4 MHz Fc = 2 MHz -20 +10 +40 +70 +100 TA (C) MB90520 Series ICCS - VCC ICCLS (A) 200 TA = +25C 180 160 Fc = 8 MHz 140 120 100 80 60 40 20 3.0 ICC - Fc ICC (mA) 120 TA = +25C 4.0 5.0 6.0 VCC (V) ICCS - Fc ICCS (mA) 40 TA = +25C 100 VCC = 6.0 V 35 VCC = 5.5 V 30 VCC = 5.0 V 80 VCC = 6.0 V VCC = 5.5 V 25 VCC = 5.0 V VCC = 4.5 V 60 20 VCC = 4.5 V VCC = 3.5 V 15 VCC = 4.0 V VCC = 3.5 V VCC = 3.0 V 10 VCC = 2.5 V 5 VCC = 4.0 V 40 20 4.0 8.0 12.0 VCC = 3.0 V VCC = 2.5 V 16.0 Fc (MHz) 4.0 8.0 12.0 16.0 Fc (MHz) ICCH - VCC ICCT - VCC ICCT (A) 50 ICCH (A) 10 TA = +25C TA = +25C 9 40 8 Fc = 8 kHz 30 7 6 5 20 4 3 10 2 1 3.0 4.0 5.0 6.0 VCC (V) 3.0 4.0 5.0 6.0 VCC (V) 103 MB90520 Series ICCH - TA ICCT - TA ICCH (A) 10 ICCT (A) 10 9 9 8 8 7 7 6 6 5 5 VCC VCC VCC VCC VCC VCC VCC VCC 4 3 2 1 -20 +10 +40 +70 = 6.0 V = 5.5 V = 5.0 V = 4.5 V = 4.0 V = 3.5 V = 3.0 V = 2.5 V 4 3 2 1 +100 -20 +10 ICCLS - TA ICCLS (A) 20 18 16 VCC = 6.0 V 14 VCC = 5.5 V 12 VCC = 5.0 V VCC = 4.5 V VCC = 4.0 V VCC = 3.5 V VCC = 3.0 V VCC = 2.5 V 10 8 6 4 2 +10 +40 +70 +100 TA (C) 104 +70 TA (C) TA (C) -20 +40 VCC = 6.0 V VCC = 5.5 V VCC = 5.0 V VCC = 4.5 V VCC = 4.0 V VCC = 3.5 V VCC = 3.0 V VCC = 2.5 V +100 MB90520 Series INSTRUCTIONS (340 INSTRUCTIONS) Table 1 Description of items in instruction list Item Mnemonic Description English upper case and symbol: Described directly in assembler code. English lower case: Converted in assembler code. Number of letters after English lower case: Describes bit width in code. # Describes number of bytes. ~ Describes number of cycles. m : For branch operation n : For non-branch operation For other letters in other items, refer to table 4. RG B Operation Describes the number of times the register is accessed during instruction execution. Used to calculate a corrective value for CPU intermittent operation. Describes correction value for calculating number of actual cycles (refer to table 5). Number of actual cycles is calculated by adding values in the ~section and section B. Describes operation of instructions. LH Describes a special operation to the upper 8-bit of the lower 16-bit of the accumulator. Z : Transfer 0. X : Sign-extend and transfer. - : No transmission AH Describes a special operation to the upper 16-bit of the accumulator. * : Transmit from AL to AH. - : No transfer. Z : Transfer 00H to AH. X : Sign-extend AL and transfer 00H or FFH to AH. I S T N Describe status of I (interrupt enable), S (stack), T (sticky bit), N (negative), Z (zero), V (overflow), and C (carry) flags. * : Changes after execution of instruction. - : No changes. S : Set after execution of instruction. R : Reset after execution of instruction. Z V C RMW Describes whether or not the instruction is a read-modify-write type (a data is read out from memory etc. in single cycle, and the result is written into memory etc.). * : Read-modify-write instruction - : Not read-modify-write instruction Note: Not used to addresses having different functions for reading and writing operations. * Number of execution cycles The number of cycles required for instruction execution is acquired by adding the number of cycles for each instruction, a corrective value depending on the condition, and the number of cycles required for program fetch. Whenever the instruction being executed exceeds the two-byte (word) boundary, a program on an internal ROM connected to a 16-bit bus is fetched. If data access is interfered with, therefore, the number of execution cycles is increased. For each byte of the instruction being executed, a program on a memory connected to an 8-bit external data bus is fetched. If data access in interfered with, therefore, the number of execution cycles is increased. When a general-purpose register, an internal ROM, an internal RAM, an internal I/O device, or an external bus is accessed during intermittent CPU operation, the CPU clock is suspended by the number of cycles specified by the CG1/0 bit of the low-power consumption mode control register. When determining the number 105 MB90520 Series of cycles required for instruction execution during intermittent CPU operation, therefore, add the value of the number of times access is done x the number of cycles suspended as the corrective value to the number of ordinary execution cycles. Table 2 Description of Symbols in Instruction Table Item A Description 32-bit accumlator The bit length is dependent on the instructions to be used. Byte : Lower 8-bit of AL Word :16-bit of AL Long : AL: 32-bit of AH AH AL Upper 16-bit of A Lower 16-bit of A SP Stack pointer (USP or SSP) PC Program counter PCB Program bank register DTB Data bank register ADB Additional data bank register SSB System stack bank register USB User stack bank register SPB Current stack bank register (SSB or USB) DPR Direct page register brg1 DTB, ADB, SSB, USB, DPR, PCB, SPB brg2 DTB, ADB, SSB, USB, DPR, SPB Ri R0, R1, R2, R3, R4, R5, R6, R7 RWi RW0, RW1, RW2, RW3, RW4, RW5, RW6, RW7 RWj RW0, RW1, RW2, RW3 RLi RL0, RL1, RL2, RL3 dir Specify shortened direct address. addr16 addr24 ad24 0 to 15 ad24 16 to 23 Specify direct address. Specify physical direct address. bit0 to bit15 of addr24 bit16 to bit 23 of addr24 io I/O area (000000H to 0000FFH) #imm4 #imm8 #imm16 #imm32 ext (imm8) disp8 disp16 bp 4-bit immediate data 8-bit immediate data 16-bit immediate data 32-bit immediate data 16-bit data calculated by sign-extending an 8-bit immediate data 8-bit displacement 16-bit displacement Bit offset value (Continued) 106 MB90520 Series (Continued) Item Description vct4 vct8 Vector number (0 to 15) Vector number (0 to 255) ( )b Bit address rel Specify PC relative branch. ear eam Specify effective address (code 00 to 07). Specify effective address (code 08 to 1F). rlst Register allocation Table 3 Code 00 01 02 03 04 05 06 07 Symbol R0 R1 R2 R3 R4 R5 R6 R7 RW0 RW1 RW2 RW3 RW4 RW5 RW6 RW7 Effective Address Field Address type RL0 (RL0) RL1 (RL1) RL2 (RL2) RL3 (RL3) Number of bytes in address extension block Register direct ea corresponds to byte, word, and long word from left respectively. -- Register indirect 08 09 0A 0B @RW0 @RW1 @RW2 @RW3 0C 0D 0E 0F @RW0 + @RW1 + @RW2 + @RW3 + 10 11 12 13 14 15 16 17 @RW0 + disp8 @RW1 + disp8 @RW2 + disp8 @RW3 + disp8 @RW4 + disp8 @RW5 + disp8 @RW6 + disp8 @RW7 + disp8 Register indirect with 8-bit displacement 18 19 1A 1B @RW0 + disp16 @RW1 + disp16 @RW2 + disp16 @RW3 + disp16 Register indirect with 16-bit displacement 1C 1D 1E 1F @RW0 + RW7 @RW1 + RW7 @PC + disp16 addr16 0 Register indirect with post increment 0 1 Register indirect with index Register indirect with index PC indirect with 16-bit displacement Direct address 2 0 0 2 2 Note: Number of bytes for address extension corresponds to "+" in the # (number of bytes) the number of bytes in detailed instruction rules part in the instruction table. 107 MB90520 Series Table 4 Number of Execution Cycles for Effective Address in Addressing Modes (a) Number of execution cycles for addressing modes Number of register accesses for addressing modes Ri RWi RLi Listed in instruction table Listed in instruction table 08 to 0B @RWj 2 1 0C to 0F @RWj + 4 2 10 to 17 @RWi + disp8 2 1 18 to 1B @RWj + disp16 2 1 1C 1D 1E 1F @RW0 + RW7 @RW1 + RW7 @PC + disp16 addr16 4 4 2 1 2 2 0 0 Code Operand 00 to 07 Note: (a) is used for ~ (number of cycles) and B (correction value) detailed instruction rules in instruction table. Table 5 Correction Value for Number of Cycles for Calculating Actual Number of Cycles (b) byte Operand (c) word (d) long Number of Number of Number of Number of Number of Number of cycles access cycles access cycles access Internal register +0 1 +0 1 +0 2 Internal memory even address Internal memory odd address +0 +0 1 1 +0 +2 1 2 +0 +4 2 4 External data bus 16-bit even address External data bus 16-bit odd address +1 +1 1 1 +1 +4 1 2 +2 +8 2 4 External data bus 8-bit +1 1 +4 2 +8 4 Notes: * (b), (c), (d) is used for ~ (number of cycles) and B (correction value) in instruction table. * When the external bus is used, cycles for wait insertion for the ready input and automatic ready operation must be added. Table 6 Correction Value for Number of Cycles for Calculating Number of Program Fetch Cycles Instruction Byte boundary Word boundary Internal memory -- +2 External data bus 16-bit -- +3 External data bus 8-bit +3 -- Notes: * When the external bus is used, cycles for wait insertion for the ready input and automatic ready operation must be added. * Because execution of instruction is not delayed for all program fetch operations, use this value to calculate the worst case. 108 MB90520 Series Table 7 Mnemonic # Transmission Instruction (Byte) [41 Instructions] ~ RG B Operation MOV MOV MOV MOV MOV MOV MOV MOV MOV MOVN 3 2 A, dir 4 3 A, addr16 2 1 A, Ri 2 2 A, ear 2 + 3 + (a) A, eam 3 2 A, io 2 2 A, #imm8 3 2 A, @A 10 A, @RLi + disp8 3 1 1 A, #imm4 0 0 1 1 0 0 0 0 2 0 (b) (b) 0 0 (b) (b) 0 (b) (b) 0 byte (A) (dir) byte (A) (addr16) byte (A) (Ri) byte (A) (ear) byte (A) (eam) byte (A) (io) byte (A) imm8 byte (A) ((A)) byte (A) ((RLi) + disp8) byte (A) imm4 MOVX MOVX MOVX MOVX MOVX MOVX MOVX MOVX MOVX MOVX 3 2 A, dir 4 3 A, addr16 2 2 A, Ri 2 2 A, ear 2 + 3 + (a) A, eam 3 2 A, io 2 2 A, #imm8 3 2 A, @A 5 A, @RWi + disp8 2 10 A, @RLi + disp8 3 0 0 1 1 0 0 0 0 1 2 byte (A) (dir) byte (A) (addr16) byte (A) (Ri) byte (A) (ear) byte (A) (eam) byte (A) (io) byte (A) imm8 byte (A) ((A)) MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV /MOV dir, A addr16, A Ri, A ear, A eam, A io, A @RLi + disp8, A Ri, ear Ri, eam ear, Ri eam, Ri Ri, #imm8 io, #imm8 dir, #imm8 ear, #imm8 eam, #imm8 @AL, AH @A, T 2 3 1 2 2+ 2 3 2 2+ 2 2+ 2 3 3 3 3+ 3 4 2 2 3 + (a) 3 10 3 4 + (a) 4 5 + (a) 2 5 5 2 4 + (a) 2 3 XCH XCH XCH XCH A, ear A, eam Ri, ear Ri, eam 4 2 2 + 5 + (a) 7 2 2 + 9 + (a) LH AH I S T N Z V C RMW Z Z Z Z Z Z Z Z Z Z * * * * * * * - * * - - - - - - - - - - - - - - - - - - - - - * - * - * - * - * - * - * - * - * - R * * * * * * * * * * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - (b) (b) 0 0 (b) (b) 0 (b) (b) (b) X X X X X X X X byte (A) ((RWi) + disp8) X byte (A) ((RLi) + disp8) X * * * * * * * - * * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * * * * * * * * * * * * * * * * * * * * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 0 1 1 0 0 2 2 1 2 1 1 0 0 1 0 (b) (b) 0 0 (b) (b) (b) 0 (b) 0 (b) 0 (b) (b) 0 (b) byte (dir) (A) byte (addr16) (A) byte (Ri) (A) byte (ear) (A) byte (eam) (A) byte (io) (A) byte ((RLi) + disp8) (A) byte (Ri) (ear) byte (Ri) (eam) byte (ear) (Ri) byte (eam) (Ri) byte (Ri) imm8 byte (io) imm8 byte (dir) imm8 byte (ear) imm8 byte (eam) imm8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * * * * * * * * * * * * - - * - * * * * * * * * * * * * - - * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 (b) byte ((A)) (AH) - - - - - * * - - - byte (A) (ear) byte (A) (eam) byte (Ri) (ear) byte (Ri) (eam) Z Z - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 2 0 2 x (b) 0 4 2 2 x (b) Note: For (a) to (d), refer to "Table 4 Number of Execution Cycles for Effective Address in Addressing Modes" and "Table 5 Correction Values for Number of Cycles for Calculating Actual Number of Cycles." 109 MB90520 Series Table 8 Mnemonic MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW # ~ RG B 3 2 4 3 1 1 2 1 2 2 2 + 3 + (a) 3 2 3 2 2 3 A, @RWi + disp8 5 2 A, @RLi + disp8 10 3 0 0 0 1 1 0 0 0 0 1 2 (c) (c) 0 0 0 (c) (c) (c) 0 (c) (c) word (A) (dir) word (A) (addr16) word (A) (SP) word (A) (RWi) word (A) (ear) word (A) (eam) word (A) (io) word (A) ((A)) word (A) imm16 - - - - - - - - - word (A) ((RWi) +disp8) - word (A) ((RLi) +disp8) - 3 4 1 2 2 3 + (a) 3 5 10 3 4 + (a) 4 5 + (a) 2 5 2 4 + (a) 0 0 0 1 1 0 0 1 2 2 1 2 1 1 0 1 0 (c) (c) 0 0 0 (c) (c) (c) (c) 0 (c) 0 (c) 0 (c) 0 (c) word (dir) (A) word (addr16) (A) word (SP) (A) word (RWi) (A) word (ear) (A) word (eam) (A) word (io) (A) 3 0 (c) 2 0 4 2 0 2 x (c) 0 2 x (c) A, dir A, addr16 A, SP A, RWi A, ear A, eam A, io A, @A A, #imm16 2 3 1 1 2 2+ 2 MOVW @RWi + disp8, A 2 MOVW @RLi + disp8, A 3 2 MOVW RWi, ear 2+ MOVW RWi, eam 2 MOVW ear, RWi 2+ MOVW eam, RWi 3 MOVW RWi, #imm16 4 MOVW io, #imm16 4 MOVW ear, #imm16 MOVW eam, #imm16 4 + MOVW MOVW MOVW MOVW MOVW MOVW MOVW Transmission Instruction (Word, Long) [38 Instructions] dir, A addr16, A SP, A RWi, A ear, A eam, A io, A MOVW @AL, AH /MOVW @A, T 2 Operation I S T N Z V C * * * * * * * - * * * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * * * * * * * * * * * * * * * * * * * * * * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - word ((RWi) +disp8) (A) - word ((RLi) +disp8) (A) - - word (RWi) (ear) - word (RWi) (eam) - word (ear) (RWi) - word (eam) (RWi) - word (RWi) imm16 - word (io) imm16 - word (ear) imm16 - word (eam) imm16 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * * * * * * * * * * * * * * - * - * * * * * * * * * * * * * * - * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - word ((A)) (AH) - - - - - * * - - - word (A) (ear) word (A) (eam) word (RWi) (ear) word (RWi) (eam) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - LH AH RMW XCHW XCHW XCHW XCHW A, ear A, eam RWi, ear RWi, eam 4 2 2 + 5 + (a) 7 2 2 + 9 + (a) MOVL MOVL MOVL A, ear A, eam A, #imm32 2 4 2 2 + 5 + (a) 0 0 3 5 0 (d) 0 long (A) (ear) long (A) (eam) long (A) imm32 - - - - - - - - - - - - - - - * * * * * * - - - - - - - - - MOVL MOVL ear, A eam, A 2 4 2 2 + 5 + (a) 0 0 (d) long (ear1) (A) long (eam1) (A) - - - - - - - - - - * * * * - - - - - - Note: For (a) to (d), refer to "Table 4 Number of Execution Cycles for Effective Address in Addressing Modes" and "Table 5 Correction Values for Number of Cycles for Calculating Actual Number of Cycles." 110 MB90520 Series Table 9 Mnemonic Add/Subtract (Byte, Word, Long) [42 Instructions] # ~ A,#imm8 A, dir A, ear A, eam ear, A eam, A A A, ear A, eam A A, #imm8 A, dir A, ear A, eam ear, A eam, A A A, ear A, eam A 2 2 2 2+ 2 2+ 1 2 2+ 1 2 2 2 2+ 2 2+ 1 2 2+ 1 2 5 3 4 + (a) 3 5 + (a) 2 3 4 + (a) 3 2 5 3 4 + (a) 3 5 + (a) 2 3 4 + (a) 3 0 0 (b) 0 0 1 (b) 0 0 2 0 2 x (b) 0 0 0 1 (b) 0 0 0 0 0 (b) 0 0 1 (b) 0 0 2 0 2 x (b) 0 0 0 1 (b) 0 0 0 byte (A) (A) +imm8 byte (A) (A) +(dir) byte (A) (A) +(ear) byte (A) (A) +(eam) byte (ear) (ear) + (A) byte (eam) (eam) + (A) byte (A) (AH) + (AL) + (C) byte (A) (A) + (ear) + (C) byte (A) (A) + (eam) + (C) ADDW A ADDW A, ear ADDW A, eam ADDW A, #imm16 ADDW ear, A ADDW eam, A ADDCW A, ear ADDCW A, eam SUBW A SUBW A, ear SUBW A, eam SUBW A, #imm16 SUBW ear, A SUBW eam, A SUBCW A, ear SUBCW A, eam 1 2 2+ 3 2 2+ 2 2+ 1 2 2+ 3 2 2+ 2 2+ 2 3 4 + (a) 2 3 5 + (a) 3 4 + (a) 2 3 4 + (a) 2 3 5 + (a) 3 4 + (a) 0 0 0 1 (c) 0 0 0 0 2 0 2 x (c) 0 1 (c) 0 0 0 0 1 (c) 0 0 0 0 2 0 2 x (c) 0 1 (c) 0 ADD ADD ADD ADD ADD ADD ADDC ADDC ADDC ADDDC SUB SUB SUB SUB SUB SUB SUBC SUBC SUBC SUBDC ADDL ADDL ADDL SUBL SUBL SUBL A, ear A, eam 6 2 2 + 7 + (a) A, #imm32 5 4 6 2 A, ear 2 + 7 + (a) A, eam 4 A, #imm32 5 RG 2 0 0 2 0 0 B 0 (d) 0 0 (d) 0 Operation LH AH I S T N Z V C RMW byte (A) (AH) - (AL) - (C) (decimal) Z Z Z Z - Z Z Z Z Z Z Z Z Z - - Z Z Z Z - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * - - - - - * - - - - - - - - - * - - - - word (A) (AH) + (AL) word (A) (A) + (ear) word (A) (A) + (eam) word (A) (A) + imm16 word (ear) (ear) + (A) word (eam) (eam) + (A) word (A) (A) + (ear) + (C) word (A) (A) + (eam) + (C) word (A) (AH) - (AL) word (A) (A) - (ear) word (A) (A) - (eam) word (A) (A) - imm16 word (ear) (ear) - (A) word (eam) (eam) - (A) word (A) (A) - (ear) - (C) word (A) (A) - (eam) - (C) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * - - - - - * - - - - - - - * - - long (A) (A) + (ear) long (A) (A) + (eam) long (A) (A) + imm32 long (A) (A) - (ear) long (A) (A) - (eam) long (A) (A) - imm32 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * * * * * * * * * * * * * * * * * * * * * * * * - - - - - - byte (A) (AH) + (AL) + (C) (decimal) byte (A) (A) - imm8 byte (A) (A) - (dir) byte (A) (A) - (ear) byte (A) (A) - (eam) byte (ear) (ear) - (A) byte (eam) (eam) - (A) byte (A) (AH) - (AL) - (C) byte (A) (A) - (ear) - (C) byte (A) (A) - (eam) - (C) Note: For (a) to (d), refer to "Table 4 Number of Execution Cycles for Effective Address in Addressing Modes" and "Table 5 Correction Values for Number of Cycles for Calculating Actual Number of Cycles." 111 MB90520 Series Table 10 Mnemonic # Increment/Decrement (Byte, Word, Long) [12 Instructions] ~ RG B Operation LH AH I S T N Z V C RMW INC INC ear eam 2 2 2 0 byte (ear) (ear) +1 2 + 5 + (a) 0 2 x (b) byte (eam) (eam) +1 - - - - - - - - - - * * * * * * - - - * DEC DEC ear eam 2 3 2 0 byte (ear) (ear) -1 2 + 5 + (a) 0 2 x (b) byte (eam) (eam) -1 - - - - - - - - - - * * * * * * - - - * INCW INCW ear eam word (ear) (ear) +1 0 2 3 2 2 + 5 + (a) 0 2 x (c) word (eam) (eam) +1 - - - - - - - - - - * * * * * * - - - * DECW ear DECW eam word (ear) (ear) -1 0 2 3 2 2 + 5 + (a) 0 2 x (c) word (eam) (eam) -1 - - - - - - - - - - * * * * * * - - - * INCL INCL ear eam long (ear) (ear) +1 0 4 7 2 2 + 9 + (a) 0 2 x (d) long (eam) (eam) +1 - - - - - - - - - - * * * * * * - - - * DECL DECL ear eam long (ear) (ear) -1 0 4 7 2 2 + 9 + (a) 0 2 x (d) long (eam) (eam) -1 - - - - - - - - - - * * * * * * - - - * Note: For (a) to (d), refer to "Table 4 Number of Execution Cycles for Effective Address in Addressing Modes" and "Table 5 Correction Values for Number of Cycles for Calculating Actual Number of Cycles." Table 11 Mnemonic # ~ Compare (Byte, Word, Long) [11 Instructions] RG B Operation LH AH I S T N Z V C RMW CMP CMP CMP CMP A A, ear A, eam A, #imm8 1 1 2 2 2 + 3 + (a) 2 2 0 1 0 0 0 0 (b) 0 byte (AH) - (AL) byte (A) - (ear) byte (A) - (eam) byte (A) - imm8 - - - - - - - - - - - - - - - - - - - - * * * * * * * * * * * * * * * * - - - - CMPW CMPW CMPW CMPW 1 1 A 2 2 A, ear 2 + 3 + (a) A, eam 2 A, #imm16 3 0 1 0 0 0 0 (c) 0 word (AH) - (AL) word (A) - (ear) word (A) - (eam) word (A) - imm16 - - - - - - - - - - - - - - - - - - - - * * * * * * * * * * * * * * * * - - - - CMPL CMPL CMPL 2 6 2 A, ear A, eam 2 + 7 + (a) 0 A, #imm32 5 3 0 0 (d) 0 word (A) - (ear) word (A) - (eam) word (A) - imm32 - - - - - - - - - - - - - - - * * * * * * * * * * * * - - - Note: For (a) to (d), refer to "Table 4 Number of Execution Cycles for Effective Address in Addressing Modes" and "Table 5 Correction Values for Number of Cycles for Calculating Actual Number of Cycles." 112 MB90520 Series Table 12 Mnemonic # ~ Unsigned Multiply/Division (Word, Long) [11 Instructions] RG B DIVU A 1 *1 0 DIVU A, ear 2 *2 1 DIVU A, eam 2 + *3 0 DIVUW A, ear 2 *4 1 DIVUW A, eam 2+ *5 0 MULU MULU MULU MULUW MULUW MULUW A 1 A, ear 2 A, eam 2 + A 1 A, ear 2 A, eam 2 + *8 *9 *10 *11 *12 *13 0 1 0 0 1 0 Operation 0 word (AH) /byte (AL) Quotient byte (AL) Remainder byte (AH) 0 word (A)/byte (ear) Quotient byte (A) Remainder byte (ear) *6 word (A)/byte (eam) Quotient byte (A) Remainder byte (eam) 0 long (A)/word (ear) Quotient word (A) Remainder word (ear) *7 long (A)/word (eam) Quotient word (A) Remainder word (eam) 0 0 (b) 0 0 (c) byte (AH) *byte (AL) word (A) byte (A) *byte (ear) word (A) byte (A) *byte (eam) word (A) word (AH) *word (AL) long (A) word (A) *word (ear) long (A) word (A) *word (eam) long (A) LH AH I S T N Z V C RMW - - - - - - - * * - - - - - - - - * * - - - - - - - - * * - - - - - - - - * * - - - - - - - - * * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - *1: Set to 3 when the division-by-0, 7 for an overflow, and 15 for normal operation. *2: Set to 4 when the division-by-0, 8 for an overflow, and 16 for normal operation. *3: Set to 6 + (a) when the division-by-0, 9 + (a) for an overflow, and 19 + (a) for normal operation. *4: Set to 4 when the division-by-0, 7 for an overflow, and 22 for normal operation. *5: Set to 6 + (a) when the division-by-0, 8 + (a) for an overflow, and 26 + (a) for normal operation. *6: When the division-by-0, (b) for an overflow, and 2 x (b) for normal operation. *7: When the division-by-0, (c) for an overflow, and 2 x (c) for normal operation. *8: Set to 3 when byte (AH) is zero, 7 when byte (AH) is not zero. *9: Set to 4 when byte (ear) is zero, 8 when byte (ear) is not zero. *10: Set to 5 + (a) when byte (eam) is zero, 9 + (a) when byte (eam) is not zero. *11: Set to 3 when word (AH) is zero, 11 when word (AH) is not zero. *12: Set to 4 when word (ear) is zero, 12 when word (ear) is not zero. *13: Set to 5 + (a) when word (eam) is zero, 13 + (a) when word (eam) is not zero. Note: For (a) to (d), refer to "Table 4 Number of Execution Cycles for Effective Address in Addressing Modes" and "Table 5 Correction Values for Number of Cycles for Calculating Actual Number of Cycles." 113 MB90520 Series Table 13 Mnemonic # ~ Signed Multiplication/Division (Word, Long) [11 Instructions] RG B DIV A 2 *1 0 DIV A, ear 2 *2 1 DIV A, eam 2 + *3 0 DIVW A, ear 2 *4 1 DIVW A, eam 2+ *5 0 MULU MULU MULU MULUW MULUW MULUW A 2 A, ear 2 A, eam 2 + A 2 A, ear 2 A, eam 2 + *8 *9 *10 *11 *12 *13 0 1 0 0 1 0 Operation 0 word (AH) /byte (AL) Quotient byte (AL) Remainder byte (AH) 0 word (A)/byte (ear) Quotient byte (A) Remainder byte (ear) *6 word (A)/byte (eam) Quotient byte (A) Remainder byte (eam) 0 long (A)/word (ear) Quotient word (A) Remainder word (ear) *7 long (A)/word (eam) Quotient word (A) Remainder word (eam) 0 0 (b) 0 0 (c) byte (AH) *byte (AL) word (A) byte (A) *byte (ear) word (A) byte (A) *byte (eam) word (A) word (AH) *word (AL) long (A) word (A) *word (ear) long (A) word (A) *word (eam) long (A) LH AH I S T N Z V C RMW Z - - - - - - * * - Z - - - - - - * * - Z - - - - - - * * - - - - - - - - * * - - - - - - - - * * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - *1: *2: *3: *4: Set to 3 when the division-by-0, 8 or 18 for an overflow, and 18 for normal operation. Set to 3 when the division-by-0, 10 or 21 for an overflow, and 22 for normal operation. Set to 4 + (a) when the division-by-0, 11 + (a) or 22 + (a) for an overflow, and 23 + (a) for normal operation. Positive dividend: Set to 4 when the division-by-0, 10 or 29 for an overflow, and 30 for normal operation. Negative dividend: Set to 4 when the division-by-0, 11 or 30 for an overflow and 31 for normal operation. *5: Positive dividend: Set to 4 + (a) when the division-by-0, 11 + (a) or 30 + (a) for an overflow, and 31 + (a) for normal operation. Negative dividend: Set to 4 + (a) when the division-by-0, 12 + (a) or 31 + (a) for an overflow, and 32 + (a) for normal operation. *6: When the division-by-0, (b) for an overflow, and 2 x (b) for normal operation. *7: When the division-by-0, (c) for an overflow, and 2 x (c) for normal operation. *8: Set to 3 when byte (AH) is zero, 12 when the result is positive, and 13 when the result is negative. *9: Set to 3 when byte (ear) is zero, 12 when the result is positive, and 13 when the result is negative. *10: Set to 4 + (a) when byte (eam) is zero, 13 + (a) when the result is positive, and 14 + (a) when the result is negative. *11: Set to 3 when word (AH) is zero, 12 when the result is positive, and 13 when the result is negative. *12: Set to 3 when word (ear) is zero, 16 when the result is positive, and 19 when the result is negative. *13: Set to 4 + (a) when word (eam) is zero, 17 + (a) when the result is positive, and 20 + (a) when the result is negative. Notes: * When overflow occurs during DIV or DIVW instruction execution, the number of execution cycles takes two values because of detection before and after an operation. * When overflow occurs during DIV or DIVW instruction execution, the contents of AL are destroyed. * For (a) to (d), refer to "Table 4 Number of Execution Cycles for Effective Address in Addressing Modes" and "Table 5 Correction Values for Number of Cycles for Calculating Actual Number of Cycles." 114 MB90520 Series Table 14 Mnemonic # ~ RG Logic 1 (Byte, Word) [39 Instructions] B Operation LH AH I S T N Z V C RMW AND AND AND AND AND A, #imm8 A, ear A, eam ear, A eam, A 2 2 3 2 2 + 4 + (a) 3 2 2 + 5 + (a) 0 0 0 1 (b) 0 0 2 0 2 x (b) byte (A) (A) and imm8 byte (A) (A) and (ear) byte (A) (A) and (eam) byte (ear) (ear) and (A) byte (eam) (eam) and (A) - - - - - - - - - - - - - - - - - - - - - - - - - * * * * * * * * * * R R R R R - - - - - - - - - * OR OR OR OR OR A, #imm8 A, ear A, eam ear, A eam, A 2 2 3 2 2 + 4 + (a) 3 2 2 + 5 + (a) 0 0 0 1 (b) 0 0 2 0 2 x (b) byte (A) (A) or imm8 byte (A) (A) or (ear) byte (A) (A) or (eam) byte (ear) (ear) or (A) byte (eam) (eam) or (A) - - - - - - - - - - - - - - - - - - - - - - - - - * * * * * * * * * * R R R R R - - - - - - - - - * XOR XOR XOR XOR XOR NOT NOT NOT A, #imm8 A, ear A, eam ear, A eam, A A ear eam 2 2 3 2 2 + 4 + (a) 3 2 2 + 5 + (a) 2 1 3 2 2 + 5 + (a) 0 0 0 1 (b) 0 0 2 0 2 x (b) 0 0 0 2 0 2 x (b) byte (A) (A) xor imm8 byte (A) (A) xor (ear) byte (A) (A) xor (eam) byte (ear) (ear) xor (A) byte (eam) (eam) xor (A) byte (A) not (A) byte (ear) not (ear) byte (eam) not (eam) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * * * * * * * * * * * * * * * * R R R R R R R R - - - - - - - - - - - - * - - * ANDW ANDW ANDW ANDW ANDW ANDW 2 1 A 2 A, #imm16 3 3 2 A, ear 2 + 4 + (a) A, eam 3 2 ear, A 2 + 5 + (a) eam, A 0 0 1 0 2 0 0 0 0 (c) 0 2 x (c) word (A) (AH) and (A) word (A) (A) and imm16 word (A) (A) and (ear) word (A) (A) and (eam) word (ear) (ear) and (A) word (eam) (eam) and (A) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * * * * * * * * * * * * R R R R R R - - - - - - - - - - - * ORW ORW ORW ORW ORW ORW 2 1 A 2 A, #imm16 3 3 2 A, ear 2 + 4 + (a) A, eam 3 2 ear, A 2 + 5 + (a) eam, A 0 0 1 0 2 0 0 0 0 (c) 0 2 x (c) word (A) (AH) or (A) word (A) (A) or imm16 word (A) (A) or (ear) word (A) (A) or (eam) word (ear) (ear) or (A) word (eam) (eam) or (A) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * * * * * * * * * * * * R R R R R R - - - - - - - - - - - * XORW XORW XORW XORW XORW XORW NOTW NOTW NOTW 2 1 A 2 A, #imm16 3 3 2 A, ear 2 + 4 + (a) A, eam 3 2 ear, A 2 + 5 + (a) eam, A 2 1 A 3 2 ear 2 + 5 + (a) eam 0 0 1 0 2 0 0 2 0 0 0 0 (c) 0 2 x (c) 0 0 2 x (c) word (A) (AH) xor (A) word (A) (A) xor imm16 word (A) (A) xor (ear) word (A) (A) xor (eam) word (ear) (ear) xor (A) word (eam) (eam) xor (A) word (A) not (A) word (ear) not (ear) word (eam) not (eam) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * * * * * * * * * * * * * * * * * * R R R R R R R R R - - - - - - - - - - - - - - * - - * Note: For (a) to (d), refer to "Table 4 Number of Execution Cycles for Effective Address in Addressing Modes" and "Table 5 Correction Values for Number of Cycles for Calculating Actual Number of Cycles." 115 MB90520 Series Table 15 Mnemonic # ~ RG Logic 2 (Long) [6 Instructions] B Operation LH AH I S T N Z V C RMW ANDL ANDL A, ear A, eam 2 6 2 2 + 7 + (a) 0 0 (d) long (A) (A) and (ear) long (A) (A) and (eam) - - - - - - - - - - * * * * R R - - - - ORL ORL A, ear A, eam 2 6 2 2 + 7 + (a) 0 0 (d) long (A) (A) or (ear) long (A) (A) or (eam) - - - - - - - - - - * * * * R R - - - - XORL XORL A, ear A, eam 2 6 2 2 + 7 + (a) 0 0 (d) long (A) (A) xor (ear) long (A) (A) xor (eam) - - - - - - - - - - * * * * R R - - - - Table 16 Mnemonic NEG A NEG NEG ear eam Mnemonic NRML A, R0 # ~ RG B Operation LH AH I S T N Z V C RMW 1 2 0 0 byte (A) 0 - (A) X - - - - * * * * - - - - - - - - - - - * * * * * * * * - * word (A) 0 - (A) - - - - - * * * * - word (ear) 0 - (ear) 0 2 x (c) word (eam) 0 - (eam) - - - - - - - - - - * * * * * * * * - * 2 3 2 0 byte (ear) 0 - (ear) 2 + 5 + (a) 0 2 x (b) byte (eam) 0 - (eam) 0 0 2 1 NEGW A NEGW ear NEGW eam Sign Reverse (Byte, Word) [6 Instructions] 2 3 2 2 + 5 + (a) 0 Table 17 Normalize Instruction (Long) [1 Instruction] # ~ RG B Operation 2 *1 1 0 long (A) Shift to where "1" is originally located byte (R0) Number of shifts in the operation LH AH - - I S T N Z V C RMW - - - - * - - - *1: Set to 4 when the accumulator is all "0", otherwise set to 6 + (R0). Note: For (a) to (d), refer to "Table 4 Number of Execution Cycles for Effective Address in Addressing Modes" and "Table 5 Correction Values for Number of Cycles for Calculating Actual Number of Cycles." 116 MB90520 Series Table 18 Mnemonic RORC A ROLC A Shift Type Instruction (Byte, Word, Long) [18 Instructions] # ~ RG B 2 2 2 2 0 0 0 0 3 Operation LH AH I S T N Z V C RMW byte (A) With right-rotate carry byte (A) With left-rotate carry - - - - - - - - - - * * * * - - * * - - 2 0 0 2 x (b) 2 0 0 2 x (b) byte (ear) With right-rotate carry byte (eam) With right-rotate carry byte (ear) With left-rotate carry byte (eam) With left-rotate carry - - - - - - - - - - - - - - - - - - - - * * * * * * * * - - - - * * * * - * - * RORC RORC ROLC ROLC ear eam ear eam 2 2+ 2 2+ ASR LSR LSL A, R0 A, R0 A, R0 2 2 2 *1 *1 *1 1 1 1 0 0 0 byte (A) Arithmetic right barrel shift (A, R0) byte (A) Logical right barrel shift (A, R0) byte (A) Logical left barrel shift (A, R0) - - - - - - - - - - - - * * - * * * * * * - - - * * * - - - ASRW A 1 LSRW A/SHRW A 1 LSLW A/SHLW A 1 2 2 2 0 0 0 0 0 0 word (A) Arithmetic right shift (A, 1 bit) word (A) Logical right shift (A, 1 bit) word (A) Logical left shift (A, 1 bit) - - - - - - - - - - - - * * * R - * * * * - - - * * * - - - ASRW A, R0 LSRW A, R0 LSLW A, R0 2 2 2 *1 *1 *1 1 1 1 0 0 0 word (A) Arithmetic right barrel shift (A, R0) word (A) Logical right barrel shift (A, R0) word (A) Logical left barrel shift (A, R0) - - - - - - - - - - - - * * - * * * * * * - - - * * * - - - ASRL A, R0 LSRL A, R0 LSLL A, R0 2 2 2 *2 *2 *2 1 1 1 0 0 0 long (A) Arithmetic right barrel shift (A, R0) long (A) Logical right barrel shift (A, R0) long (A) Logical left barrel shift (A, R0) - - - - - - - - - - - - * * - * * * * * * - - - * * * - - - 5 + (a) 3 5 + (a) *1: Set to 6 when R0 is 0, otherwise 5 + (R0). *2: Set to 6 when R0 is 0, otherwise 6 + (R0). Note: For (a) to (d), refer to "Table 4 Number of Execution Cycles for Effective Address in Addressing Modes" and "Table 5 Correction Values for Number of Cycles for Calculating Actual Number of Cycles." 117 MB90520 Series Table 19 Mnemonic BZ/BEQ rel BNZ/BNE rel BC/BLO rel BNC/BHS rel BN rel BP rel BV rel BNV rel BT rel BNT rel BLT rel BGE rel BLE rel BGT rel BLS rel BHI rel BRA rel # ~ RG B 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JMP JMP JMP JMP JMPP JMPP JMPP @A addr16 @ear @eam @ear *3 @eam *3 addr24 2 1 3 3 3 2 2 + 4 + (a) 5 2 2 + 6 + (a) 4 4 0 0 1 0 2 0 0 0 0 0 (c) 0 (d) 0 CALL CALL CALL CALLV CALLP @ear *4 6 2 @eam *4 2 + 7 + (a) addr16 *5 3 6 7 1 #vct4 *5 10 2 @ear *6 1 0 0 0 2 (c) 2 x (c) (c) 2 x (c) 2 x (c) CALLP @eam *6 CALLP addr24 *7 *1: *2: *3: *4: *5: *6: *7: 2 + 11 + (a) 0 4 10 0 *2 2 x (c) Branch 1 [31 Instructions] Operation Branch if (Z) = 1 Branch if (Z) = 0 Branch if (C) = 1 Branch if (C) = 0 Branch if (N) = 1 Branch if (N) = 0 Branch if (V) = 1 Branch if (V) = 0 Branch if (T) = 1 Branch if (T) = 0 Branch if (V) xor (N) = 1 Branch if (V) xor (N) = 0 Branch if ((V) xor (N)) or (Z) = 1 Branch if ((V) xor (N)) or (Z) = 0 Branch if (C) or (Z) = 1 Branch if (C) or (Z) = 0 Branch unconditionally word (PC) (A) word (PC) addr16 word (PC) (ear) word (PC) (eam) word (PC) (ear), (PCB) (ear + 2) word (PC) (eam), (PCB) (eam + 2) word (PC) ad24 0 - 15, (PCB) ad24 16 - 23 word (PC) (ear) word (PC) (eam) word (PC) addr16 Vector call instruction word (PC) (ear) 0 - 15 (PCB) (ear) 16 - 23 word (PC) (eam) 0 - 15 (PCB) (eam) 16 - 23 word (PC) ad24 0 - 15, (PCB) ad24 16 - 23 LH AH I S T N Z V C RMW - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Set to 4 when branch is executed, and 3 when branch is not executed. (b) + 3 x (c) Reads (word) of the branch destination address. W pushes to stack (word), and R reads (word) of the branch destination address. Pushes to stack (word). W pushes to stack (long), and R reads (long) of the branch destination address. Pushes to stack (long). Note: For (a) to (d), refer to "Table 4 Number of Execution Cycles for Effective Address in Addressing Modes" and "Table 5 Correction Values for Number of Cycles for Calculating Actual Number of Cycles." 118 MB90520 Series Table 20 Mnemonic CBNE A, #imm8, rel CWBNE A, #imm16, rel # ~ RG 3 *1 4 *1 4 4+ CWBNE ear, #imm16, rel 5 CWBNE eam, #imm16, rel*10 5 + B eam, rel 3 + *6 DWBNZ ear, rel 3 *5 DWBNZ eam, rel 3 + *6 Z V C RMW - - * * * * * * * * - - Branch if byte (ear) imm8 Branch if byte (eam) imm8 Branch if word (ear) imm16 Branch if word (eam) imm16 - - - - - - - - - - - - - - - - - - - - * * * * * * * * * * * * * * * * - - - - byte (ear) = (ear) - 1, Branch if (ear) 0 2 2 x (b) byte (eam) = (eam) - 1, Branch if (eam) 0 - - - - - * * * - - - - - - - * * * - * word (ear) = (ear) - 1, Branch if (ear) 0 2 2 x (c) word (eam) = (eam) - 1, Branch if (eam) 0 - - - - - * * * - - - - - - - * * * - * Software interrupt Software interrupt Software interrupt Software interrupt Return from interrupt - - - - - - - - - - R R R R * S S S S * - - - - * - - - - * - - - - * - - - - * - - - - * - - - - - Stores old frame pointer in the beginning of the function, set new frame pointer, and reserves local pointer area Restore old frame pointer from stack in the end of the function - - - - - - - - - - - - - - - - - - - - Return from subroutine Return from subroutine - - - - - - - - - - - - - - - - - - - - 0 DBNZ N - - 2 3 *5 T - - 0 (b) 0 (c) ear, rel S - - 1 0 1 0 DBNZ I - - *2 *3 *4 *3 ear, #imm8, rel eam, #imm8, rel*10 LH AH Branch if byte (A) imm8 0 0 CBNE Operation Branch if word (A) imm16 0 0 CBNE Branch 2 (Byte) [19 Instructions] 2 0 INT INT INTP INT9 RETI #vct8 addr16 addr24 2 3 4 1 1 20 16 17 20 17 0 0 0 0 0 8 x (c) 6 x (c) 6 x (c) 8 x (c) *7 LINK #imm8 2 6 0 (c) UNLINK 1 5 0 (c) RET *8 RETP *9 1 1 4 6 0 0 (c) (d) *1: Set to 5 when branch is executed, and 4 when branch is not executed. *2: Set to 13 when branch is executed, and 12 when branch is not executed. *3: Set to 7 + (a) when branch is executed, and 6 + (a) when branch is not executed. *4: Set to 8 when branch is executed, and 7 when branch is not executed. *5: Set to 7 when branch is executed, and 6 when branch is not executed. *6: Set to 8 + (a) when branch is executed, and 7 + (a) when branch is not executed. *7: Set to 3 x (b) + 2 x (c) when an interrupt request occurs, and 6 x (c) for return. *8: Return from stack (word). *9: Return from stack (long). *10: Do not use the addressing mode of RWj + in CBNE/CWBNE instruction. Note: For (a) to (d), refer to "Table 4 Number of Execution Cycles for Effective Address in Addressing Modes" and "Table 5 Correction Values for Number of Cycles for Calculating Actual Number of Cycles." 119 MB90520 Series Table 21 Mnemonic Miscellaneous Control Types (Byte, Word, Long) [28 Instructions] # ~ RG B Operation LH AH I S T N Z V C RMW PUSHW PUSHW PUSHW PUSHW A AH PS rlst 1 1 1 2 4 4 4 *3 0 0 0 +& (c) (c) (c) *4 word (SP) (SP) - 2, ((SP)) (A) - word (SP) (SP) - 2, ((SP)) (AH) - word (SP) (SP) - 2, ((SP)) (PS) - (PS) (PS) - 2n, ((SP)) (rlst) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - POPW POPW POPW POPW A AH PS rlst 1 1 1 2 3 3 4 *2 0 0 0 +& (c) (c) (c) *4 word (A) ((SP)), (SP) (SP) + 2 word (AH) ((SP)), (SP) (SP) + 2 word (PS) ((SP)), (SP) (SP) + 2 (rlst) ((SP)), (SP) (SP) + 2n - - - - * - - - - - * - - - * - - - * - - - * - - - * - - - * - - - * - - - - - JCTX @A 1 14 0 6 x (c) Context switch instruction - - * * * * * * * - AND OR CCR, #imm8 CCR, #imm8 2 2 3 3 0 0 0 0 byte (CCR) (CCR) and imm8 - byte (CCR) (CCR) or imm8 - - - * * * * * * * * * * * * * * - - MOV MOV RP, #imm8 2 ILM, #imm8 2 2 2 0 0 0 0 byte (RP) imm8 byte (ILM) imm8 - - - - - - - - - - - - - - - - - - - - MOVEA MOVEA MOVEA MOVEA 3 RWi, ear 2 RWi, eam 2 + 2 + (a) 1 2 A, ear 2 + 1 + (a) A, eam 1 1 0 0 0 0 0 0 word (RWi) ear word (RWi) eam word(A) ear word (A) eam - - - - - - * * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ADDSP #imm8 ADDSP #imm16 2 3 3 3 0 0 0 0 word (SP) (SP) + ext (imm8) - - word (SP) (SP) + imm16 - - - - - - - - - - - - - - - - - - MOV MOV 2 2 *1 1 0 0 0 0 byte (A) (brgl) byte (brg2) (A) Z - * - - - - - - - * * * * - - - - - - 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 No operation Prefix code for accessing AD space Prefix code for accessing DT space Prefix code for accessing PC space Prefix code for accessing SP space Prefix code for no change in flag Prefix for common register bank - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - NOP ADB DTB PCB SPB NCC CMR A, brgl brg2, A *1: PCB, ADB, SSB, USB, and SPB : 1 state DTB, DPR : 2 states *2: 7 + 3 x (number of POPs) + 2 x (the number of the last register to be POPed), 7 if rlst = 0(no transfer registers) *3: 29 + 3 x (number of PUSHes) - 3 x (the number of the last register to be PUSHed), 8 if rlst = 0(no transfer registers) *4: (Number of POPs) x (c), or (number of PUSHes) x (c) Note: For (a) to (d), refer to "Table 4 Number of Execution Cycles for Effective Address in Addressing Modes" and "Table 5 Correction Values for Number of Cycles for Calculating Actual Number of Cycles." 120 MB90520 Series Table 22 Bit Manipulation Instruction [21 Instructions] Mnemonic # ~ RG B MOVB A, dir:bp MOVB A, addr16:bp MOVB A, io:bp 3 4 3 5 5 4 0 0 0 (b) (b) (b) MOVB dir:bp, A MOVB addr16:bp, A MOVB io:bp, A 3 4 3 7 7 6 SETB dir:bp SETB addr16:bp SETB io:bp 3 4 3 CLRB dir:bp CLRB addr16:bp CLRB io:bp BBC BBC BBC Operation byte (A) (dir:bp) b byte (A) (addr16:bp) b byte (A) (io:bp) b LH AH I S T N Z V C RMW Z Z Z * * * - - - - - - - - - * * * * * * - - - - - - - - - 0 2 x (b) bit (dir:bp) b (A) 0 2 x (b) bit (addr16:bp) b (A) 0 2 x (b) bit (io:bp) b (A) - - - - - - - - - - - - - - - * * * * * * - - - - - - * * * 7 7 7 0 2 x (b) bit (dir:bp) b 1 0 2 x (b) bit (addr16:bp) b 1 0 2 x (b) bit (io:bp) b 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - * * * 3 4 3 7 7 7 0 2 x (b) bit (dir:bp) b 0 0 2 x (b) bit (addr16:bp) b 0 0 2 x (b) bit (io:bp) b 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - * * * dir:bp, rel addr16:bp, rel io:bp, rel 4 5 4 *1 *1 *2 0 0 0 (b) (b) (b) Branch if (dir:bp) b = 0 Branch if (addr16:bp) b = 0 Branch if (io:bp) b = 0 - - - - - - - - - - - - - - - - - - * * * - - - - - - - - - BBS BBS BBS dir:bp, rel addr16:bp, rel io:bpvrel 4 5 4 *1 *1 *2 0 0 0 (b) (b) (b) Branch if (dir:bp) b = 1 Branch if (addr16:bp) b = 1 Branch if (io:bp) b = 1 - - - - - - - - - - - - - - - - - - * * * - - - - - - - - - SBBS addr16:bp, rel 5 *3 0 2 x (b) Branch if (addr16:bp) b = 1, bit = 1 - - - - - - * - - * WBTS io:bp 3 *4 0 *5 Wait until (io:bp) b = 1 - - - - - - - - - - WBTC io:bp 3 *4 0 *5 Wait until (io:bp) b = 0 - - - - - - - - - - *1: *2: *3: *4: *5: Set to 8 when branch is executed, and 7 when branch is not executed. Set to 7 when branch is executed, and 6 when branch is not executed. 10 if conditions are met, 9 when conditions are not met. Indeterminate times Until conditions are met Note: For (a) to (d), refer to "Table 4 Number of Execution Cycles for Effective Address in Addressing Modes" and "Table 5 Correction Values for Number of Cycles for Calculating Actual Number of Cycles." 121 MB90520 Series Table 23 Accumulator Manipulation Instruction (Byte, Word) [6 Instructions] Mnemonic SWAP SWAPW/XCHW AL, AH EXT EXTW ZEXT ZEXTW # ~ RG B 1 1 1 1 1 1 3 2 1 2 1 1 0 0 0 0 0 0 0 0 0 0 0 0 Table 24 Operation byte (A) 0 - 7 (A) 8 - 15 word (AH) (AL) byte sign-extension word sign-extension byte zero-extension word zero-extension LH AH - - X - Z - - * - X - Z I S T N Z V C RMW - - - - - - - - - - - - - - - - - - - - * * R R - - * * * * - - - - - - - - - - - - - - - - - - I S T N Z V C RMW String Instruction [10 Instructions] Mnemonic # ~ RG MOVS/MOVSI 2 *2 - - - - - - - - - - MOVSD 2 *2 *5 *3 byte transfer @AH + @AL +, Counter = RW0 *5 *3 byte transfer @AH - @AL -, Counter = RW0 - - - - - - - - - - SCEQ/SCEQI 2 *1 - - - - - * * * * - SCEQD 2 *1 *5 *4 byte search (@AH +) - AL, Counter = RW0 *5 *4 byte search (@AH -) - AL, Counter = RW0 - - - - - * * * * - FISL/FILSI 2 6m + 6 *5 *3 byte fill @AH + AL, Counter = RW0 - - - - - * * - - - *8 *6 word transfer @AH + @AL +, Counter = RW0 *8 *6 word transfer @AH - @AL -, Counter = RW0 - - - - - - - - - - - - - - - - - - - - *8 *7 word search (@AH +) - AL, Counter = RW0 *8 *7 word search (@AH -) - AL, Counter = RW0 - - - - - * * * * - - - - - - * * * * - - - - - - * * - - - B Operation MOVSW/MOVSWI 2 *2 MOVSWD 2 *2 SCWEQ/SCWEQI 2 *1 SCWEQD 2 *1 FILSW/FILSWI 2 6m + 6 *8 *6 word fill @AH + AL, Counter = RW0 LH AH m: RW0 value (counter value) n: Number of loops *1: 5 when RW0 is 0, 4 + 7 x (RW0) when count out, and 7 x n + 5 when matched *2: 5 when RW0 is 0, otherwise 4 + 8 x (RW0) *3: To access different areas for source (b) x (RW0) + (b) x (RW0) and source destination, calculate item (b) independently. *4: (b) x n *5: 2 x (RW0) *6: To access different areas for source (c) x (RW0) + (c) x (RW0) and source destination, calculate item (b) independently. *7: (c) x n *8: 2 x (RW0) Note: For (a) to (d), refer to "Table 4 Number of Execution Cycles for Effective Address in Addressing Modes" and "Table 5 Correction Values for Number of Cycles for Calculating Actual Number of Cycles." 122 MOV MOVX MOVX A, A, @A @RL3 + d8 A, PCB +5 +6 MOVW MOVW NRML A, @A @AL, AH A, R0 ASRW ASRL ASR MOVW @RL MOVW A, A, R0 A, R0 A, R0 3 + d8, A @RL3 + d8 LSRW LSRL LSR A, R0 A, R0 A, R0 +D +E +F @RL1 + d8 MOVW A, @RL0 + d8 MOVW A, @RL3 + d8 MOV A, @RL2 + d8 MOV A, @RL1 + d8 MOV A, @RL0 + d8 MOV A, 40 LSLW LSLL LSL MOVW @RL MOVW A, A, R0 A, R0 A, R0 2 + d8, A @RL2 + d8 1 + d8, A MOVW @RL 0 + d8, A MOVW @RL + d8, A MOV @RL3 + d8, A MOV @RL2 + d8, A MOV @RL1 + d8, A MOV @RL0 30 +C +B +A +9 +8 A MOV MOV A, @A @AL, AH +4 RORC MOV MOV MOVX A, A, DPR DPR, A @RL2 + d8 +3 A MOV MOV A, USB USB, A +2 ROLC MOV MOV MOVX A, A, SSB SSB, A @RL1 + d8 +1 +7 MOV MOV A, ADB ADB, A 20 MOV MOV MOVX A, A, DTB DTB, A @RL0 + d8 10 +0 00 50 Table 25 60 DIVU MULW MUL 70 A A A 80 90 A0 2-byte Instruction Map [Byte 1 = 6 FH] B0 C0 D0 E0 F0 MB90520 Series 123 124 +F +E +D MULU A, MULU A, A, @RW3 + MULU addr16 MULU A, A, @RW2 + @PC + d16 MULU A, @RW1 + @RW1 + RW7 MULU A, @RW0 + @RW0 + RW7 MULU A, MULUW A, MUL MUL A, @RW3 + d16 MUL A, @RW2 + d16 MUL A, @RW1 + d16 MUL A, MULUW A, MUL MUL A, MULUW A, MUL MUL A, A, @RW3 + MULUW addr16 A, @RW3 + MULUW A, MUL addr16 MUL A, A, @RW2 + @PC + d16 A, @RW2 + @PC + d16 MULUW A, @RW1 + @RW1 + RW7 A, @RW1 + @RW1 + RW7 MULUW A, @RW0 + @RW0 + RW7 A, @RW0 + @RW0 + RW7 MULUW MULU MULUW MULU A, MULUW A, MUL A, @RW3 @RW3 + d16 A, @RW3 @RW3 + d16 A, @RW3 +B MULU MULU MULUW MULU A, MULUW A, MUL A, @RW2 @RW2 + d16 A, @RW2 @RW2 + d16 A, @RW2 +A +C MULU MULUW MULU A, MULUW A, MUL A, @RW1 @RW1 + d16 A, @RW1 @RW1 + d16 A, @RW1 +9 @RW0 + d16 MULW A, DIVU DIVU A, MULW A, DIVU DIVU A, MULW A, DIVU DIVU A, A, @RW3 + MULW DIVUW A, DIV DIV A, DIVUW A, DIV DIV A, DIVUW A, DIV DIV A, A, @RW2 + @PC + d16 A, @RW2 + @PC + d16 DIVUW A, @RW1 + @RW1 + RW7 A, @RW1 + @RW1 + RW7 DIVUW A, @RW0 + @RW0 + RW7 A, @RW0 + @RW0 + RW7 DIVUW DIVW A, DIVW A, DIVW A, A, @RW2 + @PC + d16 DIVW A, @RW1 + @RW1 + RW7 DIVW A, @RW0 + @RW0 + RW7 DIVW DIVU DIVU A, DIVUW A, DIV DIV A, DIVW A, DIVUW DIVW addr16 A, @RW3 + addr16 A, @RW3 + addr16 A, @RW3 + addr16 A, @RW3 + addr16 MULW A, A, @RW2 + @PC + d16 A, @RW2 + @PC + d16 MULW A, @RW1 + @RW1 + RW7 A, @RW1 + @RW1 + RW7 MULW A, @RW0 + @RW0 + RW7 A, @RW0 + @RW0 + RW7 MULW MULW DIVU DIVUW DIVW DIVU A, DIVUW A, DIV DIV A, DIVW A, MULW A, A, @RW3 @RW3 + d16 A, @RW3 @RW3 + d16 A, @RW3 @RW3 + d16 A, @RW3 @RW3 + d16 A, @RW3 @RW3 + d16 MULW DIVU DIVUW DIVW DIVU A, DIVUW A, DIV DIV A, DIVW A, MULW A, A, @RW2 @RW2 + d16 A, @RW2 @RW2 + d16 A, @RW2 @RW2 + d16 A, @RW2 @RW2 + d16 A, @RW2 @RW2 + d16 MULW DIVU DIVUW DIVW DIVU A, DIVUW A, DIV DIV A, DIVW A, MULW A, A, @RW1 @RW1 + d16 A, @RW1 @RW1 + d16 A, @RW1 @RW1 + d16 A, @RW1 @RW1 + d16 A, @RW1 @RW1 + d16 MULW DIVU DIVUW DIVW DIVU A, DIVUW A, DIV DIV A, DIVW A, MULW A, A, @RW0 @RW0 + d16 A, @RW0 @RW0 + d16 A, @RW0 @RW0 + d16 A, @RW0 @RW0 + d16 A, @RW0 @RW0 + d16 MULU MULUW MULU A, MULUW A, MUL A, @RW0 @RW0 + d16 A, @RW0 @RW0 + d16 A, @RW0 +8 MUL A, MULU MULUW MULW DIVU DIVUW DIVW MULU A, MUL A, DIVU A, DIVUW A, DIV DIV A, DIVW A, MULUW A, MUL MULW A, A, R7 @RW7 + d8 A, RW7 @RW7 + d8 A, R7 @RW7 + d8 A, RW7 @RW7 + d8 A, R7 @RW7 + d8 A, RW7 @RW7 + d8 A, R7 @RW7 + d8 A, RW7 @RW7 + d8 F0 +7 E0 MULU MULUW MULW DIVU DIVUW DIVW MULU A, MUL A, DIVU A, DIVUW A, DIV DIV A, DIVW A, MULUW A, MUL MULW A, A, R6 @RW6 + d8 A, RW6 @RW6 + d8 A, R6 @RW6 + d8 A, RW6 @RW6 + d8 A, R6 @RW6 + d8 A, RW6 @RW6 + d8 A, R6 @RW6 + d8 A, RW6 @RW6 + d8 D0 +6 C0 MULU MULUW MULW DIVU DIVUW DIVW MULU A, MUL A, DIVU A, DIVUW A, DIV DIV A, DIVW A, MULUW A, MUL MULW A, A, R5 @RW5 + d8 A, RW5 @RW5 + d8 A, R5 @RW5 + d8 A, RW5 @RW5 + d8 A, R5 @RW5 + d8 A, RW5 @RW5 + d8 A, R5 @RW5 + d8 A, RW5 @RW5 + d8 B0 +5 A0 MULU MULUW MULW DIVU DIVUW DIVW MULU A, MUL A, DIVU A, DIVUW A, DIV DIV A, DIVW A, MULUW A, MUL MULW A, A, R4 @RW4 + d8 A, RW4 @RW4 + d8 A, R4 @RW4 + d8 A, RW4 @RW4 + d8 A, R4 @RW4 + d8 A, RW4 @RW4 + d8 A, R4 @RW4 + d8 A, RW4 @RW4 + d8 90 +4 80 MULU MULUW MULW DIVU DIVUW DIVW MULU A, MUL A, DIVU A, DIVUW A, DIV DIV A, DIVW A, MULUW A, MUL MULW A, A, R3 @RW3 + d8 A, RW3 @RW3 + d8 A, R3 @RW3 + d8 A, RW3 @RW3 + d8 A, R3 @RW3 + d8 A, RW3 @RW3 + d8 A, R3 @RW3 + d8 A, RW3 @RW3 + d8 70 +3 60 MULU MULUW MULW DIVU DIVUW DIVW MULU A, MUL A, DIVU A, DIVUW A, DIV DIV A, DIVW A, MULUW A, MUL MULW A, A, R2 @RW2 + d8 A, RW2 @RW2 + d8 A, R2 @RW2 + d8 A, RW2 @RW2 + d8 A, R2 @RW2 + d8 A, RW2 @RW2 + d8 A, R2 @RW2 + d8 A, RW2 @RW2 + d8 50 +2 40 MULU MULUW MULW DIVU DIVUW DIVW MULU A, MUL A, DIVU A, DIVUW A, DIV DIV A, DIVW A, MULUW A, MUL MULW A, A, R1 @RW1 + d8 A, RW1 @RW1 + d8 A, R1 @RW1 + d8 A, RW1 @RW1 + d8 A, R1 @RW1 + d8 A, RW1 @RW1 + d8 A, R1 @RW1 + d8 A, RW1 @RW1 + d8 30 +1 20 MULU MULUW MULW DIVU DIVUW DIVW MULU A, MUL A, DIVU A, DIVUW A, DIV DIV A, DIVW A, MULUW A, MUL MULW A, A, R0 @RW0 + d8 A, RW0 @RW0 + d8 A, R0 @RW0 + d8 A, RW0 @RW0 + d8 A, R0 @RW0 + d8 A, RW0 @RW0 + d8 A, R0 @RW0 + d8 A, RW0 @RW0 + d8 10 ea Instruction (9) [Byte 1 = 78 H] +0 00 Table 26 MB90520 Series MB90520 Series ORDERING INFORMATION Part number Package MB90523PFF-G MB90522PFF-G MB90F523PFF-G 120-pin Plastic LQFP (FPT-120P-M05) MB90523PFV-G MB90522PFV MB90F523PFV-G 120-pin Plastic QFP (FPT-120P-M13) Remarks 125 MB90520 Series PACKAGE DIMENSIONS 120-pin Plastic LQFP (FPT-120P-M05) +0.20 16.000.20(.630.008)SQ 14.000.10(.551.004)SQ 90 1.50 -0.10 +.008 .059 -.004 61 (Mounting height) 0.100.10 (STAND OFF) (.004.004) 91 60 Details of "A" part 11.60 (.457) REF 15.00 (.591) NOM 0.15(.006) 0.10(.004)MAX 0.36(.014)MAX 1 PIN INDEX 120 31 "A" LEAD No. 0.15(.006) Details of "B" part 1 30 +0.08 0.40(.0157)TYP 0.14 -0.03 +.003 .006 -.001 0.065(.003) +0.05 0.127 -0.02 +.002 .005 -.001 M 0 "B" 0.10(.004) C 10 0.500.20 (.020.008) Dimensions in mm (inches) 1995 FUJITSU LIMITED F120006S-2C-3 120-pin Plastic QFP (FPT-120P-M13) 22.600.20(.890.008)SQ 3.85(.152)MAX (Mounting height) 20.000.10(.787.004)SQ 90 0.05(.002)MIN (STAND OFF) 61 91 60 14.50 (.571) REF 21.60 (.850) NOM Details of "A" part 0.15(.006) 0.15(.006) 0.15(.006)MAX INDEX 0.40(.016)MAX "A" 120 LEAD No. 31 Details of "B" part 30 1 0.50(.0197) 0.200.10 (.008.004) 0.08(.003) M 0.1250.05 (.005.002) 0 10 0.500.20(.020.008) 0.10(.004) C 126 1995 FUJITSU LIMITED F120013S-2C-3 "B" Dimensions in mm (inches) MB90520 Series FUJITSU LIMITED For further information please contact: Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-8588, Japan Tel: 81(44) 754-3763 Fax: 81(44) 754-3329 http://www.fujitsu.co.jp/ North and South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street San Jose, CA 95134-1804, USA Tel: (408) 922-9000 Fax: (408) 922-9179 Customer Response Center Mon. - Fri.: 7 am - 5 pm (PST) Tel: (800) 866-8608 Fax: (408) 922-9179 http://www.fujitsumicro.com/ Europe FUJITSU MIKROELEKTRONIK GmbH Am Siebenstein 6-10 D-63303 Dreieich-Buchschlag Germany Tel: (06103) 690-0 Fax: (06103) 690-122 http://www.fujitsu-ede.com/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE LTD #05-08, 151 Lorong Chuan New Tech Park Singapore 556741 Tel: (65) 281-0770 Fax: (65) 281-0220 All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. http://www.fmap.com.sg/ F9811 FUJITSU LIMITED Printed in Japan 127