SLES019 − DECEMBER 2001
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PRINCIPLES OF OPERATION
correlated double sampler (CDS) (continued)
The reference level is sampled during the SHP active period, and the voltage level is held by the sampling
capacitor C 1 at the trailing edge of SHP. The data level is sampled during the SHD active period, and the voltage
level is held by the sampling capacitor C2 at the trailing edge of SHD. Then, the switched-capacitor amplifier
performs the subtraction of these two levels.
The user can select the active polarity of SHP/SHD (active high or active low) through the serial interface; refer
to the serial interface section for details. The default polarity of SHP/SHD is active low. Upon power on, this value
is not defined. For this reason, it must be set to the appropriate value by using the serial interface, and reset
to the default value by strobing pin 45 (RESET). The description and the timing diagrams in this data sheet are
all based on active low polarity (default value).
input clamp and dummy pixel clamp
The buffered CCD output is capacitively coupled to the VSP2270 device. The input clamp restores the dc
component of the input signal that was lost with the ac-coupling and establishes the desired dc bias point for
the CDS. Figure 1 also shows a simplified block diagram of the input clamp. The input level is clamped to the
internal reference voltage CM (1.5 V) during the dummy pixel interval. Specifically, when both CLPDM and SHP
are active, the dummy clamp function becomes active. If the dummy pixels and/or the CLPDM pulse are not
available in your system, the CLPOB pulse can be used in place of the CLPDM pulse, as long as the clamping
takes place during black pixels. In this case, both the CPLDM (active at the same timing as CLPOB) and SHP
signals become active during the optical black pixel interval; then the dummy clamp function becomes active.
The user can select the active polarity of CLPDM and SHP (active high or active low) through the serial interface,
refer to the serial interface section for details. The default value of CLPDM and SHP is active low. Upon power
on, this value is not defined. For this reason, it must be set to the appropriate value by using the serial interface,
and reset to the default value by strobing pin 45 (RESET). The description and the timing diagrams in this data
sheet are all based on active low polarity (default value).
high performance analog-to-digital converter (ADC)
The analog-to-digital converter (ADC) utilizes a fully differential and pipelined architecture. This ADC is well
suited for low voltage operation, low power consumption requirements, and high-speed applications. Ten-bit
resolution with no missing code is assured.
The VSP2270 device includes the reference voltage generator for the ADC. Positive reference voltage, pin 38
(REFP), negative reference voltage, pin 39 (REFN), and common-mode voltage, pin 37 (CM) must be bypassed
to the ground with a 0.1-µF ceramic capacitor. Do not use these voltages elsewhere in the system. They affect
the stability of these reference levels, which causes ADC performance degradation. Also, these are analog
output pins. Do not apply external voltages.
programmable gain amplifier (PGA)
Figure 2 shows the characteristics of the PGA gain. The PGA provides a gain range of –6 dB to 42 dB, which
is linear in dB. The gain is controlled by a digital code with 10-bit resolution, and it can be set through the serial
interface, refer to the serial interface section for details. The default value of the gain control code is 128 (PGA
gain = 0 dB).
Upon power on, this value is unknown. For this reason, it must be set to the appropriate value by using the serial
interface, and reset to the default value by strobing pin 45 (RESET).