Order Number: 251902, Revision: 009
April 2005
Intel StrataFlash® Wireless Memory
(L18)
28F640L18, 28F128L18, 28F256L18
Dat ash ee t
Product Features
The Intel StrataFlash® wireless memory (L18) device is the latest genera tio n of Intel
StrataFlash® memory devices featuring flexible, multiple-partition, dual operati on. It provid es
high performance synchronous-burst read mode and asynchronous read mode using 1.8 V low-
voltage, multi-level cell (MLC) technology.
The multiple-partition architecture enables backgr oun d progr ammin g or erasin g to occur in one
partition while code execution or data reads take place in another partition. This dual-operation
architecture also allows a system to interleave code operations while program and erase
operations take place in the background. The 8-Mbit or 16-Mbit partitions allow sy stem
designers to choose the size of the code and data segments. The L18 wireless memory device is
manufactured using Intel 0.13 µm ETOX™ VIII process technology. It is available in industry-
standard chip scale packaging.
■High performance Read-While-Write/Erase
— 85 ns initial access
— 54 MHz with z er o w ai t st at e, 14 ns clock-to-
data output synchronous-burst mode
— 25 ns asynchronous-page mode
— 4-, 8-, 16- , and conti nuous- w or d burst m ode
— Burst suspend
— Programmabl e WAIT configuration
— Buffered Enhanced Factory Progra mming
(BEF P) at 5 µs/byte (Typ)
— 1.8 V lo w - power b uffered progr a mming at
7 µs/byte (Typ)
■Architecture
— Asymmetrically-blocked architecture
— Multi ple 8-Mbit part itions: 64-Mbit and 128-
Mbit devi ces
— Multiple 16-Mb it parti t ions: 256-Mb i t devices
— Four 16-K w o r d param et er bloc ks: top or
bottom c onfigu ra tions
— 64-Kword m ain bl ocks
— Dual- operati on: Read- W hile-Write (RWW) or
Read-While-Erase (RWE)
— Status Regi ster for partition and devi ce status
■Power
—V
CC (core) = 1. 7 V - 2. 0 V
—V
CCQ (I/O) = 1.35 V - 2.0 V, 1.7 V - 2.0 V
— Standby cu rrent: 30 µA (Typ) for 256-Mbit
— 4-Word synchr onou s rea d curre nt: 15 mA (Typ)
at 54 MH z
— Autom atic Pow er Savi ngs mo de
■Security
— OTP space:
• 64 unique factory device identifier bits
• 64 user-programmable OTP bits
• Additional 2048 use r-programm able OTP bits
— Absol ut e w rite pro te ct i on: VPP = GND
— Power-transition erase/program lockout
— Ind i vidual zero-lat ency block locking
— Indivi dual bl ock lock- down
■Software
— 20 µs (Typ) program su spen d
— 20 µs (Typ) erase suspend
— Intel® Flash Data Integrator optimized
— Basic Command Set (BCS) and Extended
Command Set (ECS) compatible
— Common Fla sh I nt er fa ce (CFI) capable
■Quality and Reliability
— Expanded te m perature : –25° C to +85° C
— Minim um 10 0, 000 eras e cycles per block
— ETOX™ VI I I pr ocess t echnol ogy (0.13 µm)
■Density and Pa ckaging
— 64-, 128-, an d 256-Mb i t density in V F BGA
packages
— 128/0 and 256/ 0 density in SCSP
— 16-bit w id e data bus
April 2005 Intel StrataFlash® Wireless Memory (L18) Datasheet
2 Order Number: 251902, Revision: 009
Legal Lines and Di sclai m er s
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Copyright © 2005, Intel Corporation. All Rights Reserved.
Intel StrataFlash® Wireless Memory (L18)
Datasheet Intel StrataFlash® Wireless Memory (L18) April 2005
Order Number: 251902, Revision: 009 3
Contents
1.0 Introduction ...............................................................................................................................9
1.1 Nomenclature .......................................................................................................................9
1.2 Acronyms..............................................................................................................................9
1.3 Conventions........................................................................................................................10
2.0 Functional Overview ............................................................................................................11
3.0 Package Information............................................................................................................12
3.1 VF BGA Packages..............................................................................................................12
3.2 SCSP Packages .................................................................................................................14
4.0 Ballout and Signal Descriptions......................................................................................16
4.1 Signal Ballout......................................................................................................................16
4.1.1 VF BGA Package Ballout.......................................................................................16
4.1.2 SCSP Package Ballout..........................................................................................18
4.2 Signal Descriptions.............................................................................................................19
4.2.1 VF BGA Package Signal Descriptions...................................................................19
4.2.2 128/0 and 256/0 SCSP Package Signal Descriptions ...........................................21
4.3 Memory Map.......................................................................................................................23
5.0 Maximum Ratings and Operating Conditions ...........................................................25
5.1 Absolute Maximum Ratings................................................................................................25
5.2 Operating Conditions..........................................................................................................25
6.0 Electrical Specifications.....................................................................................................26
6.1 DC Current Characteristics.................................................................................................26
6.2 DC Voltage Characteristics.................................................................................................27
7.0 AC Characteristics................................................................................................................28
7.1 AC Test Condition s............... ...... .................... ................... ...... .................... ................... . ...28
7.2 Capacitance........................................................................................................................29
7.3 AC Read Specifications (VCCQ = 1.35 V – 2.0 V) ............................................................30
7.4 AC Read Specifications for 64-Mbit and 128-Mbit Densities (VCCQ = 1.7 V – 2.0 V) .......31
7.5 AC Read Specifications for 256-Mbit Density (VCCQ = 1.7 V – 2.0 V) .............................32
7.6 AC Write Specif ic ations ........................... ................... .................... ................... ................ .37
7.7 Program and Erase Characteristics....................................................................................41
8.0 Power and Reset Specifications.....................................................................................42
8.1 Power Up and Down...........................................................................................................42
8.2 Reset ..................................................................................................................................42
8.3 Power Supply Decoupling...................................................................................................43
8.4 Automatic Power Saving.....................................................................................................44
9.0 Device Operations.................................................................................................................45
9.1 Bus Operations...................................................................................................................45
9.1.1 Reads ....................................................................................................................46
9.1.2 Writes.....................................................................................................................46
9.1.3 Output Disable.......................................................................................................46
Intel StrataFlash® Wireless Memory (L18)
April 2005 Intel StrataFlash® Wireless Memory (L18) Datasheet
4 Order Number: 251902, Revision: 009
9.1.4 Standby..................................................................................................................46
9.1.5 Reset .....................................................................................................................46
9.2 Device Commands .............................................................................................................47
9.3 Command Definitions .........................................................................................................48
10.0 Read Ope rations....................................................................................................................50
10.1 Asynchronous Page-Mode Read........................................................................................50
10.2 Synchronous Burst-Mode Read..........................................................................................50
10.2.1 Burst Suspend.......................................................................................................51
10.3 Read Configuration Register (RCR)...................................................................................51
10.3.1 Read Mode ............................................................................................................52
10.3.2 Latency Count........................................................................................................52
10.3.3 WAIT Polarity.............. ...... ....... ...... ................... ....... ................... ....... ................... .54
10.3.3.1 WAIT Signal Function............................................................................54
10.3.4 Data Hold...............................................................................................................55
10.3.5 WAIT Delay .... ................... ....... ................... ...... .................... ...... .................... ...... .56
10.3.6 Burst Sequence.....................................................................................................56
10.3.7 Clock Edge .......... .................... ...... ................... ....... ................... ....... ................... .57
10.3.8 Burst Wrap.............................................................................................................57
10.3.9 Burst Length ..........................................................................................................57
11.0 Programming Operations ..................................................................................................58
11.1 Word Programming.............................................................................................................58
11.1.1 Factory Word Programming...................................................................................59
11.2 Buffered Programming........................................................................................................59
11.3 Buffered Enhanced Factory Programming .........................................................................60
11.3.1 Buffered EFP Requirements and Considerations..................................................60
11.3.2 Buffered EFP Setup Phase....................................................................................61
11.3.3 Buffered EFP Program/Verify Phase.....................................................................61
11.3.4 Buffered EFP Exit Phase.......................................................................................62
11.4 Program Suspe nd....... ...... ....... ...... ....... ...... ....... ...... ...... .................... ...... .................... .... ...62
11.5 Program Resume. ....... ...... ....... ...... ....... ................... ...... .................... ...... .................... .......63
11.6 Program Prote cti on........... ....... ...... ....... ...... ................... ....... ................... ....... ................ ....63
12.0 Erase Operations...................................................................................................................64
12.1 Block Erase.........................................................................................................................64
12.2 Erase Suspend...................................................................................................................64
12.3 Erase Resume....................................................................................................................65
12.4 Erase Protection.................................................................................................................65
13.0 Security Modes.......................................................................................................................66
13.1 Block Locking......................................................................................................................66
13.1.1 Lock Block .............................................................................................................66
13.1.2 Unlock Block..........................................................................................................66
13.1.3 Lock-Down Block...................................................................................................66
13.1.4 Block Lock Status ..................................................................................................67
13.1.5 Block Locking During Suspend..............................................................................67
13.2 Protection Registers ...........................................................................................................68
13.2.1 Reading the Protection Registers..........................................................................69
13.2.2 Programming the Protection Registers..................................................................70
13.2.3 Locking the Protection Registers...........................................................................70
Intel StrataFlash® Wireless Memory (L18)
Datasheet Intel StrataFlash® Wireless Memory (L18) April 2005
Order Number: 251902, Revision: 009 5
14.0 Dual-Operation Considerations.......................................................................................71
14.1 Memory Partitioning............................................................................................................71
14.2 Read-While-Write Command Sequences...........................................................................71
14.2.1 Simultaneou s Op erati on Detai ls ........ ...... ...... ....... ...... ....... ...... ....... ...... .................72
14.2.2 Synchronous and Asynchronous RWW Characteristics and Waveforms..............72
14.2.2.1 Write operation to asynchronous read transition ...................................72
14.2.2.2 Write to synchronous read operation transition .....................................73
14.2.2.3 Write Operation with Clock Active..........................................................73
14.2.3 Read Operation During Buffered Programming.....................................................73
14.3 Simultaneou s Oper ati on Restri ction s ...... ....... ...... ...... ....... ...... .................... ................... ....74
15.0 Special Read States..............................................................................................................75
15.1 Read Status Register..........................................................................................................75
15.1.1 Clear Status Register.............................................................................................76
15.2 Read Device Identifier ........................................................................................................76
15.3 CFI Query ...........................................................................................................................77
Appendix A Write State Machine (WSM)...........................................................................78
Appendix B Flowcharts............................................................................................................85
Appendix C Common Flash Interface................................................................................93
Appendix D Additional Information...................................................................................103
Appendix E Ordering Information......................................................................................104
Intel StrataFlash® Wireless Memory (L18)
April 2005 Intel StrataFlash® Wireless Memory (L18) Datasheet
6 Order Number: 251902, Revision: 009
Revision History
Revision Date Revision Description
10/15/02 -001 Initial Release
01/20/03 -002 Revised 256-Mbit Partition Size
Revised 256-Mbit Memory Map
Change W AIT function to de-assert during Asynchronous Operations (Asynchronous Reads and all
Writes)
Change WAIT function to active during Synchronous Non-Array Read
Updated all Waveforms to reflect new WAIT function
Revised Section 8.2.2
Added Synchronous Read to Write transition Section
Improved 1.8 Volt I/O Bin 2 speed to 95ns from 105ns
Added new AC specs: R15, R16, R17, R111, R311, R312, W21, and W22
Various text edits
04/11/03 -003 Added SCSP for 128/0 and 256/0 Ball-out and Mechanical Drawing
08/04/03 -004 Changed ICCS and ICCR values
Added 256-Mbit AC Speed
Changed Program and Erase Spec
Combined the Buffered Programming Flow Chart and Read While Buffered programming Flow
Chart
Revised Read While Buffered Programming Flow Chart
Revised Appendix A Write St ate Machine
Revised CFI Table 21 CFI Identification
Various text edits.
01/20/04 -005 Various text clarifications, various text edits, block locking state diagram clarification, synchronous
read to write timing clarification, write to synchronous read timing clarification
05/22/04 -006 Minor text edits
Changed Capacitance values
Changed Standby Current (typ), Power Down Current (typ), Erase Suspend Current (typ), and
Automatic Power Savings Current (typ)
Updated Transient Equialent Testing Load Circuit
Intel StrataFlash® Wireless Memory (L18)
Datasheet Intel StrataFlash® Wireless Memory (L18) April 2005
Order Number: 251902, Revision: 009 7
09/02/04 -007 Added Table 7 “Bus Operations Summary” on page 45
Modified Table 32 “L18 SCSP Package Ordering Information” on page 105 and added the following
order items:
* RD48F2000L0YTQ0, RD48F2000L0YBQ0
* RD48F4000L0YTQ0, RD48F4000L0YBQ0
* PF48F3000L0YTQ0, PF48F3000L0YBQ0
* PF48F4000L0YTQ0, PF48F4000L0YBQ0
* NZ48F4000L0YTQ0, NZ48F4000L0YBQ0
* JZ48F4000LOYTQ0, JZ48F4000LOYBQ0
09/29/04 -008 Removed two mechanical drawings for 9x7.7x1.0 mm and 9x11x1.0 mm
Added mechanical drawing Figure 4 “256-Mbit, 88-ball (80-active ball) SCSP Drawing and Dimen-
sions (8x11x 1.0 mm)” on page 15
In Table 32 “L18 SCSP Package Ordering Information” on page 105, corrected 256L18 package
size from 8x10x1.2 mm to 8x11x1.2 mm
04/22/05 -009 Removed Bin 2 LC and Frequency Support Tables
Added back VF BGA mechanical drawings
Renamed 256-Mbit UT-SCSP to be 256-Mbit SCSP
Updated Ordering Info
Minor text edits
Converted datasheet to new template
In Table 4 “Bottom Par amet er Mem ory Map” on page 24 , correc ted 256-Mbit Blk 131 address
range from 100000 - 10FFFF to 800000 - 80FFFF
In Section 5.1, “Absolute Maximum Ratings” on page 25, corrected Voltage on any signal (except
VCC, VPP) from -0.5 V to +3.8 V to -0.5 V to +2.5 V
In Section E.2, “Ordering Information for SCSP” on page 105, correct ed package designators for
leaded and lead-free packages from RD/PF to NZ/JZ
Intel StrataFlash® Wireless Memory (L18)
April 2005 Intel StrataFlash® Wireless Memory (L18) Datasheet
8 Order Number: 251902, Revision: 009
Intel StrataFlash® Wireless Memory (L18)
Datasheet Intel StrataFlash® Wireless Memory (L18) April 2005
Order Number: 251902, Revision: 009 9
1.0 Introduction
This document provides information about the Intel StrataFlash® wireless memory device (L18).
This document describes the device features, operation, and specifications.
1.1 Nomenclature
1.8 V: range of 1.7 V – 2.0 V (except where noted)
1.8 V Extended Range: range of 1.35 V – 2.0 V
VPP = 9.0 V: VPP voltage range of 8.5 V – 9.5 V
Block: A group of bits, bytes or words within the flash m e mory array that erase simultan eously
when the Erase command is issued to the device. The Intel StrataFlash® Wireless Memory (L18)
has two block sizes: 16-Kword, and 64-Kword.
Main block: An array block that is usually used to store code and/or data. Main blocks are larger
than parameter blocks.
Parameter block: An array block that is usually used to store frequently changing data or small
system parameters that traditionally would be stored in EEPROM.
Top param eter device: Previously referred to as a top-boot device, a device with its parameter
partition located at the highest phy sical address of its memory map. Parameter blocks within a
parameter partition are located at the high e st physical address of the parameter partition.
Bottom parameter device: Previously referred to as a bottom-boot device, a device with its
parameter partition located at the lowest physical address of its memory map. Parameter blocks
within a parameter partition are located at the lowest p h ys ical address of the parameter partition.
Partition: A group of blocks that share common program/erase circuitry. Blocks within a partition
also share a common status register. I f any block within a partition is being programmed or erased,
only status register data (rather than array dat a ) is available wh en any add ress with in that partition
is read.
Main partition: A partition containing only main blocks.
Parameter partition: A partition containing parameter blocks and main blocks.
1.2 Acronyms
CUI: Command User Interface
MLC: Multi-Level Cell
OTP: One-Time Programmable
PLR: Protection Lock Register
PR: Protection Register
Intel StrataFlash® Wireless Memory (L18)
April 2005 Intel StrataFlash® Wireless Memory (L18) Datasheet
10 Order Number: 251902, Revision: 009
RCR: Read Configuration Register
RFU: Reserved for Future Use
SR: St atus Register
WSM: Write State Machine
1.3 Conventions
VCC: signal or voltage conn ectio n
VCC: signal or volta ge lev el
0x: hexadecimal number prefix
0b: binary numbe r pre fix
SR[4]: Denotes an individual register bit.
A[15:0]: Denotes a group of similarly named signals, such as address or data bus.
A5: Denotes one element of a signal group membership, such as an address.
bit: binary unit
byte: eight bits
word: two bytes, or sixteen bits
Kbit: 1024 bits
KByte: 1024 bytes
KWord: 1024 words
Mbit: 1,048,576 bits
MByte: 1,048,576 bytes
MWord: 1,048,576 words
Intel StrataFlash® Wireless Memory (L18)
Datasheet Intel StrataFlash® Wireless Memory (L18) April 2005
Order Number: 251902, Revision: 009 11
2.0 Functional Overview
The Intel StrataFlash® Wireless Memory (L18) provides read -while- wr ite and read-while-erase
capability with density upg rades th rough 256-Mbit. This family of d e vices pro vides h igh
performance at low v oltage on a 16- bit data bus. Ind ividually eras able memory block s are sized fo r
optimum code and data storage.
Each device density contains one parameter partition and sev eral main partitions. The flash
memory array is grouped into multiple 8-Mbit or 16-Mbit partitions. By dividing the flash memory
into partitions, program or erase operations can take place at the same time as read operations.
Although each partition has write, erase, and burst read capabilities, simultaneous operation is
limited to write or erase in one partition whil e other partitio ns are in read mode. The Intel
StrataFlash® Wireless Memory (L18) allows b urst reads that cross partition bounda r ies. User
application code is responsib le f or ensurin g that burst reads do not cross into a partition that is
programmi ng or erasin g.
Upon initial power up or return from reset, th e device defau lts to asynchronous page-mode read.
Configuring the Read Configuration Register enables synchronous burst-mode reads. In
synchronous burst mode, output data is synchronized with a user-supplied clock signal. A WAIT
signal provides easy CPU-to-flash memory synchronization.
In addition to the enhanced architecture and interface, the Intel StrataFlash® Wireless Memory
(L18) incorporates technolog y that enables fast factory prog ram and erase operations. Designed for
low-voltage systems, the Intel StrataFlash® Wireless Memory (L18) supports read operations with
VCC at 1.8 volt, and erase and program operations with VPP at 1.8 V or 9.0 V. Buffered Enhanced
Factory Pr ogr ammi ng (Bu f fered EFP) prov i des the fastest flash array programming performance
with VPP at 9.0 volt, which increases factory throughput. With VPP at 1.8 V, VCC and VPP can be
tied together for a simple, ultra-low power design. In addition to voltage flexibility, a dedicated
VPP connection provides complete data protection when VPP is less than VPPLK.
A Command User Interface (CUI) is the interface between the system processor and all internal
operations of the Intel StrataFlash® Wireless Memory (L18). An internal Write State Machine
(WSM) automatically executes the algorithms and timings necessary for block erase and program.
A Status Register indicates erase or program completion and any errors that may have occurred.
An industry-standard command sequence invokes program and erase automation. Each erase
operation erases one block. The Erase Suspend feature allows system software to pause an erase
cycle to read or program data in another block. Program Suspend allows system software to pause
programming to read other locations. Data is programmed in word increments.
The Intel StrataFlash® Wireless Memory (L18) offers power savings through Automatic Power
Savings (A PS) mode and standby mode. The dev ice automatically enters APS fol lowing read-cycle
completion. Standby is initiated when the system deselects the device by deasserting CE# or by
asserting RST#. Combined, these features can significantly reduce power consumption.
The Intel StrataFlash® Wireless Memory (L18)’s protection register allows unique flash device
identification that can be used to increase system security. Also, the individual Block Lock feature
provides zero-latency block locking and unlocking.
Intel StrataFlash® Wireless Memory (L18)
April 2005 Intel StrataFlash® Wireless Memory (L18) Datasheet
12 Order Number: 251902, Revision: 009
3.0 Package Information
3.1 VF BGA Packages
Figure 1. 64- and 128-Mbit, 56-Ball VF BGA Package Drawing and Dimensions
E
Seating
Plane
Top View - Ball Side Down Bottom View - Ball Side Up
Y
A
A1
D
A2
A1 Index
Mark
S1
S2
e
b
A1 Index
Mark
A
B
C
D
E
F
G
87654321 87654321
A
B
C
D
E
F
G
Note: D rawing not to scale
Si de V iew
Millimeters Inches
Dimensions Symbol Min Nom Max Notes Min Nom Max
Package Height A 1.000 0.0394
Ball Height A1 0.150 0.0059
Pa ckage Body Thickness A2 0.665 0.0262
Ball (Lead) Width b 0.325 0.375 0.425 0.0128 0.0148 0.0167
Pa ckage Body Length (64Mb, 128Mb) D 7.600 7.700 7.800 0.2992 0.3031 0.3071
Pa ckage Body Width (64Mb, 128Mb) E 8.900 9.000 9.100 0.3504 0.3543 0.3583
Pitch e 0.750 0.0295
Ball (Lead) Count N 56 56
Seating Plane Coplanarity Y 0.100 0.0039
Corne r to Ball A1 Distanc e Along D S1 1.125 1.225 1.325 0.0443 0.0482 0.0522
Corne r to Ball A1 Distanc e Along E S2 2.150 2.250 2.350 0.0846 0.0886 0.0925
Intel StrataFlash® Wireless Memory (L18)
Datasheet Intel StrataFlash® Wireless Memory (L18) April 2005
Order Number: 251902, Revision: 009 13
Figure 2. 256-Mbit, 79-Ball VF BGA Package Drawing and Dimensions
Dimensions Table
Side View
T op View - Ball Side Down Bottom View - Ball Side Up
A2 A
Seating
Plane
Y
A1
S2
A1 I ndex
Mark
E
b
A1 Index
Mark
S1
e
D
A
B
C
D
E
F
G
4567321
8
910111213
A
B
C
D
E
F
G
456732189
10 11 1213
Drawing not to scale
Millimeters Inches
Dimensions Symbol Min Nom Max Notes Min Nom Max
Package Height A 1.000 0.0394
Ball Height A1 0.150 0.0059
Package Body Thickness A2 0.665 0.0262
Ball (Lead) Width b 0.325 0.375 0.425 0.0128 0.0148 0.0167
Package Body L ength (256Mb) D 10.900 11.000 11.100 0.4291 0.4331 0.4370
Package Body Width (256Mb) E 8.900 9.000 9.100 0.3504 0.3543 0.3583
Pitch e 0.750 0.0295
B al l (Lead) Count N 79 79
Seating Plane Coplanarity Y 0.100 0.0039
Corner to Ball A1 Distance Along D S1 0.900 1.000 1.100 0.0354 0.0394 0.0433
Corner to Ball A1 Distance Along E S2 2.150 2.250 2.350 0.0846 0.0886 0.0925
Intel StrataFlash® Wireless Memory (L18)
April 2005 Intel StrataFlash® Wireless Memory (L18) Datasheet
14 Order Number: 251902, Revision: 009
3.2 SCSP Packages
Figure 3. 128-Mbit, 88-ball (80-active ball) SCSP Drawing and Dimensions (8x10x1.2 mm)
Millimeters Inches
Dimensions Symbol Min Nom Max Notes Min Nom Max
Package Height A 1.200 0.0472
Ball Height A1 0.200 0.0079
Pack age B ody Thickn ess A 2 0 .8 6 0 0 . 0 33 9
Ball (L ead) Width b 0.325 0.375 0.425 0.0128 0.0148 0.0167
Pack age B ody Length D 9 . 90 0 1 0 . 0 0 0 1 0 . 10 0 0 .3898 0.3937 0.3976
Pack age B ody Width E 7 . 9 0 0 8 .0 0 0 8 .1 0 0 0 .3110 0.3150 0.3189
Pitch e 0.800 0.0315
Bal l (Lead) Count N 88 88
Seating Plane Coplanarity Y 0.100 0.0039
Corner to Bal l A 1 Di stance Along E S1 1.100 1.200 1.300 0.0433 0.0472 0.0512
Corn er to B all A1 Distance Along D S 2 0.5 0 0 0 .6 0 0 0 .7 0 0 0 .0197 0.0236 0.0276
Top View - Ball Down Bottom View - Ba ll
Up
A
A2
D
E
Y
A1
Drawing not to scale.
S2
S1
A
C
B
E
D
G
F
J
H
K
L
M
e
1
2345678
b
A
C
B
E
D
G
F
J
H
K
L
M
A1 Index
Mark 12345678
8x10x1.2Q
Intel StrataFlash® Wireless Memory (L18)
Datasheet Intel StrataFlash® Wireless Memory (L18) April 2005
Order Number: 251902, Revision: 009 15
Figure 4. 256-Mbit, 88-ball (80-active ball) SCSP Drawing and Dimensions (8x11x1.0 mm)
Millimeters Inches
Dimens ions S ymbol Min Nom Max Notes Min Nom Max
P a ckage Height A 1 .0 0 0.03 94
Ball Height A1 0.117 0.0046
Package Body Thickness A2 0.740 0.0291
Ball (Lead) Width b 0.300 0.350 0.400 0.0118 0.0138 0.015 7
Package Body L ength D 10.900 11.00 11.100 0.4291 0.4331 0.437 0
Package Body Width E 7.900 8.00 8.100 0.3110 0.3150 0.3189
Pi tch e 0. 8 0 0 .0 315
Ball (L ead) Count N 88 88
S eating Plane Coplan a rity Y 0.10 0 0. 0039
C orner to Ball A1 Di stance Al ong E S1 1.100 1.200 1.300 0.043 3 0.0 472 0 .0512
C orner to Ball A1 Di stance Al ong D S2 1.000 1.100 1.200 0.039 4 0.0 433 0 .0472
Top Vi ew - Bal l D own Bottom Vi e w - Ba l l Up
A
A2
D
E
Y
A1
Drawing no t to scale.
S2
S1
A
C
B
E
D
G
F
J
H
K
L
M
e
1
2345678
b
A
C
B
E
D
G
F
J
H
K
L
M
A1 Index
Mark 12345678
Note: Dimensions A1, A2 , and b a re prel i minary
Intel StrataFlash® Wireless Memory (L18)
April 2005 Intel StrataFlash® Wireless Memory (L18) Datasheet
16 Order Number: 251902, Revision: 009
4.0 Ballout and Signal Descriptions
4.1 Si gnal Ball out
This section includes signal ballouts for the following packages:
•VF BGA Package Ballout
•SCSP Package Ballout
4.1.1 VF BGA Package Ballout
The Intel StrataFlash® Wireless Memory (L18) is available in a VF BGA package with 0.75 mm
ball-pitch. Figur e 5 shows the ballout for the 64-Mbit and 128-Mbit devices in the 56-ball VF BGA
package with a 7x8 active-ball matr ix. Figur e 6 shows the device bal lout for the 256 -Mbit device in
the 63-ball VF BGA package with a 7x9 active-ball matrix. Both package densities are ideal for
space-constrained board applications
Note: On lower-density devices, upper-address balls can be treated as NC. (e.g., for 64-Mbit density, A22 will be NC)
Figure 5. 7x8 Active-Ball Matrix for 64-, and 128-Mbit Densities in VF BGA Packages
VFBGA 7x8
Bott om V ie w - Ball S ide Up
V FBGA 7x 8
Top View - Ball Side Down
23456781
A8 VSS VCC VPP A18 A6 A4
A9 A20 CLK RST# A17 A5 A3
A10 A21 WE# A19 A7 A2
A14 WAIT A16 D12 WP# A22
D15 D6 D4 D2 D1 CE# A0
D14 D13 D11 D10 D9 D0 OE#
ADV#
A1
VSSQ VCC D3 VCCQ D8 VSSQ
A11
A12
A13
A15
VCCQ
VSS
D7 D5
A
B
C
D
E
F
G
23456781
A8VSSVCCVPPA18A6A4
A9A20CLKRST#A17A5A3
A10A21WE#A19A7A2
A14WAITA16
D12WP#
A22
D15D6
D4
D2D1CE#A0
D14D13D11D10D9D0
OE#
ADV#
A1
VSSQVCCD3VCCQD8VSSQ
A11
A12
A13
A15
VCCQ
VSS
D7D5
A
B
C
D
E
F
G
Intel StrataFlash® Wireless Memory (L18)
Datasheet Intel StrataFlash® Wireless Memory (L18) April 2005
Order Number: 251902, Revision: 009 17
Note: On lower density devices upper address balls can be treated as RFUs. (A24 is for 512-Mbit and A25 is for 1-Gbit
densities). All ball locations are populated.
Figure 6. 7x9 Active-Ball Matrix for 256-Mbit Density in VF BGA Package
RFU VCCA4 A6 A18 VPP VSS A8 A11
RFU CLK
A3 A5 A17 RST# A20 A9 A12
A25 ADV#A2 A7 A19 WE# A21 A10 A13
A24 A16A1 A22 WP# D12 WAIT A14 A15
A23 D4A0 CE# D1 D2 D6 D15 VCCQ
RFU D11OE# D0 D9 D10 D13 D14 VSS
RFU VCCVSSQ D8 VCCQ D3 D5 VSSQ D7
Bottom View - Ball Side Up
A
B
C
D
E
F
G
DU
DU DU
DU
DU
DU DU
DU DU
DU DU
DU
DU
DU DU
DU
11 101213 7 5 4 3 2 1
896
RFUVCC A4A6A18VPPVSSA8A11
RFUCLK A3A5A17RST#A20A9A12
A25
ADV# A2A7A19WE#
A21A10
A13
A24A16 A1A22WP#D12WAITA14A15
A23
D4 A0CE#D1D2
D6D15
VCCQ
RFUD11 OE#D0D9D10D13D14VSS
RFUVCC VSSQD8VCCQD3D5VSSQD7
Top View- Ball Side Down
A
B
C
D
E
F
G
DU
DUDU
DU
DU
DUDU
DU
DU
DUDU
DU
DU
DUDU
DU
1110 12 1375432
1896
Intel StrataFlash® Wireless Memory (L18)
April 2005 Intel StrataFlash® Wireless Memory (L18) Datasheet
18 Order Number: 251902, Revision: 009
4.1.2 SCSP Package Ballout
The L18 wireless memory in QUAD+ ballout device is available in an 88-ball (80-active ball)
Stacked Chip Scale Package (SCSP) for the 128- and 256-Mbit devices. For Mechanical
Information, refer to Section 3.0, “Package Information” on page 12.
Figure 7. 88-Ball (80-Active Ball) SCSP Package Ballout
Flash specific
SR AM /PSR AM sp ecific
Global
Legend:
Top View - Ball Side Down
87654321
A
B
C
D
E
F
G
H
J
K
L
M
DU
A4
DU DU DU
DUDUDU DU
A5
A3
A2 A7
A1 A6
A0
A18 A19 VSS
VSSA23
A24
A25
A17
F2-VCC
CLK
A21
A22 A12
A11
A13A9P1-CS#
F-VPP,
F-VPEN
A20 A10 A15
F-WE# A8
D8 D2 D10 D5 D13 WAIT
A14 A16
F1-CE# P-Mode
VSS VSS VSS
P2-CS#
F1-VCC
F2-VCC VCCQF3-CE#
D0 D1
D9
D3
D4 D6
D7
D15D11
D12 D14
F1-OE#
F2-OE#
P-VCC
S-CS2
R-WE#
R-UB#
R-LB#
R-OE#
S-VCC
S-CS1#
F1-VCC
F-WP# ADV#
F-RST#
F2-CE#
VCCQ
VSS VSSVCCQ VSS
Intel StrataFlash® Wireless Memory (L18)
Datasheet Intel StrataFlash® Wireless Memory (L18) April 2005
Order Number: 251902, Revision: 009 19
4.2 Signal Descriptions
This section includes signal descriptions for the following packages:
•VF BGA Package Signal Descriptions
•SCSP Package Signal Descriptions
4.2.1 VF BGA Package Signal Descriptions
Table 1 de scr ib e s the active signals used on the Intel StrataFlash® Wireless Memory (L18), VF
BGA package.
Table 1. Signal Descriptions (Sheet 1 of 2)
Symbol Type Name and Funct ion
A[MAX:0] Input ADDRESS: Device address inputs. 64-Mbit: A[21:0]; 128-Mbit: A[22:0]; 256-Mbit: A[23:0].
DQ[15:0] Input/
Output
DA TA INPUT/OUTPUTS: I nputs dat a and commands during write cycles; outputs dat a during memory,
S tatus Register, Protection Register, and Read Configuration Register reads. Data balls float when the
CE# or OE# are deasserted. Data is internally latched during writes.
ADV# Input
ADDRESS VALID: Active-low input. During synchronous read operations, addresses are latched on
the rising edge of ADV#, or on the next valid CLK edge with ADV# low, whichever occu rs first.
In asynchronous mode, the address is latched when ADV# going high or continuously flows through if
ADV# is held low.
CE# Input CHIP ENABLE: Active-low input. CE#-low selects the device. CE#-high deselects the device, placing it
in standby, with DQ[15:0] and WAIT in High-Z.
CLK Input CLOCK: Synchroniz es the device with the system’s bus frequency in synchronous-read mode and
increments the internal address generator. During synchronous read operations, addresses are latched
on the rising edge of ADV#, or on the next valid CLK edge with ADV# low, whichever occurs first.
OE# Input OUTPUT ENABLE: Active-low input. OE#-low enables the device’s output data buffers during read
cycles. OE#-high places the data outputs in High-Z and WAIT in High-Z.
RST# Input RESET: Active-low input. RST# resets internal automation and inhibits write operations. This provides
data protection during power transitions. RST#-high enables normal operation. Exit from reset places
the device in asynchronous read array mode.
WAIT Output
WAIT: Indicates data valid in synchronous array or non-array burst reads. Configuration Register bit 10
(RCR[10], WT) determines its polarity when asserted. With CE# and OE# at VIL, WAIT’s active output
is VOL or VOH when CE# and OE# are asserted. WAIT is high-Z if CE# or OE# is VIH.
• In synchronous array or non-array read modes, WAIT indicates invalid data when asserted and
valid data when deasserted.
• In asynch ronous page mode, and all write modes, WAIT is deasserted.
WE# Input WRITE ENABLE: Active-low input. WE# controls writes to the device. Address and data are latched on
the rising edge of WE#.
WP# Input WRITE PROTECT: Active-low input. WP#-low enables the lock-down mechanism. Blocks in lock-down
cannot be unlocked with the Unlock command. WP#-high overrides the lock-down function enabling
blocks to be erased or programmed using software commands.
VPP Power
/lnput
Erase and Program Power: A valid voltage on this pin allows erasing or programming. Memory
contents cannot be altered when VPP ≤ VPPLK. Block erase and program at invalid VPP voltages should
not be attempted.
Set VPP = VCC for in-system program and erase operations. To accommodate resistor or diode drops
from the system supply, the VIH level of VPP can be as low as VPPLmin. VPP must remain above
VPPLmin to perform in-system program or erase. VPP may be 0 V during read operations.
VPPH can be applied to main blocks for 1000 cycles maximum and to parameter blocks for 2500 cycles.
VPP can be connected to 9 V for a cumulative total not to exceed 80 hours. Extended use of this pin at
9 V may derate flash performance/b ehavior.
Intel StrataFlash® Wireless Memory (L18)
April 2005 Intel StrataFlash® Wireless Memory (L18) Datasheet
20 Order Number: 251902, Revision: 009
VCC Power Device Core Power Supply: Core (logic) source voltage. Writes to the flash array are inhibited when
VCC ≤ VLKO. Operations at invalid VCC voltages should not be attempted.
VCCQ Power Output Power Supply: Output-driver source voltage. This ball can be tied directly to VCC if operating
within VCC range.
VSS Power Ground: Ground reference for device logic voltages. Connect to system ground.
VSSQ Power Ground: Ground reference for device output voltages. Connect to system ground.
DU — Do Not Use: Do not use this ball. This ball should not be connected to any power supplies, signals or
other balls, and must be left floating.
RFU — Reserved for Future Use: Res erved by Intel for future device functionality and enhancement.
Table 1. Signal Descriptions (Sheet 2 of 2)
Symbol Type Name and Function
Intel StrataFlash® Wireless Memory (L18)
Datasheet Intel StrataFlash® Wireless Memory (L18) April 2005
Order Number: 251902, Revision: 009 21
4.2.2 128/0 and 256/0 SCSP Package Signal Descriptions
Table 2 describes the active signals used on the 128/0 and 256/0 SCSP.
Table 2. Device Signal Descriptions for SCSP (Sheet 1 of 2)
Symbol Type Description
A[Max:0] Input ADDRESS INPUTS: Inputs for all die addresses during read and write operations.
• 128-Mbit Die: A[Max] = A22
• 256-Mbit Die: A[Max] = A23
DQ[15:0] Input/
Output
DATA INPUTS/OUTPUTS: Inputs data and commands during write cycles, outputs data during read
cycles. Data signals float when the device or its outputs are deselected. Data is internally latched
during writes.
F1-CE#
F2-CE#
F3-CE# Input
FLASH CHIP ENABLE: Low-true: selects the associated flash memory die. When asserted, flash
internal control logic, input buffers, decoders, and sense am plifiers are active. When deasserted, the
associated flash die is deselected, power is reduced to standby levels, data and WAIT outputs are
placed in high-Z state.
F1-CE# selects the flash die.
F2-CE# and F3-CE# are available on stacked combinations with two or three flash dies else they are
RFU. They each can be tied high to VCCQ through a 10K-ohm resistor for future design flexibility.
S-CS1#
S-CS2 Input
SRAM CHIP SELECTS: When both SRAM chip selects are asserted, SRAM internal control logic,
input buffers, decoders, and sense amplifiers are active. When either/both SRAM chip selects are
deasserted (S-CS1# = VIH or S-CS2 = VIL), the SRAM is deselected and its power is reduced to
standby levels.
Treat this signal as NC (No Connect) for this device.
P-CS# Input
PSRAM CHIP SELECT: Low-true; when asserted, PSRAM internal control logic, input buffers,
decoders, and sense amplifiers are active. When deasserted, the PSRAM is deselected and its power
is reduced to standby levels.
Treat this signal as NC (No Connect) for this device.
F1-OE#
F2-OE# Input
FLASH OUTPUT ENABLE: Low-true; enables the flash output buffers. OE#-high disables the flash
output buffers, and places the flash outputs in High-Z.
F1-OE# controls the outputs of the flash die.
F2-OE# is available on stacked combinations with two or three flash dies else it is RFU. It can be
pulled high to VCCQ through a 10K-ohm resistor for future design flexibility.
R-OE# Input RAM OUTPUT ENABLE: Low-true; R-OE#-low enables the selected RAM output buf fers. R-OE#-high
disables the RAM output buffers, and places the selected RAM outputs in High-Z.
Treat this signal as NC (No Connect) for this device.
WE# Input FLASH WRITE ENABLE: Low-true; WE# controls writes to the selected flash die. Address and data
are latched on the rising edge of WE#.
R-WE# Input RAM WRITE ENABLE: Low-t rue; R-WE # controls writes to the selected RAM die.
Treat this signal as NC (No Connect) for this device.
CLK Input
FLASH CLOCK: Synchronizes the device with the system’ s bus frequency in synchronous-read mode
and increments the internal address generator. During synchronous read operations, addresses are
latched on the rising edge of ADV#, or on the next valid CLK edge with ADV# low, whichever occurs
first.
WAIT Output
FLASH WAIT: Indicates data valid in synchronous array or non-array burst reads. Configuration
Register bit 10 (RCR[10], WT) determines its polarity when asserted. With CE# and OE# at VIL,
WAIT’s active output is VOL or VOH when CE# and OE# are asserted. WAIT is high-Z if CE# or OE# is
VIH.
• In synchronous array or non-array read modes, WAIT indicates invalid data when asserted and
valid data when deasserted.
• In asy nchronous page mode, and all write modes, WA IT is deasserted.
Intel StrataFlash® Wireless Memory (L18)
April 2005 Intel StrataFlash® Wireless Memory (L18) Datasheet
22 Order Number: 251902, Revision: 009
WP# Input
FLA SH WRITE PROT E C T: Low-true; WP# enables/disables the lock-down protection mechanism of
the selected flash die. WP#-low enables the lock-down mechanism - locked down blocks cannot be
unlocked with software commands. WP#-high disables the lock-down mechanism, allowing locked
down blocks to be unlocked with software commands.
ADV# Input
FLASH ADDRESS VALID: Active-low input. During synchronous read operations, addresses are
latched on the rising edge of ADV#, or on the next valid CLK edge with ADV# low, whichever occurs
first.
In asynchronous mode, the address is latched when ADV# going high or continuously flows through if
ADV# is held low.
R-UB#
R-LB# Input RAM UPPER / LOWER BYTE ENABLES: Low-true; During RAM reads, R-UB#-low enables the RAM
high order bytes on DQ[15:8], and R-LB#-low enables the RAM low-order bytes on DQ[7:0].
Treat this signal as NC (No Connect) for this device.
RST# Input FLASH RESET: Low-true; RST#-low initializes flash internal circuitry and disables flash operations.
RST#-high enables flash operation. Exit from reset places the flash in asynchronous read array mode.
P-Mode Input PSRAM MODE: Low-true; P-MODE is used to program the configuration register, and enter/exit low
power mode.
Treat this signal as NC (No Connect) for this device.
VPP,
VPEN Power/
Input
Flash Program/Erase Power: A valid voltage on this pin allows erasing or programming. Memory
contents cannot be altered when VPP ≤ VPPLK. Block erase and program at invalid VPP voltages should
not be attempted.
Set VPP = VCC for in-system program and erase operations. To accommodate resistor or diode drops
from the system supply, the VIH level of VPP can be as low as VPPLmin. VPP must remain above
VPPLmin to perform in-system flas h modification. VPP may be 0 V during read operations.
VPPH can be applied to main blocks for 1000 cycles maximum and to parameter blocks for 2500
cycles. VPP can be connected to 9 V for a cumulative total not to exceed 80 hours. Extended use of
this pin at 9 V may reduce block cycling capability.
VPEN (Erase/Program/Block Lock Enables) is not available for L18 products.
F1-VCC
F2-VCC Power Flash Logic Power : F1-VCC supplies power to the core logic of flash die #1; F2-VCC supplies power
to the core logic of flash die #2. Write operations are inhibited when VCC ≤ VLKO. Device operations at
invalid VCC voltages should not be attempted.
S-VCC Power SRAM Power Supply: Supplies power for SRAM operations.
Treat this signal as NC (No Connect) for this device.
P-VCC Power PSRA M Power Supp ly : Supplies power for PSRAM operations.
Treat this signal as NC (No Connect) for this device.
VCCQ Power Flash I/O Power: Supply power for the input and output buffers.
VSS Power Ground: Connect to system ground. Do not float any VSS connection.
RFU — Reserved for Future Use: Reserve for future device functionality/ enhancements. Contact Intel
regarding their future use.
DU — Do Not Use: Do not connect to any other signal, or power supply; must be left floating.
NC — No Connect: No internal connection; can be driven or floated.
Table 2. Device Signal Descriptions for SCSP (Sheet 2 of 2)
Intel StrataFlash® Wireless Memory (L18)
Datasheet Intel StrataFlash® Wireless Memory (L18) April 2005
Order Number: 251902, Revision: 009 23
4.3 Memory Map
See Table 3 and Table 4. The memory array is divided into multiple partitions; one parameter
partition and several main partitions:
•64-Mbit device. This contains eight partitions: one 8-Mbit parameter partition, seven 8-Mbit
main partiti ons.
•128-Mbit device. This contains sixteen partitions: one 8-Mbit param eter partition, fifteen 8-
Mbit main partitions.
•256-Mbit device. This contains sixteen partitions: one 16-Mbit parameter partition, fifteen 16-
Mbit main partitio ns.
Table 3. Top Parameter Memory Map
Size (KW) Blk 64-Mbit Size (KW) Blk 128-Mbit
43
8-Mbit Paramete r
Partition
One Partition
16 66 3FC000-3FFFFF
8-Mbit Paramete r
Partition
One Partition
16 130 7FC000-7FFFFF
16 65 3F8000-3FBFFF 16 129 7F8000-7FBFFF
16 64 3F4000-3F7FFF 16 128 7F4000-7F7FFF
16 63 3F0000-3F3FFF 16 127 7F0000-7F3FFF
64 62 3E0000-3EFFFF 64 126 7E0000-7EFFFF
…
…
…
…
…
…
64 56 380000-38FFFF 64 120 780000-78FFFF
8-Mbit Main
Partition
Seven
Partitions
64 55 370000-37FFFF
8-Mbit Main
Partitions
Fifteen
Partitions
64 119 770000-77FFFF
…
…
…
…
64 0 000000-00FFFF 64 0 000000-00FFFF
Size (KW) Blk 256-Mbit
16-Mbit Pa ramete r
Partition
One Partition
16 258 FFC000-FFFFFF
16 257 FF8000-FFBFFF
16 256 FF4000-FF7FFF
16 255 FF0000-FF3FFF
64 254 FE0000-FEFFFF
…
…
…
64 240 F00000-FFFFFF
16-Mbit Main Partitions
Seven
Partitions
64 239 EF0000-EFFFFF
…
64 128 800000-80FFFF
Eight
Partitions
64 127 7F0000-7FFFFF
…
64 0 000000-00FFFF
Intel StrataFlash® Wireless Memory (L18)
April 2005 Intel StrataFlash® Wireless Memory (L18) Datasheet
24 Order Number: 251902, Revision: 009
Table 4. Bottom Parameter Memory Map
Size (KW) Blk 64-Mbit Size (KW) Blk 128-Mbit
8-Mbit Main
Partitions
Seven
Partitions
64 66 3F0000-3FFFFF
8-Mbit Main
Partitions
Fifteen
Partitions
64 130 7F0000-7FFFFF
…
…
…
…
…
…
64 11 080000-08FFFF 64 11 080000-08FFFF
8-Mbit Parameter
Partition
One Partition
64 10 070000-07FFFF
8-Mbit Parameter
Partition
One Partition
64 10 070000-07FFFF
…
…
…
…
…
…
64 4 010000-01FFFF 64 4 010000-01FFFF
16 3 00C000-00FFFF 16 3 00C000-00FFFF
16 2 008000-00BFFF 16 2 008000-00BFFF
16 1 004000-007FFF 16 1 004000-007FFF
16 0 000000-003FFF 16 0 000000-003FFF
Size (KW) Blk 256-M bit
16-Mbit Main Partitions
Eight
Partitions
64 258 FF0000-FFFFFF
…
…
…
64 131 800000-80FFFF
Seven
Partitions
64 130 7F0000-7FFFFF
…
…
…
64 19 100000-10FFFF
16-Mbit Parameter
Partition
One Partition
64 18 0F0000-0FFFFF
…
…
…
64 4 010000-01FFFF
16 3 00C000-00FFFF
16 2 008000-00BFFF
16 1 004000-007FFF
16 0 000000-003FFF
Intel StrataFlash® Wireless Memory (L18)
Datasheet Intel StrataFlash® Wireless Memory (L18) April 2005
Order Number: 251902, Revision: 009 25
5.0 Maximum Ratings and Op eratin g Condi tion s
5.1 Absolute Maximum Ratings
Warning: Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage.
These are stress ratings only.
5.2 Operating Conditions
Warning: Operation beyond the “Operating C ond itio ns ” i s not reco mmend ed an d ex ten ded expo su re beyond
the “Operating Conditions” may affect device reliability.
Parameter Maximum Rating Notes
Temperature under bias –25 °C to +85 °C
S torage temperature –65 °C to +125 °C
Voltage on any signal (except VCC, VPP) –0.5 V to +2.5 V 1
VPP voltage –0.2 V to +10 V 1,2,3
VCC v ol tage –0 .2 V to + 2 .5 V 1
VCC Q vol tage –0 .2 V to +2.5 V 1
Output short circuit current 100 mA 4
Notes:
1. Voltages shown are specified with respect to VSS. Minimum DC voltage is –0.5 V on input/output
signals and –0.2 V on VCC, VCCQ, and VPP. During transitions, this level may undershoot to –2.0 V for
periods < 20 ns. Maximum DC voltage on VCC is VCC +0.5 V, which, during transitions, may overshoot
to VCC +2.0 V for periods < 20 ns. Maximum DC voltage on input/output signals and VCCQ is VCCQ
+0.5 V, which, during transitions, may overshoot to VCCQ +2.0 V for periods < 20 ns.
2. M axim um DC voltage on VPP may overshoot to +14.0 V for periods < 20 ns.
3. Program/erase voltage is typically 1.7 V – 2.0 V. 9.0 V can be applied for 80 hours maximum total, to
any blocks for 1000 cycles maximum. 9.0 V program/erase voltage may reduce block cycling
capability.
4. O utput shorted for no more than one second. No more than one output shorted at a time.
Symbol Parameter Min Max Units Notes
TCOperating Temperat ure –25 +85 °C 1
VCC VCC Supply Voltage 1.7 2.0
V
VCCQ I/O Supply Voltage 1.8 V Range 1.7 2.0
1.8 V Extended Range 1.35 2.0
VPPL VPP Voltage Supply (Logic Level) 0.9 2.0
2
VPPH Factory word programming VPP 8.5 9.5
tPPH Maxi mum VPP Hours VPP = VPPH - 80 Hours
Block
Erase
Cycles
Main and Parameter Blocks V PP = VCC 100,000 - CyclesMain Blocks VPP = VPPH - 1000
Parameter Blocks VPP = VPPH - 2500
Notes:
1. TC = Case temperature
2. In typical operation, the VPP program voltage is VPPL. VPP can be connected to 8.5 V – 9.5 V for 1000
cycles on main blocks and 2500 cycles on parameter blocks.
Intel StrataFlash® Wireless Memory (L18)
April 2005 Intel StrataFlash® Wireless Memory (L18) Datasheet
26 Order Number: 251902, Revision: 009
6.0 Electrical Specifications
6.1 DC Current Characteristics
Sym Parameter VCCQ 1.7 V – 2.0 V
1.35 V - 2.0 V Unit Test Conditions Notes
Typ Max
ILI Input Load Current - ±1 µA VCC = VCCMax
VCCQ = VCCQMax
VIN = VCCQ or VSS 1
ILO Output
Leakage
Current DQ[15:0], WAIT - ±1 µA VCC = VCCMax
VCCQ = VCCQMax
VIN = VCCQ or VSS
ICCS
ICCD
VCC Standby,
Power Down
64-Mbit 15 30
µA
VCC = VCCMax
VCCQ = VCCQMax
CE# = VCCQ
RST# = VCCQ (for ICCS)
RST# = GND (for ICCD)
WP# = VIH 1,2
128-Mbit 20 70
256-Mbit 25 110
ICCAPS APS
64-Mbit 15 30
µA
VCC = VCCMax
VCCQ = VCCQMax
CE# = VSSQ
RST# = VCCQ
All inputs are at rail to rail (VCCQ
or VSSQ).
128-Mbit 20 70
256-Mbit 25 110
ICCR Average
VCC Read
Current
Asynchronous Single-Word
f = 5MHz (1 CLK) 13 15 mA
VCC = VCCMax
CE# = VIL
OE# = VIH
Inputs: VIL or
VIH
1
Page-Mode Read
f = 13 MHz (5 CLK) 8 9 mA 4-Word Read
Synchronous Burst Read
f = 40MHz, LC = 3
12 16 mA Burst length = 4
14 18 mA Burst length = 8
16 20 mA Burst length = 16
20 25 mA Burst length =
Continuous
Synchronous Burst Read
f = 54MHz, LC = 4
15 18 mA Burst length = 4
18 22 mA Burst length = 8
21 25 mA Burst length = 16
22 27 mA Burst Length =
Continuous
ICCW,
ICCE
VCC Program Current,
VCC Erase Current
35 50 mA VPP = VPPL, program/erase in
progress 1,3,4,
7
25 32 mA VPP = VPPH, program/erase in
progress 1,3,5,
7
ICCWS,
ICCES
VCC Program Suspend Current,
VCC Erase Suspend Current
64-Mbit 15 30 µA CE# = V CCQ; suspend in progress 1,6,3128-Mbit 20 70
256-Mbit 25 110
IPPS,
IPPWS,
IPPES
VPP Standby Current,
VPP Program Suspend Current,
VPP Erase Suspend Current 0.2 5 µA VPP = VPPL, suspend in progress 1,3
Intel StrataFlash® Wireless Memory (L18)
Datasheet Intel StrataFlash® Wireless Memory (L18) April 2005
Order Number: 251902, Revision: 009 27
6.2 DC Voltage Characteristics
IPPR VPP Read 2 15 µA VPP ≤ VCC
1,3
IPPW VPP Program Current 0.05 0.10 mA VPP = VPPL, program in progress
822 V
PP = VPPH, program in progress
IPPE VPP Erase Current 0.05 0.10 mA VPP = VPPL, erase in progress
822 V
PP = VPPH, erase in progress
Notes:
1. All currents are RMS unless noted. Typical values at typical VCC, TC = +25°C.
2. ICCS is the average current measu red over any 5 ms time interval 5 µs after CE# is deasserted.
3. Sampled, not 100% tested.
4. VCC read + program current is the sum of VCC read and VCC program currents.
5. VCC read + erase current is the sum of VCC read and VCC erase currents.
6. ICCES is specified with the device deselected. If device is read while in erase suspend, current is ICCES
plus ICCR
7. ICCW, ICCE measured over typical or max times specified in Section 7.7, “Program and Erase
Characteristics” on page 41
Sym Parameter VCCQ 1.35 V – 2.0 V 1.7 V – 2.0 V Unit Test Condition Notes
Min Max Min Max
VIL Input Low Voltage 0 0.2 0 0.4 V 1
VIH Input High Voltage VCCQ – 0.2 VCCQ VCCQ – 0.4 VCCQ V1
VOL Output Low Voltage - 0.1 - 0.1 V VCC = VCCMin
VCCQ = V CCQMin
IOL = 100 µA
VOH Output High Voltage VCCQ – 0.1 - V CCQ – 0.1 - V VCC = VCCMin
VCCQ = V CCQMin
IOH = –100 µA
VPPLK VPP Lock-Out Voltage - 0.4 - 0.4 V 2
VLKO VCC Lock Voltage 1.0 - 1.0 - V
VLKOQ VCCQ Lock Voltage 0.9 - 0.9 - V
NOTES:
1. VIL can undershoot to –0.4 V and VIH can overshoot to VCCQ + 0.4 V for durations of 20 ns or less.
2. VPP ≤ VPPLK inhibits erase and program operations. Do not use VPPL and VPPH outside their valid ranges.
Sym Parameter VCCQ 1.7 V – 2.0 V
1.35 V - 2.0 V Unit Test Condit ions Notes
Typ Max
Intel StrataFlash® Wireless Memory (L18)
April 2005 Intel StrataFlash® Wireless Memory (L18) Datasheet
28 Order Number: 251902, Revision: 009
7.0 AC Characteristics
7.1 AC Test Conditions
Note: AC test inputs are driven at VCCQ for Logic "1" and 0.0 V for Logic "0." Input/output timing begins/ends
at VCCQ/2. Input rise and fall times (10% to 90%) < 5 ns. Worst case speed occurs at VCC = VCCMin.
Notes:
1. S ee the following table for component values.
2. Test configuration component value for worst case speed conditions.
3. CL includes jig capacitance.
Figure 8. AC Input/Output Reference Waveform
IO_REF.WMF
Input V
CCQ
/2 V
CCQ
/2 Output
V
CCQ
0V
Test Points
Figure 9. Transient Equivalent Testing Load Circuit
Device
Under Test Ou
t
CL
Table 5. Test configuration component value for worst case speed conditions
Test Configuration CL (pF)
1.35 V Standard Test 30
1.7 V Standard Test 30
Intel StrataFlash® Wireless Memory (L18)
Datasheet Intel StrataFlash® Wireless Memory (L18) April 2005
Order Number: 251902, Revision: 009 29
7.2 Capacitance
Figure 10. Clock Input AC Waveform
CLK [C]
V
IH
V
IL
R203R202
R201
CLKINPUT.WMF
Table 6. Capacitance
Symbol Parameter Signals Min Typ Max Unit Condition Note
CIN Input Capacitance
Address, CE#,
WE#, OE#,
RST#, CLK,
ADV# , W P#
26 7 pF
Ty p temp = 25 °C,
Max t emp = 85 ° C,
VCC=VCCQ=(0- 1.95) V,
Silicon die
1,2
COUT Output Capacitance Data, WAIT 2 4 5 pF
NOTES:
1. S ampled, not 100% tested.
2. S ilicon die capacitance only, add 1 pF for discrete packages.
Intel StrataFlash® Wireless Memory (L18)
April 2005 Intel StrataFlash® Wireless Memory (L18) Datasheet
30 Order Number: 251902, Revision: 009
7.3 AC Read Specifications (VCCQ = 1.35 V – 2.0 V)
Num Symbol Parameter All DensitiesSpeed –90 Units Notes
Min Max
Asynchronous Specifications
R1 tAVAV Read cycle time 90 - ns 6
R2 tAVQV A dd ress to output val id - 90 ns
R3 tELQV CE# low to output valid - 90 ns
R4 tGLQV OE# low to output valid - 25 ns 1,2
R5 tPHQV RST# high to output valid - 150 ns 1
R6 tELQX CE# low to output in low-Z 0 - ns 1,3
R7 tGLQX OE# low to output in low-Z 0 - ns 1,2,3
R8 tEHQZ CE# high to output in high-Z - 20 ns 1,3R9 tGHQZ OE# high to output in high-Z - 20 ns
R10 tOH Output hold from first occurring address, CE#, or OE# change 0 - ns
R11 tEHEL CE# pulse wid th high 17 - ns 1
R12 tELTV CE# low to WAIT valid - 17 ns 1
R13 tEHTZ CE# high to WAIT high Z - 17 ns 1,3
R15 tGLTV OE# low to WAIT valid - 17 ns 1
R16 tGLTX OE# low to WAIT in low-Z 0 - ns 1,3
R17 tGHTZ OE# high to WAIT in high-Z - 20 ns 1,3
Latching Specifications
R101 tAVVH Address setup to ADV# high 7 - ns
1
R102 tELVH CE# low to ADV# high 10 - ns
R103 tVLQV ADV# low to output valid - 90 ns
R104 tVLVH ADV# pulse width low 7 - ns
R105 tVHVL ADV# pulse width high 7 - ns
R106 tVHAX Address hold from ADV# high 7 - ns 1,4
R108 tAPA Page address access - 30 ns 1
R111 tphvh RST# high to ADV# high 30 - ns 1
Clock Specifications
R200 fCLK CLK frequency - 47 MHz
1,3
R201 tCLK CLK period 21.3 - ns
R202 tCH/CL CLK high/low time 4.5 - ns
R203 tFCLK/RCLK CLK fall/rise time - 3 ns
Synchronous Specifications
R301 tAVCH/L Address setup to CLK 7 - ns
1
R302 tVLCH/L ADV# low setup to CLK 7 - ns
R303 tELCH/L CE# low setup to CLK 7 - ns
R304 tCHQV / tCLQV CLK to output valid - 17 ns
R305 tCHQX Output hold from CLK 3 - ns 1,5
R306 tCHAX Address hold from CLK 7 - ns 1,4,5
R307 tCHTV CLK to WAIT valid - 17 ns 1,5
R311 tCHVL CLK Valid to ADV# Setup 0 - ns 1
R312 tCHTX WAIT Hold from CLK 3 - ns 1,5
NOTES:
1. S ee Figure 8, “AC Input/Output Reference Waveform” on page 28 for timing measurements and max allowable input slew
rate.
2. OE# may be delayed by up to tELQV – tGLQV after CE#’s falling edge without impact to tELQV.
3. Sampled, not 100% tested.
4. Address hold in synchronous burst mode is tCHAX or tVHAX, whichever timing specification is satisfied first.
5. Applies only to subsequent synchronous reads.
6. T he specifications in this table will only be used by customers (1) who desire a 1.35 to 2.0 VCCQ operating range OR (2)
who desire to transition their host controller from a 1.7 V to 2.0 V VCCQ voltage now to a lower range in the future.
Intel StrataFlash® Wireless Memory (L18)
Datasheet Intel StrataFlash® Wireless Memory (L18) April 2005
Order Number: 251902, Revision: 009 31
7.4 AC Read Specifications for 64-Mbit and 128-Mbit Densities
(VCCQ = 1.7 V – 2.0 V)
Num Symbol Parameter Speed –85 Units Notes
Min Max
Asynchro nous Specif ications
R1 tAVAV Read cycle time 85 - ns 6
R2 tAVQV Address to output valid - 85 ns
R3 tELQV CE# low to output valid - 85 ns
R4 tGLQV OE# low to output valid - 20 ns 1,2
R5 tPHQV RST# high to output valid - 150 ns 1
R6 tELQX CE# low to output in low-Z 0 - ns 1,3
R7 tGLQX OE# low to output in low-Z 0 - ns 1,2,3
R8 tEHQZ CE# high to output in high-Z - 17 ns 1,3R9 tGHQZ OE# high to output in high-Z - 17 ns
R10 tOH Output hold from first occ urring address, CE#, or OE# change 0 - ns
R11 tEHEL CE# pulse width high 14 - ns 1
R12 tELTV CE# low to WAIT valid - 14 ns 1
R13 tEHTZ CE# high to WAIT high Z - 14 ns 1,3
R15 tGLTV OE# low to WAIT valid - 14 ns 1
R16 tGLTX OE# low to WAIT in low-Z 0 - ns 1,3
R17 tGHTZ OE# high to WAIT in high-Z - 17 ns 1,3
Latchi ng Spec ifications
R101 tAVVH Address setup to ADV# high 7 - ns 1
R102 tELVH CE# low to ADV# high 10 - ns
R103 tVLQV ADV# low to output valid - 85 ns 1,6
R104 tVLVH ADV# pulse width low 7 - ns 1
R105 tVHVL ADV# pulse width high 7 - ns
R106 tVHAX Address hold from ADV# high 7 - ns 1,4
R108 tAPA Page address access - 25 ns 1
R111 tphvh RST# high to ADV# high 30 - ns 1
Clock Specifications
R200 fCLK CLK freq uency - 54 MHz
1,3
R201 tCLK CLK period 18.5 - ns
R202 tCH/CL CLK high/low time 3.5 - ns
R203 tFCLK/RCLK CLK fall/rise time - 3 ns
Synchr onous Specif ic a tions
R301 tAVCH/L Address setup to CLK 7 - ns
1
R302 tVLCH/L ADV# low setup to CLK 7 - ns
R303 tELCH/L CE# low setup to CLK 7 - ns
R304 tCHQV / tCLQV CLK to output valid - 14 ns
R305 tCHQX Output hold from CLK 3 - ns 1,5
R306 tCHAX Address hold from CLK 7 - ns 1,4,5
R307 tCHTV CLK to WAIT valid - 14 ns 1,5
R311 tCHVL CLK Valid to ADV# Setup 0 - ns 1
R312 tCHTX W AIT Hold from CLK 3 - ns 1,5
NOTES:
1. S ee Figure 8, “AC Input/Ou tput Reference Waveform” on page 28 for timing measurements and maximum allowable
input slew rate.
2. O E# ma y be delayed by up to tELQV – tGLQV after CE#’s falling edge without impact to tELQV.
3. Sampled, not 100% tested.
4. A ddress hold in synchronous burst mode is tCHAX or tVHAX, whichever timing specification is satisfied first.
5. A pplies only to subsequent synchronous rea ds.
6. The specifications in Sect ion 7.3 will only be used by customers (1) who desire a 1.35 to 2.0 VCCQ operating range OR
(2) who desire to transition their host controller from a 1.7 V to 2.0 V VCCQ voltage now to a lower range in the future.
Intel StrataFlash® Wireless Memory (L18)
April 2005 Intel StrataFlash® Wireless Memory (L18) Datasheet
32 Order Number: 251902, Revision: 009
7.5 AC Read Specifications for 256-Mbit Density (VCCQ = 1. 7 V –
2.0 V)
Num Symbol Parameter Speed –85 Units Notes
Min Max
Asynchronous Specifications
R1 tAVAV Read cycle time VCC = VCCQ = 1.8 V – 2.0 V 85 - ns
6
VCC = VCCQ = 1.7 V – 2.0 V 88 -
R2 tAVQV Address to output valid VCC = VCCQ = 1.8 V – 2.0 V -85
ns
VCC = VCCQ = 1.7 V – 2.0 V -88
R3 tELQV CE# low to output valid VCC = VCCQ = 1.8 V – 2.0 V -85
ns
VCC = VCCQ = 1.7 V – 2.0 V -88
R4 tGLQV OE# low to output valid - 20 ns 1,2
R5 tPHQV RST# high to output valid - 150 ns 1
R6 tELQX CE# low to output in low-Z 0 - ns 1,3
R7 tGLQX OE# low to output in low-Z 0 - ns 1,2,3
R8 tEHQZ CE# high to output in high-Z - 17 ns 1,3R9 tGHQZ OE# high to output in high-Z - 17 ns
R10 tOH Output hold from first occurring address, CE#, or OE# change 0 - ns
R11 tEHEL CE# pulse width high 14 - ns 1
R12 tELTV CE# low to WAIT valid - 14 ns 1
R13 tEHTZ CE# high to WAIT high Z - 14 ns 1,3
R15 tGLTV OE# low to WAIT valid - 14 ns 1
R16 tGLTX OE# low to WAIT in low-Z 0 - ns 1,3
R17 tGHTZ OE# high to WAIT in high-Z - 17 ns 1,3
Latching Specifications
R101 tAVVH Address setup to ADV# high 7 - ns 1
R102 tELVH CE# low to ADV# high 10 - ns
R103 tVLQV ADV# low to output valid VCC = VCCQ = 1.8 V – 2.0 -85
ns 1,6
VCC = VCCQ = 1.7 V – 2.0 -88
R104 tVLVH ADV# pulse width low 7 - ns 1
R105 tVHVL ADV# pulse width high 7 - ns
R106 tVHAX Address hold from ADV# high 7 - ns 1,4
R108 tAPA Page address access - 25 ns 1
R111 tphvh RST# high to ADV# high 30 - ns 1
Clock Specifications
R200 fCLK CLK frequency - 54 MHz
1,3
R201 tCLK CLK period 18.5 - ns
R202 tCH/CL CLK high/low time 3.5 - ns
R203 tFCLK/RCLK CLK fall/rise time - 3 ns
Synchronous Specifications
R301 tAVCH/L Address setup to CLK 7 - ns
1
R302 tVLCH/L ADV# low setup to CLK 7 - ns
R303 tELCH/L CE# low setup to CLK 7 - ns
R304 tCHQV / tCLQV CLK to output valid - 14 ns
R305 tCHQX Output hold from CLK 3 - ns 1,5
R306 tCHAX Address hold from CLK 7 - ns 1,4,5
R307 tCHTV CLK to WAIT valid - 14 ns 1,5
Intel StrataFlash® Wireless Memory (L18)
Datasheet Intel StrataFlash® Wireless Memory (L18) April 2005
Order Number: 251902, Revision: 009 33
Note: WAIT shown deasserted during asynchronous read mode (RCR[10]=0 Wait asserted low).
R311 tCHVL CLK Valid to ADV# Setup 0 - ns 1
R312 tCHTX WAIT Hold from CLK 3 - ns 1,5
NOTES:
1. S ee Figure 8, “AC Input/Output Reference Waveform” on page 28 for timing measurements and max allowable input slew
rate.
2. O E# ma y be delayed by up to tELQV – tGLQV after CE#’s falling edge without impact to tELQV.
3. Sampled, not 100% tested.
4. A ddress hold in synchronous burst mode is tCHAX or tVHAX, whichever timing specification is satisfied first.
5. A pplies only to subsequent synchronous rea ds.
6. The specifications in Sect ion 7.3 will only be used by customers (1) who desire a 1.35 to 2.0 VCCQ operating range OR
(2) who desire to transition their host controller from a 1.7 V to 2.0 V VCCQ voltage now to a lower range in the future.
Num Symbol Parameter Speed –85 Units Notes
Min Max
Figure 11. Asynchronous Single-Word Read with ADV# Low
R5
R7
R6
R17R15
R9R4
R8R3
R1
R2 R1
A
ddress [A]
ADV#
CE # [ E}
OE# [G]
WAIT [T]
Data [ D/Q]
RST# [P ]
Intel StrataFlash® Wireless Memory (L18)
April 2005 Intel StrataFlash® Wireless Memory (L18) Datasheet
34 Order Number: 251902, Revision: 009
Note: W A IT shown deasserted during asynchronous read mode (RCR[10]=0 Wait asserted low).
Note: W A IT shown deasserted during asynchronous read mode (RCR[10]=0 Wait asserted low).
Figure 12. Asynchronous Single-Word Read with ADV# Latch
R10
R7
R6
R17R15
R9R4
R8R3
R106
R101
R105R105
R2 R1
A
ddress [A]
A[1:0][A]
ADV#
CE # [ E }
OE# [G]
WAIT [T]
Data [D/Q]
Figure 13. Asynchronous Page-Mode Read Timing
R108 R9R7
R17R15
R10R4
R8R3
R106
R101
R105R105
R1R1
R2
A
[Ma x:2] [A]
A[1:0]
ADV#
CE# [ E ]
OE# [G]
WA IT [T]
DATA [ D/Q]
Intel StrataFlash® Wireless Memory (L18)
Datasheet Intel StrataFlash® Wireless Memory (L18) April 2005
Order Number: 251902, Revision: 009 35
Notes:
1. WAIT is driven per OE# assertion during synchronous array or non-array read, and can be configured to
assert either during or one data cycle before valid data.
2. This diagram illustrates the case in which an n-word burst is initiated to the flash memory array and it is
terminated by CE# deassertion after the first word in the burst.
Notes:
1. WAIT is driven per OE# assertion during synchronous array or non-array read. WAIT asserted during
initial latency and deasserted during valid data (RCR[10] = 0 Wait asserted low).
2. At the end of Word Line; the delay incurred when a burst access crosses a 16-word boundary and the
starting address is not 4-word boundary aligned.
Figure 14. Synchronous Single-Word Array or Non-array Read Timing
R312
R305R304
R4
R17R307R15
R9R7
R8
R303
R102 R3
R104
R106R101
R104
R105R105
R2
R306R301
CLK [C]
A
ddress [A]
ADV# [V]
CE# [E]
OE# [G]
WAIT [T]
Data [D/Q]
Figure 15. Continuous Burst Read, showing an Output Delay Timing
R305R305R305R305
R304
R4
R7
R312R307R15
R303
R102 R3
R106
R105R105
R101 R2
R304R304R304R306
R302
R301
CLK [ C]
A
ddress [A]
ADV# [V]
CE # [E]
OE# [G]
WAIT [T]
Data [D/Q]
Intel StrataFlash® Wireless Memory (L18)
April 2005 Intel StrataFlash® Wireless Memory (L18) Datasheet
36 Order Number: 251902, Revision: 009
Note: WAIT is driven per OE# assertion during synchronous array or non-array read. WAIT asserted during
initial latency and deasserted during valid data (RCR[10] = 0 Wait asserted low).
Notes:
1. CLK can be stopped in either high or low state.
2. WAIT is driven per OE# assertion during synchronous array or non-array read. WAIT asserted during
initial latency and deasserted during valid data (RCR[10] = 0 Wait asserted low).
Figure 16. Synchronous Burst-Mode Four-Word Read Timing
Latency Count
A
Q0 Q1 Q2 Q3
R307
R10
R304
R305R304
R4
R7
R17R15
R9
R8
R303
R3
R106
R102
R105R105
R101 R2
R306
R302
R301
CLK [ C]
A
ddress [A]
ADV# [V]
CE# [ E]
OE# [G]
WAIT [T]
Data [D/Q]
Figure 17. Burst Suspend Timing
Q0 Q1 Q1 Q2
R15R17
R304R304
R7
R6
R312R15
R4R9R4
R3
R106
R101
R105R105
R1R1
R2
R305R305R304
CLK
Address [A]
ADV#
CE# [E]
OE# [G]
WAIT [T]
WE# [W ]
D
AT A [D/Q]
Intel StrataFlash® Wireless Memory (L18)
Datasheet Intel StrataFlash® Wireless Memory (L18) April 2005
Order Number: 251902, Revision: 009 37
7.6 AC Write S pecifications
Nbr. Symbol Parameter (1, 2) Min Max Units Notes
W1 tPHWL RST# high recovery to WE# low 150 - ns 1,2,3
W2 tELWL CE# setup to WE# low 0 - ns 1,2,3
W3 tWLWH W E# write pulse width low 50 - ns 1,2,4
W4 tDVWH Data setup to WE# high 50 - ns
1,2
W5 tAVWH Address setup to WE# high 50 - ns
W6 tWHEH CE# hold from WE# high 0 - ns
W7 tWHDX Data hold from WE# high 0 - ns
W8 tWHAX Address hold from WE# high 0 - ns
W9 tWHWL WE# pulse width high 20 - ns 1,2,5
W10 tVPWH V
PP setup to WE# high 200 - ns 1,2,3,7
W11 tQVVL VPP hold from Status read 0 - ns
W12 tQVBL WP# hold from St atus read 0 - ns 1,2,3,7
W13 tBHWH W P# setup to WE# high 200 - ns
W14 tWHGL WE# high to OE# low 0 - ns 1,2,9
W16 tWHQV WE# high to read valid tAVQV + 35 - ns 1,2,3,6,10
Wr ite to Asynchronous Re a d Specif ic a tions
W18 tWHAV WE# high to Address valid 0 - ns 1,2,3,6
Write to Synchronous Read Specifications
W19 tWHCH/L WE# high to Clock valid 19 - ns 1,2,3,6,10
W20 tWHVH WE# high to ADV# high 19 - ns
Write Specifications with Clock Active
W21 tVHWL ADV# high to WE# low - 20 ns 1,2,3,11
W22 tCHWL Clock high to WE# low - 20 ns
Notes:
1. Write timing characteristics during erase suspend are the same as write-only operations.
2. A write operation can be terminated with either CE# or WE#.
3. Sam pled, not 100% tested.
4. Write pulse width low (tWLWH or tELEH) is defined from CE# or WE# low (whichever occurs last) to CE#
or WE# high (whichever occurs first). Hence, tWLWH = tELEH = tWLEH = tELWH.
5. Write pulse width high (tWHWL or tEHEL) is defined from CE# or WE# high (whichever occurs first) to
CE# or WE# low (whichever occurs last). Hence, tWHWL = tEHEL = tWHEL = tEHWL).
6. tWHVH or tWHCH/L must be met when transitioning from a write cycle to a synchronous burst read.
7. VPP and WP# should be at a valid level until erase or program success is determined.
8. This specification is only applicable when transitioning from a write cycle to an asynchronous read.
See spec W19 and W20 for synchronous read.
9. W hen doing a Read Status operation following any command that alters the Status Register, W14 is
20 ns.
10. Add 10ns if the write operations results in a RCR or block lock status change, for the subsequent read
operation to reflect this change.
11. These specs are required only when the device is in a synchronous mode and clock is active during
address setup phase.
Intel StrataFlash® Wireless Memory (L18)
April 2005 Intel StrataFlash® Wireless Memory (L18) Datasheet
38 Order Number: 251902, Revision: 009
Note: Wait deasserted during asynchronous read and during write. WAIT High-Z during write per OE#
deasserted.
Figure 18. Write to Write Timing
W1
W7W4W7W4
W3W9 W3W9W3W3
W6W2W6W2
W8W8 W5W5
Address [A]
CE# [E}
WE# [W ]
OE# [G]
WAIT [T]
Data [D/Q]
RST# [P ]
Figure 19. Asynchronous Read to Write Timing
Q D
R5
W7
W4R10
R7
R6
R17R15
W6W3W3W2
R9R4
R8R3
W8W5
R1
R2 R1
A
ddress [A]
CE# [ E }
OE# [G]
WE# [W ]
WAIT [T]
Data [D/Q]
RST# [P]
Intel StrataFlash® Wireless Memory (L18)
Datasheet Intel StrataFlash® Wireless Memory (L18) April 2005
Order Number: 251902, Revision: 009 39
Note: WAIT shown deasserted and High-Z per OE# deassertion during write operation (RCR[10]=0 Wait
asserted low). Clock is ignored during write operation.
Figure 20. Write to As ynchronous Read Timing
D Q
W1
R9 R8
R4
R3
R2
W7W4
R17R15
W14
W18W3W3
R10W6W2
R1R1W8W5
A
ddress [A]
ADV# [V]
CE# [E}
WE# [W ]
OE# [G]
WAIT [T]
Data [ D/Q]
RST# [ P]
Figure 21. Synchronous Read to Write Timing
Latency C ount
Q D D
W7R305
R304
R7
R312R307R16
W15
W22
W21
W9
W8 W9W3
W22 W21
W3W2
R8
R4
W6
R11R13
R11
R303
R3
R104R104
R106
R102
R105R105
W18
W5
R101 R2
R306
R302
R301
CLK [C]
A
ddr e s s [A]
ADV# [V]
CE# [E]
OE# [ G]
WE#
WAIT [T]
Data [D/Q]
Intel StrataFlash® Wireless Memory (L18)
April 2005 Intel StrataFlash® Wireless Memory (L18) Datasheet
40 Order Number: 251902, Revision: 009
Note: W A IT shown deasserted and High-Z per OE# deassertion during write operation (RCR[10]=0 Wait
asserted low).
Figure 22. Write to Synchronous Read Timing
Latency C ount
D Q Q
W1
R304
R305R304
R3
W7
W4
R307R15
R4
W20
W19
W18
W3W3
R11 R303
R11
W6
W2
R104 R106
R104
R306W8W5
R302 R301 R2
CLK
A
ddre s s [A]
ADV#
CE# [E}
WE# [W]
OE# [G]
WAIT [T]
Data [D/Q]
RST# [P]
Intel StrataFlash® Wireless Memory (L18)
Datasheet Intel StrataFlash® Wireless Memory (L18) April 2005
Order Number: 251902, Revision: 009 41
7.7 P rogram and Erase Characteristics
Nbr. Symbol Parameter VPPL VPPH Units Notes
Min Typ Max Min Typ Max
Conventional Word Programming
W200 tPROG/W Program
Time Single word - 90 180 - 85 170 µs 1
Single cell - 30 60 - 30 60
Buffered Programmi ng
W200 tPROG/W Program
Time Single word - 90 180 - 85 170 µs 1
W201 tPROG/PB One Buffer (32 words) - 440 880 - 340 680
Buffered Enhan ced Factory Programmin g
W451 tBEFP/W Program Single word n/a n/a n/a - 10 - µs 1,2
W452 tBEFP/
Setup Buffered EFP Setup n/a n/a n/a 5 - - 1
Erasi ng a nd Suspending
W500 tERS/PB E rase Time 16-Kword Parameter - 0.4 2.5 - 0.4 2.5 s1
W501 tERS/MB 64-Kword Main - 1.2 4 - 1.0 4
W600 tSUSP/P Suspend
Latency Program suspend - 20 25 - 20 25 µs
W601 tSUSP/E Erase suspend - 20 25 - 20 25
Notes:
1. Typical values measured at TC = +25 °C and nominal voltages. Performance numbers are valid for all
speed versions. Excludes syst em overhead. Sampled, but not 100% tested.
2. Averaged over entire device.
Intel StrataFlash® Wireless Memory (L18)
April 2005 Intel StrataFlash® Wireless Memory (L18) Datasheet
42 Order Number: 251902, Revision: 009
8.0 Power and Reset Specifications
8.1 Power Up and Down
Power supply sequencing is not required if VCC, VCCQ, and VPP are connected together; If
VCCQ and/or VPP are not connected to the VCC supply, then VCC should attain VCCMIN before
applying V CCQ and VPP. Device inp uts should not be driv en befor e supply vo ltag e equals VCCMIN.
Power supply transitions should only occur when RST# is low. This protects the device from
accidental programming or erasure during power transitions.
8.2 Reset
Asserting RST# during a system reset is important with automated program/erase devices because
systems typically expect to read from flash memory when coming out of reset. If a CPU reset
occurs without a flash memory reset, proper CPU initialization may not occur. This is because the
flash memory may be providing status information, instead of array data as expected. Connect
RST# to the same active-low reset signal used for CPU initialization.
Also, because the device is disabled when RST# is asserted, it ignores its control inputs during
power-up/down. Invalid bus conditions are masked, providing a level of memory protection.
System designers should guard against spurious writes when VCC voltages are above VLKO.
Because both WE# and CE# must be asserted for a write operation, deasserting either signal
inhibits writes to the device.
The Command User Interface (CUI) architecture provides additional protection because alteration
of memory contents can only occur after successful completion of a two-step command sequence
(see Section 9.2, “Device Commands” on page 47).
Nbr. Symbol Parameter Min Max Unit Notes
P1 tPLPH RST# pulse width low 100 - ns 1, 2, 3,4
P2 tPLRH RST# low to device reset during erase - 25 µs 1,3,4,7
RST# low to device reset during program - 25 1,3,4,7
P3 tVCCPH VCC Power valid to RST# deassertion (high) 60 - 1,4,5,6
Notes:
1. T hese specifications are valid for all device versions (packages and speeds).
2. The device may reset if tPLPH is < tPLPHm in, but this is not guaranteed.
3. Not applicable if RST# is tied to Vcc.
4. Sam pled, but not 100% tested.
5. If RS T# is tie d to th e VCC supply, device will not be ready until tVCCPH after VCC ≥ VCC min.
6. If RST# is tied to any supply/signal with VCCQ voltage levels, the RST# input voltage must not exceed
VCC until VCC ≥ VCC(min).
7. Reset completes within tPLPH if RST# is asserted while no erase or program operation is executing.
Intel StrataFlash® Wireless Memory (L18)
Datasheet Intel StrataFlash® Wireless Memory (L18) April 2005
Order Number: 251902, Revision: 009 43
8.3 Power Supply Decoupling
Flash memory devices require carefu l power supp ly decoupling. Th ree bas ic power supply current
considerations are: 1) standby current levels; 2) active current levels; and 3) transient peaks
produced when CE# and OE# are asserted and deasserted.
When the device is accessed, many internal conditions change. Circuits within the device enable
charge-pumps, and internal logic states change at high speed. All of these internal activities
produce transient sign als. Transient current magnitudes depend on the device outputs ’ capacitiv e
and inductive loading. Two-line control and correct decoupling capacitor selection suppress
transient voltage peaks.
Because Intel® Multi-Level Cell (MLC) flash memory devices draw their power from VCC, VPP,
and VCCQ, each power connection should have a 0.1 µF ceramic capacitor connected to a
correspond ing grou nd connecti on. High-freque ncy, inherently l ow-inductan ce capacitors should be
placed as close as possible to package leads.
Additionally, for every eight devices used in the system, a 4.7 µF electr ol ytic capacitor should be
placed between power and ground close to the devices. The bulk capacitor is meant to overcome
voltage droop caused by PCB trace inductance.
Figure 23. Reset Operation Waveforms
(
A) Reset during
read mod e
(B) Reset du ri ng
program or block erase
P1
≤
P2
(C) Reset du ri ng
program or block erase
P1
≥
P2
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
RST# [P]
RST# [P]
RST# [P]
Abort
Complete
Abort
Complete
V
CC
0V
V
CC
(D) VCC Power-up to
RST# high
P1 R5
P2
P3
P2 R5
R5
Intel StrataFlash® Wireless Memory (L18)
April 2005 Intel StrataFlash® Wireless Memory (L18) Datasheet
44 Order Number: 251902, Revision: 009
8.4 Automatic Power Saving
Automatic Power Saving (APS) provides low power operation during a read’s active state. ICCAPS
is the average current measured over any 5 ms time interval, 5 µs after CE# is deasserted. During
APS, average current is measured over the same time interval 5 µs after the following events
happen: (1) there is no internal read, prog ram or erase oper ations cease; (2) CE# is asserted; (3) the
address lines are quiescent and at VSSQ or VCCQ. OE# may also be driven during APS.
Intel StrataFlash® Wireless Memory (L18)
Datasheet Intel StrataFlash® Wireless Memory (L18) April 2005
Order Number: 251902, Revision: 009 45
9.0 Device Operations
This section provides an ov erview of device ope rations. The system CPU pro vides control of all in-
system read, write, and erase operations of the device via the system bus. The on-chip Write State
Machine (WSM) manages all block-erase and word-program algorithms.
Device commands are written to the Command User Interface (CUI) to control all flash memory
device operations. The CUI does not occupy an addressable memory location; it is the mechanism
through which the flash device is controlled.
9.1 Bu s Operations
CE#-low and RST#-high enable device read operations. The device internally decodes upper
address inputs to det e rmin e th e accessed partition. ADV#-low opens the internal address latches.
OE#-low activates the outputs and gates selected data onto the I/O bus.
In asynch ronous m ode, the addres s is la tched when ADV# goes hi gh or co ntinuousl y flows through
if ADV# is held low. In sy nchr ono us mod e , the address is latched by the first of either the rising
ADV# edge or the next valid CLK edge with ADV# low (WE# and RST# must be VIH; CE# must
be VIL).
Bus cycles to/from the L18 device conform to standard microprocessor bus operations. Table 7
summarizes the bus operations and the logic levels that must be applied to the device’s control
signal input s.
Table 7. Bus Operations Summary
Bus Operation RST# CLK ADV# CE# OE# WE# WAIT DQ[15:0] Notes
Read
Asynchronous VIH X L L L H Deasserted Output
Synchronous VIH Running L L L H Driven Output
Burst Suspend VIH Halted X L H H High-Z Output
Write VIH X L L H L High-Z Input 1
Output Disable VIH X X L H H High-Z High-Z 2
Standby VIH X X H X X High-Z High-Z 2
Reset VIL X X X X X High-Z High-Z 2,3
Notes:
1. Refer to the Table 8, “Command Bus Cycles” on page 47 for valid DQ[15:0] during a write operation.
2. X = Don’t Care (H or L).
3. RST # must be at VSS ± 0.2 V to meet the maximum specified power-down current.
Intel StrataFlash® Wireless Memory (L18)
April 2005 Intel StrataFlash® Wireless Memory (L18) Datasheet
46 Order Number: 251902, Revision: 009
9.1.1 Reads
To perform a read operation, RS T# and WE# must be deasserted while CE# and OE# are asserted.
CE# is the device-select control. When asserted, it enables the flash memory device. OE# is the
data-output control. When asserted, the addressed flash memory data is driven onto the I/O bus.
See Section 10.0, “Read Operations” on page 50 for details on the available read modes, and see
Section 15.0, “Special Read States” on page 75 for details regarding the available read states.
The Automatic Power Savings (APS) feature provides low pow er operati on fo llowing r eads du ring
active mode. After data is read from the memory array and the address lines are quiescent, APS
automatically places the device into standby. In APS, device current is reduced to ICCAPS (see
Section 6.1, “DC Current Characteristics” on page 26).
9.1.2 Writes
To perform a write oper ation, both CE# and WE# ar e asserted wh ile RST# and OE# are deas serted.
During a write operation, address and data are latched on the rising edge of WE# or CE#,
whichever occu rs fi rs t. Table 8, “Command Bus Cycles” on page 47 shows the bus cy cle sequence
for each of the supported dev ice commands, while Table 9, “Command Codes and Definitions” on
page 48 describes each command. See Section 7.0, “AC Characteristics” on page 28 for signal-
timing details.
Note: Wr ite operations w ith invalid V CC and/or VPP voltages can produce s purious res ults an d should not
be attempted.
9.1.3 Output Disable
When OE# is deasserted, device outputs DQ[15:0] are disabled and placed in a high-impedance
(High-Z) state, WAIT is also placed in High-Z.
9.1.4 Standby
When CE# is deasserted the device is deselected and placed in standby, substantially reducing
power consumption. In standby, the data outputs are placed in High-Z, independent of the level
placed on OE#. S tandby current, ICCS, is the average current m easured over any 5 ms time interval,
5 µs after CE# is deasserted. During standby, average current is measured over the same time
interval 5 µs after CE# is deasserted.
When the device is deselected (while CE# is deasserted) during a program or erase operation, it
continues to consume active power until the program or erase operation is completed.
9.1.5 Reset
As with any automated device, it is imp ortan t to asser t RST# when the system is reset. When the
system comes out of reset, the syste m proc e ssor atte m pts to read from the flash memor y if it is th e
system boot device. If a CPU reset occurs with no flash memory reset, improper CPU initialization
may occur because the flash memory may be providing status information rather than array data.
Flash memory devices from Intel allow proper CPU initialization following a system reset through
the use of the RST# input. RST# should be controlled by the same low-true reset signal that resets
the system CPU.
Intel StrataFlash® Wireless Memory (L18)
Datasheet Intel StrataFlash® Wireless Memory (L18) April 2005
Order Number: 251902, Revision: 009 47
After initial power-up or reset, the device defaults to asynchronous Read Array, and the Status
Register is set to 0x80. Asserting RST# de-energizes all internal circuits, and places the output
drivers in High-Z. When RST# is asserted, the device shuts down the operation in progress, a
process whic h ta kes a mi n im um am oun t of t ime to complete. When RST # has b een d easserted, the
device is reset to asynchronous Read Array state.
Note: If RST# is asserted during a program or erase operation, the operation is terminated and the
memory contents at th e aborted location ( for a program) o r block (fo r an erase) are no lo nger valid,
because the data may have been only partially written or erased.
When returning from a reset (RST# deasserted), a minimum wait is required before the initial read
access outputs valid data. Also, a minimum delay is required after a reset before a write cycle can
be initiated. After this wake-up interval passes, normal oper atio n is restored. See Section 7. 0, “AC
Characteristics” on page 28 for details about signal-timing.
9.2 Device Commands
Device operations are initiated by writing specific device commands to the Com mand User
Interface (CUI). See Table 8, “Command Bus Cycles” on page 47.
Several commands are used to modify array data including Word Program and Block Erase
commands. Writing either command to the CUI ini tiates a sequence of internally-timed f unc tions
that culminate in the completio n of the re quested task. However, the operation can be aborted by
either asserting RST# or by issuing an appropriate suspend command.
Table 8. Command Bus Cycles (Sheet 1 of 2)
Mode Command Bus
Cycles
First Bus Cycle Second Bus Cycle
Oper Addr1Data2Oper Addr1Data2
Read
Read Array 1 Write PnA 0xFF
Read Device Identifier ≥ 2 Write PnA 0x90 Read PBA+IA ID
CFI Query ≥ 2 Write PnA 0x98 Read PnA+QA QD
Read Status Register 2 Write PnA 0x70 Read PnA SRD
Clear Status Register 1 Write X 0x50
Program
Word Program 2 Write WA 0x40/
0x10 Write WA WD
Buffered Program3 > 2 Write W A 0xE8 Write WA N - 1
Buffered Enhanced Factory Program
(Buffered EFP)4> 2 Write WA 0x80 Write WA 0xD0
Erase Block Erase 2 Write BA 0x20 Write BA 0xD0
Suspend Program /Erase Sus pend 1 Write X 0xB 0
Program/Erase R esum e 1 Write X 0xD0
Block
Locking/
Unlocking
Lock Block 2 Write BA 0x60 Writ e BA 0x01
Unlock Block 2 Write BA 0x 60 W rite BA 0xD0
Lock-down Block 2 Write BA 0x60 Write BA 0x2F
Intel StrataFlash® Wireless Memory (L18)
April 2005 Intel StrataFlash® Wireless Memory (L18) Datasheet
48 Order Number: 251902, Revision: 009
9.3 Command Definitions
Valid device command codes and descriptions are shown in Table 9.
Protection Program Protection Register 2 Write PRA 0xC0 Write PRA PD
Program Lock Register 2 Write LRA 0xC0 Write LRA LRD
Configuration Program Read Configuration Register 2 Write RCD 0x60 Write RCD 0x03
Notes:
1. Firs t command cy cle address should be the same as the operation’s target address.
PnA = Address within the partition.
PBA = Partition base address.
IA = Identification code address offset.
QA = CFI Query address offset.
BA = Address within the block.
WA = Word address of memory location to be written.
PRA = Protection Register address.
LRA = Lock Register address.
X = Any valid address within the device.
2. ID = Identifier data.
QD = Query data on DQ[15:0].
SRD = Status Register data.
WD = Word data.
N = Word count of data to be loaded into the write buffer.
PD = Protection Register data.
PD = Protection Register data.
LRD = Lock Register data.
RCD = Read Configuration Register data on A[15:0]. A[MAX:16] can select any partition.
3. The second cycle of the Buffered Program Command is the word count of the data to be loaded into the write buf fer. This
is followed by up to 32 words of data.Then the confirm command (0xD0) is issued, triggering the array programming
operation.
4. The confirm command (0xD0) is followed by the buffer data.
Table 8. Command Bus Cycles (Sheet 2 of 2)
Mode Command Bus
Cycles
First Bus Cycle Seco nd Bus Cycle
Oper Addr1Data2Oper Addr1Data2
Table 9. Command Codes and Definitions (Sheet 1 of 2)
Mode Code Device Mode Description
Read
0xFF Read Array Places the addressed partition in Read Array mode. Array data is output on DQ[15:0].
0x70 Read S tatus
Register
Places the addressed partition in Read St at us Register mode. The partition enters this
mode after a program or erase command is issued. Status Register data is output on
DQ[7:0].
0x90
Read Device
ID or
Configuration
Register
Places the addressed partition in Read Device Identifier mode. Subsequent reads from
addresses within the partition outputs manufacturer/device codes, Configuration Register
data, Block Lock status, or Protection Register data on DQ[15:0].
0x98 Read Query Places the addressed partition in Read Query mode. Subsequent reads from the partition
addresses output Common Flash Interface information on DQ[7:0].
0x50 Clear Status
Register The WSM can only set Status Register error bits. The Clear Status Register command is
used to clear the SR error bits.
Intel StrataFlash® Wireless Memory (L18)
Datasheet Intel StrataFlash® Wireless Memory (L18) April 2005
Order Number: 251902, Revision: 009 49
Write
0x40 Word Program
Setup
First cycle of a 2-cycle programming command; prepares the CUI for a write operation.
On the next write cycle, the address and data are latched and the WSM executes the
programming algorithm at the addressed location. During program operations, the
partition responds only to Read S tatus Register and Program Suspend commands. CE#
or OE# must be toggled to update the Status Register in asynchronous read. CE# or
ADV# must be toggled to update the Status Register Data for synchronous Non-array
read. The Read Array command must be issued to read array data af ter programming has
finished.
0x10 Alternate Word
Program
Setup Equivalent to the Word Program Setup command, 0x40.
0xE8 Buffered
Program This command loads a variable number of bytes up to the buffer size of 32 words onto the
program buffer.
0xD0 Buffered
Program
Confirm
The confirm command is Issued after the data streaming for writing into the buffer is done.
This instructs the WSM to perform the Buffered Program algorithm, writing the data from
the buffer to the flash memory array.
0x80
Buffered
Enhanced
Factory
Programming
Setup
First cycle of a 2-cycle command; initiates Buffered Enhanced Factory Program mode
(Buffered EFP). The CUI then waits for the Buffered EFP Confirm command, 0xD0 , that
initiates the Buffered EFP algorithm. All other commands are ignored when Buffered EFP
mode begins.
0xD0 Buffered EFP
Confirm If the previous command was Buffered EFP Setup (0x80), the CUI latches the address
and data, and prepares the device for Buffered EFP mode.
Erase
0x20 Block Eras e
Setup
First cycle of a 2-cycle command; prepares the CUI for a block-erase operation. The
WSM performs the erase algorithm on the block addressed by the Erase Confirm
command. If the next command is not the Erase Confirm (0xD0) command, the CUI sets
Status Register bits SR[4] and SR[5], and places the addressed partition in read status
register mode.
0xD0 Block Erase
Confirm
If the first command was Block Erase Setup (0x20), the CUI latches the address and data,
and the WSM erases the addressed block. During block-erase operations, the partition
responds only to Read S tat us Register and Erase Suspend commands. CE# or OE# must
be toggled to update the Status Register in asynchronous read. CE# or ADV# must be
toggled to update the Status Register Data for synchronous Non-array read.
Suspend 0xB0 Program or
Erase
Suspend
This command issued to any device address initiates a suspend of the currently-
executing program or block erase operation. The Status Register indicates successful
suspend operation by setting either SR[2] (program suspended) or SR[6] (erase
suspended), along with SR[7] (ready). The Write State Machine remains in the suspend
mode regardless of control signal states (except for RST# asserted).
0xD0 Suspend
Resume This command issued to any device address resumes the suspended program or block-
erase operation.
Block Lo cking/
Unlocking
0x60 Lock Block
Setup
First cycle of a 2-cycle command; prepares the CUI for block lock configuration changes.
If the next command is not Block Lock (0x01), Block Unlock (0xD0), or Block Lock-Down
(0x2F), the CUI sets Status Register bits SR[4] and SR[5], indicating a command
sequence error.
0x01 Lock Block If the previous command was Block Lock Setup (0x60), the addressed block is locked.
0xD0 Unlock Block If the previous command was Block Lock Setup (0x60), the addressed block is unlocked.
If the addressed block is in a lock-down state, the operation has no effect.
0x2F Lock-Down
Block If the previous command was Block Lock Setup (0x60), the addressed block is locked
down.
Protection 0xC0
Program
Protection
Register
Setup
First cycle of a 2-cycle command; prepares the device for a Protection Register or Lock
Register program operation. The second cycle latches the register address and data, and
start s the programming algorithm.
Configuration
0x60
Read
Configuration
Register
Setup
First cycle of a 2-cycle command; prepares the CUI for device read configuration. If the
Set Read Configuration Register command (0x03) is not the next command, the CUI sets
Status Register bits SR[4] and SR[5], indicating a command sequence error.
0x03 Read
Configuration
Register
If the previous command was Read Configuration Register Setup (0x60), the CUI latches
the address and writes A[15:0] to the Read Configuration Register. Following a Configure
Read Configuration Register command, subsequent read operations access array data.
Table 9. Command Codes and Definitions (Sheet 2 of 2)
Mode Code Device Mode Description
Intel StrataFlash® Wireless Memory (L18)
April 2005 Intel StrataFlash® Wireless Memory (L18) Datasheet
50 Order Number: 251902, Revision: 009
10.0 Read Operations
The device supports two read modes: asynchronous page mode and synchronous burst mode.
Asynchronous page mode is the default read mode after device power-up or a reset. The Read
Configuration Register must be configured to enable synchronous burst reads of the flash memory
array (see Section 10.3, “Read Configuration Register (RCR)” on page 51).
Each partition of the device can be in any of four read states: Read Array, Read Identifier, Read
Status or Read Query. Upon power-up, or after a reset, all partitions of the device default to Read
Array. To change a partition’s read state, the appropriate read command must be written to the
device (see Section 9.2, “Device Commands” on page 47). See Section 15.0, “Special Read S tates”
on page 75 for details regarding Read Status, Read ID, and CFI Query modes.
The following sections describe read-mode operations in detail.
10.1 Asynchronous Page-Mode Read
Following a device power-up or reset, asynchronous page mode is the default read mode and all
partitions are set to Read Array. Ho wever, to perform array reads after any other device operation
(e.g. write operation), the Read Array command must be issued in order to read from the flash
memory array.
Note: Asynchronous page-mode reads can only be performed when Read Configuration Register bit
RCR[15] is set (see Section 10.3, “Read Configuration Register (RCR)” on page 51).
To perform an asynchronous page-mode read, an address is driven onto A[MAX:0], and CE# and
ADV# are asserted. WE# and RST# must already have been deasserted. WAIT is deasserted during
asynchronous page mode. ADV# can be driven high to latch the address, or it must be held low
throughout the read cycle. CLK is not used for asynchronous page-mode reads, and is ignored. If
only asynchronous reads are to be performed, CLK should be tied to a valid VIH level, WAIT
signal can be floated and ADV# must be tied to ground. Array data is driven onto DQ[15:0] after
an initial access time tAVQV delay. (see Section 7.0, “AC Characteristics” on page 28).
In asynchronous page mode, four data words are “sensed” simultaneously from the flash memory
array and loaded into an internal page buf fer. The buffer word corresponding to the initial address
on A[MAX:0] is driven onto DQ[15:0] after the initial access delay. Address bits A[MAX:2] select
the 4-word page. Address bits A[1:0] determine which word of the 4-word page is output from the
data buffer at any given time.
10.2 Synchronous Burst-Mode Read
Section 10.3, “Read Configuration Register (RCR)” on page 51continuous-wordsTo perform a
synchronous burst- read, an initial address is driven onto A[ MAX:0], and CE# and ADV# are
asserted. WE# and RST# must already have been deasserted. ADV# is asserted, and then
deasserted to latch the address . Alternately , ADV# can r emain asserted thro ughout the burst acces s,
in which case the address is lat ched on th e nex t vali d CLK edge while ADV# is asserted.
Intel StrataFlash® Wireless Memory (L18)
Datasheet Intel StrataFlash® Wireless Memory (L18) April 2005
Order Number: 251902, Revision: 009 51
During synchronous array and non-array read modes, the first word is output from the data buffer
on the next valid CLK edge after the initial access latency delay (see Section 10.3.2, “Latency
Cou nt” on pag e 52). Subsequent data is output on valid CLK edges following a minimum delay.
However, for a synchronous non-array read, the same word of data will be output on successive
clock edges until the burst length requirements are satisfied.
Figure 14Figu re 16
10.2.1 Burst Suspend
The Burst Suspend feature of the device can reduce or eliminate the initial access latency incurred
when system software needs to suspend a burst sequence that is in progress in order to retrieve data
from another device on the same system bus. The system processor can resume the burst sequence
later. Burst suspend provides maximum benefit in non-cache systems.
Burst accesses can be suspended during the initial access latency (before data is received) or after
the device has output data. When a burst access is suspended, internal array sensing continues and
any previously latched internal data is retained. A burst sequence can be suspended and resumed
without limit as long as d evice op e rati on cond itions are met.
Burst Suspend occurs when CE# is asserted, the current address has b een latched (either ADV#
rising edge or valid CLK edge), CLK is halted, and OE# is deasserted. CLK can be halted when it
is at VIH or VIL. WAIT is in High-Z during OE# deassertion.
To resume the burst access, OE# is reasserted, and CLK is restarted. Subsequent CLK edges
resume the burst sequence.
Within the device, CE# and OE# gate WAIT. Therefore, during Burst Suspend WAIT is placed in
high-impedance state when OE# is deasserted and resumed active when OE# is re-asserted. See
Figure 17, “Burst Suspend Timing” on page 36.
10.3 Read Configuration Register (RCR)
The RCR is used to select the read mode (synchronous or asynchronous), and it defines the
synchronous burst characteristics of the device. To modify RCR settings, use the Configure Read
Configuration Register command (see Section 9.2, “Device Commands” on page 47).
RCR contents can be examined using the Read Device Identifier command, and then reading from
<partition base address> + 0x05 (see Section 15.2, “Read Device Identifier” on page 76).
The RCR is shown in Table 10. The following sections describe each RCR bit.
Table 10. Read Configuration Register Description (Sheet 1 of 2)
Read Configuration Register (RCR)
Read
Mode RES Latency Count WAIT
Polarity Data
Hold WAIT
Delay Burst
Seq CLK
Edge RES RES Burst
Wrap Burst Length
RM RLC[2:0] WP DH WD BS CE R R BW BL[2:0]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit Name Description
Intel StrataFlash® Wireless Memory (L18)
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10.3.1 Read Mode
The Read Mode (RM) bit selects synchronous burst-mode or asynchronous page-mode operation
for the device. When the RM bit is set, as yn chro nou s pag e mo de is se lected (defau lt). W hen RM is
cleared, synchronous burst mode is selected.
10.3.2 Latency Count
The Latency Count bits, LC[2:0], tell the device how many clock cycles must elapse from the
rising edge of ADV# (or from the first valid clock edge after ADV# is asserted) until the first data
word is to be driven onto DQ[15:0]. The input clock frequency is used to determine this value.
Figure 24 shows the data output latency for the di fferent settings of LC[2:0] .
Synchrono us burst wit h a Latency Count sett ing of Code 4 will res ult in zero WAIT state; however ,
a Latency Count setting of Code 5 will cause 1 WAIT state (Code 6 will cause 2 WAIT states, and
Code 7 will cause 3 WAIT states) af ter every four words, r egard less of whether a 16-word
boundary is crossed. If RCR[9] (Data Hold) bit is set (data hold of two clocks) this WAIT condition
will not occur because enough clocks elapse d uring each burst cycle to eliminate subsequent WAIT
states.
Refer to Table 11 and Table 12 for Latency Code Settings.
15 Read Mode (RM) 0 = Synchronous burst-mode read
1 = Asynchronous page-mode read (default)
14 Reserved (R) Reserved bits should be cleared (0)
13:11 Latency Count (LC[2:0]) 010 =Code 2
011 =Code 3
100 =Code 4
101 =Code 5
110 =Code 6
111 =Code 7 (default)
(Other bit settings are reserved)
10 Wait Polarity (WP) 0 =WAIT signal is active low
1 =WAIT signal is active high (default)
9 Data Hold (DH) 0 =Data held for a 1-clock data cycle
1 =Data held for a 2-clock data cycle (default)
8 Wait Delay (WD) 0 =WAIT deasserted with valid data
1 =WAIT deasserted one data cycle before valid data (default)
7 Burst Sequen ce (BS) 0 =Reserved
1 =Linear (default)
6 Clock Edge (CE) 0 = Falling edge
1 = Rising edge (default)
5:4 Reserved (R) Reserved bits should be cleared (0)
3 Burst Wrap (BW) 0 =Wrap; Burst accesses wrap within burst length set by BL[2:0]
1 =No Wrap; Burst accesses do not wrap within burst length (default)
2:0 Burst Length (BL[2:0]) 001 =4-word burst
010 =8-word burst
011 =16-word burst
111 =Continuous-word burst (default)
(Other bit settings are reserved)
Note: Latency Code 2, Data Hold for a 2-clock data cycle (DH = 1) Wait must be deasserted with valid data (WD =
0). WD = 1 is not supported.
Table 10. Read Configuration Register Description (Sheet 2 of 2)
Intel StrataFlash® Wireless Memory (L18)
Datasheet Intel StrataFlash® Wireless Memory (L18) April 2005
Order Number: 251902, Revision: 009 53
See Figure 25, “Exa mple Latency Coun t Setting” on page 54.
Figure 24. First-Access Latency Count
Table 11. LC and Frequency Support (tAVQV/tCHQV = 85 ns / 14 ns)
VCCQ = 1.7 V to 2.0 V
Latency Count Settings Frequency Support (MHz)
2≤ 28
3≤ 40
4, 5, 6 or 7 ≤ 54
Table 12. LC and Frequency Support (tAVQV/tCHQV = 90 ns / 17 ns)
VCCQ = 1.35 V to 2.0 V
Latency Count Settings Frequency Support (MHz)
2≤ 27
3, 4, 5, 6 or 7 ≤ 40
Code 1
(Reserved
Code 6
Code 5
Code 4
Code 3
Code 2
Code 0 (Reserved)
Code 7
Valid
Address
Valid
Output Valid
Output Valid
Output Valid
Output Valid
Output Valid
Output Valid
Output Valid
Output
Valid
Output Valid
Output Valid
Output Valid
Output Valid
Output Valid
Output Valid
Output
Valid
Output Valid
Output Valid
Output Valid
Output Valid
Output Valid
Output
Valid
Output Valid
Output Valid
Output Valid
Output Valid
Output
Valid
Output Valid
Output Valid
Output Valid
Output
Valid
Output Valid
Output Valid
Output
Valid
Output Valid
Output
Valid
Output
Addres s [ A]
ADV # [V]
D
Q15-0 [D/Q]
CLK [C]
D
Q15-0 [D/Q]
D
Q15-0 [D/Q]
D
Q15-0 [D/Q]
D
Q15-0 [D/Q]
D
Q15-0 [D/Q]
D
Q15-0 [D/Q]
D
Q15-0 [D/Q]
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10.3.3 WAIT Polarity
The WAIT Polarity bit (WP), RCR[10] determin es the asserted level (VOH or VOL) of WAIT.
When WP is set, WAIT is asserted-high (default). When WP is cleared, WAIT is asserted-low.
WAIT changes state on valid clock edges during active bus cycles (CE# asserted, OE# asserted,
RST# deasserted).
10.3.3.1 WAIT Signal Function
The WAIT signal indicates data valid when the device is operating in synchronous mode
(RCR[15]=0). The WAIT signal is only “deasserted” when data is valid on the bus.
Wh en the device is op erat ing in sync hronous non-array read mode, such as read status, read ID, or
read query the WAIT signal is also “deasserted” when data is valid on the bus.
WAIT behavior during synchronous non-array reads at the end of word line works correctly only
on the first data access.
When the device is operating in asynchronous page mode, asynchronous single word read mode,
and all write operations, WAI T is set to a deasserted state as determined by RCR[10]. See Figure
12, “Asynchronous Single-Word Read with ADV# Latch” on page 34, an d Figure 13,
“Asynchronous Page-Mode Read Timing” on page 34.
Figure 25. Example Latency Count Setting
CLK
CE#
ADV#
A
[MAX:0]
D[15:0]
tData
Code 3
Address
Data
012
34
R103
High-Z
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Datasheet Intel StrataFlash® Wireless Memory (L18) April 2005
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10.3.4 Data Hold
For burst read operations, the Data Hold (DH) bit determines whether the data output remains valid
on DQ[15:0] for one or two-clock cycles. This period of time is called the “data cycle”. When DH
is set, output data is held for two clocks (default) . When DH is cleared, output data is held for one
clock (see Figure 26). The processor’s d ata s etup time and th e flash memory ’s clock-to-d ata o utput
delay shou ld be consider ed when determ ining w hether to hol d output dat a for one or t wo clocks. A
method for determining the Data Hold configuration is s hown below:
To set the device at one clock data hold for subsequent reads, the following condition must be
satisfied:tCHQV (ns) + tDATA (ns) ≤ One CLK Period (ns)
tDATA = Data set up to Clock (defined by CPU)
For example, with a clock frequency of 40 MHz, the clock period is 25 ns. Assuming
tCHQV = 20 ns and tDATA = 4ns. Applying these values to the formula above:
20 ns + 4 ns ≤ 25 ns
The equation is satisfied and data will b e available at ev ery clo ck peri od with data hol d setting at
one clock.
If tCHQV (ns) + tDATA (ns) > One CLK Period (ns), d ata hold setting of 2 clock periods mu st be
used.
Table 13. WAIT Functionality Table
Condition WAIT Notes
CE# = ‘1’, OE# = ‘X’
CE# = ‘X’, OE# = ‘1’
High-Z 1
CE# =’0’, OE# = ‘0’ Active 1
Synchronous Array Reads Active 1
Synchronous Non-Array Reads Active 1
All Asynchronous Reads Deasserted 1
All Writes High-Z 1,2
Notes:
1. Active: WAIT is asserted until data becomes valid, then
deasserts
2. When OE# = VIH during writes, WAIT = High-Z
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10.3.5 WAIT Delay
The WAIT Delay (WD) bit controls the WAIT assertion-delay behavior during synchronous burst
reads. WAIT can be asserted either during or one data cycle before invalid data is output on
DQ[15:0]. When WD is set, WAIT is asserted one data cycle before invalid data (default). When
WD is cleared, WAIT is asserted during invalid data.
10.3.6 Burst Sequence
The Burst Sequence (BS) bit selects linear-burst sequence (default). Only linear-burst sequence is
supported. Table 14 shows the synchronous burst sequence for all burst lengths, as well as the
effect of the Burst Wrap (BW) setting.
Figure 26. Data Hold Timing
Valid
Output
Valid
Output
Valid
Output Valid
Output Valid
Output
CLK [C]
D[15:0] [Q]
D[15:0] [Q]
2 CLK
Data Hold
1 CLK
Data Hold
Table 14. Burst Sequence Word Ordering (Sheet 1 of 2)
Start
Addr.
(DEC) Burst Wrap
(RCR[3])
Burst Addressing Sequence (DEC)
4-Word Burst
(BL[2:0] = 0b001) 8-Word Burst
(BL[2:0] = 0b010) 16-Word Burst
(BL[2:0] = 0b011) Conti nuous Burst
(BL[2:0] = 0b111)
0 0 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2-3-4…14-15 0-1-2-3-4-5-6-…
1 0 1-2-3-0 1-2-3-4-5-6-7-0 1-2-3-4-5…15-0 1-2-3-4-5-6-7-…
2 0 2-3-0-1 2-3-4-5-6-7-0-1 2-3-4-5-6…15-0-1 2-3-4-5-6-7-8-…
3 0 3-0-1-2 3-4-5-6-7-0-1-2 3-4-5-6-7…15-0-1-2 3-4-5-6-7-8-9-…
40 4-5-6-7-0-1-2-3 4-5-6-7-8…15-0-1-2-3 4-5-6-7-8-9-10…
50 5-6-7-0-1-2-3-4 5-6-7-8-9…15-0-1-2-3-4 5-6-7-8-9-10-11…
60 6-7-0-1-2-3-4-5 6-7-8-9-10…15-0-1-2-3-4-5 6-7-8-9-10-11-12-…
70 7-0-1-2-3-4-5-6 7-8-9-10…15-0-1-2-3-4-5-6 7-8-9-10-11-12-13…
…
…
…
…
…
…
14 0 14-15-0-1-2…12-13 14-15-16-17-18-19-20-…
15 0 15-0-1-2-3…13-14 15-16-17-18-19-20-21-…
…
…
…
…
…
…
0 1 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2-3-4…14-15 0-1-2-3-4-5-6-…
1 1 1-2-3-4 1-2-3-4-5-6-7-8 1-2-3-4-5…15-16 1-2-3-4-5-6-7-…
2 1 2-3-4-5 2-3-4-5-6-7-8-9 2-3-4-5-6…16-17 2-3-4-5-6-7-8-…
3 1 3-4-5-6 3-4-5-6-7-8-9-10 3-4-5-6-7…17-18 3-4-5-6-7-8-9-…
41 4-5-6-7-8-9-10-11 4-5-6-7-8…18-19 4-5-6-7-8-9-10…
51 5-6-7-8-9-10-11-12 5-6-7-8-9…19-20 5-6-7-8-9-10-11…
61 6-7-8-9-10-11-12-13 6-7-8-9-10…20-21 6-7-8-9-10-11-12-…
71 7-8-9-10-11-12-13-14 7-8-9-10-11…21-22 7-8-9-10-11-12-13…
Intel StrataFlash® Wireless Memory (L18)
Datasheet Intel StrataFlash® Wireless Memory (L18) April 2005
Order Number: 251902, Revision: 009 57
10.3.7 Clock Edge
The Clock Edge (CE) bit selects either a rising (default) or falling clock edge for CLK. This clock
edge is used at the start of a burst cycle, to output synchronous data, and to assert/deassert WAIT.
10.3.8 Burst Wrap
The Burst Wrap (BW) bit determines whether 4-word, 8-word, or 16-word burst length accesses
wrap within the selected word-length boundaries or cross word-length boundaries. When BW is
set, burst wrapping does not occur (default). When BW is cleared, burst wrapping occurs.
When performing synchronous burst reads with BW set (no wrap), an output delay may occur
when the burst sequence crosses its first device-row (16-word) boundar y. If the burst sequence’s
start address is 4-word aligned, then no delay occurs. If the start address is at the end of a 4-word
boundary, the worst case output delay is one clock cycle less than the first access Latency Count.
This delay can take place only once, and doesn’t occur if the burst sequence does not cross a
device-row boundary. WAIT informs the system of this delay when it occurs.
10.3.9 Burst Length
The Burst Length bit (BL[2:0]) selects the linear burst length for all synchronous burst reads of the
flash memory array. The burst lengths are 4-word, 8-word, 16-word, and continuous word.
Continuous-bu rst accesses are linear o nly, and do not wrap within an y word length bound aries (see
Table 14, “Burst Sequence Word Ordering” on page 56). When a burst cycle begins, the device
outputs synchronous burst data until it reaches the end of the “burstable” address space.
…
…
…
…
…
…
14 1 14-15-16-17-18…28-29 14-15-16-17-18-19-20-…
15 1 15-16-17-18-19…29-30 15-16-17-18-19-20-21-…
Table 14. Burst Sequence Word Ordering (Sheet 2 of 2)
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11.0 Programming Operations
The device supports three programming methods: Word Programming (40h/10h), Buffered
Programming (E8h, D0h), and Buffered Enhanced Factory Programming (Buffered EFP) (80h,
D0h). See Section 9.0, “Device Operations” on page 45 for details on the various programming
commands issued to the device.
Successful progr amming requir es the add res sed block to be u nlocke d. If the b lock is locked do wn,
WP# must be deasserted and the block must be unlocked before attempting to program the block.
Attempting to progr am a locked block causes a program error (SR[4] and SR[1] set) and
termination of the operation. See Section 13.0, “Security Modes” on page 66 for details on locking
and unlocking blocks.
The following sections describe device programming in detail.
11.1 Word Progr amm ing
Word programming oper ations are initiated by writing the Word Progra m Setup command to the
device (see Section 9.0 , “Device Operations” on page 45). This is fo llowed by a second write to the
device with the address and data to be programmed. The partition accessed during both write
cycles outputs Status Register data when read. The partition accessed during the second cycle (the
data cycle) of the program co mmand sequence is the location where the data is written. See Figure
39, “Word Program Flowchart” on page 85.
Programming can occur in only one partition at a time; all other partitions must be in a read state or
in erase suspend. VPP must be above VPPLK, and within the specified VPPL min/max values
(nominally 1.8 V) .
During programming, the Write State Machine (WSM) executes a sequence of internally-timed
events that program the desired data bits at the addressed location, and verifies that the bits are
sufficiently programmed. Programming the flash memory array changes “ones” to “zeros.”
Memory array bits that are zeros can be changed to ones only by erasin g the block (see Section
12.0, “Erase Operations” on page 64).
The Status Register can be examined for programming progress and errors by reading any address
within the partition that is being programm ed. The partition remains in the Read Status Register
state until another command is written to that partition. Issuing the Read Status Register command
to another partit ion addr ess sets that partitio n to the Read Status Register state, allowing
programming progress to be monitored at that partition’s address.
Status Register bit SR[7] indicates the programming status while the sequence executes.
Commands that can be issued to the programming partition during programming are Program
Suspend, Read Status Register, Read Device Identifier, CFI Query, and Read Array (this returns
unknown data).
When programming has finished, Status Register bit SR[4] (when set) indicates a programming
failure. If SR[3] is set, the WSM could not perform the word programming operation because VPP
was outside of its acceptable limits. If SR[1] is set, the word programming operation attempted to
program a locked block, causing the operation to abort.
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Before issuing a new command, the Status Register contents should be examined and then cleared
using the Clear Status Register command. Any valid command can follow, when word
programmi ng has compl eted .
11.1.1 Factory Word Programming
Factory word programming is similar to word programming in that it uses the same commands and
progra mmin g algori t hms . However, fact ory w ord programming enha nce s t he progr amming
performance with VPP = VPPH. This can enable faster programming times during OEM
manufactur ing processes . Factory word progr amming is not intended for exte nded use. See Section
5.2, “Operating Conditions” on page 25 for limitations when VPP = VPPH.
Note: When VPP = VPPL, the device draws programming current from the VCC supply. If VPP is driven
by a logic signal, VPPL must remain above VPPL MIN to program the device. When VPP = VPPH,
the device draws programming current from the VPP supply. Figure 27, “Example VPP Supply
Connection s” on page 63 shows examples of device power supply configurations.
11.2 Buffered Programming
The device features a 32-word buffer to enable optimum programming performance. For Buffered
Programming, data is first written to an on-chip write buffer. Then the buffer data is programmed
into the flash memory array in buffer-size increments. This can improve system programming
performance significantly over non-buffered programming.
When the Buf fer ed Prog rammin g Setup comman d is issued (se e Section 9.2 , “Device C omm ands”
on page 47), Status Register information is updated and reflects the availability of the write buffer.
SR[7] indicates buffer availability: if set, the buffer is available; if cleared, the write buffer is not
available. To retry, issue the Buffered Programming Setup command again, and re-check SR[7].
When SR[7] is set, the buffer is ready for loading. (see Fig ure 41, “Buffer Prog ram Flowchart” on
page 87).
On the next write, a word count is written to the device at the buffer address. This tells the device
how many data words will be written to the buffer, up to the maximum size of the buffer.
On the next write, a device start address is given along with the first data to be written to the flash
memory array. Su bs equent writes provide additio nal device addresses and data. All data addresse s
must lie within the start address plus the word count. Optimum programming performance and
lower power usage are obtained by aligning the starting address at the beginning of a 32-word
boundary (A [4:0] = 0x00). Cro ssing a 32-word bo undary duri ng programmi ng will double t he total
programmi ng time .
After the last data is written to the buffer, the Buffered Programming Confirm comman d must be
issued to the original block address. The WSM begins to program buffer contents to the flash
memory array . If a command other than the Buffered Programming Confirm command is written to
the device, a command sequence error occu rs and Status Register bits SR[7,5,4] are set. If an error
occurs while writing to the array, the device stops programming, and Status Register bits SR[7,4]
are set, indicating a programming failure.
Reading from another partition is allowed wh ile data is being programmed into the array from the
write buffer (see Section 14.0, “Dual-Operation Considerations” on page 71 ).
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When Buffered Programming has completed, additional buffer writes can be initiated by issuing
another Buffered Programming Setup command and repeating the buffered program sequence.
Buffered programming may be performed with VPP = VPPL or VPPH (see Section 5.2, “Operating
Conditions” on page 25 f o r limitations when operating the device with VPP = VPPH).
If an attempt is made to program past an erase-block boundary using the Buffered Program
command, the device aborts the operation. This generates a command sequence error, and Status
Register bits SR[5,4] are set.
If Buffered programming is attempted while VPP is below VPPLK, Status Register bits SR[4,3] are
set. If any errors are detected that have set Status Register bits, the Status Register should be
cleared using the Clear Status Register command.
11.3 Buffered Enhanced Factory Programming
Buffered Enhanced Factory Programing (Buffered EFP) speeds up Multi-Level Cell (MLC) flash
programming for today's beat-rate-sensitive manufacturing environments. The enhanced
programming algorithm used in Buffered EFP eliminates traditional programming elements that
drive up overhead in device programmer systems.
Buffered EFP consists of three phases: Setup, Program/Verify, and Exit (see Figure 42, “Buffered
EFP Flowchart” on page 88). It uses a write buffer to sp read MLC pr ogr am perf ormance across 32
data words. Verification occurs in the same phase as programming to accurately program the flash
memory cell to the correct bit state.
A single two-cycle command sequence programs the entire block of data. This enhancement
eliminates three write cycles per buffer: two commands and the word count for each set of 32 data
words. Host programmer bu s cycles fill the device’s write buffer followed by a status check. SR[0]
indicates when data from the buffer has been programmed into sequential flash memory array
locations.
Following the buffer-to-flash array programming sequence, the Write State Machine (WSM)
increments internal addressing to automatically select the next 32-word array boundary. This
aspect of Buffered EFP saves host programming equipment the address-bus setup overhead.
With adequate continuity testing, programming equipment can rely on the WSM’s internal
verification to ensure that the device has programmed properly. This eliminates the external post-
program verification and its associated overhead.
11.3.1 Buffered EFP Requirements and Considerations
Buffered EFP requirements:
•Ambient temperature: TA = 25°C, ±5 °C
•VCC within specified operating range.
•VPP driven to VPPH.
•Target block unlocked before issuing the Buffered EFP Setup and Confirm commands.
•The first-word addres s (WA0) for the block to be pro gramm ed mus t be hel d con stant fr om t he
setup phase through all data streaming into the target block, until transition to the exit phase is
desired.
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•WA0 must align with the start of an array buffer boundary1.
Buffered EFP cons iderat ions :
•For optimum performance, cycling must be limited below 100 erase cycles per block2.
•Buffered EFP programs one block at a time; all buffer data must fall within a single block3.
•Buffered EFP cannot be suspended.
•Programming to the flash memory array can occur only when the buffer is full4.
•Read operation while performing Buffered EFP is not supported.
NOTES:
1. Word buffer boundaries in the array are determined by A[4:0] (0x00 through 0x1F). The alignment start
point is A[4:0] = 0x00.
2. S ome degradat ion in performance may occur if this limit is exceeded, but the internal algorithm
continues to work properly.
3. I f the internal address counter increments beyond the block's maximum address, addressing wraps
around to the beginning of the block.
4. If the number of words is less than 32, remaining locations must be filled with 0xFFFF.
11.3.2 Buffered EFP Setup Phase
After receiving the Buf fered EFP Setup and Confirm comman d sequence, St atus Register bit SR[7]
(Ready) is cleared, indicating that the WSM is busy with Buffered EFP algorithm star tup. A delay
before checking SR[7] is required to allow the WSM enough time to perform all of its setups and
checks (Block-Lock status, VPP level, etc.). If an error is detected, SR[4] is set and Buffered EFP
operation terminates. If the block was found to be locked, SR[1] is also set. SR[3] is set if the error
occurred due to an incorrect VPP leve l .
Note: Reading from the device after the Buffered EFP Setup and Confirm command sequence outputs
Status Register data. Do not issue the Read Status Register command; it will be interpreted as data
to be loaded into the buffer.
11.3.3 Buffered EFP Program/Verify Phase
After the Buffered EFP Setup Phase has completed, the host programming system must check
SR[7,0] to determine the availability of the write buffer for data s treamin g. SR[7] clear ed indicates
the device is busy and the Buffered EFP program/verify phase is activated. SR[0] indicates the
write buffer is available.
Two basic sequences repeat in this phase: loading of the writ e buffer, followed by buffe r data
programming to the array. For Buffered EFP, the count value for buffer loading is always the
maximum bu f f e r size of 32 words. Dur i ng t he bu f f e r-load ing sequence, data is stored to sequen t ial
buffer locations starting at address 0x00. Programming of the buffer contents to the flash memory
array starts as so on as the buf fer is full. If the nu mber of words is less than 32, the remaining buf fer
locations must be filled with 0xFFFF.
Caution: The buffer must be completel y filled for progr amming to occu r. Supplying an ad dress outside of t he
current block's range during a buffer-fill sequence causes the algorithm to exit immediately. Any
data previously loaded into the buffer during the fill cycle is not programmed into the array.
The starting address for data entry must be buffer size aligned, if not the Buffered EFP algorithm
will be aborted and the program fail (SR [ 4]) flag will be set.
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Data words from the write buffer are directed to sequential memory locations in the flash memory
array; programming continues from where the previous buffer sequence ended. The host
programming system must po ll SR[0] to determine when the buffer program sequence completes.
SR[0] cleared indicates that all buffer data has been transferred to the flash array; SR[0] set
indicates that the buffer is not available yet for the next fill cycle. The host system may check full
status fo r err ors at any t ime, but it is on ly necessary on a block bas is afte r Bu ffered EF P exit . Aft er
the buffer fill cycle, no write cycles should be issued to the device until SR[0] = 0 and the device is
ready for the next buffer fill.
Note: A ny sp urio us writes are ignored after a buffer fill operation and when internal program is
proceeding.
The host programming system continues the Buffered EFP algorithm by providing the next group
of data words to be written to the buffer. Alternatively, it can terminate this phase by changing the
block address to one outside of the current block’s range.
The Program/Verify phase concludes when the programmer writes to a different block address;
data supplied must be 0xFFFF. Upon Program/Verify phase completion, the device enters the
Buffered EFP Exit phase.
11.3.4 Buffered EFP Exit Phase
When SR[7] is set, the device has returned to normal operating conditions. A full status check
should be performed on the partition being pr ogr ammed at this time to ensure the entir e block
programmed successfully. When exiting the Buffered EFP algorithm with a block address change,
the read mode of both the programmed and the addressed partition will not change. After Buffered
EFP exit, any valid command can be issued to the device.
11.4 Program Suspend
Issuin g the Program Suspend co mmand w hi le programming suspends the programmi ng o perat ion .
This allows data to be accessed from memory locations oth er than the one being pr ogr ammed. The
Program Suspend command can be issued to any device address; the corresponding partition is not
affected. A program operation can be suspended to perform reads only. Additionally, a program
operation that is running during an erase suspend can be suspended to perform a read operation
(see Figure 40, “Program Suspend/Resume Flowchart” on page 86).
When a programming operation is executing, issuing the Program Suspend command requests the
WSM to suspend the programming algorithm at pred eter mined points. The partition that is
suspended continues to output Status Register data after the Program Suspend command is issued.
Programming is suspended when Status Register bits SR[7,2] are set. Suspend latency is specified
in Section 7.7, “Program and Erase Characteristics” on page 41.
To read data from blocks within the suspended partition, the Read Array command must be issued
to that partition. Read Array, Read Status Register, Read Device Identifier, CFI Query, and
Program Resume are valid commands during a program suspend.
A program operation does not need to be suspended in order to read data from a block in another
partition that is not prog rammin g. If the other parti tio n is already in a Read Array, Read Device
Identifier, or CFI Query state, issuing a valid address returns corresponding read data. If the other
partition is n ot in a read mode, one of th e read commands m ust be issued to the partition b efor e
data can be read.
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Datasheet Intel StrataFlash® Wireless Memory (L18) April 2005
Order Number: 251902, Revision: 009 63
During a program suspend, deasserting CE# places the device in standby, reducing active current.
VPP must remain at its programming level, and WP# must remain unchanged while in program
suspend. If RST# is asserted, the device is reset.
11.5 Program R esume
The Resume command instructs the device to continue programming, and automa tically clears
Status Register bits SR[7,2]. This command can be written to any partition. When read at the
partition that’s programming, the device outputs data corresponding to the partition’s last state. If
error bits are set, the Status Register should be cleared before issuing the next instruction. RST#
must remain deasserted (see Figure 40, “Program Suspend/Resume Flowchart” on page 86).
11.6 Program Protection
When VPP = VIL, absolute hardware write protection is provided for all device blocks. If VPP is
below VPPLK, programming operations halt and SR[3] is set indicating a VPP-level error. Block
lock registers a re not af f ected by the v oltage level o n VPP; they may s till be pro gram med an d read ,
even if VPP is less than VPPLK.
Figure 27. Example VPP Supply Connections
• Factory Programming with VPP = VPPH
• Complete write/Erase Protect i on when VPP ≤ VPPLK
VCC
VPP
VCC
VPP
• Low Voltage and Factory Programming
• Low-vol t a ge Programming onl y
• Logic Contro l of Devi ce Protection
VCC
VPP
• Low Voltage Programming Only
• Full Device Protection Unav ailable
VCC
VPP
≤ 10K Ω
VPP
VCC VCC
PROT #
VCC
VPP=VPPH
VCC
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12.0 Erase Operations
Flash erasing is p erfo rmed on a b lock bas i s. An entire b lock is eras ed each time an er ase comm and
sequence is issued, and only one block is erased at a time. When a block is erased, all bits within
that block read as logical ones. The following sections describe block erase operations in detail.
12.1 Block Erase
Block erase operations are initiated by writing the Block Erase Setup command to the address of
the block to be erased (see Section 9.2, “Device Commands” on page 47). Next, the Block Erase
Confirm command is written to the address of the block to be erased. Erasing can occu r in only one
partition at a time; all other partitions must be in a read state. If the device is placed in standby
(CE# deasserted) during an erase operation, the device completes the erase operation before
entering stand by.VPP must be above VPPLK and the block must be unlocked (see Figure 43 , “Block
Erase Flowchart” on page 89).
During a block erase, the Write State Machine (WSM) executes a sequence of internally-timed
events that conditions, erases, and verifies all bits within the block. Erasing the flash memory array
changes “zeros” to “ones.” Memory array bits that are ones can be changed to zeros only by
programming the block (see Section 11.0, “Programming Operations” on page 58).
The Status Register can be examined for block erase prog res s and error s by reading any addr ess
within the partit ion that is being erased. The partiti on remains in the Read Status Register state
until another command is written to that partition. Issuing the Read Status Register command to
another partition address sets that partition to the Read Status Register state, allowing erase
progress to be monitored at that partition’ s address. SR[0] indicates whether the addressed partition
or another partition is erasing. The partition’s Status Register bit SR[7] is se t upon erase
completion.
Status Register bit SR[7] indicates block erase status while the sequence executes. When the erase
operation has finished, Status Register bit SR[5] indicates an erase failure if set. SR[3] set would
indicate that the WSM could not perform the erase operation because VPP was outside of its
acceptable limits. SR[1] set indicates that the erase operation attempted to erase a locked block,
causing the operati on to abort.
Before issuing a new command, the Status Register contents should be examined and then cleared
using the Clear Status Register command. Any valid command can follow once the block erase
operation has completed.
12.2 Erase Suspend
Issuing the Erase Suspend co mmand while erasing suspends the block erase operation. This allows
data to be accessed from memory locations other than the one being erased. The Erase Suspend
command can be issued to any device address; the corresponding partition is not affected. A block
erase operation can be suspended to perform a word or buffer program operation, or a read
operation within any block except the block that is erase suspended (see F ig ure 40, “Program
Sus pend / Resume Fl owcha rt” on page 86).
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Order Number: 251902, Revision: 009 65
When a block erase operation is executing, issuing the Erase Suspend command reques ts the WSM
to suspend the erase algorithm at predetermined points. The partition that is suspended continues to
output Status Register data after the Erase Suspend command is issued. Block erase is suspended
when Status Register bits SR[7,6] are set. Suspend latency is specified in Section 7.7, “Program
and Erase Characteristics” on page 41.
To read data from blocks within the suspended partition (other than an erase-suspended block), the
Read Array command must be iss ued to that par tition first. During Erase Suspend, a Program
command can be issued to any block other than the erase-suspended block. Block erase cannot
resume until program operations initiated during erase suspend complete. Read Array, Read Status
Register, R ead Device Identifier, CFI Query, and Erase Resume are valid commands during Erase
Suspend. Additionally, Clear Status Register, Program, Program Suspend, Block Lock, Block
Unlock, and Block Lock-Down are valid commands during Erase Suspend.
To read data from a block in a partition that is not erasing, the erase operation does not need to be
suspended. If the other partition is already in Read Ar ray, Read Device Identifier, or CFI Query,
issuing a valid address returns corresponding data. If the other partition is not in a read state, one of
the read commands must be issued to the partition before data can be read.
During an erase suspend, deasserting CE# places the device in standby, reducing active current.
VPP must re m ain at a valid level, and WP# must remain unchanged while in erase suspend. If
RST# is asserted, the device is reset.
12.3 Erase Resume
The Erase Resume command instructs the device to continue erasing, and automatically clears
status register bits SR[7,6]. This command can be written to any partition. When read at the
partition that’s erasing, the device outputs data corresponding to the partition’s last state. If status
register error bits are set, the Status Register should be cleared before issuing the next instruction.
RST# must remain deasserted (see Figure 40, “Program Suspend/Resume Flowchart” on page 86).
12.4 Erase Protecti on
When VPP = VIL, absolute hardware erase protection is provided for all device blocks. If VPP is
below VPPLK, erase operations halt and SR[3] is set indicating a VPP-level error.
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13.0 Security Modes
The device features security modes used to protect the information stored in the flash memory
array. The following sections describe each security mode in detail.
13.1 Block Locking
Individual instant block locking is used to protect user code and/or data within the flash memory
array. All blocks power up in a locked state to protect array data from being altered during power
transitions. Any block can be locked or unlocked with no latency. Locked blocks cannot be
programmed or erased; they can only be read.
Software-controlled security is implemented using the Block Lock and Block Unlock commands.
Hardware-controlled security can be implemented using the Block Lock-Down command along
with assertin g W P# . Also, VPP data security can be used to inhibit program and erase operations
(see Section 11.6, “Program Protection” on page 63 and Section 12.4, “Erase Protection” on
page 65).
13.1.1 Lock Block
To lock a block, issue the Lock Block Setup command. The next comm and must be the Lock Blo ck
command issued to the desired block’s address (see Section 9.2, “Device Commands” on page 47
and Figure 45, “Block Lock Operations Flowchart” on page 91). If the Set Read Configuration
Register command is issued after the Block Lock Setup command, the device configures the RCR
instead.
Block lock and unlock operations are not affected by the voltage level on VPP. The block lock bits
may be modified and/or read even if VPP is below VPPLK.
13.1.2 Unlock Block
The Unlock Block command is used to unlock blocks (see Section 9.2, “Device Commands” on
page 47). Unlocked blocks can be read, programmed, and erased. Unlocked blocks return to a
locked state when the device is reset or powered down. If a block is in a lock-down state, WP#
must be deasserted before it can be unlocked (see Figure 28, “Block Locking State Diagram” on
page 67).
13.1.3 Lock-Down Block
A locked or unlocked block can be locked-down by writing the Lock-Down Block command
sequence (see Section 9.2, “Device Commands” on page 47). Blocks in a lock-down state cannot
be programmed or eras ed; they can only be r ead. However, unlike locked blocks, their locked s tate
cannot be changed by software commands alone. A locked-down block can only be unlocked by
issuing the Unlock Block command with WP# deasserted. To return an unlocked block to locked-
down state, a Lock-Down command must be issued prior to changing WP# to VIL. Locked-down
blocks revert to the locked state upo n reset or power up the device (see Figur e 28, “Block Lock ing
State Diagram” on page 67).
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Datasheet Intel StrataFlash® Wireless Memory (L18) April 2005
Order Number: 251902, Revision: 009 67
13.1.4 Block Lock Status
The Read Device Identifier command is used to determine a block’s lock status (see Section 15.2,
“Read Device Identifier” on page 76). Data b i ts DQ [1:0] displ ay t he ad dres s ed block’s lock statu s;
DQ0 is th e add ressed block’s lock bit , whil e DQ1 is the a ddressed block’s lock- down bit.
13.1.5 Block Locking During Suspend
Block lock and unlock changes can be performed during an erase suspend. To change block
locking during an erase operation, first issue the Erase Suspend command. Monitor the Status
Register until SR[7] and SR[6] are set, indicating the device is suspended and ready to accept
another comman d.
Next, write the desired lock command sequence to a block, which changes the lock state of that
block. After completing block lock or unlock operations, resume the erase operation using the
Erase Resume command.
Note: A Lock Block Setup command followed by any command other than Lock Block, Unlock Block,
or Lock-Down Block produces a command sequence error and set Status Register bits SR[4] and
SR[5]. If a comman d sequ ence error occu rs du ring an erase susp end, SR[4 ] and SR[ 5] r emains set,
even after the erase operation is resumed. Unless the Status Register is cleared using the Clear
Status Register command before resuming the erase operation, possible erase errors may be
masked by the command sequence error.
Figure 28. Block Locking St ate Diagram
[X00]
[X01]
P
ower-Up/Reset
Unlocked
Locked
[011]
[111] [110]
Locked-
Down4,5
Software
Locked
[011]
Hard w are
Locked5
Unlocked
W P # Ha rdw are C ontrol
No tes: 1. [a,b,c] repres e nts [WP #, DQ 1 , DQ 0 ]. X = Don ’t Ca re .
2. DQ1 indicates Block Lock-Down status. DQ1 = ‘0’, Lock-Down has not been issued
to this block. DQ 1 = ‘1’, Lock-Do wn has be en issued to this block .
3. DQ0 indicates block lock status. DQ0 = ‘0’, block is unlocked. DQ 0 = ‘1’, block is
locke d.
4. Locked-down = Hardware + Software locked.
5. [011] states should be tracked by system software to determine difference between
Hardware Locked and Locked-Down states.
Software Block Lock (0x6 0/0x01) or Software B lock Unlock (0x60 /0xD 0)
Software Block Lock-D ow n (0x6 0/0x 2F)
WP# hardware control
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If a block is locked or locked-down during an erase suspend of the same block, the lock status bits
change immediately. However, the erase operation completes when it is resumed. Block lock
operations cannot occur during a program suspend. See Appendix A, “Write State Machine
(WSM)” on page 78, which shows valid commands during an erase suspend.
13.2 Protection Registers
The device contains 17 Protection Registers (PRs) that can be used to implement system security
measures and/or device identification. Each Protection Register can be individually locked.
The first 128-bit Protection Register is comprised of two 64-bit (8-word) segments. The lower 64-
bit segment is pre-programmed at the factory with a unique 64- bit number. The other 64-bit
segment, as well as the other sixteen 128-bit Protection Registers, are blank. Users can program
these registers as needed. When programmed, users can then lock the Protection Regis ter (s) to
prevent additional bit pro g ramm in g (see Figure 29, “Protection Register Map” on page 69).
The user-programmable Protection Registers contain one-time programmable (OTP) bits; when
programmed, register bits cannot be erased. Each Protection Register can be accessed multiple
times to program individual bits, as long as the register remains unlocked.
Each Protection Register has an associated Lock Register bit. When a Lock Register bit is
programmed, the associated Protection Register can onl y b e r ead; it can no longer be p rog rammed.
Additionally, because the Lock Register bits themselves are OTP, when programmed, Lock
Register bits cannot be erased. Therefore, when a Protection Register is locked, it cannot be
unlocked
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Datasheet Intel StrataFlash® Wireless Memory (L18) April 2005
Order Number: 251902, Revision: 009 69
.
13.2.1 Reading the Protection Registers
The Protection Registers can be read from within any partition’s address space. To read the
Protection Register, first issue the Read Device Identifier command at any partitio ns ’ address to
place that partition in the Read Device Identifier state (see Section 9.2, “Device Commands” on
page 47). Next, perform a read operation at that partition’s base address plus the address offset
corresponding to the register to be read. Table 17, “Device Identifier Information” on page 77
shows the address offsets of the Protection Registers and Lock Registers. Register data is read 16
bits at a time.
Note: If a program or erase operation occurs within the device while it is reading a Protection Register,
certain restrictions may apply. See T ab le 15, “Simulta neous Ope ration Rest rictions ” on page 74 for
details.
Figure 29. Protection Register Map
0x89 Lock Register 1
15 14 13 12 11 10 9876543210
0x102
0x109
0x8A
0x91
128-bit Protection Register 16
(User-Programmable)
128-bit Protection Register 1
(User-Programmable)
0x88
0x85
64-bit Segment
(User-Programmable)
0x84
0x81
0x80 Lock Register 0
64-bit Segment
(Factory-Programmed)
15 14 13 12 11 10 9876543210
128-Bit Prote ction Register 0
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13.2.2 Programming the Protection Registers
To program any of the Protection Registers, first issue the Program Protection Register command
at the parameter partition’s base address plus the offset to the desired Protection Register (see
Section 9.2, “Device Commands” on page 47). Next, write the desired Protection Register data to
the same Protection Register address (see Figu re 29 , “Prote ction Register Map” on pag e 69).
The device programs the 64-bit and 128-bit user-programmable Protection Register data 16 bits at
a time (see Figure 46, “Protection Register Programming Flowchart” on page 92). Issuing the
Program Protection Register command outside of the Protection Register’s address space causes a
program error (SR[4] set). Attempt ing to program a locked Protection Register causes a program
error (SR[4] set) and a lock error (SR[1] set).
Note: If a program or erase operation occurs when programming a Protection Register, certain
restriction s may appl y. See Table 15, “Simul taneou s Operat ion Rest ricti ons” on page 74 for details.
13.2.3 Locking the Protection Registers
Each Protection Register can be locked by programming its respective lock bi t in the Lock
Register. To lock a Protection Register, program the corresponding bit in the Lock Register by
issuing the Program Lock Register command, followed by t he desir ed Lo ck Re giste r data (see
Section 9.2, “Device Commands” on page 47). The physical addresses of the Lock Registers are
0x80 for register 0 and 0x89 for register 1. These addresses are used when programming the lock
registers (see Table 17, “Device Identifier Informatio n” on page 7 7).
Bit 0 of Lock Register 0 is already programmed at the factory, locking the lower, pre-programmed
64-bit region of the first 128-bit Protection Register containing the unique identification number of
the device. Bit 1 of Lock Register 0 can be p rogrammed by the us er to lock the user -programmab le,
64-bit regi on of t h e firs t 1 28- bi t P rotect i on R egis t er. The other bi t s in Lock Regi st er 0 ar e not u sed .
Lock Register 1 controls the locking of the upper sixteen 128-bit Protection Registers. Each of the
16 bits of Lock Register 1 correspond to each of the upper sixteen 128-bit Protection Registers.
Programming a bit in Lock Register 1 locks the corresponding 128-bit Protection Register.
Caution: After being locked, the Protection Registers cannot be unlocked.
Intel StrataFlash® Wireless Memory (L18)
Datasheet Intel StrataFlash® Wireless Memory (L18) April 2005
Order Number: 251902, Revision: 009 71
14.0 Dual-Operation Considerations
The multi-partition architectu re of the device allows background pro gramming (or erasing) to
occur in one partition while data reads (or code execution) take place in another partition.
14.1 Memory Partitioning
The L18 flash memory array is divided into multiple 8-Mbit partitions, which allows simultaneous
read-while-write operations . Simultaneous program and erase is not allowed. Only one partition at
a time can be in program or erase mode.
The flash device supp orts read-w hile-write operations with bus cycle g ranularity and not command
granulari ty. In other wo rds, it is not assumed th at both bus cycles of a two cycle comm and (an erase
command for example) will always occur as back to back bus cycles to the flash device. In
practice, code fetches (reads) may be interspersed between write cycles to the flash device, and
they will likely be directed to a different partition than the one being written. This is especially true
when a processor is executing code fr om one partition that instru cts the processor to progr am or
erase in another partition.
14.2 Read-While-Write Command Sequences
When issuing commands to the device, a read operation can occur between 2-cycle Write
command’s (Figure 30, and Figure 31). However, a write operation issued between a 2-cycle
commands write sequence causes a command sequence error. (See Figure 32)
When reading from the same partition after issuing a Setup comm a nd, Status Register data is
returned, regardless of the read mode of the partition prior to issuing th e Setup co mman d.
Figure 30. Operating Mode with Correct Command Sequence Example
Partition A
Partition A
Partition B
0x20
0xD0
0xFF
Address [A]
WE# [W]
OE# [G]
Data [D/Q]
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14.2.1 Simultaneous Operation Details
The Intel StrataFlash® Wireless Memory (L18) supports simultaneous read from one partition
while programming or erasing in any other partition. Certain features like the Protection Registers
and Query data have special requirements with respect to simultaneous operation capability . These
will be detailed in the fol lowing sections.
14.2.2 Synchronous and Asynchronous RWW Characteristics and
Waveforms
This section describes the transition of write operation to asynchronous read, write to synchronous
read, and write operation with clock active.
14.2.2.1 Write operation to asynchronous read transition
W18 - tWHAV
The AC parameter W18 (tWHAV-WE# High to Address Valid) is required when transitioning from a
write cycle (WE# going high) to perform an asynchronous read (only address valid is required).
Figure 31. Operating Mode with Correct Command Sequence Example
Figure 32. Operating Mode with Illegal Command Sequence Example
Partition A
Partition B Partition A
0x20 Valid Array Data
0xD0
Address [A]
WE# [W ]
OE# [G]
Data [D/Q]
Partition A
Partiti on B
Partiti on A
Partition A
0x20
0xFF 0xD0
SR[7:0]
Address [A]
WE# [W]
OE# [G]
Dat a [D/Q]
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14.2.2.2 Write to synchronous read operation transition
W19 and W20 - tWHCV and tWHVH
The AC parameters W19 or W20 (tWHCV-WE# High to Clock Valid, and tWHVH - WE# High to
ADV# High) is required when transitioning from a write cycle (WE# going high) to perform a
synchronous burst read. A delay from WE# going high to a valid clock edge or ADV# going high
to latch a new address must be m et.
14.2.2.3 Write Operation with Clock Active
W21 - tVHWL
W22 - tCHWL
The AC parameters W21 (tVHWL- ADV# High to WE# Low) and W22 (tCHWL -Clock high to
WE# low) are required during write operatio ns when the device is in a synchronous mode and the
clock is active. A write bus cycle consists of two parts:
•the host provides an address to the flash device; and
•the host then provides data to the flash device.
The flash device in turn binds the received data with the received address. When operating
synchron ousl y (RCR[ 15] = 0), the add ress of a write cycle may b e provided to the flash by the first
active clock edge with ADV# low, or rising edge of ADV# as long as the applicable cycle
separation conditions are met between each cycle.
If neither a cloc k edge nor a r ising ADV# edg e is used to prov ide a new addr ess at the beginn ing of
a write cycle (the clock is stopped and ADV# is low), the address may also be provided to the flash
device by holding the address bus stable for the required amount of time (W5, tAVWH) before the
rising WE# edge.
Alternatively, the host may choose not to provide an address to the flash device during subsequent
write cycles (if ADV# is high and only CE# or WE# is toggled to separate the prior cycle from the
current write cycle). In this case, the flash device will use the most recently provided address from
the host.
Refer to Figure 20, “Write to Asynchronous Read Timing” on page 39, Figure 21, “Synchronous
Read to Write Timing” on page 39, and Figure 22, “Write to Synchronous Read Timing” on
page 40, for representation of these timings.
14.2.3 Read Operation During Buffered Programming
The multi-partition architectu re of the device allows background pro gramming (or erasing) to
occur in one partition while data reads (or code execution) take place in another partition.
To perform a read while buffered programming operation, first issue a Buffered Program set up
command in a partition. When a read oper ation occurs in the same partition after issuing a setu p
command, Status Register data will be returned, regardless of the read mode of the partition prior to
issuing the setup command.
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To read data from a block in other partition and the other partiti on alr eady in read array mode, a
new block address must be issued. However , if the other partition is not already in read array mode,
issuing a read array command will cause the buffered program operation to abort and a command
sequence error would be p osted in the S t atus Register. See Fi gu re 41, “Buffer Pro gram Flowch art”
on page 87 for more details.
Note: Simultaneous read-while-Buffered EFP is not supported.
14.3 Simultaneous Operation Restrict ions
Since the Intel StrataFlash® Wireless Memory (L18) supports simultaneous read from one
partition whil e progra m mi ng or er asin g in another partition, certain features like the Pr ot ection
Registers and CFI Query data have special requirements with respect to simultaneous operation
capability. (Table 15 provides details on restrictions during simultaneous operations.)
Table 15. Simultaneous Operation Restrictions
Protection
Register or
CFI data
Parameter
Partition
Array Data
Other
Partitions Notes
Read (See Notes) Write/Erase
While programming or erasing in a main partition, the Protection Register or CFI
data may be read from any other partition.
Reading the parameter partition array data is not allowed if the Protection Register
or Query data is being read from addresses within the parameter partition.
(See Notes) Read Write/Erase
While programming or erasing in a main partition, read operations are allowed in the
parameter partition.
Accessing the Protection Registers or CFI data from parameter partition addresses
is not allowed when reading array data from the parameter partition.
Read Read Write/Erase
While programming or erasing in a main partition, read operations are allowed in the
parameter partition.
Accessing the Protection Registers or CFI data in a partition that is different from the
one being programed/erased, and also different from the parameter partition is
allowed.
Write No Access
Allowed Read
While programming the Protection Register , reads are only allowed in the other
main partitions.
Access to array data in the parameter partition is not allowed. Programming of the
Protection Register can only occur in the parameter partition, which means this
partition is in Read Status.
No Access
Allowed Write/Erase Read While programming or erasing the parameter partition, reads of the Protection
Registers or CFI data are not allowed in any partition.
Reads in partitions other than the parameter partition are supported.
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Datasheet Intel StrataFlash® Wireless Memory (L18) April 2005
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15.0 Special Read States
The following sections des cribe non-array read states. Non-array reads can be performed in
asynchronous read or synchronous burs t mode. A non-array read operatio n occurs as asynchronous
single-word mode. When non-array reads are performed in asynchronous page mode only the first
data is valid and all subsequent data are undefined. When a non-array read operation occurs as
synchronous burst mode, the sa me word of d ata requ ested will be output o n successiv e clock edges
until the burst length requirements are satisfied.
Each partition can be in one of its read states independent of other partitions’ modes. See Figure 1 1 ,
“Asynchronous Single-Word Read with ADV# Low” on page 33 and Figure 14, “Synchronous
Single-Word Array or Non-array Read Timing” on page 35 for details.
15.1 Read Status Register
The status of any partition is determined by reading the Status Register from th e address o f that
particular partition. To read the S tatus R egister, issue the Read Status Register command within the
desired partition’s address range. Status Register information is available at the partition address to
which the Read Status Register, Word Program, or Block Erase command was issued. Status
Register data is automatically made availab le followin g a Word Program , Block Erase, or Block
Lock command sequence. Reads from a partition after any of these command sequences outputs
that partition’s status until another valid command is written to that partition (e.g. Read Array
command).
The Status Register is read using single asynchronous-mode or synchronous burst mode reads.
Status Register data is output on DQ[7:0], while 0x00 is output on DQ[15:8]. In asynchronous
mode the falling edge of OE#, or CE# (whichever occurs first) updates and latches the Status
Register contents. However , reading the Statu s Register in synchronous burst mode, CE# or ADV#
must be toggled to update status data. The Status Register read operations do not affect the read
state of the other partitions.
The Device Write Status bit (SR[7]) provides overall status of the device. The Partition Status bit
(SR[0]) indicates whether the addressed partition or so me oth e r par tition is actively programming
or erasing. Status register bits SR[6:1] present status and error information about the program,
erase, suspend, VPP, and block-locked operations.
Table 16. Status Register Description (Sheet 1 of 2)
Status Register (SR) Default Value = 0x80
Device
Write Status Erase
Suspend
Status Erase
Status Program
Status VPP Status Program
Suspend
Status
Block-
Locked
Status Partition
Status
DWS ESS ES PS VPPS PSS BLS PWS
76543210
Bit Name Description
7Device Write Status
(DWS) 0 = Device is busy; program or erase cycle in progress; SR[0] valid.
1 = Device is ready; SR[6:1] are valid.
6Erase Suspend Status
(ESS) 0 = Erase suspend not in effect.
1 = Erase suspend in effect.
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76 Order Number: 251902, Revision: 009
Always clear the Status Register prior to resuming erase operations. This avoids Status Register
ambiguity when issuing commands during Erase Suspend. If a command sequence error occurs
during an erase-suspend state, the Status Register contains the command sequence error status
(SR[7,5,4] set). When the erase operation resumes and finishes, possible errors during the erase
operation cannot be detected via the Status Register because it contains the previous error status.
15.1.1 Clear Status Register
The Clear Status Register command clears the status register, leaving all partition read states
unchanged. It functions independent of VPP. The Write State Machine (WSM) sets and clears
SR[7,6,2,0], but it sets bits SR[5:3,1] without clearing them. The Status Regis ter shou ld be cleared
before starting a command sequence to avoid any ambiguity. A device reset also clears the Status
Register.
15.2 Read Device Identifier
The Read Device Identifier command instructs the addressed partitio n to output manufacturer
code, device identifier code, block-lock status, protection register data, or configuration register
data when that partition’s addresses are read (see Secti on 9. 2, “Devi ce Comm ands” on page 47 for
details on issuing the Read Device Identifier command). Table 17, “Device Identifier Information”
on page 77 and Table 18, “Device ID codes” on page 77 show the address offsets and data values
for this device.
Issuing a Read Device Identifier command to a partition that is programming or erasing places that
partition in the Read I dentif ier state while the partition continues to pr ogr am or erase in the
background.
5 Erase Status (ES) 0 = Erase successful.
1 = Erase fail or program sequence error when set with SR[4,7].
4 Program Status (PS) 0 = Program successful.
1 = Program fail or program sequence error when set with SR[5,7]
3V
PP Status (VPPS) 0 = VPP within acceptable limits during program or erase operation.
1 = VPP < VPPLK during program or erase operation.
2Program Suspend Status
(PSS) 0 = Program suspend not in effect.
1 = Program suspend in effect.
1Block-Locked Status
(BLS) 0 = Block not locked during program or erase.
1 = Block locked during program or erase; operation aborted.
0Partition Write Stat us
(PWS)
DWS PWS
0 0 = Program or erase operation in addressed partition.
0 1 = Program or erase operation in other partition.
1 0 = No active program or erase operations.
1 1 = Reserved.
(Non-buffered EFP operation. For Buffered EFP operation, see
Section 11.3, “Buffered Enhanced Factory Programming” on
page 60).
Table 16. Status Register Description (Sheet 2 of 2)
Status Register (SR) Default Value = 0x80
Intel StrataFlash® Wireless Memory (L18)
Datasheet Intel StrataFlash® Wireless Memory (L18) April 2005
Order Number: 251902, Revision: 009 77
15.3 CFI Query
The CFI Query command instructs the device to outpu t Common Flash Interface (CFI) data when
partition addresses are read. See Section 9.2, “Device Commands” on page 47 for details on
issuing the CFI Query command. Appendix C, “Common Flash Interface” on page 93 shows CFI
information and addres s offsets within the CFI database.
Issuing the CFI Query command to a partition that is programming or erasing places that partition’ s
outputs in the CFI Query state, while the partition continues to program or erase in the background.
The CFI Query command is subject to read restrictions depend ent on param eter par titio n
availability, as described in Table 15.
Table 17. Device Identifier Information
Item Address(1,2) Data
Manufacturer Code PBA + 0x00 0089h
Device ID Code PBA + 0x01 ID (see Table 18)
Block Lock Configuration:
BBA + 0x0 2
Lock Bit:
• Block Is Unlocked DQ0 = 0b0
• Block Is Locked DQ0 = 0b1
• Block Is not Locked-Down DQ1 = 0b0
• Block Is Locked-Dow n DQ1 = 0b1
Configuration Register PBA + 0x05 Configuration Register Data
Lock Register 0 PBA + 0x80 PR-LK0
64-bit Factory-Programmed Protection Register PBA + 0x81–0x84 Factory Protection Register Data
64-bit User-Programmable Protection Register P BA + 0x85–0x88 User Protecti on Register Data
Lock Register 1 PBA + 0x89 P rotection Register Data
16x128-bit User-Programmable Protection
Registers PBA + 0x8A–0x109 PR-LK1
Notes:
1. PBA = Partitio n Ba se Add r ess.
2. BBA = Block Base Address.
Table 18. Device ID codes
ID Code Type Device Density Device Identifier Codes
–T
(Top Parameter) –B
(Bottom Parameter)
Device Code 64 Mbit 880B 880E
128 Mbit 880C 880F
256 Mbit 880D 8810
Intel StrataFlash® Wireless Memory (L18)
April 2005 Intel StrataFlash® Wireless Memory (L18) Datasheet
78 Order Number: 251902, Revision: 009
Appendix A Write State Machine (WSM)
Figure 33 through Figure 38 show the command state transitions (Next State Table) based on
incoming commands. Only one partition can be actively programming or erasing at a time. Each
partition stay s in its last read state (Read Array, Read Device ID, CFI Query or Read Status
Register) until a new command changes it. The next WSM state does not depend on the partition’s
output state.
Figure 33. Write State Machine—Next State Table (Sheet 1 of 6)
Read
Array
(2)
Word
Program (3,4)
Buffered
Program
(BP)
Erase
Setup (3,4)
Buffered
Enhanced
Factory Pgm
Setup (3, 4)
BE Con firm,
P/E
Resume,
ULB,
Confirm (8)
BP / Prg /
Erase
Suspend
Read
Status
Clear
Status
Register (5)
Read
ID/Query
Lock, Unlock,
Lock-down
,
CR setup (4)
(FFH) (10H/40H) (E8H) (20H) (80H) (D0H) (B0H) (70H) (50H) (90H, 98H) (60H)
Ready Program
Setup BP Set up Erase
Setup BEFP Setup Lock/CR
Setup
Ready
(Unlock
Block)
Setup
Busy
Setup
Busy Word
Program
Suspend
Suspend Word
Program
Busy
Setup
BP Load 1
BP Load 2
BP
Confirm BP Busy
BP Busy
BP Suspend
BP
Suspend BP Busy
Setup Erase Busy
Busy Erase
Suspend
Suspend Erase
Suspend
Word
Program
Setu p in
Erase
Suspend
BP Setu p in
Erase
Su spen d Erase Busy
Lock/CR
Setu p in
Erase
Suspend
BP Suspend
Erase
BP Busy
Erase Busy
Erase Suspend Erase Suspend
Ready (Error)
Erase Busy
BP Suspend
Ready (Error)
Word
Program
Program Busy
Word Program Suspen d
Word Program Busy
OTP
Ready (Loc k Error)
Ready Ready
Ready (Lock Error)
OTP Bu s y
Current Chip
State (7)
Command I nput to Chip an d resulting
Chip
Next State
BP
BP Busy
Lock /CR Setu p
BP Load 2
Ready (Error)Ready (Error)
Word Program Busy
BP Confirm if Dat a load into Pr ogram Bu ff er is complete; Else BP Load 2
Word Program Suspend
BP Load 1
Intel StrataFlash® Wireless Memory (L18)
Datasheet Intel StrataFlash® Wireless Memory (L18) April 2005
Order Number: 251902, Revision: 009 79
Figure 34. Write State Machine—Next State Table (Sheet 2 of 6)
Setup
Busy
Word
Program
Suspend in
Erase
Suspend
Suspend
Word
Program
Busy in
Erase
Suspend
Setup
BP Load 1
BP Load 2
BP
Confirm
BP Busy in
Erase
Suspend
BP Busy
BP Suspend
in Erase
Suspend
BP
Suspend
BP Busy in
Erase
Suspend
Erase
Suspend
(Unlock
Block)
Setup BEFP
Loading
Data (X=32)
Erase Suspend (Error)
Erase Suspend (Lock Error [ Botch])
Ready (Error) Ready (Error)
BP Suspend in Erase Suspend
Ready (Error in Erase Suspend)
BP Busy in Erase Suspend
BP Suspend in Eras e Suspend
BP Busy in Erase Suspend
Word Program Busy in Erase Suspend
Word
Program in
Erase
Suspend
Word Program Bu sy in Erase Suspend
Word Program Suspend in Erase Suspend
Lock/CR Setup in Erase
Suspend Erase Suspend (Lock Error)
BP Confirm if Data load into Program Buffer is complete; Else BP Load 2
BP in Erase
Suspend
BP Load 2
Word Program Bu sy in Erase Suspend Busy
Word Program Sus pend in Erase Su spend
BEFP Program and Verify Busy (if Block Address given matches address given on BEFP Setup command). Commands treated as data. (7)
BEFP
Busy
Buffered
Enhanced
Factory
Program
Mode
BP Load 1
Read
Array
(2)
Word
Program (3,4)
Buffered
Program
(BP)
Erase
Setup (3,4)
Buffered
Enhanced
Factory Pgm
Setup (3, 4)
BE Confirm ,
P/E
Resume,
ULB,
Confirm (8)
BP / Prg /
Erase
Suspend
Read
Status
Clear
Status
Register (5)
Read
ID/Query
Lock, Unlock ,
Lock-down
,
CR setup (4)
(FFH) (10H/40H) (E8H) (20H) (80H) (D0H) (B0H) (70H) (50 H) (90H, 98H) (60H)
Current Chip
State (7)
Command Input to Chip and resulting
Chip
Next St a t e
Intel StrataFlash® Wireless Memory (L18)
April 2005 Intel StrataFlash® Wireless Memory (L18) Datasheet
80 Order Number: 251902, Revision: 009
Figure 35. Write State Machine—Next State Table (Sheet 3 of 6)
Setup
Busy
Setup
Busy
Suspend
Setup
BP Load
1
BP Load
2
BP
Confirm
BP Busy
BP
Suspend
Setup
Busy
Suspend
Erase
Word
Program
OTP
Ready
Current Chip
State (7)
BP
Lock/CR Setup
OTP
Setup (4)
Lock
Block
Confirm (8)
Lock-Down
Block
Confirm (8)
Write RCR
Confirm (8) Block Address
(?WA0) 9 Illegal Cmds or
BEFP Data (1)
(C0H) (01H) (2FH) (03H) (X XXXH) (all other codes)
OTP
Setup
Ready
(Lock
Error)
Ready
(Lock
Block)
Ready
(Lock Down
Blk)
Ready
(Set CR)
Ready
N/A
Ready
Ready (BP Load 2 BP Load 2
Ready
BP Confirm if
Data load into
Program Buffer is
complete; ELSE
BP Load 2
Ready (Error)
(Proceed if
unlocked or lock
error)
Ready (Er ror)
Ready
Ready
N/A
BP Confirm if Data load into Program Buffer is
comp lete; ELSE BP load 2
Ready (Error)
BP Busy
Erase Busy
Word Program Suspend
BP Load 1
BP Load 2
OTP Busy
Word Program Busy
Word Program Busy
WSM
Operation
Completes
Command Input to Chip and resulting
Chip
Next State
N/A
Ready (Lock Error)
Ready
BP Suspend
Ready (Error)
Erase Suspend
N/A
N/A
Intel StrataFlash® Wireless Memory (L18)
Datasheet Intel StrataFlash® Wireless Memory (L18) April 2005
Order Number: 251902, Revision: 009 81
Figure 36. Write State Machine—Next State Table (Sheet 4 of 6)
OTP
Setup (4)
Lock
Block
Confirm (8)
Lock-Down
Block
Confirm (8)
Write RCR
Confirm (8) Block Address
(?WA0) 9 Illegal Cmds or
BEFP Data (1)
(C0H) (01H) (2FH) (03H) (XXXXH) (all other codes)
WSM
Operation
Completes
Command Input to Chip and resulting
Chip
Next State
Current Chip
State (7)
NA
Erase Suspen
d
N/A
Ready (BP L oad 2 BP Load 2
Ready
BP Confirm if
Data load into
Progr a m Bu ffer is
comp lete ; Else
BP Load 2
Ready (Error)
(Proceed if
unlocked or lock
error)
Ready (Error)
Erase Suspen
d
Erase
Suspend
(Lock
Error)
Erase
Suspend
(Lock
Block)
Erase
Suspend
(Lock Down
Block)
Erase
Suspend
(Set CR)
Ready (BEFP
Loading Data) Ready (Error)
BEFP Program and Verify Busy (if Block Address
given matches address given on BEFP Setup
command). Commands treated as data. (7)
BP Load 1
Ready (Error)
BP Confirm if Data load into Program Buffer is
complete; Else BP Load 2
Ready (Error in Erase Suspend)
Word Program Suspend in Erase Suspend
BP Load 2
Ready
Word Prog r am Bu sy in Erase Suspend Bu sy
Word Program Busy in Erase Suspend
BEFP Busy
Ready
Erase Suspend (Lock Error) N/A
BP Busy in Eras e Su spen d
BP Suspen d i n Er a se Suspen d
N/A
Setup
Busy
Suspend
Setup
BP Load
1
BP Load
2
BP
Confirm
BP Busy
BP
Suspend
Setup
BEFP
Busy
Buffered
Enhanced
Factory
Program
Mode
Lock/CR Setup in Erase
Suspend
BP in Erase
Suspend
Word
Program in
Erase
Suspend
Intel StrataFlash® Wireless Memory (L18)
April 2005 Intel StrataFlash® Wireless Memory (L18) Datasheet
82 Order Number: 251902, Revision: 009
Figure 37. Write State Machine—Next State Table (Sheet 5 of 6)
Read
Array
(2)
Word
Program
Setup (3,4) BP Setu p Erase
Setup (3,4)
Buffered
Enhanced
Factory Pgm
Setup (3, 4)
BE Confirm ,
P/E
Resume,
ULB Confirm
(8)
Program/
Erase
Suspend
Read
Status
Clear
Status
Register (5)
Read
ID/Query
Lock, Unlock ,
Lock-down
,
CR setup (4)
(FFH) (10H/40H) (E8H) (20H) (30H) (D0H) (B0H) (70H) (50H) (90H, 98H) (60H)
Status Read
Command Input to Chip and resulting Output M ux N e xt Sta t e
Output Next State Table
Status Read
Output mux
does n ot
change.
Status
Read
ID Read Statu s Read
Ready,
Erase Suspend,
BP Suspend
Statu s Read
Lock/CR Setup,
Lock/CR Setup in
Erase Susp
Output does not change. Status Read
BEFP Setup,
BEFP Pgm & Ver ify
Busy,
Erase Setup,
OTP Se t u p ,
BP: Setup, Load 1,
Load 2, Confirm,
Word Pgm Setup,
Word Pgm Setup in
Erase Susp,
BP Setup, Load1,
Load 2, Confirm in
Erase Suspend
Current chip state
OTP Bu s y
BP Busy,
Word Program
Busy,
Erase Busy,
BP Busy
BP Busy in Erase
Suspend
Word Pgm
Suspend,
Wo rd Pg m Busy in
Erase Suspend,
Pgm Suspend In
Erase Suspend
Read Array
Intel StrataFlash® Wireless Memory (L18)
Datasheet Intel StrataFlash® Wireless Memory (L18) April 2005
Order Number: 251902, Revision: 009 83
Notes:
1. "Illegal commands" include commands outside of the allowed command set (allowed commands: 40H
[pgm], 20H [erase], etc.)
2. I f a "Read Array" is attempted from a busy partition, the result will be invalid data. The ID and Query
data are located at different locations in the address map.
3. 1st and 2nd cycles of "2 cycles write commands" must be given to the same partition address, or
unexpected results will occur.
4. To protect memory contents against erroneous command sequences, there are specific instances in a
multi-cycle command sequence in which the second cycle will be ignored. For example, when the
device is program suspended and an erase setup command (0x20) is given followed by a confirm/
Figure 38. Write State Machine—Next State Table (Sheet 6 of 6)
OTP Busy
BP Busy,
Word Program
Busy,
Erase Busy,
BP Busy
BP Busy in Erase
Suspend
Word Pgm
Suspend,
Word Pgm Busy in
Erase Suspend,
Pgm Suspend In
Erase Suspend
BEFP Setup,
BEFP P gm & Verify
Busy,
Erase Setup,
OTP Setup,
BP: Setup, Load 1,
Load 2, Confir m,
Word Pgm Setup,
Word Pgm Setup in
Erase Susp,
BP Setup, Load1,
Load 2, Confirm in
Erase Suspend
Current chip state
Ready,
Erase Suspend,
BP Suspend
Lock/ C R Setup,
Lock/ C R Setup in
Erase Susp
OTP
Setup (4)
Lock
Block
Confirm (8)
Lock-Down
Block
Confirm (8)
Write CR
Confirm (8) Block A ddr ess
(?WA0) Illegal Cmds or
BEFP Data (1)
(C0H) (01H) (2FH) (03H) (FFFFH) (all oth er codes)
WSM
Operation
Completes
Outpu t does
not change.
Array
Read
Statu s Read
Array Read Outp ut does not
change.
Output does not change.
Status
Read
Status Read
Statu s Read
Command Input to Chip and resulting Output Mux Next State
Output Next State Table
Intel StrataFlash® Wireless Memory (L18)
April 2005 Intel StrataFlash® Wireless Memory (L18) Datasheet
84 Order Number: 251902, Revision: 009
resume command (0xD0), the second command will be ignored because it is unclear whether the user
intends to erase the block or resume the program operation.
5. The Clear Status command only clears the error bits in the status register if the device is not in the
following modes: WSM running (Pgm Busy , Erase Busy, Pgm Busy In Erase Suspend, OTP Busy , BEFP
modes).
6. BEFP writes are only allowed when the status register bit #0 = 0, or else the data is ignored.
7. The "current state" is that of the "chip" and not of the "partition"; Each partition "remembers" which
output (Array , ID/CFI or S tatus) it was last pointed to on the last instruction to the "chip", but the next
state of the chip does not depend on where the partition's output mux is presently pointing to.
8. Confirm commands (Lock Block, Unlock Block, Lock-Down Block , Conf iguration Register ) perform the
operation and then move to the Ready St ate.
9. WA0 refers to the block address latched during the first write cycle of the current operation.
Intel StrataFlash® Wireless Memory (L18)
Datasheet Intel StrataFlash® Wireless Memory (L18) April 2005
Order Number: 251902, Revision: 009 85
Appendix B Flow charts
Figure 39. W ord Program Flowchart
Program
Suspend
Loop
Start
Write 0x40,
Word Address
Write Data,
Word Address
Read Status
Register
SR[7] =
Full Status
Check
(if desired)
Program
Complete
Suspend?
1
0
No
Yes
WORD PROGRAM PROCEDURE
Repeat for subsequent Word Program operations.
Full Status Register c heck c an be done after each program, o
r
after a sequence of program operations.
Write 0xFF after the last operation to set t o the R ead A rray
state.
Comments
Bus
Operation Command
Data = 0x40
Addr = Location to program
Write Program
Setup
Data = Data to program
Addr = Location to program
Write Data
Status register dat aRead None
Check SR[7]
1 = WSM Ready
0 = WSM Busy
Idle None
(Setup)
(Confirm)
FULL STATUS CHECK PROCEDURE
Read Status
Register
Program
Successful
SR[3] =
SR[1] =
0
0
SR[4] =
0
1
1
1VPP Range
Error
Device
Protect Error
Program
Error
If an error is detected, clear t he St at us Regis ter before
continuing operations - only the Clear Staus Register
command clears the St at us Register error bits.
Idle
Idle
Bus
Operation
None
None
Command
Check SR[3]:
1 = VPP Error
Check SR[4]:
1 = Data Program Error
Comments
Idle None Check SR[1]:
1 = Block locked; operation aborted
Intel StrataFlash® Wireless Memory (L18)
April 2005 Intel StrataFlash® Wireless Memory (L18) Datasheet
86 Order Number: 251902, Revision: 009
Figure 40. Program Suspend/Resume Flowchart
Read Status
Register
SR.7 =
SR.2 =
Write FFh
Susp Partition
Rea d Array
Data
Program
Completed
Done
Reading
Write FFh
Pgm'd Partition
Write D0h
Any Address
Program
Resumed Read A rray
Data
0
No
0
Yes
1
1
PR OGR AM SUSP EN D / R ESU M E PR OC ED U R E
Write Program
Resume Dat a = D0h
Addr = Suspended block (BA)
Bus
Operation Command Comments
Write Program
Suspend Dat a = B 0h
Addr = Block t o suspend (BA )
Standby Check SR.7
1 = WSM ready
0 = WSM busy
Standby Check SR.2
1 = Program suspended
0 = Program completed
Write Read
Array
Data = FFh
Addr = Any address within the
suspended partition
Read Read array data from block other than
the one being programmed
Read Status register data
Addr = Suspended block (BA)
PGM_SUS.WM
F
Start
Write B0h
Any Address
Program Suspend
Read Status
Progra m Resu me Read Array
Read Array
Write 70h
Sa me Pa rtit ion Write Read
Status Data = 70 h
Addr = Same partition
I f the suspended pa r ti ti on was pl aced i n Read Ar r ay m ode:
Write Read
Status
Return partition to Status mode:
Data = 70 h
Addr = Same partition
Write 70h
Sa me Pa rtit ion
Read Status
Intel StrataFlash® Wireless Memory (L18)
Datasheet Intel StrataFlash® Wireless Memory (L18) April 2005
Order Number: 251902, Revision: 009 87
Figure 41. Buffer Program Flowchart
B uffer Programming Pro cedure
Start
Get Next
Targe t A d dress
Iss u e B u ffe r P ro g. C md.
0xE8,
Word Address
Read Status Register
at W ord A ddress
W rite Buffer
Available?
SR[7] =
1 = Yes
Device
Su pp orts B uffer
Writes?
S et Time ou t o r
Loop Counter
Timeout
or Count
Expired?
W rite Confirm 0 xD 0
and Word Ad dress
(Note 5)
Yes
No
B uffe r P ro g ram Da ta ,
Start Word Address
X = 0
0 = No Ye s
Use Single Word
Programming
A bo rt B u ffe r
Program?
No
X = N?
W rite B uffe r D a ta ,
W ord Address
X = X + 1
W rite to another
Block Address
Buffer Program Aborted
No
Yes
Yes
W rite Word Count,
Word Address
Suspend
Program
Loop
Re ad Status Re gister
(Note 7)
Is BP finish e d?
SR[7] =
Full Status
Che ck if Desired
Program Complete
Suspend
Program?
1=Yes
0=No Yes
No
Issue Read
Status Register
Command
No
1. Word count value on D[7:0] is loaded into the word count
reg iste r. C o u nt ra ng e s for th is d e vice a re N = 0x0 0 to 0 x 1F.
2. The device outputs the Status Register when read.
3. Write Buffer contents will be programmed at the issued word
address.
4. Align the start address on a Write Buffer boundary for
ma ximu m p rog ramm ing performa nce (i.e., A[4:0] of the Start
Word Address = 0x00).
5. The B uffered Program m ing C o nfirm command m u st be
issued to an address in the same block, for example, the
original Start Word Address, or the last address used during the
loop that loaded the buffer data.
6. The Status Register indicates an improper command
sequence if the Buffer Program command is aborted; use the
Clear Status Register command to clear error bits.
7. The Status Register can be read from any addresses within
the programming partition.
Full status check can be done after all erase and write
sequences complete. Write 0xFF after the last operation to
place the partition in the Read Array state.
Bus
Operation
Idle
Read
Command
None
None
Write Bu ffe r Pr og .
Setup
Read None
Idle None
Comments
C h e ck SR[7]:
1 = WSM R eady
0 = WSM Busy
Status register Data
Ad d r = N o te 7
Data = 0xE8
Addr = Word Address
SR[7] = V alid
Addr = Word Address
Check S R [7]:
1 = Write Buffer available
0 = No W rite Buffer available
Write
(Notes 5, 6) B uffe r P rog .
Conf. Data = 0xD0
Add r = Original W o rd Address
Write
(Notes 1, 2) None Data = N-1 = Word Count
N = 0 co rresponds to coun t = 1
Addr = Word Address
Write
(Notes 3, 4) None D ata = Write Buff e r D ata
Addr = Start Word Address
Write
(Note 3) None Data = Write Buff e r D ata
Addr = Word Address
Other partitions of the device can be read by addressing those partitions
and driving OE# low. (An y wr ite commands are not allowe d dur ing this
period.)
0
xFF commands can be issued to read from
a
ny blocks in other partitions
Intel StrataFlash® Wireless Memory (L18)
April 2005 Intel StrataFlash® Wireless Memory (L18) Datasheet
88 Order Number: 251902, Revision: 009
Figure 42. Buffered EFP Flowchart
Write Data @ 1ST
Word Address
Last
Data?
Write 0xFFFF,
Address Not within
Current Block
Program
Done?
Read Status Reg.
Y
No (SR[7]=0)
Full Status Check
Procedure
Program
Complete
Read Status Reg.
BEFP
Exited?
Yes (SR[7]=1)
Start
Write 0x80 @
1ST Wo rd Add r es s
VPP app lied,
Block unlocked
Write 0xD0 @
1STWordAddress
BEFP Setup
Done?
Read Status Reg.
Exit
N
Program & Verify Phase Exit PhaseSetup Phase
BUFFERED ENHANCED FACTORY PRO GRAMMING (Buffered-EFP) PROCEDURE
X = 32?
Initialize Count:
X = 0
Increment Count:
X = X+1
Y
NOTES:
1. First-word address to be programmed within the target block must be aligned on a wr ite-buff er boundary.
2. Write-buffer contents are progr ammed sequentially to th e flash ar ray starting at the firs t word addr es s;WSM inter nally inc r em ents addre ssing.
N
Check VPP, Loc k
Errors (SR[3,1])
Yes (SR[7]=0)
Comments
Bus
State Operation
BEFP setup delay
Data Stream
Ready?
Read Status Reg.
No (SR[0]=1)
Repeat for subseque nt blocks;
After BEFP exit, a full Status Register check can
determine if any program error occurred;
See full Status Register check procedure in the
Word Program flowchart.
Write 0xFF to enter Read Array state.
Check SR[7 ]:
0 = Ex it Not Co m ple t e d
1 = Exit Completed
Check Exit
Status
Read Status
Register Data = Status Reg. Data
Address = 1ST Word Addr
BEFP Exit
Standby
If SR[7] is set, check:
SR[3] set = VPP Error
SR[1] se t = Loc k ed B l oc k
Error
Condition
Check
Standby
Check S R[7 ]:
0 = BEFP Ready
1 = BEFP Not Ready
BEFP
Setup
Done?
Standby
Data = Status Reg. Data
Address = 1ST
Word Addr
Status
Register
Read
Data = 0xD0 @
1ST Word
Address
BEFP
Confirm
Write
Data = 0x80 @ 1
ST Word
Address
BEFP
Setup
Write
(Note 1)
VPPH
applied to VPP
Unlock
Block
Write
BEFP Setup
Bus
State CommentsOperation
No (SR[0]=1)
Yes (SR[0]=0)
No (S R[ 7]=1)
Yes (SR[0]=0)
BEFP Pr ogr a m & Veri f y
CommentsBus State Operation
Write
(Note 2) Load
Buffer
Standby Increment
Count
Standby Initialize
Count
Data = Data to Program
Address = 1ST Word Addr.
X = X+1
X = 0
Standby Buffer
Full?
X = 32?
Yes = Read SR[0]
No = Load Ne xt Data Word
Read
Standby
Status
Register
Data S tr eam
Ready?
Data = Status Register Data
Address = 1ST Word Addr.
Check S R[0 ]:
0 = Rea dy for Data
1 = Not Ready for Data
Read
Standby
Standby
Write
Status
Register
Program
Done?
Last
Data?
Exit Prog &
Verify Phase
Data = Status Reg. data
Address = 1ST Word Addr.
Check S R[0 ]:
0 = Program Done
1 = Program in Progress
No = Fill buffer again
Yes = Exit
Data = 0x FFFF @ addr e ss not i n
current block
Intel StrataFlash® Wireless Memory (L18)
Datasheet Intel StrataFlash® Wireless Memory (L18) April 2005
Order Number: 251902, Revision: 009 89
Figure 43. Block Erase Flowchart
Start
FULL ERASE STATUS CHECK PRO CEDURE
Repeat for subsequent block eras ures.
Full Status register chec k can be done after eac h block eras e
or after a sequence of block eras ures.
Write 0xFF after the last operation to enter read array m ode.
Only the Clear Status R egist er c ommand c l ears SR [ 1, 3, 4, 5
].
If an error is detected, cl ear t he Stat us register before
attempting an erase retry or other error recovery.
No
Suspend
Erase
1
0
0
0
1
1,1
1
1
0Yes
Suspend
Erase
Loop
0
Write 0x20,
Block Address
Write 0xD0,
Block Address
Read Status
Register
SR[7] =
Full Erase
Status C hec k
(if desired)
Block Erase
Complete
Read Status
Register
Block Erase
Successful
SR[1] = Block Locked
Error
BLOCK ERASE PROCEDURE
Bus
Operation Command Comments
Write Block
Erase
Setup
Data = 0x20
Addr = Block to be erased (BA )
Write Erase
Confirm Data = 0xD0
Addr = Block to be erased (BA )
Read None Status Regis t er dat a.
Idle None Check SR[7]:
1 = WSM ready
0 = WSM busy
Bus
Operation Command Comments
SR[3] = VPP Range
Error
SR[4,5] = Command
Sequence Error
SR[5] = Block Eras e
Error
Idle None Check SR[3]:
1 = VPP Range Error
Idle None Check SR[4,5]:
Both 1 = Command Sequenc e E rror
Idle None Check SR[5]:
1 = Block Erase Error
Idle None Check SR[1]:
1 = Attempted erase of lock ed block;
erase aborted.
(Bloc k Er ase)
(Erase Confirm)
Intel StrataFlash® Wireless Memory (L18)
April 2005 Intel StrataFlash® Wireless Memory (L18) Datasheet
90 Order Number: 251902, Revision: 009
Figure 44. Era se Su spen d/R esu me Flowc ha rt
Erase
Completed
Read Array
Data
0
0
No
Read
1
Program
Program
Loop
Read A rray
Data
1
Start
Read Status
Register
SR[7] =
SR[6] =
Erase
Resumed
Read or
Program?
Done
Write
Write
Idle
Idle
Write
Erase
Suspend
Read A rray
or Program
None
None
Program
Resume
Dat a = 0x B0
Addr = Same partition address as
above
Data = 0xFF or 0x40
Addr = Any address within the
suspended partition
Che ck SR[7]:
1 = WSM ready
0 = WSM busy
Che ck SR[6]:
1 = Erase suspended
0 = Era se co mple ted
Dat a = 0x D0
Addr = Any address
Bus
Operation Command Comments
Read None Status Register data.
Addr = Same partition
Read or
Write None Read array or program data from/to
block other than the one being erased
ERASE SUSPEND / RESUME PROCEDURE
If the sus pende d partition w as pl ac ed in
Rea d Ar ray mode or a Progr am Lo op :
Write 0xB0,
Any Address
(Erase Suspend)
Write 0x70,
Same Partition
(Read Status)
Write 0xD0,
Any Address
(
Erase Resume)
Write 0x70,
Same Partition
(Read Status)
Write 0xFF,
Erased Partition
(Read Array)
Write Read
Status Data = 0x 70
Addr = Any partition address
Write Read
Status
Register
Return partition to Status mode:
Dat a = 0x 70
Addr = Same partition
Intel StrataFlash® Wireless Memory (L18)
Datasheet Intel StrataFlash® Wireless Memory (L18) April 2005
Order Number: 251902, Revision: 009 91
Figure 45. Block Lock Operations Flowchart
No
Start
Write 0x60,
Block Address
Write 0x90
Read Block
Lock Status
Locking
Change?
Lock Change
Complete
Write either
0x01/0xD0/0x2F,
Block Address
Write 0xFF
Partition Address
Yes
Write
Write
Write
(Optional)
Read
(Optional)
Idle
Write
Lock
Setup
Lock,
Unlock, or
Lock-Down
Confirm
Read
Device ID
Block Lock
Status
None
Read
Array
Data = 0x60
Addr = Block to lock/unlock/lock-down
Data = 0x01 (Block Lock)
0xD0 (Block Unlock)
0x2F (Lock-Dow n Blo ck)
Addr = Block to lock/unlock/lock-down
Data = 0x90
Addr = Block address + offset 2
Block Lock status data
Addr = Block address + offset 2
Confirm locking change on D[1,0].
Data = 0xFF
Addr = Block address
Bus
Operation Command Comments
LOCKING OPERATIONS PROCEDURE
(Lock Confirm)
(Read Device ID)
(Read Array)
Optional
(Lock Setup)
Intel StrataFlash® Wireless Memory (L18)
April 2005 Intel StrataFlash® Wireless Memory (L18) Datasheet
92 Order Number: 251902, Revision: 009
Figure 46. Protection Register Programming Flowchart
FULL STATUS CHECK PROCEDURE
Program Protection Regist er operat ion address es m ust be
within the Protection R egis ter addres s spac e. Addresses
outside this space will return an error.
Repeat for subsequent programming operat ions .
Full Status Register c heck c an be done after each program , o
r
after a sequence of program operations.
Write 0xFF after the last operation to set Read Array state.
Only the Clear Staus Regist er c om mand cl ears SR [ 1, 3, 4].
If an error is detected, cl ear t he Stat us register before
attempting a program retry or other error rec overy.
1
0
1
1
1
PROTECTION REGISTER PROGRAMMING PROCEDURE
Start
Write 0xC0,
PR Address
Writ e PR
Address & Data
Read Status
Register
SR[7] =
Full Status
Check
(if desired)
Program
Complete
Read Status
Register Data
Program
Successful
SR[3] =
SR[4] =
SR[1] =
VPP Range Error
Program Error
Register Locked;
Program Abort ed
Idle
Idle
Bus
Operation
None
None
Command
Check SR[3]:
1 =VPP Range Error
Check SR[4]:
1 =Programming Error
Comments
Write
Write
Idle
Program
PR Setup
Protection
Program
None
Data = 0xC0
Addr = First Location to Program
Data = Data to Program
Addr = Location to Program
Check SR[7]:
1 = WSM Ready
0 = WSM Busy
Bus
Operation Command Comments
Read None Status Regis t er Data.
Idle None Check SR[1]:
1 =Block locked; operation aborted
(Program Setup)
(Confirm Data )
0
0
0
Intel StrataFlash® Wireless Memory (L18)
Datasheet Intel StrataFlash® Wireless Memory (L18) April 2005
Order Number: 251902, Revision: 009 93
Appendix C Common Flash Interface
The Common Flash Interface (CFI) is part of an overall specification for multiple command-set
and control-interface descriptions. This appendix describes the database structure containing the
data returned by a read operation after issuing the CFI Query command (see Section 9.2, “Device
Commands” on pa ge 47). System software can parse this database str ucture to obtain information
about the flash device, such as block size, density, bus width, and electrical specifications. The
system software will then know which command set(s) to use to properly perform flash writ es,
block erases, reads and otherwise control the flash device.
C.1 Query Structure Output
The Query database allows system software to obtain information f or contro lling the flash device.
This section describes the device’s CFI-compliant interface that allows access to Query data.
Query data ar e presented on the lowest-order data outputs (DQ7-0) only. The numerical of fset value
is the address relative to the maximum bus width supported by the device. On this fam ily of
devices, the Query table device starting address is a 10h, which is a word address for x16 devices.
For a word-wide (x16) device, the first two Query-structure bytes, ASCII “Q” and “R,” appear on
the low byte at word addresses 10h and 11h. This CFI-compliant devi ce outpu t s 00 h data on up per
bytes. The device outputs ASCII “Q” in the low byte (DQ7-0) and 00h in the high byte (DQ15-8).
At Qu ery addresses c ont aining two or mo re by t es of informatio n, the least significant data byte is
presented at the lower add res s, and the most s ignifican t data byte is presented at th e hig her addr ess.
In all of the following tables, addresses and data are represented in hexadecimal notation, so the
“h” suffix has been dropped. In addition, since the upper byte of word-wide devices is always
“00h,” the leading “00” has been dropped from the table notation and only the lower byte value is
shown. Any x16 device outputs can be assumed to have 00h on the upper byte in this mode.
Table 20. Example of Query Structure Output of x16- Devices
Table 19. Summary of Query Structure Output as a Function of Device and Mode
Device Hex
Offset Hex
Code ASCII
Value
Device Addres ses
00010: 51 “Q”
00011: 52 “R”
00012: 59 “Y”
Intel StrataFlash® Wireless Memory (L18)
April 2005 Intel StrataFlash® Wireless Memory (L18) Datasheet
94 Order Number: 251902, Revision: 009
C.2 Query Structure Overview
The Query command causes the flash component to display the Common Flash Inter f ace (C FI )
Query structure or “database.” The s tructure s ub- sections and address locations are summarized in
Table 21.
Table 21. Query Structure
Notes:
1. Refer to the Query S tructure Output section and offset 28h for the detailed definition of offset address as
a function of device bus width and mode.
2. BA = Block Address beginning location (i.e., 08000h is block 1’s beginning location when the block size
is 16-Kword).
3. Offset 15 defines “P” which points to the Primary Intel-specific Extended Query Table.
C.3 CFI Query Identification S tring
The Identification String pro vi des verif icatio n that the component supports the Common Flash
Interface specification. It also indicates the specification version and supported vendor-specified
command se t(s).
Table 22. CFI Identification
Word Addressing:
Byte Addressing:
Offset
Hex Code
Value
Offset
Hex Code
Value
A
X
–A
0
D
15
–D
0
A
X
–A
0
D
7
–D
0
00010h 0051 "Q" 00010h 51 "Q"
00011h 0052 "R" 00011h 52 "R"
00012h 0059 "Y" 00012h 59 "Y"
00013h
P_ID
LO
PrVendor 00013h
P_ID
LO
PrVendor
00014h
P_ID
HI
ID # 00014h
P_ID
LO
ID #
00015h
P
LO
PrVendor 00015h
P_ID
HI
ID #
00016h
P
HI
TblAdr 00016h ... ...
00017h
A_ID
LO
AltVendor 00017h
00018h
A_ID
HI
ID # 00018h
... ... ... ...
Offset
Sub-Section Name
Description
(1)
00001-F h Reserved Re served for vendor-specific information
00010h CFI query identification string Command set ID and vendor data offset
0001Bh System interface information Device timing & voltage information
00027h Device geometry definition Flash device layout
P
(3)
Primary Intel-specific Extended Query Table Vendor-de fined ad ditional information specific
Intel StrataFlash® Wireless Memory (L18)
Datasheet Intel StrataFlash® Wireless Memory (L18) April 2005
Order Number: 251902, Revision: 009 95
Table 23. System Interface Information
C.4 Device Geometry Definition
Table 24. Device Geometry Definition
Offset Length Description Add.
Hex
Code Value
10h 3 Query-uniqu e AS C II string “QRY “ 10: --51 "Q"
11: --52 "R"
12: --59 "Y"
13h 2 Primary vend or comm an d set and control interface ID code. 13: --01
16-bit ID cod e for vend or-specified algorithms 14: --00
15h 2 Extended Q u ery Tab le primary algorithm address 15 : --0A
16: --01
17h 2 Alternate vendor command set and control interface ID code. 17: --00
0000h means no second vendor-specified algorithm exists 18: --00
19h 2 Secondary algorithm Extended Query Table address. 19: --00
0000h means none exists 1A: --00
Offset Length Description Add.
Hex
Code Value
1Bh 1 1B: --17 1.7V
1Ch 1 1C: --20 2.0V
1Dh 1 1D: --85 8.5V
1Eh 1 1E: --95 9.5V
1Fh 1
“n” such t hat typical single word program t i me-out = 2
n
µ-sec
1F: --08 256µs
20h 1
“n” such t hat typical max. buffer write t i me-out = 2
n
µ-sec
20: --09 512µs
21h 1
“n” such t hat typical bl ock erase tim e-out = 2
n
m-sec
21: --0A 1s
22h 1
“n” such t hat typical f ul l chip erase t i me-out = 2
n
m-sec
22: --00 NA
23h 1
“n” such t hat maximum word program t i me-out = 2
n
times typical
23: --01 512µs
24h 1
“n” such t hat maximum buffer write time-out = 2
n
times typical
24: --01 1024µ
s
25h 1
“n” such t hat maximum bloc k erase ti me-out = 2
n
times typical
25: --02 4s
26h 1
“n” such t hat maximum chi p erase time-out = 2
n
times typical
26: --00 NA
VPP [program ming] supply m i ni mum program /erase volt age
bits 0–3 B CD 100 mV
bits 4–7 HEX volts
VPP [program ming] supply m aximum program/erase voltage
bits 0–3 B CD 100 mV
bits 4–7 HEX volts
VCC logic s uppl y mini mum program/erase volt age
bits 0–3 B CD 100 mV
bits 4–7 BCD volts
VCC logic s upply maximum program/erase voltage
bits 0–3 B CD 100 mV
bits 4–7 BCD volts
Intel StrataFlash® Wireless Memory (L18)
April 2005 Intel StrataFlash® Wireless Memory (L18) Datasheet
96 Order Number: 251902, Revision: 009
Offset
Length
Description
Code
27h 1
“n” such t hat device s i ze = 2
n
in number of byt es
27: See table below
76543210
28h 2 ————x64x32x16x828:--01x16
15 14 13 12 11 10 9 8
————————29:--00
2Ah 2
“n” such t hat maxim um number of bytes in write buffer = 2
n
2A: --06 64
2B: --00
2Ch 1 2C:
2Dh 4 Erase Block Region 1 Inf ormation 2D:
bits 0–15 = y, y+1 = number of identi cal-size erase block s 2E:
bits 16–31 = z, region erase block (s) size are z x 256 bytes 2F:
30:
31h 4 Erase Block Region 2 Inf ormation 31:
bits 0–15 = y, y+1 = number of identi cal-size erase block s 32:
bits 16–31 = z, region erase block (s) size are z x 256 bytes 33:
34:
35h 4 Reserved for future eras e bl ock regi on i nformation 35:
36:
37:
38:
See table below
See table below
See table below
See table below
Flash devic e i nterface c ode ass i gnment:
"n" such that n+1 s pecifies the bi t field that represents the flash
device width capabilities as described in the table:
Number of erase block regi ons (x) within device:
1. x = 0 means no eras e bl ock i ng; the devic e erases in bulk
2. x specifi es the number of d evi ce regions with one or
more c ontiguous s ame-si ze erase blocks.
3. Sym metri cally bloc ked part i t i ons have one blocking region
Address 64 Mbit
–B –T –B –T –B –T
27: --17 --17 --18 --18 --19 --19
28: --01 --01 --01 --01 --01 --01
29: --00 --00 --00 --00 --00 --00
2A: --06 --06 --06 --06 --06 --06
2B: --00 --00 --00 --00 --00 --00
2C: --02 --02 --02 --02 --02 --02
2D: --03 --3E --03 --7E --03 --FE
2E: --00 --00 --00 --00 --00 --00
2F: --80 --00 --80 --00 --80 --00
30: --00 --02 --00 --02 --00 --02
31: --3E --03 --7E --03 --FE --03
32: --00 --00 --00 --00 --00 --00
33: --00 --80 --00 --80 --00 --80
34: --02 --00 --02 --00 --02 --00
35: --00 --00 --00 --00 --00 --00
36: --00 --00 --00 --00 --00 --00
37: --00 --00 --00 --00 --00 --00
38: --00 --00 --00 --00 --00 --00
128 Mbit 256 Mbit
Intel StrataFlash® Wireless Memory (L18)
Datasheet Intel StrataFlash® Wireless Memory (L18) April 2005
Order Number: 251902, Revision: 009 97
C.5 Intel-Specific Extended Query Table
Table 25. Primary Vendor-Specific Extended Query
Offset
(1)
Length
Description
Hex
P = 10Ah
(Optional flash features and commands)
Add.
Code
Value
(P+0)h 3 Primary extended query table 10A --50 "P "
(P+1)h Unique A S CII string “PRI“ 10B: --52 "R"
(P+2)h 10C: --49 "I"
(P+3)h 1 Major version number, AS CII 10D: --31 " 1"
(P+4)h 1 Minor version number, AS CI I 10E: --33 " 3"
(P+5)h 4 Optional f eat ure and com mand support (1=yes, 0=no) 10F: --E6
(P+6)h
bits 10–31 are reserved; undef i ned bits are “0. ” If bit 31 i s
110: --03
(P+7)h
“1” then another 31 bit field of Opt ional features follows at
111: --00
(P+8)h
the end of the bi t–30 field.
112: --00
bit 0 Chip eras e supported bit 0 = 0 No
bit 1 Sus pend erase supported bit 1 = 1 Yes
bit 2 Sus pend program supported bit 2 = 1 Yes
bit 3 Legacy l ock/unl ock supported bit 3 = 0 No
bit 4 Queued erase supported bit 4 = 0 No
bit 5 Ins tant indivi dual bl ock locking s upported bit 5 = 1 Yes
bit 6 Prot ection bit s supported bi t 6 = 1 Yes
bit 7 Pagemode read support ed bit 7 = 1 Yes
bit 8 Sync hronous read supported bit 8 = 1 Yes
bit 9 Simult aneous operations supported bit 9 = 1 Yes
(P+9)h 1 113: --01
bit 0 Program support ed af ter erase suspend bit 0 = 1 Yes
(P+A)h 2 Block status register mask 114: --03
(P+B)h
bits 2–15 are Reserved; undefined bits are “0”
115: --00
bit 0 Block Loc k-Bit S tatus regi ster active bit 0 = 1 Yes
bit 1 Bl ock Lock-Down Bit St atus ac t ive bit 1 = 1 Yes
(P+C)h 1 116: --18 1.8V
(P+D)h 1 117: --90 9.0V
Supported functions after suspend: read Array, Status, Query
Other supported operations are:
bits 1–7 reserved; undefi ned bi t s are “0”
VCC logic s uppl y hi ghest performanc e program/erase voltage
bits 0–3 BCD value in 100 mV
bits 4–7 BCD value in volt s
VPP optimum program/erase supply vol t age
bits 0–3 BCD value in 100 mV
bits 4–7 HEX value in volts
Intel StrataFlash® Wireless Memory (L18)
April 2005 Intel StrataFlash® Wireless Memory (L18) Datasheet
98 Order Number: 251902, Revision: 009
Table 26. Protection Register Information
Table 27. Burst Read Information
Offset
(1)
Length
Description
Hex
P = 10Ah
(Optional flash features and commands)
Add.
Code
Value
(P+E)h 1 118: --02 2
(P+F)h 4 Protection Field 1: Protec tion Des cription 119: --80 80h
(P+10)h This fiel d describes user-availa bl e One Ti me Programm abl e 11A: --00 00h
(P+11)h (OTP) Protection register bytes. Some are pre-programm ed 11B: --03 8 byte
(P+12)h 11C: --03 8 byt e
(P+13)h 10 Protecti on Fi el d 2: Protect i on Desc ri pt i on 11D: --89 89h
(P+14)h 11E: --00 00h
(P+15)h 11F: --00 00h
(P+16)h 120: --00 00h
(P+17)h 121: --00 0
(P+18)h
bits 40–47 = “n”
∴
n = factory pgm ' d groups (high byte)
122: --00 0
(P+19)h 123: --00 0
(P+1A)h 124: --10 16
(P+1B)h 125: --00 0
(P+1C)h 126: --04 16
bits 48–55 = “n” \ 2n = fac tory programmable byt es/group
bits 56–63 = “n” ∴ n = user pgm'd groups (l ow byte)
bits 64–71 = “n”
∴
n
= user pgm'd groups (hi gh byte)
bits 72–79 = “n” ∴ 2n = user program mable bytes/group
with device-unique s eri al numb ers. Others are user
programmable. B i ts 0–15 point to the Protect i on regi ster Lock
byte, the sect i on’ s firs t byte. The foll owing bytes are factory
pre-programmed and user-programmable.
bits 0–7 = Lock/bytes Jedec-plane physical l ow address
bits 8–15 = Lock/bytes Jedec-plane physical hi gh address
bits 16–23 = “n” such that 2n = factory pre-programmed bytes
bits 24–31 = “n” such that 2n = user programmable byt es
Bits 0–31 poi nt to the P rotecti on register physic al Lock-word
address in the Jedec-pl ane.
Following bytes are f actory or u ser-programmable.
bits 32–39 = “n” ∴ n = f actory pgm'd groups (low byte)
Number of P rotecti on regi ster fields i n JEDEC I D space.
“00h,” indic ates that 256 protec tion fiel ds are available
Offset
(1)
Length
Description
Hex
P = 10Ah
(Optional flash features and commands)
Add.
Code
Value
(P+1D)h 1 127: --03 8 byte
(P+1E)h 1 128: --04 4
(P+1F)h 1 129: --01 4
(P+20)h 1 Synchronous m ode read capability c onfiguration 2 12A: --02 8
(P+21)h 1 Synchronous m ode read capability c onfiguration 3 12B: --03 16
(P+22)h 1 Synchronous m ode read capability c onfiguration 4 12C: --07 Cont
Page Mode Read capability
bits 0–7 = “n” such that 2n HEX value represents the number of
read-page bytes. S ee offset 28h for devi ce word width to
determi ne page-mode data output width. 00h i ndi cates no
read page buffer.
Number of synchronous mode read configurat i on f i el ds that
follow. 00h indicates no burst capability.
Synchronous mode read capability configuration 1
Bits 3–7 = Reserved
bits 0–2 “n” such that 2n+1 HEX value represent s the
maximum number of continuous synchronous reads when
the device i s confi gured for its maximum word width. A value
of 07h indic at es that the device is c apabl e of conti nuous
linear bursts t hat will output data until the internal burst
counter reac hes the end of t he device’ s burstabl e address
space. Thi s field’ s 3-bit value can be written di rectly to the
Read Configurati on Regi ster bi ts 0–2 if the device is
configured f o r i t s maximum word width. See off set 28h for
word width to det ermine t he burst dat a output width.
Intel StrataFlash® Wireless Memory (L18)
Datasheet Intel StrataFlash® Wireless Memory (L18) April 2005
Order Number: 251902, Revision: 009 99
Table 28. Partition and Erase-block Region Information
Offset
(1)
See table below
P= 10Ah
Description
Address
Bottom
Top
(Optional flash features and commands)
Len
Bot Top
(P+23)h (P+23)h 1 12D: 12D:Number of devi ce hardware-partition regions within the device.
x = 0: a single hardware partition devi ce (no fields follow).
x specifies the num ber of device part i tion regions containing
one or more c ontiguous eras e bl ock regions .
Intel StrataFlash® Wireless Memory (L18)
April 2005 Intel StrataFlash® Wireless Memory (L18) Datasheet
100 Order Number: 251902, Revision: 009
Table 29. Partition Region 1 Information
Offset
(1)
See table below
P = 10Ah
Description
Address
Bottom
Top
(Optional flash features and commands)
Len
Bot Top
(P+24)h (P+24)h Number of identical partitions within the partition region 2 12E: 12E:
(P+25)h (P+25)h 12F: 12F:
(P+26)h (P+26)h 1 130: 130:
(P+27)h (P+27)h 1 131: 131:
(P+28)h (P+28)h 1 132: 132:
(P+29)h (P+29)h 1 133: 133:
(P+2A)h (P+2A)h Partition Region 1 Erase Block Type 1 Inform at ion 4 134: 134:
(P+2B)h (P+2B)h bits 0–15 = y, y+1 = number of identical-size erase blocks 135: 135:
(P+2C)h (P+2C)h bit s 16–31 = z, region erase block(s) size are z x 256 bytes 136: 136:
(P+2D)h (P+2D)h 137: 137:
(P+2E)h (P+2E)h Partition 1 (Erase Block Type 1) 2 138: 138:
(P+2F)h (P+2F)h Minimum block erase cycles x 1000 139: 139:
(P+30)h (P+30)h 1 13A: 13A:
(P+31)h (P+31)h 1 13B: 13B:
(P+32)h Part ition Region 1 Erase Block Type 2 Inform at ion 4 13C:
(P+33)h bits 0–15 = y, y+1 = number of identical-size erase blocks 13D:
(P+34)h bits 16–31 = z, region erase block(s) size are z x 256 bytes 13E:
(P+35)h (bottom param eter device only) 13F:
(P+36)h Part it i on 1 (Erase block T ype 2) 2 140:
(P+37)h Minimum block erase cycles x 1000 141:
(P+38)h 1 142:
(P+39)h 1 143:
Partition 1 (erase block Type 1) bits per cell; internal ECC
bits 0–3 = bits per cell in erase region
bit 4 = reserved for “internal ECC used” (1=yes, 0=no)
bits 5–7 = reserve for future use
Partition 1 (erase block Type 1) page mode and synchronous
mode capabilities def ined i n Table 10.
bit 0 = page-mode host reads permitted (1=yes, 0=no)
bit 1 = synchronous host reads permitted (1=yes, 0=no)
bit 2 = synchronous host writes permitted (1=yes, 0=no)
bits 3–7 = reserved for future use
Partition 1 (Erase block Type 2) bits per cell
bits 0–3 = bits per cell in erase region
bit 4 = reserved for “internal ECC used” (1=yes, 0=no)
bits 5–7 = reserve for future use
Partition 1 (Erase block T ype 2) pagemode and synchronous
mode capabilities def ined i n Table 10
bit 0 = page-mode host reads permitted (1=yes, 0=no)
bit 1 = synchronous host reads permitted (1=yes, 0=no)
bit 2 = synchronous host writes permitted (1=yes, 0=no)
bits 3–7 = reserved for future use
Number of program or erase operations allowed in a partition
bits 0–3 = number of simultaneous Program operations
bits 4–7 = number of simultaneous Erase operations
Simultaneous program or erase operations allowed in other
partitions while a partition in this region is in Program mode
bits 0–3 = number of simultaneous Program operations
bits 4–7 = number of simultaneous Erase operations
Simultaneous program or erase operations allowed in other
partitions while a partition in this region is in Erase m ode
bits 0–3 = number of simultaneous Program operations
bits 4–7 = number of simultaneous Erase operations
Types of erase block regions in this Parti t ion Region.
x = 0 = no erase blocking; the Partition Region erases in bulk
x = number of erase block regions w/ contiguous same-size
erase blocks. Symmetrically blocked partitions have one
blocking region. Partition s ize = (Type 1 blocks)x(Type 1
block sizes) + (Type 2 blocks)x(Type 2 block sizes) +…+
(Type n blocks)x(Type n block si zes)
Intel StrataFlash® Wireless Memory (L18)
Datasheet Intel StrataFlash® Wireless Memory (L18) April 2005
Order Number: 251902, Revision: 009 101
Table 30. Partition Region 2 Information
Offset
(1) See table below
P = 10Ah
Description
Address
Bottom
Top
(Optional flash features and commands)
Len
Bot Top
(P+3A)h (P+32)h Number of i dentical partitions within the part i t i on regi on 2 144: 13C:
(P+3B)h (P+33)h 145: 13D:
(P+3C)h (P+34)h 1 146: 13E:
(P+3D)h (P+35)h 1 147: 13F:
(P+3E)h (P+36)h 1 148: 140:
(P+3F)h (P+37)h 1 149: 141:
(P+40)h (P +38)h Part i tion Region 2 Erase Bloc k Type 1 Information 4 14A: 142:
(P+41)h (P +39)h bits 0–15 = y, y+1 = number of identical-size erase block s 14B: 143:
(P+42)h (P+3A)h bit s 16–31 = z, region eras e bl ock(s ) size are z x 256 bytes 14C: 144:
(P+43)h (P+3B)h 14D: 145:
(P+44)h (P+3C)h P artition 2 (E rase block Type 1) 2 14E: 146:
(P+45)h (P+3D)h Minimum block erase cycl es x 1000 14F: 147:
(P+46)h (P+3E)h 1 150: 148:
(P+47)h (P+3F)h 1 151: 149:
(P+40)h Partition Region 2 Erase Block Type 2 Information 4 14A:
(P+41)h bits 0–15 = y, y+1 = number of ident i cal-size erase block s 14B:
(P+42)h bit s 16–31 = z, region eras e bl ock(s ) size are z x 256 bytes 14C:
(P+43)h 14D:
(P+44)h Partition 2 (Erase block Type 2) 2 14E:
(P+45)h Minimum block erase cyc l es x 1000 14F:
(P+46)h 1 150:
(P+47)h 1 151:
Partit i on 2 (Erase bloc k Type 1) bits per cell
bits 0–3 = bi t s per cell i n erase region
bit 4 = reserved for “internal E CC used” (1=yes, 0=no)
bits 5–7 = reserve for fut ure use
Partit i on 2 (erase block Type 1) pagemode and synchronous
mode capabilities as def ined in Table 10.
bit 0 = page-m ode host reads permit ted (1=yes, 0=no)
bit 1 = sync hronous host reads permi tted (1=yes, 0=no)
bit 2 = sync hronous host writes permi t ted (1=yes, 0=no)
bits 3–7 = reserved for fut ure use
Partit i on 2 (Erase bloc k Type 2) bits per cell
bits 0–3 = bi t s per cell i n erase region
bit 4 = reserved for “internal E CC used” (1=yes, 0=no)
bits 5–7 = reserve for fut ure use
Partit i on 2 (erase block Type 2) pagemode and synchronous
mode capabilities as def ined in Table 10.
bit 0 = page-m ode host reads permit ted (1=yes, 0=no)
bit 1 = sync hronous host reads permi tted (1=yes, 0=no)
bit 2 = sync hronous host writes permi t ted (1=yes, 0=no)
bits 3–7 = reserved for fut ure use
Number of program or erase operat i ons allowed in a partition
bits 0–3 = number of s i mult aneous Program operations
bits 4–7 = number of s i mult aneous Erase operat i ons
Sim ul taneous program or erase operati ons allowed in other
partitions while a partiti on i n this region is in Program mode
bits 0–3 = number of s i mult aneous Program operations
bits 4–7 = number of s i mult aneous Erase operat i ons
Sim ul taneous program or erase operati ons allowed in other
partitions while a partiti on i n this region is in Erase mode
bits 0–3 = number of s i mult aneous Program operations
bits 4–7 = number of s i mult aneous Erase operat i ons
Types of eras e bl ock regions i n this P artition Regi on.
x = 0 = no erase blocking; the Partition Region erases in bulk
x = number of erase block regions w/ c ontiguous s ame-si ze
erase blocks. Symmetrically blocked partitions have one
blocking region. Partition size = (Type 1 blocks)x(Type 1
block sizes) + (Type 2 blocks)x(Type 2 block sizes) +…+
(Type n blocks)x(Type n block sizes)
Intel StrataFlash® Wireless Memory (L18)
April 2005 Intel StrataFlash® Wireless Memory (L18) Datasheet
102 Order Number: 251902, Revision: 009
Table 31. Partition and Erase Block Region Information
Add ress 64 Mbi t
–B –T –B –T –B –T
12D: --02 --02 --02 --02 --02 --02
12E: --01 --07 --01 --0F --01 --0F
12F: --00 --00 --00 --00 --00 --00
130: --11 --11 --11 --11 --11 --11
131: --00 --00 --00 --00 --00 --00
132: --00 --00 --00 --00 --00 --00
133: --02 --01 --02 --01 --02 --01
134: --03 --07 --03 --07 --03 --0F
135: --00 --00 --00 --00 --00 --00
136: --80 --00 --80 --00 --80 --00
137: --00 --02 --00 --02 --00 --02
138: --64 --64 --64 --64 --64 --64
139: --00 --00 --00 --00 --00 --00
13A: --02 --02 --02 --02 --02 --02
13B: --03 --03 --03 --03 --03 --03
13C: --06 --01 --06 --01 --0E --01
13D: --00 --00 --00 --00 --00 --00
13E: --00 --11 --00 --11 --00 --11
13F: --02 --00 --02 --00 --02 --00
140: --64 --00 --64 --00 --64 --00
141: --00 --02 --00 --02 --00 --02
142: --02 --06 --02 --06 --02 --0E
143: --03 --00 --03 --00 --03 --00
144: --07 --00 --0F --00 --0F --00
145: --00 --02 --00 --02 --00 --02
146: --11 --64 --11 --64 --11 --64
147: --00 --00 --00 --00 --00 --00
148: --00 --02 --00 --02 --00 --02
149: --01 --03 --01 --03 --01 --03
14A: --07 --03 --07 --03 --0F --03
14B: --00 --00 --00 --00 --00 --00
14C: --00 --80 --00 --80 --00 --80
14D: --02 --00 --02 --00 --02 --00
14E: --64 --64 --64 --64 --64 --64
14F: --00 --00 --00 --00 --00 --00
150: --02 --02 --02 --02 --02 --02
151: --03 --03 --03 --03 --03 --03
128 Mbit 256 Mbit
Intel StrataFlash® Wireless Memory (L18)
Datasheet Intel StrataFlash® Wireless Memory (L18) April 2005
Order Number: 251902, Revision: 009 103
Appendix D Additional Information
Order/Document
Number Document/Tool
251903 Intel StrataFl ash® Wireless Memory (L30) Datasheet
290701 Intel® Wireless Flash Memory (W18) Datasheet
290702 Intel® Wireless Flash Memory (W30) Datasheet
290737 Intel StrataFl ash® Synchronous Memory (K3/K18) Datasheet
251908 Migration Guide for 1.8 Volt Intel® Wireless Flash Memory (W18/W30) to 1.8 Volt Intel
StrataFlash® Wireless Memory (L18/L30), Application Note 753
251909 Migration Guide for 3 Volt Synchronous Intel S trataF lash® Memory (K3/K18) to 1.8 Volt
Intel S trataFlash® Wireless Memory (L18/L30), Application Note 754
298161 Intel® Flash Memory Chip Scale Package User’s Guide
297833 Intel® Flash Data Integrator (FDI) User’s Guide
298136 Intel® Persistent Storage Manager User Guide
Notes:
1. Please call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International
customers should contact their local Intel or distribution sales office.
2. Visit Intel’s World Wide Web home page at http://www.intel.com for technical documentation and
tools.
3. For th e most current informat ion on Intel StrataFlash® memory, visit our website at http://
developer.intel.com/design/flash/isf.
Intel StrataFlash® Wireless Memory (L18)
April 2005 Intel StrataFlash® Wireless Memory (L18) Datasheet
104 Order Number: 251902, Revision: 009
Appendix E Ordering Information
E.1 Ordering Information for VF BGA Package
Figure 47. Ordering Information for L18 in VF BGA
F 6 4 1 8 T 88E 2G 0 L 5
Product Line Designator
for a ll Inte l® Flas h products
Package Designator
Expanded Temperature
(-2 5 C to +8 5 C)
GE = leaded, 0.75mm V F BGA
PH = lead-free, 0.75mm VF BGA Parameter Location
T = Top Parameter Blocking
B = Bottom Parameter Blocking
Device Density
640 =x16 (64-Mbit)
128 =x16 (128-Mbit)
256 =x16 (256-Mbit)
Product Fam ily
L18 = In te l Stra taflas h® W ireless Memory
VCC = 1.7 V - 2.0 V
VCCQ = 1.35 V - 2.0 V or 1.7 V -2.0 V
Access Speed (ns)
85
Intel StrataFlash® Wireless Memory (L18)
Datasheet Intel StrataFlash® Wireless Memory (L18) April 2005
Order Number: 251902, Revision: 009 105
E.2 Order ing Info rm a ti on for SCSP
Figure 48 and Table 32 show the ordering information f or th e Intel StrataFlash® wireless memory
in QUAD+ ballout produc ts.
Figure 48. Ordering Information for L18 in QUAD+
Table 32. L18 SCSP Package Ordering Information
I/O
Voltage Flash Component RAM Component Package
Part Order Number
(V) Density in Mbit and
Family Density in Mbit and
Type Size
(mm) Ball Type Type
1.8
128 L18 0 8x10x1.2 Leaded QUAD+
SCSP NZ48F3000L0YTQ0
NZ48F3000L0YBQ0
128 L18 0 8x10x1.2 Lead-Free QUAD+
SCSP JZ48F3000L0YTQ0
JZ48F3000L0YBQ0
256 L18 0 8x11x1 .0 Leaded QUAD+
SCSP NZ48F4000L0YTQ0
NZ48F4000L0YBQ0
256 L18 0 8x11x1 .0 Lead-Free QUAD+
SCSP JZ48F4000L0YTQ0
JZ48F4000L0YBQ0
F 4 0 L 0 Y B8Z 4N 0 0 Q
P
roduct Line Designator
4
8F = Flash Memory only
P
ackage Designator
N
Z = Intel® SCSP, leaded
J
Z = Intel® SCSP, lead-free
F
lash Densit y
0
= No d ie
3
= 128-Mbit
4
= 256-Mbit
Flash #1
Flash #2
Flash #3
Flash #4
Flash Family 1
/2
Flash Family 3
/4
0
P
roduct Family
L
= Intel StrataFlash® Wireless Family Memory
0
= No d ie
Device Details
0 = Original version of the
products ( r e fer to the late
st
vers i on of th e da ta s h ee t
for det ails ).
Pinout Indicator
Q = QUAD+ ballout
B = x16D Performance
Parameter Location
B = Bottom Parameter
T = Top Parameter
Voltage
Z = 3.0 V I/O
Y = 1.8 V I/O
Intel StrataFlash® Wireless Memory (L18)
April 2005 Intel StrataFlash® Wireless Memory (L18) Datasheet
106 Order Number: 251902, Revision: 009
