MT28C3224P18FL-85B - Micron

MT28C3224P20_3.p65 – Rev. 3, Pub. 7/02

2 MEG x 16 PAGE FLASH

256K x 16 SRAM COMBO MEMORY

ADVANCE‡

‡PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE

SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S

PRODUCTION DATA SHEET SPECIFICATIONS.

FLASH AND SRAM

COMBO MEMORY

MT28C3224P20

MT28C3224P18

Low Voltage, Extended Temperature

0.18µm Process Technology

FEATURES

• Flexible dual-bank architecture

• Support for true concurrent operations with no

latency:

Read bank b during program bank a and vice versa

Read bank b during erase bank a and vice versa

• Organization: 2,048K x 16 (Flash)

256K x 16 (SRAM)

• Basic configuration:

Flash

Bank a (8Mb Flash for data storage)

– Eight 4K-word parameter blocks

– Fifteen 32K-word blocks

Bank b (24Mb Flash for program storage)

– Forty-eight 32K-word main blocks

SRAM

4Mb SRAM for data storage

– 256K-words

• F_VCC, VCCQ, F_VPP, S_VCC voltages

MT28C3224P20

1.80V (MIN)/2.20V (MAX) F_VCC read voltage

1.80V (MIN)/2.20V (MAX) S_VCC read voltage

1.80V (MIN)/2.20V (MAX) VCCQ

MT28C3224P18

1.70V (MIN)/1.90V (MAX) F_VCC read voltage

1.70V (MIN)/1.90V (MAX) S_VCC read voltage

1.70V (MIN)/1.90V (MAX) VCCQ

MT28C3224P20/P18

1.80V (TYP) F_VPP (in-system PROGRAM/ERASE)

1.0V (MIN) S_VCC (SRAM data retention)

12V ±5% (HV) F_VPP (production programming

compatibility)

• Asynchronous access time

Flash access time: 80ns @ 1.80V F_VCC

SRAM access time: 85ns @ 1.80V S_VCC

• Page Mode read access

Interpage read access: 80ns @ 1.80V F_VCC

Intrapage read access: 30ns @ 1.80V F_VCC

• Low power consumption

• Enhanced suspend options

ERASE-SUSPEND-to-READ within same bank

PROGRAM-SUSPEND-to-READ within same bank

ERASE-SUSPEND-to-PROGRAM within same bank

• Read/Write SRAM during program/erase of Flash

• Dual 64-bit chip protection registers for security

purposes

• PROGRAM/ERASE cycles

100,000 WRITE/ERASE cycles per block

• Cross-compatible command set support

Extended command set

Common flash interface (CFI) compliant

OPTIONS MARKING

• Timing

80ns -80

85ns -85

• Boot Block Configuration

Top T

Bottom B

• Operating Voltage Range

VCC = 1.70V–1.90V 18

VCC = 1.80V–2.20V 20

• Operating Temperature Range

Commercial (0oC to +70oC) None

Extended (-40oC to +85oC) ET

• Package

66-ball FBGA (8 x 8 grid) FL

Part Number Example:

MT28C3224P20FL-80 BET

BALL ASSIGNMENT

66-Ball FBGA (Top View)

1 2 3 4 5 6 7 8 9 10 11 12

Top View

(Ball Down)

A14

DQ11

A15

A10

A19

S_OE#

A20

A16

F_WE#

S_V

F_WP#

S_LB#

A18

F_V

A12

S_WE#

DQ6

S_CE2

DQ10

DQ8

F_V

DQ14

DQ4

S_V

DQ2

DQ0

F_OE#

DQ7

DQ5

F_V

DQ3

DQ1

S_CE1#

A13

DQ15

DQ13

DQ12

DQ9

F_CE#

A11

F_RP#

F_V

S_UB#

A17

2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.

2 MEG x 16 PAGE FLASH

256K x 16 SRAM COMBO MEMORY

ADVANCE

Table 1

Cross Reference for Abbreviated Device Marks

PRODUCT SAMPLE MECHANICAL

PART NUMBER MARKING MARKING SAMPLE MARKING

MT28C3224P20FL-80 BET FW448 FX448 FY448

MT28C3224P20FL-80 TET FW446 FX446 FY446

MT28C3224P18FL-85 BET FW449 FX449 FY449

MT28C3224P18FL-85 TET FW450 FX450 FY450

GENERAL DESCRIPTION

The MT28C3224P20 and MT28C3224P18 combi-

nation Flash and SRAM memory devices provide a com-

pact, low-power solution for systems where PCB real

estate is at a premium. The dual-bank Flash devices

are high-performance, high-density, nonvolatile

memory with a revolutionary architecture that can sig-

nificantly improve system performance.

This new architecture features:

• A two-memory-bank configuration supporting

dual-bank operation;

• A high-performance bus interface providing a fast

page data transfer; and

• A conventional asynchronous bus interface.

The devices also provide soft protection for blocks

by configuring soft protection registers with dedicated

command sequences. For security purposes, dual 64-

bit chip protection registers are provided.

The embedded WORD WRITE and BLOCK ERASE

functions are fully automated by an on-chip write state

machine (WSM). The WSM simplifies these operations

and relieves the system processor of secondary tasks.

An on-chip status register, one for each bank, can be

used to monitor the WSM status to determine the

progress of a PROGRAM/ERASE command.

The erase/program suspend functionality allows

compatibility with existing EEPROM emulation soft-

ware packages.

The devices take advantage of a dedicated power

source for the Flash memory (F_VCC) and a dedicated

power source for the SRAM memory (S_VCC), both at

1.70V–2.20V for optimized power consumption and im-

proved noise immunity. A dedicated I/O power supply

(VCCQ) is provided with an extended range (1.70V–

2.20V), to allow a direct interface to most common logic

controllers and to ensure improved noise immunity.

The separate S_VCC pin for the SRAM provides data

retention capability when required. The data reten-

tion S_VCC is specified as low as 1.0V. The

MT28C3224P20 and MT28C3224P18 devices support

two VPP voltage ranges, an in-circuit voltage of 0.9V–

2.2V and a production compatibility voltage of 12V ±5%.

The 12V ±5% VPP2 is supported for a maximum of 100

cycles and 10 cumulative hours.

The MT28C3224P20 and MT28C3224P18 devices

contain an asynchronous 4Mb SRAM organized as 256K-

words by 16 bits. These devices are fabricated using an

advanced CMOS process and high-speed/ultra-low-

power circuit technology.

The devices are packaged in a 66-ball FBGA pack-

age with 0.80mm pitch.

ARCHITECTURE AND MEMORY

ORGANIZATION

The Flash memory contains two separate memory

banks (bank a and bank b) for simultaneous READ and

WRITE operations. Bank a is 8Mb deep and contains 8

x 4K-word parameter blocks and fifteen 32K-word

blocks. Bank b is 24Mb deep, is equally sectored, and

contains forty-eight 32K-word blocks.

Figures 2 and 3 show the top and bottom memory

organizations.

DEVICE MARKING

Due to the size of the package, Micron’s standard

part number is not printed on the top of each device.

Instead, an abbreviated device mark comprised of a

five-digit alphanumeric code is used. The abbreviated

device marks are cross referenced to Micron part num-

bers in Table 1.

2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.

2 MEG x 16 PAGE FLASH

256K x 16 SRAM COMBO MEMORY

ADVANCE

PART NUMBERING INFORMATION

Micron’s low-power devices are available with sev-

eral different combinations of features (see Figure 1).

Table 2

Valid Part Number Combinations

BOOT BLOCK OPERATING

ACCESS STARTING TEMPERATURE

PART NUMBER TIME (ns) ADDRESS RANGE

MT28C3224P20FL-80 BET 80 Bottom -40oC to +85oC

MT28C3224P20FL-80 TET 80 Top -40oC to +85oC

MT28C3224P18FL-85 BET 85 Bottom -40oC to +85oC

MT28C3224P18FL-85 TET 85 Top -40oC to +85oC

Figure 1

Part Number Chart

Valid combinations of features and their correspond-

ing part numbers are listed in Table 2.

MT 28C 322 4 P 20 FL-80 T ET

Micron Technology

Flash Family

28C = Dual-Supply Flash/SRAM Combo

Density/Organization/Banks

322 = 32Mb (2,048K x 16)

bank a = 1/4; bank b = 3/4

SRAM Density

4 = 4Mb SRAM (256K x 16)

Access Time

-80 = 80ns

-85 = 85ns

Read Mode Operation

P = Asynchronous/Page Read

Package Code

FL = 66-ball FBGA (8 x 8 grid)

Operating Temperature Range

None = Commercial (0ºC to +70ºC)

ET = Extended (-40ºC to +85ºC)

Boot Block Starting Address

B = Bottom boot

T = Top boot

Operating Voltage Range

20 = 1.80V–2.20V

18 = 1.70V–1.90V

2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.

2 MEG x 16 PAGE FLASH

256K x 16 SRAM COMBO MEMORY

ADVANCE

BLOCK DIAGRAM

F_V

S_OE#

S_CE2

S_CE1#

S_WE#

DQ0

–

DQ15

A18

–

A20

–

A17

F_RP#

F_CE#

F_OE#

F_WE#

F_V

F_WP#

FLASH

SRAM

S_UB#

S_LB#

2,048K x 16

256K x 16

Bank a

Bank b

S_V

FLASH FUNCTIONAL BLOCK DIAGRAM

Address

Input

Buffer

X DEC

Y/Z DEC

Data Input

Buffer

Output

Multiplexer

Address

CNT/WSM

Output

Buffer

Status

Reg.

WSM

Program/

Erase

Pump Voltage

Generators

Address Latch

DQ0-DQ15

DQ0–DQ15

CSM

F_RST#

F_CE#

X DEC

Y/Z DEC

F_WE#

F_OE#

I/O Logic

A0–A20

Address

Multiplexer

Bank 2 Blocks

Y/Z Gating/Sensing

Data

Bank 1 Blocks

Y/Z Gating/Sensing

ID Reg.

RCR

Block Lock

Device ID

Manufacturer’s ID

OTP

Query

PR Lock

Query/OTP

PR Lock

2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.

2 MEG x 16 PAGE FLASH

256K x 16 SRAM COMBO MEMORY

ADVANCE

BALL DESCRIPTIONS

66-BALL FBGA

NUMBERS SYMBOL TYPE DESCRIPTION

H6, G9, G8, G7, A0–A20 Input Address Inputs: Inputs for the addresses during READ and WRITE

H5, H4, G6, G5, operations. Addresses are internally latched during READ and WRITE

B4, B6, B5, A4, cycles. Flash: A0–A20; SRAM: A0–A17.

A8, A7, A6, A5,

B3, G4, G3, E5,

H7 F_CE# Input Flash Chip Enable: Activates the device when LOW. When CE# is HIGH,

the device is disabled and goes into standby power mode.

H9 F_OE# Input Flash Output Enable: Enables Flash output buffers when LOW. When

F_OE# is HIGH, the output buffers are disabled.

C3 F_WE# Input Flash Write Enable: Determines if a given cycle is a Flash WRITE cycle.

F_WE# is active LOW.

D4 F_RP# Input Reset. When F_RP# is a logic LOW, the device is in reset, which drives

the outputs to High-Z and resets the WSM. When F_RP# is a logic HIGH,

the device is in standard operation. When F_RP# transitions from logic

LOW to logic HIGH, the device resets all blocks to locked and defaults to

the read array mode.

E3 F_WP# Input Flash Write Protect. Controls the lock down function of the flexible

locking feature.

G10 S_CE1# Input SRAM Chip Enable1: Activates the SRAM when it is LOW. HIGH level

deselects the SRAM and reduces the power consumption to standby

levels.

D8 S_CE2 Input SRAM Chip Enable2: Activates the SRAM when it is HIGH. LOW level

deselects the SRAM and reduces the power consumption to standby

levels.

F5 S_OE# Input SRAM Output Enable: Enables SRAM output buffers when LOW. When

S_OE# is HIGH, the output buffers are disabled.

B8 S_WE# Input SRAM Write Enable: Determines if a given cycle is an SRAM WRITE cycle.

S_WE# is active LOW.

F3 S_LB# Input SRAM Lower Byte: When LOW, it selects the SRAM address lower byte

(DQ0–DQ7).

F4 S_UB# Input SRAM Upper Byte: When LOW, it selects the SRAM address upper byte

(DQ8–DQ15).

F9, F10, E9, DQ0–DQ15 Input/ Data Inputs/Outputs: Input array data on the second CE# and WE#

E10, C9, C10, Output cycle during PROGRAM command. Input commands to the command

C8, B10, F8, user interface when CE# and WE# are active. Output data when CE#

F7, E8, E6, D7, and OE# are active.

C7, B9, B7

(continued on next page)

2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.

2 MEG x 16 PAGE FLASH

256K x 16 SRAM COMBO MEMORY

ADVANCE

BALL DESCRIPTIONS (continued)

66-BALL FBGA

NUMBERS SYMBOL TYPE DESCRIPTION

E4 F_VPP Input/ Flash Program/Erase Power Supply: [0.9V–2.2V or 11.4V–12.6V].

Supply Operates as input at logic levels to control complete device protection.

Provides backward compatibility for factory programming when driven

to 11.4V–12.6V. A lower F_VPP voltage range (0.0V–2.2V) is available.

Contact factory for more information.

D10, H3 F_VCC Supply Flash Power Supply: [1.70V–1.90V or 1.80V–2.20V]. Supplies power for

device operation.

A9, H8 F_VSS Supply Flash Specific Ground: Do not float any ground pin.

D9 S_VCC Supply SRAM Power Supply: [1.70V–1.90V or 1.80V–2.20V]. Supplies power for

device operation.

D3 S_VSS Supply SRAM Specific Ground: Do not float any ground pin.

A10 VCCQ Supply I/O Power Supply: [1.70–1.90V or 1.80V–2.20V].

A1, A2, A11, NC – No Connect: Lead is not internally connected; it may be driven or

A12, C4, H1, floated.

H2, H10, H11,

H12

2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.

2 MEG x 16 PAGE FLASH

256K x 16 SRAM COMBO MEMORY

ADVANCE

NOTE: 1. Two devices may not drive the memory bus at the same time.

2. Allowable Flash read modes include read array, read query, read configuration, and read status.

3. Outputs are dependent on a separate device controlling bus outputs.

4. Modes of the Flash and SRAM can be interleaved so that while one is disabled, the other controls outputs.

5. SRAM is enabled and/or disabled with the logical function: S_CE1# or S_CE2.

6. Simultaneous operations can exist, as long as the operations are interleaved such that only one device attempts to

control the bus outputs at a time.

7. Data output on lower byte only; upper byte High-Z.

8. Data output on upper byte only; lower byte High-Z.

9. Data input on lower byte only.

10. Data input on upper byte only.

TRUTH TABLE – FLASH

FLASH SIGNALS SRAM SIGNALS MEMORY OUPUT

MODES

F_RP# F_CE# F_OE# F_WE# S_CE1# S_CE2 S_OE# S_WE# S_UB# S_LB#

MEMORY DQ0–DQ15 NOTES

BUS CONTROL

Read H L L H SRAM must be High-Z Flash DOUT 1, 2, 3

Write H L H L Flash DIN 1

Standby H H X X Other High-Z 4

Output Disable H L H H SRAM any mode allowable Other High-Z 4, 5

Reset L X X X Other High-Z 4, 6

TRUTH TABLE – SRAM

FLASH SIGNALS SRAM SIGNALS MEMORY OUPUT

MODES

F_RP# F_CE# F_OE# F_WE# S_CE1# S_CE2 S_OE# S_WE# S_UB# S_LB#

MEMORY DQ0–DQ15 NOTES

BUS CONTROL

Read

DQ0–DQ15 L H L H L L SRAM DOUT 1, 3

DQ0–DQ7 L H L H H L SRAM DOUT LB 7

DQ8–DQ15 Flash must be High-Z L H L H L H SRAM DOUT UB 8

Write

DQ0–DQ15 L H H L L L SRAM DIN 1, 3

DQ0–DQ7 L H H L H L SRAM DIN LB 9

DQ8–DQ15 L H H L L H SRAM DIN UB 10

Standby H X X X X X Other High-Z 4

Flash any mode allowable X L X X X X Other High-Z 4

Output Disable L H X X X X Other High-Z 4

FLASH

2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.

2 MEG x 16 PAGE FLASH

256K x 16 SRAM COMBO MEMORY

ADVANCE

Figure 2

Bottom Boot Block Device

Bank b = 24Mb

Block Block Size Address Range

(K-bytes/K-words) (x16)

70 64/32 1F8000h-1FFFFFh

69 64/32 1F0000h-1F7FFFh

68 64/32 1E8000h-1EFFFFh

67 64/32 1E0000h-1E7FFFh

66 64/32 1D8000h-1DFFFFh

65 64/32 1D0000h-1D7FFFh

64 64/32 1C8000h-1CFFFFh

63 64/32 1C0000h-1C7FFFh

62 64/32 1B8000h-1BFFFFh

61 64/32 1B0000h-1B7FFFh

60 64/32 1A8000h-1AFFFFh

59 64/32 1A0000h-1A7FFFh

58 64/32 198000h-19FFFFh

57 64/32 190000h-197FFFh

56 64/32 188000h-18FFFFh

55 64/32 180000h-187FFFh

54 64/32 178000h-17FFFFh

53 64/32 170000h-177FFFh

52 64/32 168000h-16FFFFh

51 64/32 160000h-167FFFh

50 64/32 158000h-15FFFFh

49 64/32 150000h-157FFFh

48 64/32 148000h-14FFFFh

47 64/32 140000h-147FFFh

46 64/32 138000h-13FFFFh

45 64/32 130000h-137FFFh

44 64/32 128000h-12FFFFh

43 64/32 120000h-127FFFh

42 64/32 118000h-11FFFFh

41 64/32 110000h-117FFFh

40 64/32 108000h-10FFFFh

39 64/32 100000h-107FFFh

38 64/32 0F8000h-0FFFFFh

37 64/32 0F0000h-0F7FFFh

36 64/32 0E8000h-0EFFFFh

35 64/32 0E0000h-0E7FFFh

34 64/32 0D8000h-0DFFFFh

33 64/32 0D0000h-0D7FFFh

32 64/32 0C8000h-0CFFFFh

31 64/32 0C0000h-0C7FFFh

30 64/32 0B8000h-0BFFFFh

29 64/32 0B0000h-0B7FFFh

28 64/32 0A8000h-0AFFFFh

27 64/32 0A0000h-0A7FFFh

26 64/32 098000h-097FFFh

25 64/32 090000h-097FFFh

24 64/32 088000h-087FFFh

23 64/32 080000h-087FFFh

Bank a = 8Mb

Block Block Size Address Range

(K-bytes/K-words) (x16)

22 64/32 078000h-07FFFFh

21 64/32 070000h-077FFFh

20 64/32 068000h-067FFFh

19 64/32 060000h-067FFFh

18 64/32 058000h-05FFFFh

17 64/32 050000h-057FFFh

16 64/32 048000h-04FFFFh

15 64/32 040000h-047FFFh

14 64/32 038000h-03FFFFh

13 64/32 030000h-037FFFh

12 64/32 028000h-02FFFFh

11 64/32 020000h-027FFFh

10 64/32 018000h-01FFFFh

9 64/32 010000h-017FFFh

8 64/32 008000h-00FFFFh

7 8/4 007000h-007FFFh

6 8/4 006000h-006FFFh

5 8/4 005000h-005FFFh

4 8/4 004000h-004FFFh

3 8/4 003000h-003FFFh

2 8/4 002000h-002FFFh

1 8/4 001000h-001FFFh

0 8/4 000000h-000FFFh

FLASH

2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.

2 MEG x 16 PAGE FLASH

256K x 16 SRAM COMBO MEMORY

ADVANCE

Figure 3

Top Boot Block Device

Bank b = 24Mb

Block Block Size Address Range

(K-bytes/K-words) (x16)

47 64/32 178000h-17FFFFh

46 64/32 170000h-177FFFh

45 64/32 168000h-16FFFFh

44 64/32 160000h-167FFFh

43 64/32 158000h-15FFFFh

42 64/32 150000h-157FFFh

41 64/32 148000h-14FFFFh

40 64/32 140000h-147FFFh

39 64/32 138000h-13FFFFh

38 64/32 130000h-137FFFh

37 64/32 128000h-12FFFFh

36 64/32 120000h-127FFFh

35 64/32 118000h-11FFFFh

34 64/32 110000h-117FFFh

33 64/32 108000h-10FFFFh

32 64/32 100000h-107FFFh

31 64/32 0F8000h-0FFFFFh

30 64/32 0F0000h-0F7FFFh

29 64/32 0E8000h-0EFFFFh

28 64/32 0E0000h-0E7FFFh

27 64/32 0D8000h-0DFFFFh

26 64/32 0D0000h-0D7FFFh

25 64/32 0C8000h-0CFFFFh

24 64/32 0C0000h-0C7FFFh

23 64/32 0B8000h-0BFFFFh

22 64/32 0B0000h-0B7FFFh

21 64/32 0A8000h-0AFFFFh

20 64/32 0A0000h-0A7FFFh

19 64/32 098000h-09FFFFh

18 64/32 090000h-097FFFh

17 64/32 088000h-08FFFFh

16 64/32 080000h-087FFFh

15 64/32 078000h-07FFFFh

14 64/32 070000h-077FFFh

13 64/32 068000h-06FFFFh

12 64/32 060000h-067FFFh

11 64/32 058000h-05FFFFh

10 64/32 050000h-057FFFh

9 64/32 048000h-04FFFFh

8 64/32 040000h-047FFFh

7 64/32 038000h-03FFFFh

6 64/32 030000h-037FFFh

5 64/32 028000h-02FFFFh

4 64/32 020000h-027FFFh

3 64/32 018000h-01FFFFh

2 64/32 010000h-017FFFh

1 64/32 008000h-00FFFFh

0 64/32 000000h-007FFFh

Bank a = 8Mb

Block Block Size Address Range

(K-bytes/K-words) (x16)

70 8/4 1FF000h-1FFFFFh

69 8/4 1FE000h-1FEFFFh

68 8/4 1FD000h-1FDFFFh

67 8/4 1FC000h-1FCFFFh

66 8/4 1FB000h-1FBFFFh

65 8/4 1FA000h-1FAFFFh

64 8/4 1F9000h-1F9FFFh

63 8/4 1F8000h-1F8FFFh

62 64/32 1F0000h-1F7FFFh

61 64/32 1E8000h-1EFFFFh

60 64/32 1E0000h-1E7FFFh

59 64/32 1D8000h-1DFFFFh

58 64/32 1D0000h-1D7FFFh

57 64/32 1C8000h-1CFFFFh

56 64/32 1C0000h-1C7FFFh

55 64/32 1B8000h-1BFFFFh

54 64/32 1B0000h-1B7FFFh

53 64/32 1A8000h-1AFFFFh

52 64/32 1A0000h-1A7FFFh

51 64/32 198000h-19FFFFh

50 64/32 190000h-197FFFh

49 64/32 188000h-18FFFFh

48 64/32 180000h-187FFFh

FLASH

2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.

2 MEG x 16 PAGE FLASH

256K x 16 SRAM COMBO MEMORY

ADVANCE

FLASH MEMORY OPERATING MODES

COMMAND STATE MACHINE

Commands are issued to the command state ma-

chine (CSM) using standard microprocessor write tim-

ings. The CSM acts as an interface between external

microprocessors and the internal write state machine

(WSM). The available commands are listed in Table 3,

their definitions are given in Table 4 and their descrip-

tions in Table 5. Program and erase algorithms are

automated by the on-chip WSM. For more specific in-

formation about the CSM transition states, see Micron

technical note TN-28-33, “Command State Machine

Description and Command Definition.”

Once a valid PROGRAM/ERASE command is en-

tered, the WSM executes the appropriate algorithm,

which generates the necessary timing signals to con-

trol the device internally. A command is valid only if the

exact sequence of WRITEs is completed. After the WSM

completes its task, the write state machine status

(WSMS) bit (SR7) (see Table 7) is set to a logic HIGH

level (VIH), allowing the CSM to respond to the full com-

mand set again.

OPERATIONS

Device operations are selected by entering a stan-

dard JEDEC 8-bit command code with conventional

microprocessor timings into an on-chip CSM through

I/Os DQ0–DQ7. The number of bus cycles required to

activate a command is typically one or two. The first

operation is always a WRITE. Control signals F_CE#

and F_WE# must be at a logic LOW level (VIL), and F_OE#

and F_RP# must be at logic HIGH (VIH). The second

operation, when needed, can be a WRITE or a READ

depending upon the command. During a READ opera-

tion, control signals F_CE# and F_OE# must be at a

logic LOW level (VIL), and F_WE# and F_RP# must be at

logic HIGH (VIH).

Table 6 illustrates the bus operations for all the

modes: write, read, reset, standby, and output disable.

When the device is powered up, internal reset cir-

cuitry initializes the chip to a read array mode of opera-

tion. Changing the mode of operation requires that a

command code be entered into the CSM. For each one

of the two Flash memory partitions, an on-chip status

toring of the progress of various operations that can

take place on a memory bank. One of the two status

registers is interrogated by entering a READ STATUS

ing an address within the memory partition boundary,

and reading the register data on I/O pins DQ0–DQ7

(cycle 2). Status register bits SR0-SR7 correspond to

DQ0–DQ7 (see Table 7).

COMMAND DEFINITION

Once a specific command code has been entered,

the WSM executes an internal algorithm, generating

the necessary timing signals to program, erase, and

verify data. See Table 4 for the CSM command defini-

tions and data for each of the bus cycles.

STATUS REGISTER

The status register allows the user to determine

whether the state of a PROGRAM/ERASE operation is

pending or complete. The status register is monitored

by toggling F_OE# and F_CE# and reading the result-

ing status code on I/Os DQ0–DQ7. The high-order I/Os

(DQ8–DQ15) are set to 00h internally, so only the low-

Table 3

Command State Machine Codes For Device Mode Selection

COMMAND DQ0–DQ7 CODE ON DEVICE MODE

40h/10h Program setup/alternate program setup

20h Block erase setup

50h Clear status register

60h Protection configuration setup

70h Read status register

90h Read protection configuration register

98h Read query

B0h Program/erase suspend

C0h Protection register program/lock

D0h Program/erase resume – erase confirm

FFh Read array

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ADVANCE

order I/Os (DQ0–DQ7) need to be interpreted. Address

lines select the status register pertinent to the selected

memory partition.

edge of F_OE# or F_CE#, whichever occurs last. Latch-

ing the data prevents errors from occurring if the regis-

ter input changes during a status register read.

The status register provides the internal state of the

WSM to the external microprocessor. During periods

when the WSM is active, the status register can be polled

to determine the WSM status. Table 7 defines the sta-

tus register bits.

After monitoring the status register during a

PROGRAM/ERASE operation, the data appearing on

DQ0–DQ7 remains as status register data until a new

command is issued to the CSM. To return the device to

other modes of operation, a new command must be

issued to the CSM.

COMMAND STATE MACHINE OPERATIONS

The CSM decodes instructions for the commands

listed in Table 3. The 8-bit command code is input to

the device on DQ0–DQ7 (see Table 4 for command

definitions). During a PROGRAM or ERASE cycle, the

CSM informs the WSM that a PROGRAM or ERASE cycle

has been requested.

During a PROGRAM cycle, the WSM controls the

program sequences and the CSM responds to a PRO-

GRAM SUSPEND command only.

During an ERASE cycle, the CSM responds to an

ERASE SUSPEND command only. When the WSM has

completed its task, the WSMS bit (SR7) is set to a logic

HIGH level and the CSM responds to the full command

set. The CSM stays in the current command state until

the microprocessor issues another command.

The WSM successfully initiates an ERASE or PRO-

GRAM operation only when VPP is within its correct volt-

age range.

Table 4

Command Definitions

FIRST BUS CYCLE SECOND BUS CYCLE

COMMAND OPERATION ADDRESS1DATA OPERATION ADDRESS1DATA

READ ARRAY WRITE WA FFh

READ PROTECTION CONFIGURATION REGISTER WRITE IA 90h READ IA ID

READ STATUS REGISTER WRITE BA 70h READ BA SRD

CLEAR STATUS REGISTER WRITE BA 50h

READ QUERY WRITE QA 98h READ QA QD

BLOCK ERASE SETUP WRITE BA 20h WRITE BA D0h

PROGRAM SETUP/ALTERNATE PROGRAM SETUP WRITE WA 40h/10h WRITE WA WD

PROGRAM/ERASE SUSPEND WRITE BA B0h

PROGRAM/ERASE RESUME – ERASE CONFIRM WRITE BA D0h

LOCK BLOCK WRITE BA 60h WRITE BA 01h

UNLOCK BLOCK WRITE BA 60h WRITE BA D0h

LOCK DOWN BLOCK WRITE BA 60h WRITE BA 2Fh

PROTECTION REGISTER PROGRAM WRITE PA C0h WRITE PA PD

PROTECTION REGISTER LOCK WRITE LPA C0h WRITE LPA FFFDh

NOTE: 1. BA: Address within the block

IA: Identification code address

ID: Identification code data

LPA: Lock protection register address

PA: Protection register address

PD: Data to be written at location PA

QA: Query code address

QD: Query code data

SRD: Data read from the status register

WA: Word address of memory location to be written, or read

WD: Data to be written at the location WA

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ADVANCE

Table 5

Command Descriptions

CODE DEVICE MODE BUS CYCLE DESCRIPTION

10h Alt. Program Setup First Operates the same as a PROGRAM SETUP command.

20h Erase Setup First Prepares the CSM for an ERASE CONFIRM command. If the next

command is not an ERASE CONFIRM command, the command will

be ignored, and the device will go to read status mode and wait for

another command.

40h Program Setup First A two-cycle command: The first cycle prepares for a PROGRAM

operation, the second cycle latches addresses and data and initiates

the WSM to execute the program algorithm. The Flash outputs status

occurs first.

50h Clear Status First The WSM can set the program status (SR4), and erase status (SR5) bits

this command clears those bits to “0.”

60h Protection First Prepares the CSM for changes to the block locking status. If the next

Configuration command is not BLOCK UNLOCK, BLOCK LOCK or BLOCK LOCK

Setup DOWN, the command will be ignored, and the device will go to read

status mode.

70h Read Status First Places the device into read status register mode. Reading the device

The device automatically enters this mode for the addressed bank

after a PROGRAM or ERASE operation has been initiated.

90h Read Protection First Puts the device into the read protection configuration mode so that

Configuration reading the device outputs the manufacturer/device codes or block

lock status.

98h Read Query First Puts the device into the read query mode so that reading the device

outputs common Flash interface information.

B0h Program Suspend First Suspends the currently executing PROGRAM/ERASE operation. The

status register indicates when the operation has been successfully

Erase Suspend First suspended by setting either the program suspend (SR2) or erase

suspend (SR6) and the WSMS bit (SR7) to a “1” (ready). The WSM

continues to idle in the suspend state, regardless of the state of all

input control pins except F_RP#, which immediately shuts down the

WSM and the remainder of the chip if F_RP# is driven to VIL.

C0h Program Device First Writes a specific code into the device protection register.

Protection Register

Lock Device First Locks the device protection register; data can no longer be changed.

Protection Register

(continued on the next page)

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ADVANCE

Table 5

Command Descriptions (continued)

CODE DEVICE MODE BUS CYCLE DESCRIPTION

D0h Erase Confirm Second If the previous command was an ERASE SETUP command, then the

CSM closes the address and data latches, and it begins erasing the

block indicated on the address pins. During programming/erase, the

device responds only to the READ STATUS REGISTER, PROGRAM

SUSPEND, or ERASE SUSPEND commands and outputs status register

data on the falling edge of F_OE# or F_CE#, whichever occurs last.

Program/Erase First If a PROGRAM or ERASE operation was previously suspended, this

Resume command resumes the operation.

FFh Read Array First During the array mode, array data is output on the data bus.

01h Lock Block Second If the previous command was PROTECTION CONFIGURATION SETUP,

the CSM latches the address and locks the block indicated on the

address bus.

2Fh Lock Down Second If the previous command was PROTECTION CONFIGURATION SETUP,

the CSM latches the address and locks down the block indicated on

the address bus.

D0h Unlock Block Second If the previous command was PROTECTION CONFIGURATION SETUP,

the CSM latches the address and unlocks the block indicated on the

address bus. If the block had been previously set to lock down, this

operation has no effect.

00h Invalid/Reserved Unassigned command that should not be used.

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CLEAR STATUS REGISTER

The internal circuitry can set, but not clear, the block

lock status bit (SR1), the VPP status bit (SR3), the pro-

gram status bit (SR4), and the erase status bit (SR5) of

the status register. The CLEAR STATUS REGISTER com-

mand (50h) allows the external microprocessor to clear

these status bits and synchronize to the internal op-

erations. When the status bits are cleared, the device

returns to the read array mode.

READ OPERATIONS

The following READ operations are available: READ

ARRAY, READ PROTECTION CONFIGURATION REG-

ISTER, READ QUERY and READ STATUS REGISTER.

READ ARRAY

The array is read by entering the command code

FFh on DQ0–DQ7. Control signals F_CE# and F_OE#

must be at a logic LOW level (VIL), and F_WE# and F_RP#

must be at a logic HIGH level (VIH) to read data from the

array. Data is available on DQ0–DQ15. Any valid ad-

dress within any of the blocks selects that address and

allows data to be read from that address. Upon initial

power-up or device reset, the device defaults to the

read array mode.

READ CHIP PROTECTION IDENTIFICATION DATA

The chip identification mode outputs three types

of information: the manufacturer/device identifier, the

block locking status, and the protection register. Two

bus cycles are required for this operation: the chip iden-

tification data is read by entering the command code

90h on DQ0–DQ7 to the bank containing address 00h

and the identification code address on the address

lines. Control signals F_CE# and F_OE# must be at a

logic LOW level (VIL), and F_WE# and F_RP# must be at

a logic HIGH level (VIH) to read data from the protection

configuration register. Data is available on DQ0–DQ15.

After data is read from the protection configuration

sued to the bank containing address 00h prior to issu-

ing other commands. See Table 9 for further details.

READ QUERY

The read query mode outputs common flash inter-

face (CFI) data when the device is read (see Table 11).

Two bus cycles are required for this operation. It is

possible to access the query by writing the read query

command code 98h on DQ0–DQ7 to the bank contain-

ing address 0h. Control signals F_CE# and F_OE# must

be at a logic LOW level (VIL), and F_WE# and F_RP#

must be at a logic HIGH level (VIH) to read data from the

query. The CFI data structure contains information

such as block size, density, command set, and electri-

cal specifications. To return to read array mode, write

the read array command code FFh on DQ0–DQ7.

READ STATUS REGISTER

The status register is read by entering the command

code 70h on DQ0–DQ7. Two bus cycles are required for

this operation: one to enter the command code and a

second to read the status register. In a READ cycle, the

address is latched and register data is updated on the

falling edge of F_OE# or F_CE#, whichever occurs last.

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ADVANCE

plished only by blocks; data at single address locations

within the array cannot be erased individually. The

block to be erased is selected by using any valid ad-

dress within that block. Block erasure is initiated by a

command sequence to the CSM: BLOCK ERASE setup

(20h) followed by BLOCK ERASE CONFIRM (D0h) (see

Table 4). A two-command erase sequence protects

against accidental erasure of memory contents.

When the BLOCK ERASE CONFIRM command is

complete, the WSM automatically executes a sequence

of events to complete the block erasure. During this

sequence, the block is programmed with logic 0s, data

is verified, all bits in the block are erased, and finally

verification is performed to ensure that all bits are cor-

rectly erased. Monitoring of the ERASE operation is

possible through the status register (see the Status

During the execution of an ERASE operation, the

ERASE SUSPEND command (B0h) can be entered to

direct the WSM to suspend the ERASE operation. Once

the WSM has reached the suspend state, it allows the

CSM to respond only to the READ ARRAY, READ STA-

TUS REGISTER, READ QUERY, READ CHIP PROTEC-

TION CONFIGURATION, PROGRAM SETUP, PRO-

GRAM RESUME, ERASE RESUME and LOCK SETUP

(see the Block Locking section). During the ERASE SUS-

PEND operation, array data must be read from a block

other than the one being erased. To resume the ERASE

operation, an ERASE RESUME command (D0h) must

be issued to cause the CSM to clear the suspend state

previously set (see Figure 7). It is also possible that an

ERASE in any bank can be suspended and a WRITE to

another block in the same bank can be initiated. After

the completion of a WRITE, an ERASE can be resumed

by writing an ERASE RESUME command.

PROGRAMMING OPERATIONS

There are two CSM commands for programming:

PROGRAM SETUP and ALTERNATE PROGRAM SETUP

(see Table 3).

After the desired command code is entered (10h or

40h command code on DQ0–DQ7), the WSM takes over

and correctly sequences the device to complete the

PROGRAM operation. The WRITE operation may be

monitored through the status register (see the Status

sponds to a PROGRAM SUSPEND command until the

PROGRAM operation has been completed, after which

time all commands to the CSM become valid again.

The PROGRAM operation can be suspended by issuing

a PROGRAM SUSPEND command (B0h). Once the WSM

reaches the suspend state, it allows the CSM to re-

spond only to READ ARRAY, READ STATUS REGISTER,

READ PROTECTION CONFIGURATION, READ QUERY,

PROGRAM SETUP, or PROGRAM RESUME. During the

PROGRAM SUSPEND operation, array data should be

read from an address other than the one being pro-

grammed. To resume the PROGRAM operation, a PRO-

GRAM RESUME command (D0h) must be issued to

cause the CSM to clear the suspend state previously

set (see Figure 4 for programming operation and Figure

5 for program suspend and program resume).

Taking F_RP# to VIL during programming aborts the

PROGRAM operation.

ERASE OPERATIONS

An ERASE operation must be used to initialize all

bits in an array block to “1s.” After BLOCK ERASE con-

firm is issued, the CSM responds only to an ERASE

SUSPEND command until the WSM completes its task.

Block erasure inside the memory array sets all bits

within the address block to logic 1s. Erase is accom-

Table 6

Bus Operations

MODE F_RP# F_CE# F_OE# F_WE# ADDRESS DQ0–DQ15

Read (array, status registers, VIH VIL VIL VIH XDOUT

device identification register, or

query)

Standby VIH VIH X X X High-Z

Output Disable VIH VIH X X X High-Z

Reset VIL X X X X High-Z

Write VIH VIL VIH VIL XDIN

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STATUS

BIT # STATUS REGISTER BIT DESCRIPTION

SR7 WRITE

STATE

MACHINE

STATUS

(WSMS) Check write state machine bit first to determine word

1 = Ready program or block erase completion, before checking

0 = Busy program or erase status bits.

SR6 ERASE SUSPEND STATUS (ESS) When ERASE SUSPEND is issued, WSM halts execution and

1 = BLOCK ERASE Suspended sets both WSMS and ESS bits to “1.” ESS bit remains set to

0 = BLOCK ERASE in “1” until an ERASE RESUME command is issued.

Progress/Completed

SR5 ERASE STATUS (ES) When this bit is set to “1,” WSM has applied the maximum

1 = Error in Block Erasure number of erase pulses to the block and is still unable to

0 = Successful BLOCK ERASE verify successful block erasure.

SR4 PROGRAM STATUS (PS) When this bit is set to “1,” WSM has attempted but failed to

1 = Error in PROGRAM program a word.

0 = Successful PROGRAM

SR3 VPP STATUS (VPPS) The VPP status bit does not provide continuous indication

1 = VPP Low Detect, Operation Abort of the VPP level. The WSM interrogates the VPP level only

0 = VPP = OK after the program or erase command sequences have been

entered and informs the system if VPP < 0.9V. The VPP level is

also checked before the PROGRAM/ERASE operation is

verified by the WSM. A factory option allows PROGRAM or

ERASE at 0V, in which case SR3 is held at “0.”

SR2 PROGRAM SUSPEND STATUS (PSS) When PROGRAM SUSPEND is issued, WSM halts execution

1 = PROGRAM Suspended and sets both WSM and PSS bits to “1.” PSS bit remains set to

0 = PROGRAM in Progress/Completed “1” until a PROGRAM RESUME command is issued.

SR1 BLOCK LOCK STATUS (BLS) If a PROGRAM or ERASE operation is attempted to one of

1 = PROGRAM/ERASE Attempted on a the locked blocks, this is set by the WSM. The operation

Locked Block; Operation Aborted specified is aborted, and the device is returned to read status

0 = No Operation to Locked Blocks mode.

SR0 RESERVED FOR FUTURE This bit is reserved for future.

ENHANCEMENT

Table 7

Status Register Bit Definition

WSMS ESS ES PS VPPS PSS BLS R

7654 3210

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ADVANCE

Figure 4

Automated Word Programming

Flowchart

NOTE: 1. Full status register check can be done after each word or after a sequence of words.

2. SR3 must be cleared before attempting additional PROGRAM/ERASE operations.

3. SR4 is cleared only by the CLEAR STATUS REGISTER command, but it does not prevent additional program operation

attempts.

BUS

OPERATION COMMAND COMMENTS

WRITE WRITE Data = 40h or 10h

PROGRAM Addr = Address of word to be

SETUP programmed

WRITE WRITE Data = Word to be

DATA programmed

Addr = Address of word to be

programmed

READ Status register data;

toggle OE# or CE# to update

status register.

Standby Check SR7

1 = Ready, 0 = Busy

Repeat for subsequent words.

Write FFh after the last word programming operation

to reset the device to read array mode.

BUS

OPERATION COMMAND COMMENTS

Standby Check SR1

1 = Detect locked block

Standby Check SR3

1 = Detect V

low

Standby Check SR4

1 = Word program error

YES

Full Status Register

Check (optional)

YES

PROGRAM

SUSPEND?

SR7 = 1?

Issue PROGRAM SETUP

Command and

Word Address

Start

Word Program Passed

VPP Range Error

Word Program Failed

FULL STATUS REGISTER CHECK FLOW

Read Status Register

Bits

Issue Word Address

and Word Data

PROGRAM

SUSPEND Loop

YES

SR1 = 0?

YES

SR3 = 0?

YES

SR4 = 0?

Word Program

Completed

Read Status Register

Bits

PROGRAM Attempted

on a Locked Block

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Issue READ ARRAY

Command

PROGRAM

Complete

Finished

Reading

Issue PROGRAM

RESUME Command

YES

SR2 = 1?

Start

PROGRAM Resumed

Read Status Register

Bits

Issue PROGRAM

SUSPEND Command

YES

SR7 = 1?

Figure 5

PROGRAM SUSPEND/

PROGRAM RESUME Flowchart

BUS

OPERATION COMMAND COMMENTS

WRITE PROGRAM Data = B0h

SUSPEND

READ Status register data;

toggle OE# or CE# to update

status register.

Standby Check SR7

1 = Ready

Standby Check SR2

1 = Suspended

WRITE READ Data = FFh

MEMORY

READ Read data from block other

than that being programmed.

WRITE PROGRAM Data = D0h

RESUME

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ADVANCE

YES

Full Status Register

Check (optional)

YES

ERASE

SUSPEND?

SR 7 = 1?

Start

BLOCK ERASE Passed

VPP Range Error

BLOCK ERASE Failed

FULL STATUS REGISTER CHECK FLOW

Read Status Register

Bits

ERASE

SUSPEND Loop

YES

SR1 = 0?

YES

BLOCK ERASE

Completed

Read Status Register

Bits

ERASE Attempted

on a Locked Block

SR3 = 0?

SR5 = 0?

Issue ERASE SETUP

Command and

Block Address

Issue BLOCK ERASE

CONFIRM Command

and Block Address

Figure 6

BLOCK ERASE Flowchart

NOTE: 1. Full status register check can be done after each block or after a sequence of blocks.

2. SR3 must be cleared before attempting additional PROGRAM/ERASE operations.

3. SR5 is cleared only by the CLEAR STATUS REGISTER command in cases where multiple blocks are erased before full

status is checked.

BUS

OPERATION COMMAND COMMENTS

WRITE WRITE Data = 20h

ERASE Block Addr = Address

SETUP within block to be erased

WRITE ERASE Data = D0h

Block Addr = Address

within block to be erased

READ Status register data;

toggle OE# or CE# to

update status register.

Standby Check SR7

1 = Ready, 0 = Busy

Repeat for subsequent blocks.

Write FFh after the last BLOCK ERASE operation to

reset the device to read array mode.

BUS

OPERATION COMMAND COMMENTS

Standby Check SR1

1 = Detect locked block

Standby Check SR32

1 = Detect VPP block

Standby Check SR4 and SR5

1 = BLOCK ERASE

command error

Standby Check SR53

1 = BLOCK ERASE error

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READ

PROGRAM

Issue READ ARRAY

Command

PROGRAM

Loop

ERASE

Complete

READ or

PROGRAM?

YES

Issue ERASE

RESUME Command

READ or

PROGRAM

Complete?

YES

SR6 = 1?

Start

ERASE Continued

Read Status Register

Bits

Issue ERASE

SUSPEND Command

(Note 1)

YES

SR7 = 1?

Figure 7

ERASE SUSPEND/ERASE RESUME

Flowchart

NOTE: 1. See BLOCK ERASE Flowchart for complete erasure procedure.

2. See Word Programming Flowchart for complete programming procedure.

BUS

OPERATION COMMAND COMMENTS

WRITE ERASE Data = B0h

SUSPEND

READ Status register data;

toggle OE# or CE# to

update status register.

Standby Check SR7

1 = Ready

Standby Check SR6

1 = Suspended

WRITE READ Data = FFh

MEMORY

READ Read data from block

other than that being

erased.

WRITE ERASE Data = D0h

RESUME

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READ-WHILE-WRITE/ERASE

CONCURRENCY

It is possible for the device to read from one bank

while erasing/writing to another bank. Once a bank

enters the WRITE/ERASE operation, the other bank

automatically enters read array mode. For example,

during a READ CONCURRENCY operation, if a PRO-

GRAM/ERASE command is issued in bank a, then bank

a changes to the read status mode and bank b defaults

to the read array mode. The device reads from bank b if

the latched address resides in bank b (see Figure 8).

Similarly, if a PROGRAM/ERASE command is issued in

bank b, then bank b changes to read status mode and

bank a defaults to read array mode. When returning to

bank a, the device reads program/erase status if the

latched address resides in bank a. A correct bank ad-

dress must be specified to read status register after

returning from concurrent read in the other bank.

When reading the CFI or the chip protection regis-

ter, concurrent operation is not allowed on the top boot

device. Concurrent READ of the CFI or the chip protec-

tion register is only allowed when a PROGRAM or ERASE

operation is performed on bank b on the bottom boot

device. For a bottom boot device, reading of the CFI

table or the chip protection register is only allowed if

bank b is in read array mode. For a top boot device,

reading of the CFI table or the chip protection register

is only allowed if bank a is in read array mode.

Figure 8

READ-While-WRITE Concurrency

Bank a

1 - Erasing/writing to bank a

2 - Erasing in bank a can be

suspended, and a WRITE to

another block in bank a

can be initiated.

3 - After the WRITE in that block

is complete, an ERASE can

be resumed by writing an

ERASE RESUME command.

1 - Reading bank a

Bank b

1 - Reading from bank b

1 - Erasing/writing to bank b

2 - Erasing in bank b can be

suspended, and a WRITE to

another block in bank b

can be initiated.

3 - After the WRITE in that block

is complete, an ERASE can

be resumed by writing an

ERASE RESUME command.

BLOCK LOCKING

The Flash memory of the MT28C3224P20 and

MT28C3224P18 devices provide a flexible locking

scheme which allows each block to be individually

locked or unlocked with no latency.

The devices offer two-level protection for the blocks.

The first level allows software-only control of block lock-

ing (for data which needs to be changed frequently),

while the second level requires hardware interaction

before locking can be changed (code which does not

require frequent updates).

Control signals F_WP#, DQ0, and DQ1 define the

state of a block; for example, state [001] means F_WP#

= 0, DQ0 = 0 and DQ1 = 1.

Table 8 defines all of the possible locking states.

NOTE: All blocks are software-locked upon comple-

tion of the power-up sequence.

LOCKED STATE

After a power-up sequence completion, or after a

reset sequence, all blocks are locked (states [001] or

[101]). This means full protection from alteration. Any

PROGRAM or ERASE operations attempted on a locked

block will return an error on bit SR1 of the status regis-

ter. The status of a locked block can be changed to

unlocked or lock down using the appropriate software

commands. Writing the lock command sequence, 60h

followed by 01h, can lock an unlocked block.

UNLOCKED STATE

Unlocked blocks (states [000], [100], [110]) can be

programmed or erased. All unlocked blocks return to

the locked state when the device is reset or powered

down. An unlocked block can be locked or locked down

using the appropriate software command sequence,

60h followed by D0h. (See Table 4.)

LOCKED DOWN STATE

Blocks locked down (state [011]) are protected from

PROGRAM and ERASE operations, but their protection

status cannot be changed using software commands

alone. A locked or unlocked block can be locked down

by writing the lock down command sequence, 60h fol-

lowed by 2Fh. Locked down blocks revert to the locked

state when the device is reset or powered down.

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The LOCK DOWN function is dependent on the

F_WP# input. When F_WP# = 0, blocks in lock down

[011] are protected from program, erase, and lock sta-

tus changes. When F_WP# = 1, the LOCK DOWN func-

tion is disabled ([111]) and locked down blocks can be

individually unlocked by a software command to the

[110] state, where they can be erased and programmed.

These blocks can then be relocked [111] and unlocked

[110], as desired, as long as F_WP# remains HIGH.

When F_WP# goes LOW, blocks that were previously

locked down return to the lock down state [011] regard-

less of any changes made while F_WP# was HIGH. De-

vice reset or power-down resets all locks, including

those in lock down, to the locked state (see Table 9).

READING A BLOCK’S LOCK STATUS

The lock status of every block can be read in the

read device identification mode. To enter this mode,

write 90h to the bank containing address 00h. Subse-

quent READs at block address +00002 will output the

lock status of that block. The lowest two outputs, DQ0

and DQ1, represent the lock status. DQ0 indicates the

block lock/unlock status and is set by the LOCK com-

mand and cleared by the UNLOCK command. It is also

automatically set when entering lock down. DQ1 indi-

cates lock down status and is set by the LOCK DOWN

command. It can only be cleared by reset or power-

down, not by software. Table 8 shows the block locking

state transition scheme. After data is read from the

Table 8

Block Locking State Transition

ERASE/PROGRAM LOCK

F_WP# DQ1 DQ0 NAME ALLOWED LOCK UNLOCK DOWN

0 0 0 Unlocked Yes To [001] – To [011]

0 0 1 Locked (Default) No – To [000] To [011]

0 1 1 Lock Down No – – –

1 0 0 Unlocked Yes To [101] – To [111]

1 0 1 Locked No – To [100] To [111]

1 1 0 Lock Down Yes To [111] – To [111]

Disabled

1 1 1 Lock Down No – To [110] –

Disabled

ITEM ADDRESS2DATA

Manufacturer Code (x16) 00000h 002Ch

Device Code 00001h

·Top boot configuration 44B4h

·Bottom boot configuration 44B5h

Block Lock Configuration XX002h Lock

·Block is unlocked DQ0 = 0

·Block is locked DQ0 = 1

·Block is locked down DQ1 = 1

Chip Protection Register Lock 80h PR Lock

Chip Protection Register 1 81h–84h Factory Data

Chip Protection Register 2 85h–88h User Data

NOTE: 1. Other locations within the configuration address space are reserved by

Micron for future use.

2. “XX” specifies the block address of lock configuration.

Table 9

Chip Configuration Addressing1

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ADVANCE

protection configuration register, the READ ARRAY

command, FFh, must be issued to the bank containing

address 00h prior to issuing other commands.

LOCKING OPERATIONS DURING ERASE

SUSPEND

Changes to block lock status can be performed dur-

ing an ERASE SUSPEND by using the standard locking

command sequences to unlock, lock, or lock down. This

is useful in the case when another block needs to be

updated while an ERASE operation is in progress.

To change block locking during an ERASE opera-

tion, first write the ERASE SUSPEND command (B0h),

then check the status register until it indicates that the

ERASE operation has been suspended. Next, write the

desired lock command sequence to block lock, and the

lock status will be changed. After completing any de-

sired LOCK, READ, or PROGRAM operations, resume

the ERASE operation with the ERASE RESUME com-

mand (D0h).

If a block is locked or locked down during an ERASE

SUSPEND on the same block, the locking status bits

are changed immediately. When the ERASE is resumed,

the ERASE operation completes.

A locking operation cannot be performed during a

PROGRAM SUSPEND.

STATUS REGISTER ERROR CHECKING

Using nested locking or program command se-

quences during ERASE SUSPEND can introduce ambi-

guity into status register results.

Following protection configuration setup (60h), an

invalid command produces a lock command error (SR4

and SR5 are set to “1”) in the status register. If a lock

command error occurs during an ERASE SUSPEND,

SR4 and SR5 are set to “1” and remain at “1” after the

ERASE SUSPEND command is issued. When the ERASE

is complete, any possible error during the ERASE can-

not be detected via the status register because of the

previous locking command error.

A similar situation happens if an error occurs during

a program operation error nested within an ERASE

SUSPEND.

CHIP PROTECTION REGISTER

A 128-bit chip protection register can be used to

fullfill the security considerations in the system (pre-

venting device substitution).

The 128-bit security area is divided into two 64-bit

segments. The first 64 bits are programmed at the

manufacturing site with a unique 64-bit number. The

other segment is left blank for customers to program as

desired. (See Figure 9).

READING THE CHIP PROTECTION REGISTER

The chip protection register is read in the device

identification mode, loading the 90h command. Once

in this mode, READ cycles from addresses shown in

Table 9 retrieve the specified information. To return to

the read array mode, write the READ ARRAY command

(FFh).

PAGE READ MODE

The initial portion of the page mode cycle is the

same as the asynchronous access cycle. Holding CE#

LOW and toggling addresses A0–A1 allows random ac-

cess of other words in the page.

The page size can be customized at the factory to

four or eight words as required; but if no specification is

made, the normal size is four words.

ASYNCHRONOUS READ CYCLE

When accessing addresses in a random order or

when switching between pages, the access time is given

by tAA.

When F_CE# and F_OE# are LOW, the data is placed

on the data bus and the processor can read the data.

Figure 9

Protection Register Memory Map

4 Words

Factory-Programmed

4 Words

User-Programmed

PR Lock 0

88h

85h

84h

81h

80h

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ADVANCE

STANDBY MODE

Icc supply current is reduced by applying a logic

HIGH level on F_CE# and F_RP# to enter the standby

mode. In the standby mode, the outputs are placed in

High-Z. Applying a CMOS logic HIGH level on F_CE#

and F_RP# reduces the current to ICC3 (MAX). If the

device is deselected during an ERASE operation or dur-

ing programming, the device continues to draw cur-

rent until the operation is complete.

AUTOMATIC POWER SAVE (APS) MODE

Substantial power savings are realized during peri-

ods when the Flash array is not being read and the

device is in the active mode. During this time the de-

vice switches to the automatic power save (APS) mode.

When the device switches to this mode, ICC is reduced

to a level comparable to ICC3. Further power savings can

be realized by applying a logic HIGH level on CE# to

place the device in standby mode. The low level of

power is maintained until another operation is initi-

ated. In this mode, the I/Os retain the data from the

last memory address read until a new address is read.

This mode is entered automatically if no addresses or

control signals toggle.

VPP/VCC PROGRAM AND ERASE

VOLTAGES

The Flash memory devices provide in-system

programming and erase with VPP in the 0.9V–2.2V range.

In addition to the flexible block locking, the VPP pro-

gramming voltage can be held LOW for absolute hard-

ware write protection of all blocks in the Flash device.

When VPP is below VPPLK, any PROGRAM or ERASE op-

eration results in an error, prompting the correspond-

ing status register bit (SR3) to be set.

A factory option provides in-system programming

and erase with VPP in the 0.0V–2.2V range.

VPP at 12V ±5% (VPP2) is supported for a maximum

of 100 cycles and 10 cumulative hours. The device

can withstand 100,000 WRITE/ERASE operations when

VPP = VCC.

During WRITE and ERASE operations, the WSM

monitors the VPP voltage level. WRITE/ERASE opera-

tions are allowed only when VPP is within the ranges

specified in Table 10.

When VCC is below VLKO or VPP is below VPPLK, any

WRITE/ERASE operation is prevented.

DEVICE RESET

To correctly reset the device, the RST# signal must

be asserted (RST# = VIL) for a minimum of tRP. After

reset, the device can be accessed for a READ operation

with a delayed access time of tRWH from the rising edge

of RST#. The circuitry used for generating the RST#

signal needs to be common with the rest of the system

reset to ensure that correct system initialization occurs.

Please refer to the timing diagram for further details.

POWER-UP SEQUENCE

The following power-up sequence is recommended

to properly initialize internal chip operations:

• At power-up, RST# should be kept at VIL for 2µs

after VCC reaches VCC (MIN).

•VCCQ should not come up before VCC.

•VPP should be kept at VIL to maximize data

integrity.

When the power-up sequence is completed, RST#

should be brought to VIH. To ensure proper power-up,

the rise time of RST# (10%–90%) should be < 10µs.

Table 10

VPP Ranges (V)

DEVICE MIN MAX

In-System 0.9 2.2

In-Factory 11.4 12.6

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ADVANCE

ABSOLUTE MAXIMUM RATINGS*

Voltage to Any Ball Except VCC and VPP

with Respect to VSS ............................ -0.5V to +2.45V

VPP Voltage (for BLOCK ERASE and PROGRAM

with Respect to VSS) ....................... -0.5V to +13.5V**

VCC and VCCQ Supply Voltage

with Respect to VSS ............................ -0.3V to +2.45V

Output Short Circuit Current............................... 100mA

Operating Temperature Range .............. -40oC to +85oC

Storage Temperature Range ................. -55oC to +125oC

Soldering Cycle ........................................... 260oC for 10s

*Stresses greater than those listed under “Absolute

Maximum Ratings” may cause permanent damage to

the device. This is a stress rating only and functional

operation of the device at these or any other conditions

above those indicated in the operational sections of

this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may

affect reliability.

**Maximum DC voltage on VPP may overshoot to +13.5V

for periods <20ns.

RECOMMENDED OPERATING CONDITIONS

PARAMETER SYMBOL MIN MAX UNITS NOTES

Operating temperature tA -40 +85 oC

VCC supply voltage (MT28C3224P18) F_VCC, S_VCC 1.70 1.90 V

VCC supply voltage (MT28C3224P20) F_VCC, S_VCC 1.80 2.20 V

I/O supply voltage (MT28C3224P18) VCCQ 1.70 1.90 V

I/O supply voltage (MT28C3224P20) VCCQ 1.80 2.20 V

VPP voltage (when used as logic control) VPP10.9 2.2 V

VPP in-factory programming voltage VPP211.4 12.6 V

Data retention supply voltage S_VDR 1.0 – V

Block erase cycling (VPP1)VPP = VPP1VPP1– 100,000 Cycles

VPP = VPP2VPP2– 100 Cycles 1

FLASH ELECTRICAL SPECIFICATIONS

NOTE: 1. VPP = VPP2 is a maximum of 10 cumulative hours.

Figure 11

Output Load Circuit

I/O

14.5K

30pF

VCC

VSS

14.5K

OutputTest PointsInput

AC test inputs are driven at VCC for a logic 1 and VSS for a logic 0. Input timing begins at VCC/2, and output timing ends

at VCCQ/2. Input rise and fall times (10% to 90%) < 5ns.

Q/2V

Figure 10

AC Input/Output Reference Waveform

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ADVANCE

COMBINED DC CHARACTERISTICS1

VCC/VCCQ = 1.70V–1.90V

or 1.80V–2.20V

DESCRIPTION CONDITIONS SYMBOL MIN TYP MAX UNITS NOTES

Input Low Voltage VIL 0 – 0.4 V 2

Input High Voltage VIH VCCQ - – VCCQV 2

0.4

Output Low Voltage VOL – – 0.10 V

IOL = 100µA (Flash)

Output Low Voltage VOL – – 0.3 V

IOL = 100µA (SRAM)

Output High Voltage VOH VCCQ - – – V

IOH = -100µA (Flash) 0.1

Output High Voltage VOH VCCQ - – – V

IOH = -100µA (SRAM) 0.3

VPP Lockout Voltage VPPLK – – 0.4 V

VPP During PROGRAM/ERASE VPP10.9 – 2.2 V

Operations VPP211.4 – 12.6 V 3

VCC Program/Erase Lock Voltage VLKO 1––V

Input Leakage Current IL––1µA

Output Leakage Current IOZ ––1µA

VCC Read Current ICC14, 5

Asynchronous Random Read – – 15 mA

100ns cycle

Asynchronous Page Read ICC2––5mA4, 5

100ns/35ns cycle

F_VCC plus S_VCC Standby Current ICC3–2560µA

F_VCC Program Current ICC4––55mA

F_VCC Erase Current ICC5–1845mA

F_VCC plus S_VCC ICC6–660µA6

Erase Suspend Current

F_VCC plus S_VCC ICC7–660µA6

Program Suspend Current

Read-While-Write Current ICC8––80mA

NOTE: 1. All currents are in RMS unless otherwise noted.

2. VIL may decrease to -0.4V and VIH may increase to VCCQ + 0.3V for durations not to exceed 20ns.

3. 12V VPP is supported for a maximum of 100 cycles and may be connected for up to 10 cumulative hours.

4. APS mode reduces ICC to approximately ICC3 levels.

5. Test conditions: Vcc = VCC (MAX), CE# = VIL, OE# = VIH. All other inputs = VIH or VIL.

6. ICC6 and ICC7 values are valid when the device is deselected. Any READ operation performed while in suspend mode will

add a current draw of ICC1 or ICC2.

7. Operating current is a linear function of operating frequency and voltage. Operating current can be calculated using

the formula shown with operating frequency (f) expressed in MHz and operating voltage (V) in volts.

Example: When operating at 2 MHz at 2V, the device will draw a typical active current of 0.8*2*2 = 3.2mA in the page

access mode. This parameter is specified with the outputs disabled to avoid external loading effects. The user must add

current required to drive output capacitance expected in the actual system.

(continued on next page)

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ADVANCE

COMBINED DC CHARACTERISTICS (continued)1

VCC/VCCQ = 1.70V–1.90V

or 1.80V–2.20V

DESCRIPTION CONDITIONS SYMBOL MIN TYP MAX UNITS NOTES

S_VCC Read/Write Operating VIN = VIH or VIL ICC9–1225mA7

Supply Current – Page Access chip enabled, IOL = 0

Mode

VPP Current IPP1

(Read, Standby, Erase Suspend, VPP ≤ VCC ––1µA

Program Suspend) VPP ≥ VCC – – 200 µA

NOTE: 1. All currents are in RMS unless otherwise noted.

2. VIL may decrease to -0.4V and VIH may increase to VCCQ + 0.3V for durations not to exceed 20ns.

3. 12V VPP is supported for a maximum of 100 cycles and may be connected for up to 10 cumulative hours.

4. APS mode reduces ICC to approximately ICC3 levels.

5. Test conditions: Vcc = VCC (MAX), CE# = VIL, OE# = VIH. All other inputs = VIH or VIL.

6. ICC6 and ICC7 values are valid when the device is deselected. Any READ operation performed while in suspend mode will

add a current draw of ICC1 or ICC2.

7. Operating current is a linear function of operating frequency and voltage. Operating current can be calculated using

the formula shown with operating frequency (f) expressed in MHz and operating voltage (V) in volts.

Example: When operating at 2 MHz at 2V, the device will draw a typical active current of 0.8*2*2 = 3.2mA in the page

access mode. This parameter is specified with the outputs disabled to avoid external loading effects. The user must add

current required to drive output capacitance expected in the actual system.

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ADVANCE

CAPACITANCE

(TA = +25ºC; f = 1 MHz)

PARAMETER/CONDITION SYMBOL TYP MAX UNITS

Input Capacitance C 7 12 p F

Output Capacitance COUT 13 15 pF

FLASH READ CYCLE TIMING REQUIREMENTS

-80 -85

VCC = 1.80V–2.20V VCC = 1.70V–1.90V

PARAMETER SYMBOL MIN MAX MIN MAX UNITS

Address to output delay tAA 80 85 ns

CE# LOW to output delay tACE 80 85 ns

Page address access tAPA 30 35 ns

OE# LOW to output delay tAOE 25 30 ns

F_RP# HIGH to output delay tRWH 200 250 ns

CE# or OE# HIGH to output High-Z tOD 25 25 ns

Output hold from address, CE# or OE# change tOH 0 0 ns

READ cycle time tRC 80 85 ns

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ADVANCE

FLASH WRITE CYCLE TIMING REQUIREMENTS

-80/-85

PARAMETER SYMBOL MIN MAX UNITS

Reset HIGH recovery to WE# going LOW tRS 150 ns

CE# setup to WE# going LOW tCS 0 ns

Write pulse width tWP 50 ns

Data setup to WE# going HIGH tDS 50 ns

Address setup to WE# going HIGH tAS 50 ns

CE# hold from WE# HIGH tCH 0 ns

Data hold from WE# HIGH tDH 0 ns

Address hold from WE# HIGH tAH 1.5 ns

Write pulse width HIGH tWPH 30 ns

WP# setup to WE# going HIGH tRHS 0 ns

VPP setup to WE# going HIGH tVPS 200 ns

Write recovery before READ tWOS 50 ns

Write recovery before READ in opposite bank tWOA 0 ns

WP# hold from valid SRD tRHH 0 ns

VPP hold from valid SRD tVPPH 0 ns

WE# HIGH to data valid tWB tAA + 50 ns

FLASH ERASE AND PROGRAM CYCLE TIMING REQUIREMENTS

-80/-85

PARAMETER TYP MAX UNITS

4KW parameter block program time 40 800 ms

32KW parameter block program time 320 6,400 ms

Word program time 8 10,000 µs

4KW parameter block erase time 0.3 6 s

32KW parameter block erase time 0.5 6 s

Program suspend latency 510µs

Erase suspend latency 520µs

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ADVANCE

TWO-CYCLE PROGRAMMING/ERASE OPERATION

VALID ADDRESS VALID ADDRESS VALID ADDRESS

UNDEFINED

RHS

A0–A20

OE#

CE#

WE#

RST#

WP#

IPPLK

IPPH

WPH

WOS

CMD CMD/

DATA

DQ0–DQ15

RHH

VPS

VPPH

STATUS

High-Z

NOTE: 1. The WRITE cycles for the WORD PROGRAMMING command are followed by a READ ARRAY DATA cycle.

-80/-85

SYMBOL MIN MAX UNITS

WRITE TIMING PARAMETERS

-80/-85

SYMBOL MIN MAX UNITS

tRS 150 ns

tCS 0 ns

tWP 50 ns

tDS 50 ns

tAS 50 ns

tCH 0 ns

tDH 0 ns

tAH 1.5 ns

tRHS 0 ns

tVPS 200 ns

tWOS 50 ns

tRHH 0 ns

tVPPH 0 ns

tWB tAA+50 ns

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ADVANCE

SINGLE ASYNCHRONOUS READ OPERATION

VALID ADDRESS

UNDEFINED

ACE

A0–A20

OE#

CE#

WE#

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

RWH

DQ0–DQ15

RP#

VOH

VOL

VALID OUTPUT

High-Z

AOE

-80 -85

VCC = 1.80V–2.20V VCC = 1.70V–1.90V

SYMBOL MIN MAX MIN MAX UNITS

READ TIMING PARAMETERS

-80 -85

VCC = 1.80V–2.20V VCC = 1.70V–1.90V

SYMBOL MIN MAX MIN MAX UNITS

tAA 80 85 ns

tACE 80 85 ns

tAOE 25 30 n s

tRWH 200 250 ns

tOD 25 25 n s

tOH 0 0 ns

tRC 80 85 n s

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ADVANCE

ASYNCHRONOUS PAGE MODE READ OPERATION

VALID ADDRESS

VALID

ADDRESS

VALID

ADDRESS

VALID

ADDRESS

VALID

OUTPUT

VALID

OUTPUT

VALID

OUTPUT

VALID

OUTPUT

UNDEFINED

ACE

AOE

RMH

A0–A1

F_OE#

F_CE#

F_WE#

VALID ADDRESS

A2–A20 V

F_RP#

DQ0–DQ15

High-Z

-80 -85

VCC = 1.80V–2.20V VCC = 1.70V–1.90V

SYMBOL MIN MAX MIN MAX UNITS

READ TIMING PARAMETERS

-80 -85

VCC = 1.80V–2.20V VCC = 1.70V–1.90V

SYMBOL MIN MAX MIN MAX UNITS

tAA 80 85 n s

tACE 80 85 ns

tA P A 30 35 n s

tAOE 25 30 n s

tRWH 200 250 ns

tOD 25 25 n s

tOH 0 0 ns

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ADVANCE

RESET OPERATION

F_OE#

DQ0–DQ15

VIH

VIL

F_RST# VIH

VIL

F_CE# VIH

VIL

VOH

VOL

tRWH

tRP

READ TIMING PARAMETERS

-80 -85

VCC = 1.80V–2.20V VCC = 1.70V–1.90V

SYMBOL MIN MAX MIN MAX UNITS

tRWH 200 250 ns

tRP 100 100 ns

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ADVANCE

Table 11

CFI

OFFSET DATA DESCRIPTION

00 2Ch Manufacturer Code

01 B4h Top boot block device code

B5h Bottom boot block device code

02–0F reserved Reserved

10, 11 0051,0052 “QR”

12 0059 “Y”

13, 14 0003, 0000 Primary OEM command set

15, 16 0039, 0000 Address for primary extended table

17, 18 0000, 0000 Alternate OEM command set

19, 1A 0000, 0000 Address for OEM extended table

1B 0017 VCC MIN for Erase/Write; Bit7–Bit4 Volts in BCD; Bit3–Bit0 100mV in BCD

1C 0022 VCC MAX for Erase/Write; Bit7–Bit4 Volts in BCD; Bit3–Bit0 100mV in BCD

1D 00B4 VPP MIN for Erase/Write; Bit7–Bit4 Volts in Hex; Bit3–Bit0 100mV in BCD

1E 00C6 VPP MAX for Erase/Write; Bit7–Bit4 Volts in Hex; Bit3–Bit0 100mV in BCD

1F 0003 Typical timeout for single byte/word program, 2n µs, 0000 = not supported

20 0000 Typical timeout for maximum size multiple byte/word program, 2n µs, 0000 = not

supported

21 0009 Typical timeout for individual block erase, 2n ms, 0000 = not supported

22 0000 Typical timeout for full chip erase, 2n ms, 0000 = not supported

23 000C Maximum timeout for single byte/word program, 2n µs, 0000 = not supported

24 0000 Maximum timeout for maximum size multiple byte/word program, 2n µs, 0000 = not

supported

25 0003 Maximum timeout for individual block erase, 2n ms, 0000 = not supported

26 0000 Maximum timeout for full chip erase, 2n ms, 0000 = not supported

27 0016 Device size, 2n bytes

28 0001 Bus interface x8 = 0, x16 = 1, x8/x16 = 2

29 0000 Flash device interface description 0000 = async

2A, 2B 0000, 0000 Maximum number of bytes in multi-byte program or page, 2n

2C 0003 Number of erase block regions within device (4K words and 32K words)

2D, 2E 002F, 0000 Top boot block device erase block region information 1, 8 blocks …

0007, 0000 Bottom boot block device erase block region information 1, 8 blocks …

2F, 30 0000, 0001 Erase block region information 1, 8 blocks …

0020, 0000 …of 8KB

31, 32 000E, 0000 7 blocks of ….

33, 34 0000, 0001 ……64KB

35, 36 0007, 0000 Top boot block device ……48 blocks of

002F, 0000 Bottom boot block device ……48 blocks of

(continued on the next page)

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ADVANCE

Table 11

CFI (continued)

OFFSET DATA DESCRIPTION

37, 38 0020, 0000 Top boot block device……64KB

0000, 0001 Bottom boot block device……64KB

39, 3A 0050, 0052 “PR”

3B 0049 “I”

3C 0030 Major version number, ASCII

3D 0031 Minor version number, ASCII

3E 00E6 Optional Feature and Command Support

3F 0002 Bit 0 Chip erase supported no = 0

40 0000 Bit 1 Suspend erase supported = yes = 1

41 0000 Bit 2 Suspend program supported = yes = 1

Bit 3 Chip lock/unlock supported = no = 0

Bit 4 Queued erase supported = no = 0

Bit 5 Instant individual block locking supported = yes = 1

Bit 6 Protection bits supported = yes = 1

Bit 7 Page mode read supported = yes = 1

Bit 8 Synchronous read supported = yes = 1

Bit 9 Simultaneous operation supported = yes = 1

42 0001 Program supported after erase suspend = yes

43, 44 0003,0000 Bit 0 block lock status active = yes; Bit 1 block lock down active = yes

45 0018 VCC supply optimum; Bit7–Bit4 Volts in BCD; Bit3–Bit0 100mV in BCD

46 00C0 VPP supply optimum; Bit7–Bit4 Volts in Hex; Bit3–Bit0 100mV in BCD

47 0001 Number of protection register fields in JEDEC ID space

48, 49 0080, 0000 Lock bytes LOW address, lock bytes HIGH address

4A, 4B 0003, 0003 2n factory programmed bytes, 2n user programmable bytes

4C 0003 Background Operation

0000 = Not used

0001 = 4% block split

0002 = 12% block split

0003 = 25% block split

0004 = 50% block split

4D 0000 Burst Mode Type

0000 = No burst mode

00x1 = 4 words max

00x2 = 8 words max

00x3 = 16 words max

001x = Linear burst, and/or

002x = Interleaved burst, and/or

004x = Continuous burst

4E 0002 Page Mode Type

0000 = No page mode

0001 = 4-word page

0002 = 8-word page

0003 = 16-word page

0004 = 32-word page

4F 0004 SRAM density, 4Mb (256K x 16)

SRAM

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ADVANCE

SRAM OPERATING MODES

SRAM READ ARRAY

The operational state of the SRAM is determined by

S_CE1#, S_CE2, S_WE#, S_OE#, S_UB#, and S_LB#, as

indicated in the Truth Table. To perform an SRAM

READ operation, S_CE1#, and S_OE#, must be at VIL,

and S_CE2 and S_WE# must be at VIH. When in this

state, S_UB# and S_LB# control whether the lower byte

is read (S_UB# VIH, S_LB# VIL), the upper byte is read

(S_UB# VIL, S_LB# VIH), both upper and lower bytes are

read (S_UB# VIL, S_LB# VIL), or neither are read (S_UB#

VIH, S_LB# VIH) and the device is in a standby state.

While performing an SRAM READ operation, cur-

rent consumption may be reduced by reading within a

16-word page. This is done by holding S_CE1# and

SRAM FUNCTIONAL BLOCK DIAGRAM

DQ0–DQ7

WORD

ADDRESS

DECODE

LOGIC

PAGE

ADDRESS

DECODE

LOGIC

CONTROL

LOGIC

16K-PAGE

x16 WORD

x16 BIT

RAM ARRAY

WORD

MUX DQ8–DQ15

INPUT/

OUTPUT

MUX

AND

BUFFERS

S_CE1#

A4–A17

A0–A3

S_OE#

S_UB#

S_LB#

S_CE2

S_WE#

S_OE# at VIL, S_WE# and S_CE2 at VIH, and toggling

addresses A0–A3. S_UB# and S_LB# control the data

width as described above.

SRAM WRITE ARRAY

In order to perform an SRAM WRITE operation,

S_CE1# and S_WE# must be at VIL, and S_CE2 and

S_OE# must be at VIH. When in this state, S_UB# and

S_LB# control whether the lower byte is written (S_UB#

VIH, S_LB# VIL), the upper byte is written (S_UB# VIL,

S_LB# VIH), both upper and lower bytes are written

(S_UB# VIL, S_LB# VIL), or neither are written (S_UB#

VIH, S_LB# VIH) and the device is in a standby state.

SRAM

2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.

2 MEG x 16 PAGE FLASH

256K x 16 SRAM COMBO MEMORY

ADVANCE

TIMING TEST CONDITIONS

Input pulse levels .................... 0.1V VCC to 0.9V VCC

Input rise and fall times .................................... 5ns

Input timing reference levels ......................... 0.5V

Output timing reference levels ..................... 0.5V

Operating Temperature ............... -40oC to +85oC

SRAM WRITE CYCLE TIMING

-80/-85

DESCRIPTION SYMBOL MIN MAX UNITS

Write cycle time tWC 85 ns

Chip enable to end of write tCW 50 ns

Address valid to end of write tAW 50 ns

Byte select to end of write tLBW, tUBW 50 ns

Address setup time tAS 0 ns

Write pulse width tWP 50 ns

Write recovery time tWR 0 ns

Write to High-Z output tWHZ 0 15 ns

Data to write time overlap tDW 50 ns

Data hold from write time tDH 0 ns

End write to Low-Z output tOW 0 ns

NOTE: For input/output contacts, refer to the Capacitance Table.

SRAM READ CYCLE TIMING

-80/-85

VCC = 1.70V–1.90V VCC = 1.80V–2.20V

DESCRIPTION SYMBOL MIN MAX MIN MAX UNITS

Read cycle time tRC 100 85 ns

Address access time tAA 100 85 ns

Chip enable to valid output tCO 100 85 ns

Output enable to valid output tOE 35 35 ns

Byte select to valid output tLB, tUB 100 85 ns

Chip enable to Low-Z output tLZ 0 0 ns

Output enable to Low-Z output tOLZ 0 0 ns

Byte select to Low-Z output tLBZ, tUBZ 0 0 ns

Chip enable to High-Z output tHZ 0 15 0 15 ns

Output disable to High-Z output tOHZ 0 15 0 15 ns

Byte select disable to High-Z output tLBHZ, tUBHZ 0 15 0 15 ns

Output hold from address change tOH 5 5 ns

SRAM

2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.

2 MEG x 16 PAGE FLASH

256K x 16 SRAM COMBO MEMORY

ADVANCE

DON’T CARE

ADDRESS

S_CE1#

S_CE2

S_OE#

S_LB#, S_UB#

DATA-OUT

tRC

tAA tHZ (1, 2)

tCO

tLBLZ, tUBLZ tLBHZ, tUBHZ

DATA VALID

High-Z

tOE

tLZ(2)

tOLZ

tOHZ (1)

tLB, tUB

READ CYCLE 1

(S_CE1# = S_OE# = VIL; S_CE2, S_WE# = VIH)

ADDRESS

DATA-OUT

tRC

tAA

tOH

DATA VALID DATA VALID

READ CYCLE 2

(S_WE# = VIH)

READ TIMING PARAMETERS

-80/-85

VCC = 1.70V–1.90V VCC = 1.80V–2.20V

SYMBOL MIN MAX MIN MAX UNITS

tRC 100 85 ns

tAA 100 85 ns

tCO 100 85 ns

tOE 35 35 n s

tLB,

tUB 100 85 ns

tLZ 0 0 ns

-80/-85

VCC = 1.70V–1.90V VCC = 1.80V–2.20V

SYMBOL MIN MAX MIN MAX UNITS

tOLZ 0 0 ns

tHZ 0 15 0 15 ns

tOHZ 0 15 0 15 ns

tLBHZ,

tUBHZ 0 15 0 15 ns

tOH 5 5 ns

SRAM

2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.

2 MEG x 16 PAGE FLASH

256K x 16 SRAM COMBO MEMORY

ADVANCE

WRITE CYCLE

(S_WE# CONTROL)

DON’T CARE

ADDRESS

S_CE1#

S_CE2

DATA-OUT

tWC

tAW tWR

tCW

tWHZ tOW

High-Z

S_LB#, S_UB#

tLBW, tUBW

S_WE#

DATA-IN

tAS tWP

tDH

tDW

DATA VALID

High-Z

-80/-85

SYMBOL MIN MAX UNITS

WRITE TIMING PARAMETERS

-80/-85

SYMBOL MIN MAX UNITS

tWC 85 ns

tCW 50 ns

tAW 50 ns

tLBW,

tUBW 50 ns

tAS 0 ns

tWP 50 ns

tWR 0 ns

tWHZ 0 15 ns

tDW 50 ns

tDH 0 ns

tOW 0 ns

SRAM

2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.

2 MEG x 16 PAGE FLASH

256K x 16 SRAM COMBO MEMORY

ADVANCE

WRITE CYCLE 2

(S_CE1# CONTROL)

DON’T CARE

ADDRESS

S_CE1#

DATA-OUT

tWC

tAW tWR

tCW

tWHZ

tLZ

High-Z

S_LB#, S_UB#

S_WE#

DATA-IN

tAS

tWP

tLBW, tUBW

tDH

tDW

DATA VALID

-80/-85

SYMBOL MIN MAX UNITS

WRITE TIMING PARAMETERS

-80/-85

SYMBOL MIN MAX UNITS

tWC 85 ns

tCW 50 ns

tAW 50 ns

tLBW,

tUBW 50 ns

tAS 0 ns

tWP 50 ns

tWR 0 ns

tWHZ 0 15 ns

tDW 50 ns

tDH 0 ns

tOW 0 ns

2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.

2 MEG x 16 PAGE FLASH

256K x 16 SRAM COMBO MEMORY

ADVANCE

66-BALL FBGA

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900

E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992

Micron is a registered trademark and the Micron logo and M logo are trademarks of Micron Technology, Inc.

SOLDER BALL MATERIAL: EUTECTIC 63% Sn, 37% Pb or

62% Sn, 36% Pb, 2%Ag

SOLDER BALL PAD: Ø .27mm

MOLD COMPOUND: EPOXY NOVOLAC

SUBSTRATE: PLASTIC LAMINATE

1.40 MAX

0.80

(TYP)

8.80

0.80

(TYP)

8.00 ±0.10

12.00 ±0.10

4.40 ±0.05 6.00 ±0.05

66X Ø

0.35

BALL A12 BALL A1

BALL A1

BALL #1 ID

5.60

2.80 ±0.05

4.00 ±0.05

0.10

1.05 ±0.075

SEATING PLANE

SOLDER BALL DIAMETER

REFERS TO POST REFLOW

CONDITION. THE PRE-

REFLOW DIAMETER IS Ø 0.33

NOTE: 1. All dimensions in millimeters.

2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.27mm per side.

DATA SHEET DESIGNATION

Advance: This data sheet contains initial descriptions of products still under development.

2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.

2 MEG x 16 PAGE FLASH

256K x 16 SRAM COMBO MEMORY

ADVANCE

REVISION HISTORY

Rev. 3, ADVANCE .............................................................................................................................................................. 7/02

• Updated Status Register Section

• Updated command descriptions

• Updated Read-While-Write Concurrency section

• Updated timing diagrams

• Changed Cout from 9 (TYP) and 12 (MAX) to 13 (TYP) and 15 (MAX)

• Changed tRHS from 200ns to 0ns

• Updated DC Characteristics

Rev. 2, ADVANCE .............................................................................................................................................................. 4/02

• Updated the DC CHARACTERISTICS table

• Updated the chip protection mode and register information

• Updated the block locking information

Rev. 2, ADVANCE .............................................................................................................................................................. 3/02

• Updated Table 4

• Updated Figure 9

• Updated notes for Combined DC Characteristics

Original document, Rev. 1, ADVANCE ....................................................................................................................... 12/01